1 /*- 2 * Copyright (c) 2008 Benno Rice. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 19 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 20 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 23 */ 24 25 #include <sys/cdefs.h> 26 __FBSDID("$FreeBSD$"); 27 28 /* 29 * Driver for SMSC LAN91C111, may work for older variants. 30 */ 31 32 #ifdef HAVE_KERNEL_OPTION_HEADERS 33 #include "opt_device_polling.h" 34 #endif 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/errno.h> 39 #include <sys/kernel.h> 40 #include <sys/sockio.h> 41 #include <sys/malloc.h> 42 #include <sys/mbuf.h> 43 #include <sys/queue.h> 44 #include <sys/socket.h> 45 #include <sys/syslog.h> 46 #include <sys/taskqueue.h> 47 48 #include <sys/module.h> 49 #include <sys/bus.h> 50 51 #include <machine/bus.h> 52 #include <machine/resource.h> 53 #include <sys/rman.h> 54 55 #include <net/ethernet.h> 56 #include <net/if.h> 57 #include <net/if_arp.h> 58 #include <net/if_dl.h> 59 #include <net/if_types.h> 60 #include <net/if_mib.h> 61 #include <net/if_media.h> 62 63 #ifdef INET 64 #include <netinet/in.h> 65 #include <netinet/in_systm.h> 66 #include <netinet/in_var.h> 67 #include <netinet/ip.h> 68 #endif 69 70 #include <net/bpf.h> 71 #include <net/bpfdesc.h> 72 73 #include <dev/smc/if_smcreg.h> 74 #include <dev/smc/if_smcvar.h> 75 76 #include <dev/mii/mii.h> 77 #include <dev/mii/miivar.h> 78 79 #define SMC_LOCK(sc) mtx_lock(&(sc)->smc_mtx) 80 #define SMC_UNLOCK(sc) mtx_unlock(&(sc)->smc_mtx) 81 #define SMC_ASSERT_LOCKED(sc) mtx_assert(&(sc)->smc_mtx, MA_OWNED) 82 83 #define SMC_INTR_PRIORITY 0 84 #define SMC_RX_PRIORITY 5 85 #define SMC_TX_PRIORITY 10 86 87 devclass_t smc_devclass; 88 89 static const char *smc_chip_ids[16] = { 90 NULL, NULL, NULL, 91 /* 3 */ "SMSC LAN91C90 or LAN91C92", 92 /* 4 */ "SMSC LAN91C94", 93 /* 5 */ "SMSC LAN91C95", 94 /* 6 */ "SMSC LAN91C96", 95 /* 7 */ "SMSC LAN91C100", 96 /* 8 */ "SMSC LAN91C100FD", 97 /* 9 */ "SMSC LAN91C110FD or LAN91C111FD", 98 NULL, NULL, NULL, 99 NULL, NULL, NULL 100 }; 101 102 static void smc_init(void *); 103 static void smc_start(struct ifnet *); 104 static void smc_stop(struct smc_softc *); 105 static int smc_ioctl(struct ifnet *, u_long, caddr_t); 106 107 static void smc_init_locked(struct smc_softc *); 108 static void smc_start_locked(struct ifnet *); 109 static void smc_reset(struct smc_softc *); 110 static int smc_mii_ifmedia_upd(struct ifnet *); 111 static void smc_mii_ifmedia_sts(struct ifnet *, struct ifmediareq *); 112 static void smc_mii_tick(void *); 113 static void smc_mii_mediachg(struct smc_softc *); 114 static int smc_mii_mediaioctl(struct smc_softc *, struct ifreq *, u_long); 115 116 static void smc_task_intr(void *, int); 117 static void smc_task_rx(void *, int); 118 static void smc_task_tx(void *, int); 119 120 static driver_filter_t smc_intr; 121 static timeout_t smc_watchdog; 122 #ifdef DEVICE_POLLING 123 static poll_handler_t smc_poll; 124 #endif 125 126 static __inline void 127 smc_select_bank(struct smc_softc *sc, uint16_t bank) 128 { 129 130 bus_write_2(sc->smc_reg, BSR, bank & BSR_BANK_MASK); 131 } 132 133 /* Never call this when not in bank 2. */ 134 static __inline void 135 smc_mmu_wait(struct smc_softc *sc) 136 { 137 138 KASSERT((bus_read_2(sc->smc_reg, BSR) & 139 BSR_BANK_MASK) == 2, ("%s: smc_mmu_wait called when not in bank 2", 140 device_get_nameunit(sc->smc_dev))); 141 while (bus_read_2(sc->smc_reg, MMUCR) & MMUCR_BUSY) 142 ; 143 } 144 145 static __inline uint8_t 146 smc_read_1(struct smc_softc *sc, bus_addr_t offset) 147 { 148 149 return (bus_read_1(sc->smc_reg, offset)); 150 } 151 152 static __inline void 153 smc_write_1(struct smc_softc *sc, bus_addr_t offset, uint8_t val) 154 { 155 156 bus_write_1(sc->smc_reg, offset, val); 157 } 158 159 static __inline uint16_t 160 smc_read_2(struct smc_softc *sc, bus_addr_t offset) 161 { 162 163 return (bus_read_2(sc->smc_reg, offset)); 164 } 165 166 static __inline void 167 smc_write_2(struct smc_softc *sc, bus_addr_t offset, uint16_t val) 168 { 169 170 bus_write_2(sc->smc_reg, offset, val); 171 } 172 173 static __inline void 174 smc_read_multi_2(struct smc_softc *sc, bus_addr_t offset, uint16_t *datap, 175 bus_size_t count) 176 { 177 178 bus_read_multi_2(sc->smc_reg, offset, datap, count); 179 } 180 181 static __inline void 182 smc_write_multi_2(struct smc_softc *sc, bus_addr_t offset, uint16_t *datap, 183 bus_size_t count) 184 { 185 186 bus_write_multi_2(sc->smc_reg, offset, datap, count); 187 } 188 189 int 190 smc_probe(device_t dev) 191 { 192 int rid, type, error; 193 uint16_t val; 194 struct smc_softc *sc; 195 struct resource *reg; 196 197 sc = device_get_softc(dev); 198 rid = 0; 199 type = SYS_RES_IOPORT; 200 error = 0; 201 202 if (sc->smc_usemem) 203 type = SYS_RES_MEMORY; 204 205 reg = bus_alloc_resource(dev, type, &rid, 0, ~0, 16, RF_ACTIVE); 206 if (reg == NULL) { 207 if (bootverbose) 208 device_printf(dev, 209 "could not allocate I/O resource for probe\n"); 210 return (ENXIO); 211 } 212 213 /* Check for the identification value in the BSR. */ 214 val = bus_read_2(reg, BSR); 215 if ((val & BSR_IDENTIFY_MASK) != BSR_IDENTIFY) { 216 if (bootverbose) 217 device_printf(dev, "identification value not in BSR\n"); 218 error = ENXIO; 219 goto done; 220 } 221 222 /* 223 * Try switching banks and make sure we still get the identification 224 * value. 225 */ 226 bus_write_2(reg, BSR, 0); 227 val = bus_read_2(reg, BSR); 228 if ((val & BSR_IDENTIFY_MASK) != BSR_IDENTIFY) { 229 if (bootverbose) 230 device_printf(dev, 231 "identification value not in BSR after write\n"); 232 error = ENXIO; 233 goto done; 234 } 235 236 #if 0 237 /* Check the BAR. */ 238 bus_write_2(reg, BSR, 1); 239 val = bus_read_2(reg, BAR); 240 val = BAR_ADDRESS(val); 241 if (rman_get_start(reg) != val) { 242 if (bootverbose) 243 device_printf(dev, "BAR address %x does not match " 244 "I/O resource address %lx\n", val, 245 rman_get_start(reg)); 246 error = ENXIO; 247 goto done; 248 } 249 #endif 250 251 /* Compare REV against known chip revisions. */ 252 bus_write_2(reg, BSR, 3); 253 val = bus_read_2(reg, REV); 254 val = (val & REV_CHIP_MASK) >> REV_CHIP_SHIFT; 255 if (smc_chip_ids[val] == NULL) { 256 if (bootverbose) 257 device_printf(dev, "Unknown chip revision: %d\n", val); 258 error = ENXIO; 259 goto done; 260 } 261 262 device_set_desc(dev, smc_chip_ids[val]); 263 264 done: 265 bus_release_resource(dev, type, rid, reg); 266 return (error); 267 } 268 269 int 270 smc_attach(device_t dev) 271 { 272 int type, error; 273 uint16_t val; 274 u_char eaddr[ETHER_ADDR_LEN]; 275 struct smc_softc *sc; 276 struct ifnet *ifp; 277 278 sc = device_get_softc(dev); 279 error = 0; 280 281 sc->smc_dev = dev; 282 283 ifp = sc->smc_ifp = if_alloc(IFT_ETHER); 284 if (ifp == NULL) { 285 error = ENOSPC; 286 goto done; 287 } 288 289 mtx_init(&sc->smc_mtx, device_get_nameunit(dev), NULL, MTX_DEF); 290 291 /* Set up watchdog callout. */ 292 callout_init_mtx(&sc->smc_watchdog, &sc->smc_mtx, 0); 293 294 type = SYS_RES_IOPORT; 295 if (sc->smc_usemem) 296 type = SYS_RES_MEMORY; 297 298 sc->smc_reg_rid = 0; 299 sc->smc_reg = bus_alloc_resource(dev, type, &sc->smc_reg_rid, 0, ~0, 300 16, RF_ACTIVE); 301 if (sc->smc_reg == NULL) { 302 error = ENXIO; 303 goto done; 304 } 305 306 sc->smc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &sc->smc_irq_rid, 0, 307 ~0, 1, RF_ACTIVE | RF_SHAREABLE); 308 if (sc->smc_irq == NULL) { 309 error = ENXIO; 310 goto done; 311 } 312 313 SMC_LOCK(sc); 314 smc_reset(sc); 315 SMC_UNLOCK(sc); 316 317 smc_select_bank(sc, 3); 318 val = smc_read_2(sc, REV); 319 sc->smc_chip = (val & REV_CHIP_MASK) >> REV_CHIP_SHIFT; 320 sc->smc_rev = (val * REV_REV_MASK) >> REV_REV_SHIFT; 321 if (bootverbose) 322 device_printf(dev, "revision %x\n", sc->smc_rev); 323 324 callout_init_mtx(&sc->smc_mii_tick_ch, &sc->smc_mtx, 325 CALLOUT_RETURNUNLOCKED); 326 if (sc->smc_chip >= REV_CHIP_91110FD) { 327 (void)mii_attach(dev, &sc->smc_miibus, ifp, 328 smc_mii_ifmedia_upd, smc_mii_ifmedia_sts, BMSR_DEFCAPMASK, 329 MII_PHY_ANY, MII_OFFSET_ANY, 0); 330 if (sc->smc_miibus != NULL) { 331 sc->smc_mii_tick = smc_mii_tick; 332 sc->smc_mii_mediachg = smc_mii_mediachg; 333 sc->smc_mii_mediaioctl = smc_mii_mediaioctl; 334 } 335 } 336 337 smc_select_bank(sc, 1); 338 eaddr[0] = smc_read_1(sc, IAR0); 339 eaddr[1] = smc_read_1(sc, IAR1); 340 eaddr[2] = smc_read_1(sc, IAR2); 341 eaddr[3] = smc_read_1(sc, IAR3); 342 eaddr[4] = smc_read_1(sc, IAR4); 343 eaddr[5] = smc_read_1(sc, IAR5); 344 345 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 346 ifp->if_softc = sc; 347 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 348 ifp->if_init = smc_init; 349 ifp->if_ioctl = smc_ioctl; 350 ifp->if_start = smc_start; 351 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen); 352 IFQ_SET_READY(&ifp->if_snd); 353 354 ifp->if_capabilities = ifp->if_capenable = 0; 355 356 #ifdef DEVICE_POLLING 357 ifp->if_capabilities |= IFCAP_POLLING; 358 #endif 359 360 ether_ifattach(ifp, eaddr); 361 362 /* Set up taskqueue */ 363 TASK_INIT(&sc->smc_intr, SMC_INTR_PRIORITY, smc_task_intr, ifp); 364 TASK_INIT(&sc->smc_rx, SMC_RX_PRIORITY, smc_task_rx, ifp); 365 TASK_INIT(&sc->smc_tx, SMC_TX_PRIORITY, smc_task_tx, ifp); 366 sc->smc_tq = taskqueue_create_fast("smc_taskq", M_NOWAIT, 367 taskqueue_thread_enqueue, &sc->smc_tq); 368 taskqueue_start_threads(&sc->smc_tq, 1, PI_NET, "%s taskq", 369 device_get_nameunit(sc->smc_dev)); 370 371 /* Mask all interrupts. */ 372 sc->smc_mask = 0; 373 smc_write_1(sc, MSK, 0); 374 375 /* Wire up interrupt */ 376 error = bus_setup_intr(dev, sc->smc_irq, 377 INTR_TYPE_NET|INTR_MPSAFE, smc_intr, NULL, sc, &sc->smc_ih); 378 if (error != 0) 379 goto done; 380 381 done: 382 if (error != 0) 383 smc_detach(dev); 384 return (error); 385 } 386 387 int 388 smc_detach(device_t dev) 389 { 390 int type; 391 struct smc_softc *sc; 392 393 sc = device_get_softc(dev); 394 SMC_LOCK(sc); 395 smc_stop(sc); 396 SMC_UNLOCK(sc); 397 398 if (sc->smc_ifp != NULL) { 399 ether_ifdetach(sc->smc_ifp); 400 } 401 402 callout_drain(&sc->smc_watchdog); 403 callout_drain(&sc->smc_mii_tick_ch); 404 405 #ifdef DEVICE_POLLING 406 if (sc->smc_ifp->if_capenable & IFCAP_POLLING) 407 ether_poll_deregister(sc->smc_ifp); 408 #endif 409 410 if (sc->smc_ih != NULL) 411 bus_teardown_intr(sc->smc_dev, sc->smc_irq, sc->smc_ih); 412 413 if (sc->smc_tq != NULL) { 414 taskqueue_drain(sc->smc_tq, &sc->smc_intr); 415 taskqueue_drain(sc->smc_tq, &sc->smc_rx); 416 taskqueue_drain(sc->smc_tq, &sc->smc_tx); 417 taskqueue_free(sc->smc_tq); 418 sc->smc_tq = NULL; 419 } 420 421 if (sc->smc_ifp != NULL) { 422 if_free(sc->smc_ifp); 423 } 424 425 if (sc->smc_miibus != NULL) { 426 device_delete_child(sc->smc_dev, sc->smc_miibus); 427 bus_generic_detach(sc->smc_dev); 428 } 429 430 if (sc->smc_reg != NULL) { 431 type = SYS_RES_IOPORT; 432 if (sc->smc_usemem) 433 type = SYS_RES_MEMORY; 434 435 bus_release_resource(sc->smc_dev, type, sc->smc_reg_rid, 436 sc->smc_reg); 437 } 438 439 if (sc->smc_irq != NULL) 440 bus_release_resource(sc->smc_dev, SYS_RES_IRQ, sc->smc_irq_rid, 441 sc->smc_irq); 442 443 if (mtx_initialized(&sc->smc_mtx)) 444 mtx_destroy(&sc->smc_mtx); 445 446 return (0); 447 } 448 449 static void 450 smc_start(struct ifnet *ifp) 451 { 452 struct smc_softc *sc; 453 454 sc = ifp->if_softc; 455 SMC_LOCK(sc); 456 smc_start_locked(ifp); 457 SMC_UNLOCK(sc); 458 } 459 460 static void 461 smc_start_locked(struct ifnet *ifp) 462 { 463 struct smc_softc *sc; 464 struct mbuf *m; 465 u_int len, npages, spin_count; 466 467 sc = ifp->if_softc; 468 SMC_ASSERT_LOCKED(sc); 469 470 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 471 return; 472 if (IFQ_IS_EMPTY(&ifp->if_snd)) 473 return; 474 475 /* 476 * Grab the next packet. If it's too big, drop it. 477 */ 478 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 479 len = m_length(m, NULL); 480 len += (len & 1); 481 if (len > ETHER_MAX_LEN - ETHER_CRC_LEN) { 482 if_printf(ifp, "large packet discarded\n"); 483 ++ifp->if_oerrors; 484 m_freem(m); 485 return; /* XXX readcheck? */ 486 } 487 488 /* 489 * Flag that we're busy. 490 */ 491 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 492 sc->smc_pending = m; 493 494 /* 495 * Work out how many 256 byte "pages" we need. We have to include the 496 * control data for the packet in this calculation. 497 */ 498 npages = (len * PKT_CTRL_DATA_LEN) >> 8; 499 if (npages == 0) 500 npages = 1; 501 502 /* 503 * Request memory. 504 */ 505 smc_select_bank(sc, 2); 506 smc_mmu_wait(sc); 507 smc_write_2(sc, MMUCR, MMUCR_CMD_TX_ALLOC | npages); 508 509 /* 510 * Spin briefly to see if the allocation succeeds. 511 */ 512 spin_count = TX_ALLOC_WAIT_TIME; 513 do { 514 if (smc_read_1(sc, IST) & ALLOC_INT) { 515 smc_write_1(sc, ACK, ALLOC_INT); 516 break; 517 } 518 } while (--spin_count); 519 520 /* 521 * If the allocation is taking too long, unmask the alloc interrupt 522 * and wait. 523 */ 524 if (spin_count == 0) { 525 sc->smc_mask |= ALLOC_INT; 526 if ((ifp->if_capenable & IFCAP_POLLING) == 0) 527 smc_write_1(sc, MSK, sc->smc_mask); 528 return; 529 } 530 531 taskqueue_enqueue_fast(sc->smc_tq, &sc->smc_tx); 532 } 533 534 static void 535 smc_task_tx(void *context, int pending) 536 { 537 struct ifnet *ifp; 538 struct smc_softc *sc; 539 struct mbuf *m, *m0; 540 u_int packet, len; 541 uint8_t *data; 542 543 (void)pending; 544 ifp = (struct ifnet *)context; 545 sc = ifp->if_softc; 546 547 SMC_LOCK(sc); 548 549 if (sc->smc_pending == NULL) { 550 SMC_UNLOCK(sc); 551 goto next_packet; 552 } 553 554 m = m0 = sc->smc_pending; 555 sc->smc_pending = NULL; 556 smc_select_bank(sc, 2); 557 558 /* 559 * Check the allocation result. 560 */ 561 packet = smc_read_1(sc, ARR); 562 563 /* 564 * If the allocation failed, requeue the packet and retry. 565 */ 566 if (packet & ARR_FAILED) { 567 IFQ_DRV_PREPEND(&ifp->if_snd, m); 568 ++ifp->if_oerrors; 569 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 570 smc_start_locked(ifp); 571 SMC_UNLOCK(sc); 572 return; 573 } 574 575 /* 576 * Tell the device to write to our packet number. 577 */ 578 smc_write_1(sc, PNR, packet); 579 smc_write_2(sc, PTR, 0 | PTR_AUTO_INCR); 580 581 /* 582 * Tell the device how long the packet is (including control data). 583 */ 584 len = m_length(m, 0); 585 len += PKT_CTRL_DATA_LEN; 586 smc_write_2(sc, DATA0, 0); 587 smc_write_2(sc, DATA0, len); 588 589 /* 590 * Push the data out to the device. 591 */ 592 data = NULL; 593 for (; m != NULL; m = m->m_next) { 594 data = mtod(m, uint8_t *); 595 smc_write_multi_2(sc, DATA0, (uint16_t *)data, m->m_len / 2); 596 } 597 598 /* 599 * Push out the control byte and and the odd byte if needed. 600 */ 601 if ((len & 1) != 0 && data != NULL) 602 smc_write_2(sc, DATA0, (CTRL_ODD << 8) | data[m->m_len - 1]); 603 else 604 smc_write_2(sc, DATA0, 0); 605 606 /* 607 * Unmask the TX empty interrupt. 608 */ 609 sc->smc_mask |= TX_EMPTY_INT; 610 if ((ifp->if_capenable & IFCAP_POLLING) == 0) 611 smc_write_1(sc, MSK, sc->smc_mask); 612 613 /* 614 * Enqueue the packet. 615 */ 616 smc_mmu_wait(sc); 617 smc_write_2(sc, MMUCR, MMUCR_CMD_ENQUEUE); 618 callout_reset(&sc->smc_watchdog, hz * 2, smc_watchdog, sc); 619 620 /* 621 * Finish up. 622 */ 623 ifp->if_opackets++; 624 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 625 SMC_UNLOCK(sc); 626 BPF_MTAP(ifp, m0); 627 m_freem(m0); 628 629 next_packet: 630 /* 631 * See if there's anything else to do. 632 */ 633 smc_start(ifp); 634 } 635 636 static void 637 smc_task_rx(void *context, int pending) 638 { 639 u_int packet, status, len; 640 uint8_t *data; 641 struct ifnet *ifp; 642 struct smc_softc *sc; 643 struct mbuf *m, *mhead, *mtail; 644 645 (void)pending; 646 ifp = (struct ifnet *)context; 647 sc = ifp->if_softc; 648 mhead = mtail = NULL; 649 650 SMC_LOCK(sc); 651 652 packet = smc_read_1(sc, FIFO_RX); 653 while ((packet & FIFO_EMPTY) == 0) { 654 /* 655 * Grab an mbuf and attach a cluster. 656 */ 657 MGETHDR(m, M_DONTWAIT, MT_DATA); 658 if (m == NULL) { 659 break; 660 } 661 MCLGET(m, M_DONTWAIT); 662 if ((m->m_flags & M_EXT) == 0) { 663 m_freem(m); 664 break; 665 } 666 667 /* 668 * Point to the start of the packet. 669 */ 670 smc_select_bank(sc, 2); 671 smc_write_1(sc, PNR, packet); 672 smc_write_2(sc, PTR, 0 | PTR_READ | PTR_RCV | PTR_AUTO_INCR); 673 674 /* 675 * Grab status and packet length. 676 */ 677 status = smc_read_2(sc, DATA0); 678 len = smc_read_2(sc, DATA0) & RX_LEN_MASK; 679 len -= 6; 680 if (status & RX_ODDFRM) 681 len += 1; 682 683 /* 684 * Check for errors. 685 */ 686 if (status & (RX_TOOSHORT | RX_TOOLNG | RX_BADCRC | RX_ALGNERR)) { 687 smc_mmu_wait(sc); 688 smc_write_2(sc, MMUCR, MMUCR_CMD_RELEASE); 689 ifp->if_ierrors++; 690 m_freem(m); 691 break; 692 } 693 694 /* 695 * Set the mbuf up the way we want it. 696 */ 697 m->m_pkthdr.rcvif = ifp; 698 m->m_pkthdr.len = m->m_len = len + 2; /* XXX: Is this right? */ 699 m_adj(m, ETHER_ALIGN); 700 701 /* 702 * Pull the packet out of the device. Make sure we're in the 703 * right bank first as things may have changed while we were 704 * allocating our mbuf. 705 */ 706 smc_select_bank(sc, 2); 707 smc_write_1(sc, PNR, packet); 708 smc_write_2(sc, PTR, 4 | PTR_READ | PTR_RCV | PTR_AUTO_INCR); 709 data = mtod(m, uint8_t *); 710 smc_read_multi_2(sc, DATA0, (uint16_t *)data, len >> 1); 711 if (len & 1) { 712 data += len & ~1; 713 *data = smc_read_1(sc, DATA0); 714 } 715 716 /* 717 * Tell the device we're done. 718 */ 719 smc_mmu_wait(sc); 720 smc_write_2(sc, MMUCR, MMUCR_CMD_RELEASE); 721 if (m == NULL) { 722 break; 723 } 724 725 if (mhead == NULL) { 726 mhead = mtail = m; 727 m->m_next = NULL; 728 } else { 729 mtail->m_next = m; 730 mtail = m; 731 } 732 packet = smc_read_1(sc, FIFO_RX); 733 } 734 735 sc->smc_mask |= RCV_INT; 736 if ((ifp->if_capenable & IFCAP_POLLING) == 0) 737 smc_write_1(sc, MSK, sc->smc_mask); 738 739 SMC_UNLOCK(sc); 740 741 while (mhead != NULL) { 742 m = mhead; 743 mhead = mhead->m_next; 744 m->m_next = NULL; 745 ifp->if_ipackets++; 746 (*ifp->if_input)(ifp, m); 747 } 748 } 749 750 #ifdef DEVICE_POLLING 751 static void 752 smc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 753 { 754 struct smc_softc *sc; 755 756 sc = ifp->if_softc; 757 758 SMC_LOCK(sc); 759 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 760 SMC_UNLOCK(sc); 761 return; 762 } 763 SMC_UNLOCK(sc); 764 765 if (cmd == POLL_AND_CHECK_STATUS) 766 taskqueue_enqueue_fast(sc->smc_tq, &sc->smc_intr); 767 } 768 #endif 769 770 static int 771 smc_intr(void *context) 772 { 773 struct smc_softc *sc; 774 775 sc = (struct smc_softc *)context; 776 taskqueue_enqueue_fast(sc->smc_tq, &sc->smc_intr); 777 return (FILTER_HANDLED); 778 } 779 780 static void 781 smc_task_intr(void *context, int pending) 782 { 783 struct smc_softc *sc; 784 struct ifnet *ifp; 785 u_int status, packet, counter, tcr; 786 787 (void)pending; 788 ifp = (struct ifnet *)context; 789 sc = ifp->if_softc; 790 791 SMC_LOCK(sc); 792 793 smc_select_bank(sc, 2); 794 795 /* 796 * Get the current mask, and then block all interrupts while we're 797 * working. 798 */ 799 if ((ifp->if_capenable & IFCAP_POLLING) == 0) 800 smc_write_1(sc, MSK, 0); 801 802 /* 803 * Find out what interrupts are flagged. 804 */ 805 status = smc_read_1(sc, IST) & sc->smc_mask; 806 807 /* 808 * Transmit error 809 */ 810 if (status & TX_INT) { 811 /* 812 * Kill off the packet if there is one and re-enable transmit. 813 */ 814 packet = smc_read_1(sc, FIFO_TX); 815 if ((packet & FIFO_EMPTY) == 0) { 816 smc_write_1(sc, PNR, packet); 817 smc_write_2(sc, PTR, 0 | PTR_READ | 818 PTR_AUTO_INCR); 819 tcr = smc_read_2(sc, DATA0); 820 if ((tcr & EPHSR_TX_SUC) == 0) 821 device_printf(sc->smc_dev, 822 "bad packet\n"); 823 smc_mmu_wait(sc); 824 smc_write_2(sc, MMUCR, MMUCR_CMD_RELEASE_PKT); 825 826 smc_select_bank(sc, 0); 827 tcr = smc_read_2(sc, TCR); 828 tcr |= TCR_TXENA | TCR_PAD_EN; 829 smc_write_2(sc, TCR, tcr); 830 smc_select_bank(sc, 2); 831 taskqueue_enqueue_fast(sc->smc_tq, &sc->smc_tx); 832 } 833 834 /* 835 * Ack the interrupt. 836 */ 837 smc_write_1(sc, ACK, TX_INT); 838 } 839 840 /* 841 * Receive 842 */ 843 if (status & RCV_INT) { 844 smc_write_1(sc, ACK, RCV_INT); 845 sc->smc_mask &= ~RCV_INT; 846 taskqueue_enqueue_fast(sc->smc_tq, &sc->smc_rx); 847 } 848 849 /* 850 * Allocation 851 */ 852 if (status & ALLOC_INT) { 853 smc_write_1(sc, ACK, ALLOC_INT); 854 sc->smc_mask &= ~ALLOC_INT; 855 taskqueue_enqueue_fast(sc->smc_tq, &sc->smc_tx); 856 } 857 858 /* 859 * Receive overrun 860 */ 861 if (status & RX_OVRN_INT) { 862 smc_write_1(sc, ACK, RX_OVRN_INT); 863 ifp->if_ierrors++; 864 } 865 866 /* 867 * Transmit empty 868 */ 869 if (status & TX_EMPTY_INT) { 870 smc_write_1(sc, ACK, TX_EMPTY_INT); 871 sc->smc_mask &= ~TX_EMPTY_INT; 872 callout_stop(&sc->smc_watchdog); 873 874 /* 875 * Update collision stats. 876 */ 877 smc_select_bank(sc, 0); 878 counter = smc_read_2(sc, ECR); 879 smc_select_bank(sc, 2); 880 ifp->if_collisions += 881 (counter & ECR_SNGLCOL_MASK) >> ECR_SNGLCOL_SHIFT; 882 ifp->if_collisions += 883 (counter & ECR_MULCOL_MASK) >> ECR_MULCOL_SHIFT; 884 885 /* 886 * See if there are any packets to transmit. 887 */ 888 taskqueue_enqueue_fast(sc->smc_tq, &sc->smc_tx); 889 } 890 891 /* 892 * Update the interrupt mask. 893 */ 894 if ((ifp->if_capenable & IFCAP_POLLING) == 0) 895 smc_write_1(sc, MSK, sc->smc_mask); 896 897 SMC_UNLOCK(sc); 898 } 899 900 static u_int 901 smc_mii_readbits(struct smc_softc *sc, int nbits) 902 { 903 u_int mgmt, mask, val; 904 905 SMC_ASSERT_LOCKED(sc); 906 KASSERT((smc_read_2(sc, BSR) & BSR_BANK_MASK) == 3, 907 ("%s: smc_mii_readbits called with bank %d (!= 3)", 908 device_get_nameunit(sc->smc_dev), 909 smc_read_2(sc, BSR) & BSR_BANK_MASK)); 910 911 /* 912 * Set up the MGMT (aka MII) register. 913 */ 914 mgmt = smc_read_2(sc, MGMT) & ~(MGMT_MCLK | MGMT_MDOE | MGMT_MDO); 915 smc_write_2(sc, MGMT, mgmt); 916 917 /* 918 * Read the bits in. 919 */ 920 for (mask = 1 << (nbits - 1), val = 0; mask; mask >>= 1) { 921 if (smc_read_2(sc, MGMT) & MGMT_MDI) 922 val |= mask; 923 924 smc_write_2(sc, MGMT, mgmt); 925 DELAY(1); 926 smc_write_2(sc, MGMT, mgmt | MGMT_MCLK); 927 DELAY(1); 928 } 929 930 return (val); 931 } 932 933 static void 934 smc_mii_writebits(struct smc_softc *sc, u_int val, int nbits) 935 { 936 u_int mgmt, mask; 937 938 SMC_ASSERT_LOCKED(sc); 939 KASSERT((smc_read_2(sc, BSR) & BSR_BANK_MASK) == 3, 940 ("%s: smc_mii_writebits called with bank %d (!= 3)", 941 device_get_nameunit(sc->smc_dev), 942 smc_read_2(sc, BSR) & BSR_BANK_MASK)); 943 944 /* 945 * Set up the MGMT (aka MII) register). 946 */ 947 mgmt = smc_read_2(sc, MGMT) & ~(MGMT_MCLK | MGMT_MDOE | MGMT_MDO); 948 mgmt |= MGMT_MDOE; 949 950 /* 951 * Push the bits out. 952 */ 953 for (mask = 1 << (nbits - 1); mask; mask >>= 1) { 954 if (val & mask) 955 mgmt |= MGMT_MDO; 956 else 957 mgmt &= ~MGMT_MDO; 958 959 smc_write_2(sc, MGMT, mgmt); 960 DELAY(1); 961 smc_write_2(sc, MGMT, mgmt | MGMT_MCLK); 962 DELAY(1); 963 } 964 } 965 966 int 967 smc_miibus_readreg(device_t dev, int phy, int reg) 968 { 969 struct smc_softc *sc; 970 int val; 971 972 sc = device_get_softc(dev); 973 974 SMC_LOCK(sc); 975 976 smc_select_bank(sc, 3); 977 978 /* 979 * Send out the idle pattern. 980 */ 981 smc_mii_writebits(sc, 0xffffffff, 32); 982 983 /* 984 * Start code + read opcode + phy address + phy register 985 */ 986 smc_mii_writebits(sc, 6 << 10 | phy << 5 | reg, 14); 987 988 /* 989 * Turnaround + data 990 */ 991 val = smc_mii_readbits(sc, 18); 992 993 /* 994 * Reset the MDIO interface. 995 */ 996 smc_write_2(sc, MGMT, 997 smc_read_2(sc, MGMT) & ~(MGMT_MCLK | MGMT_MDOE | MGMT_MDO)); 998 999 SMC_UNLOCK(sc); 1000 return (val); 1001 } 1002 1003 int 1004 smc_miibus_writereg(device_t dev, int phy, int reg, int data) 1005 { 1006 struct smc_softc *sc; 1007 1008 sc = device_get_softc(dev); 1009 1010 SMC_LOCK(sc); 1011 1012 smc_select_bank(sc, 3); 1013 1014 /* 1015 * Send idle pattern. 1016 */ 1017 smc_mii_writebits(sc, 0xffffffff, 32); 1018 1019 /* 1020 * Start code + write opcode + phy address + phy register + turnaround 1021 * + data. 1022 */ 1023 smc_mii_writebits(sc, 5 << 28 | phy << 23 | reg << 18 | 2 << 16 | data, 1024 32); 1025 1026 /* 1027 * Reset MDIO interface. 1028 */ 1029 smc_write_2(sc, MGMT, 1030 smc_read_2(sc, MGMT) & ~(MGMT_MCLK | MGMT_MDOE | MGMT_MDO)); 1031 1032 SMC_UNLOCK(sc); 1033 return (0); 1034 } 1035 1036 void 1037 smc_miibus_statchg(device_t dev) 1038 { 1039 struct smc_softc *sc; 1040 struct mii_data *mii; 1041 uint16_t tcr; 1042 1043 sc = device_get_softc(dev); 1044 mii = device_get_softc(sc->smc_miibus); 1045 1046 SMC_LOCK(sc); 1047 1048 smc_select_bank(sc, 0); 1049 tcr = smc_read_2(sc, TCR); 1050 1051 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 1052 tcr |= TCR_SWFDUP; 1053 else 1054 tcr &= ~TCR_SWFDUP; 1055 1056 smc_write_2(sc, TCR, tcr); 1057 1058 SMC_UNLOCK(sc); 1059 } 1060 1061 static int 1062 smc_mii_ifmedia_upd(struct ifnet *ifp) 1063 { 1064 struct smc_softc *sc; 1065 struct mii_data *mii; 1066 1067 sc = ifp->if_softc; 1068 if (sc->smc_miibus == NULL) 1069 return (ENXIO); 1070 1071 mii = device_get_softc(sc->smc_miibus); 1072 return (mii_mediachg(mii)); 1073 } 1074 1075 static void 1076 smc_mii_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1077 { 1078 struct smc_softc *sc; 1079 struct mii_data *mii; 1080 1081 sc = ifp->if_softc; 1082 if (sc->smc_miibus == NULL) 1083 return; 1084 1085 mii = device_get_softc(sc->smc_miibus); 1086 mii_pollstat(mii); 1087 ifmr->ifm_active = mii->mii_media_active; 1088 ifmr->ifm_status = mii->mii_media_status; 1089 } 1090 1091 static void 1092 smc_mii_tick(void *context) 1093 { 1094 struct smc_softc *sc; 1095 1096 sc = (struct smc_softc *)context; 1097 1098 if (sc->smc_miibus == NULL) 1099 return; 1100 1101 SMC_UNLOCK(sc); 1102 1103 mii_tick(device_get_softc(sc->smc_miibus)); 1104 callout_reset(&sc->smc_mii_tick_ch, hz, smc_mii_tick, sc); 1105 } 1106 1107 static void 1108 smc_mii_mediachg(struct smc_softc *sc) 1109 { 1110 1111 if (sc->smc_miibus == NULL) 1112 return; 1113 mii_mediachg(device_get_softc(sc->smc_miibus)); 1114 } 1115 1116 static int 1117 smc_mii_mediaioctl(struct smc_softc *sc, struct ifreq *ifr, u_long command) 1118 { 1119 struct mii_data *mii; 1120 1121 if (sc->smc_miibus == NULL) 1122 return (EINVAL); 1123 1124 mii = device_get_softc(sc->smc_miibus); 1125 return (ifmedia_ioctl(sc->smc_ifp, ifr, &mii->mii_media, command)); 1126 } 1127 1128 static void 1129 smc_reset(struct smc_softc *sc) 1130 { 1131 u_int ctr; 1132 1133 SMC_ASSERT_LOCKED(sc); 1134 1135 smc_select_bank(sc, 2); 1136 1137 /* 1138 * Mask all interrupts. 1139 */ 1140 smc_write_1(sc, MSK, 0); 1141 1142 /* 1143 * Tell the device to reset. 1144 */ 1145 smc_select_bank(sc, 0); 1146 smc_write_2(sc, RCR, RCR_SOFT_RST); 1147 1148 /* 1149 * Set up the configuration register. 1150 */ 1151 smc_select_bank(sc, 1); 1152 smc_write_2(sc, CR, CR_EPH_POWER_EN); 1153 DELAY(1); 1154 1155 /* 1156 * Turn off transmit and receive. 1157 */ 1158 smc_select_bank(sc, 0); 1159 smc_write_2(sc, TCR, 0); 1160 smc_write_2(sc, RCR, 0); 1161 1162 /* 1163 * Set up the control register. 1164 */ 1165 smc_select_bank(sc, 1); 1166 ctr = smc_read_2(sc, CTR); 1167 ctr |= CTR_LE_ENABLE | CTR_AUTO_RELEASE; 1168 smc_write_2(sc, CTR, ctr); 1169 1170 /* 1171 * Reset the MMU. 1172 */ 1173 smc_select_bank(sc, 2); 1174 smc_mmu_wait(sc); 1175 smc_write_2(sc, MMUCR, MMUCR_CMD_MMU_RESET); 1176 } 1177 1178 static void 1179 smc_enable(struct smc_softc *sc) 1180 { 1181 struct ifnet *ifp; 1182 1183 SMC_ASSERT_LOCKED(sc); 1184 ifp = sc->smc_ifp; 1185 1186 /* 1187 * Set up the receive/PHY control register. 1188 */ 1189 smc_select_bank(sc, 0); 1190 smc_write_2(sc, RPCR, RPCR_ANEG | (RPCR_LED_LINK_ANY << RPCR_LSA_SHIFT) 1191 | (RPCR_LED_ACT_ANY << RPCR_LSB_SHIFT)); 1192 1193 /* 1194 * Set up the transmit and receive control registers. 1195 */ 1196 smc_write_2(sc, TCR, TCR_TXENA | TCR_PAD_EN); 1197 smc_write_2(sc, RCR, RCR_RXEN | RCR_STRIP_CRC); 1198 1199 /* 1200 * Set up the interrupt mask. 1201 */ 1202 smc_select_bank(sc, 2); 1203 sc->smc_mask = EPH_INT | RX_OVRN_INT | RCV_INT | TX_INT; 1204 if ((ifp->if_capenable & IFCAP_POLLING) != 0) 1205 smc_write_1(sc, MSK, sc->smc_mask); 1206 } 1207 1208 static void 1209 smc_stop(struct smc_softc *sc) 1210 { 1211 1212 SMC_ASSERT_LOCKED(sc); 1213 1214 /* 1215 * Turn off callouts. 1216 */ 1217 callout_stop(&sc->smc_watchdog); 1218 callout_stop(&sc->smc_mii_tick_ch); 1219 1220 /* 1221 * Mask all interrupts. 1222 */ 1223 smc_select_bank(sc, 2); 1224 sc->smc_mask = 0; 1225 smc_write_1(sc, MSK, 0); 1226 #ifdef DEVICE_POLLING 1227 ether_poll_deregister(sc->smc_ifp); 1228 sc->smc_ifp->if_capenable &= ~IFCAP_POLLING; 1229 sc->smc_ifp->if_capenable &= ~IFCAP_POLLING_NOCOUNT; 1230 #endif 1231 1232 /* 1233 * Disable transmit and receive. 1234 */ 1235 smc_select_bank(sc, 0); 1236 smc_write_2(sc, TCR, 0); 1237 smc_write_2(sc, RCR, 0); 1238 1239 sc->smc_ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1240 } 1241 1242 static void 1243 smc_watchdog(void *arg) 1244 { 1245 struct smc_softc *sc; 1246 1247 sc = (struct smc_softc *)arg; 1248 device_printf(sc->smc_dev, "watchdog timeout\n"); 1249 taskqueue_enqueue_fast(sc->smc_tq, &sc->smc_intr); 1250 } 1251 1252 static void 1253 smc_init(void *context) 1254 { 1255 struct smc_softc *sc; 1256 1257 sc = (struct smc_softc *)context; 1258 SMC_LOCK(sc); 1259 smc_init_locked(sc); 1260 SMC_UNLOCK(sc); 1261 } 1262 1263 static void 1264 smc_init_locked(struct smc_softc *sc) 1265 { 1266 struct ifnet *ifp; 1267 1268 ifp = sc->smc_ifp; 1269 1270 SMC_ASSERT_LOCKED(sc); 1271 1272 smc_reset(sc); 1273 smc_enable(sc); 1274 1275 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1276 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1277 1278 smc_start_locked(ifp); 1279 1280 if (sc->smc_mii_tick != NULL) 1281 callout_reset(&sc->smc_mii_tick_ch, hz, sc->smc_mii_tick, sc); 1282 1283 #ifdef DEVICE_POLLING 1284 SMC_UNLOCK(sc); 1285 ether_poll_register(smc_poll, ifp); 1286 SMC_LOCK(sc); 1287 ifp->if_capenable |= IFCAP_POLLING; 1288 ifp->if_capenable |= IFCAP_POLLING_NOCOUNT; 1289 #endif 1290 } 1291 1292 static int 1293 smc_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1294 { 1295 struct smc_softc *sc; 1296 int error; 1297 1298 sc = ifp->if_softc; 1299 error = 0; 1300 1301 switch (cmd) { 1302 case SIOCSIFFLAGS: 1303 if ((ifp->if_flags & IFF_UP) == 0 && 1304 (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1305 SMC_LOCK(sc); 1306 smc_stop(sc); 1307 SMC_UNLOCK(sc); 1308 } else { 1309 smc_init(sc); 1310 if (sc->smc_mii_mediachg != NULL) 1311 sc->smc_mii_mediachg(sc); 1312 } 1313 break; 1314 1315 case SIOCADDMULTI: 1316 case SIOCDELMULTI: 1317 /* XXX 1318 SMC_LOCK(sc); 1319 smc_setmcast(sc); 1320 SMC_UNLOCK(sc); 1321 */ 1322 error = EINVAL; 1323 break; 1324 1325 case SIOCGIFMEDIA: 1326 case SIOCSIFMEDIA: 1327 if (sc->smc_mii_mediaioctl == NULL) { 1328 error = EINVAL; 1329 break; 1330 } 1331 sc->smc_mii_mediaioctl(sc, (struct ifreq *)data, cmd); 1332 break; 1333 1334 default: 1335 error = ether_ioctl(ifp, cmd, data); 1336 break; 1337 } 1338 1339 return (error); 1340 } 1341