1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2000 Orion Hodson <O.Hodson@cs.ucl.ac.uk> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * The order of pokes in the initiation sequence is based on Linux 31 * driver by Thomas Sailer, gw boynton (wesb@crystal.cirrus.com), tom 32 * woller (twoller@crystal.cirrus.com). Shingo Watanabe (nabe@nabechan.org) 33 * contributed towards power management. 34 */ 35 36 #ifdef HAVE_KERNEL_OPTION_HEADERS 37 #include "opt_snd.h" 38 #endif 39 40 #include <dev/sound/pcm/sound.h> 41 #include <dev/sound/pcm/ac97.h> 42 43 #include <dev/pci/pcireg.h> 44 #include <dev/pci/pcivar.h> 45 46 #include <dev/sound/pci/cs4281.h> 47 48 SND_DECLARE_FILE("$FreeBSD$"); 49 50 #define CS4281_DEFAULT_BUFSZ 16384 51 52 /* Max fifo size for full duplex is 64 */ 53 #define CS4281_FIFO_SIZE 15 54 55 /* DMA Engine Indices */ 56 #define CS4281_DMA_PLAY 0 57 #define CS4281_DMA_REC 1 58 59 /* Misc */ 60 61 #define inline __inline 62 63 #ifndef DEB 64 #define DEB(x) /* x */ 65 #endif /* DEB */ 66 67 /* ------------------------------------------------------------------------- */ 68 /* Structures */ 69 70 struct sc_info; 71 72 /* channel registers */ 73 struct sc_chinfo { 74 struct sc_info *parent; 75 76 struct snd_dbuf *buffer; 77 struct pcm_channel *channel; 78 79 u_int32_t spd, fmt, bps, blksz; 80 81 int dma_setup, dma_active, dma_chan; 82 }; 83 84 /* device private data */ 85 struct sc_info { 86 device_t dev; 87 u_int32_t type; 88 89 bus_space_tag_t st; 90 bus_space_handle_t sh; 91 bus_dma_tag_t parent_dmat; 92 93 struct resource *reg, *irq, *mem; 94 int regtype, regid, irqid, memid; 95 void *ih; 96 97 int power; 98 unsigned long bufsz; 99 struct sc_chinfo pch; 100 struct sc_chinfo rch; 101 }; 102 103 /* -------------------------------------------------------------------- */ 104 /* prototypes */ 105 106 /* ADC/DAC control */ 107 static u_int32_t adcdac_go(struct sc_chinfo *ch, u_int32_t go); 108 static void adcdac_prog(struct sc_chinfo *ch); 109 110 /* power management and interrupt control */ 111 static void cs4281_intr(void *); 112 static int cs4281_power(struct sc_info *, int); 113 static int cs4281_init(struct sc_info *); 114 115 /* talk to the card */ 116 static u_int32_t cs4281_rd(struct sc_info *, int); 117 static void cs4281_wr(struct sc_info *, int, u_int32_t); 118 119 /* misc */ 120 static u_int8_t cs4281_rate_to_rv(u_int32_t); 121 static u_int32_t cs4281_format_to_dmr(u_int32_t); 122 static u_int32_t cs4281_format_to_bps(u_int32_t); 123 124 /* -------------------------------------------------------------------- */ 125 /* formats (do not add formats without editing cs_fmt_tab) */ 126 127 static u_int32_t cs4281_fmts[] = { 128 SND_FORMAT(AFMT_U8, 1, 0), 129 SND_FORMAT(AFMT_U8, 2, 0), 130 SND_FORMAT(AFMT_S8, 1, 0), 131 SND_FORMAT(AFMT_S8, 2, 0), 132 SND_FORMAT(AFMT_S16_LE, 1, 0), 133 SND_FORMAT(AFMT_S16_LE, 2, 0), 134 SND_FORMAT(AFMT_U16_LE, 1, 0), 135 SND_FORMAT(AFMT_U16_LE, 2, 0), 136 SND_FORMAT(AFMT_S16_BE, 1, 0), 137 SND_FORMAT(AFMT_S16_BE, 2, 0), 138 SND_FORMAT(AFMT_U16_BE, 1, 0), 139 SND_FORMAT(AFMT_U16_BE, 2, 0), 140 0 141 }; 142 143 static struct pcmchan_caps cs4281_caps = {6024, 48000, cs4281_fmts, 0}; 144 145 /* -------------------------------------------------------------------- */ 146 /* Hardware */ 147 148 static inline u_int32_t 149 cs4281_rd(struct sc_info *sc, int regno) 150 { 151 return bus_space_read_4(sc->st, sc->sh, regno); 152 } 153 154 static inline void 155 cs4281_wr(struct sc_info *sc, int regno, u_int32_t data) 156 { 157 bus_space_write_4(sc->st, sc->sh, regno, data); 158 DELAY(100); 159 } 160 161 static inline void 162 cs4281_clr4(struct sc_info *sc, int regno, u_int32_t mask) 163 { 164 u_int32_t r; 165 r = cs4281_rd(sc, regno); 166 cs4281_wr(sc, regno, r & ~mask); 167 } 168 169 static inline void 170 cs4281_set4(struct sc_info *sc, int regno, u_int32_t mask) 171 { 172 u_int32_t v; 173 v = cs4281_rd(sc, regno); 174 cs4281_wr(sc, regno, v | mask); 175 } 176 177 static int 178 cs4281_waitset(struct sc_info *sc, int regno, u_int32_t mask, int tries) 179 { 180 u_int32_t v; 181 182 while (tries > 0) { 183 DELAY(100); 184 v = cs4281_rd(sc, regno); 185 if ((v & mask) == mask) break; 186 tries --; 187 } 188 return tries; 189 } 190 191 static int 192 cs4281_waitclr(struct sc_info *sc, int regno, u_int32_t mask, int tries) 193 { 194 u_int32_t v; 195 196 while (tries > 0) { 197 DELAY(100); 198 v = ~ cs4281_rd(sc, regno); 199 if (v & mask) break; 200 tries --; 201 } 202 return tries; 203 } 204 205 /* ------------------------------------------------------------------------- */ 206 /* Register value mapping functions */ 207 208 static u_int32_t cs4281_rates[] = {48000, 44100, 22050, 16000, 11025, 8000}; 209 #define CS4281_NUM_RATES sizeof(cs4281_rates)/sizeof(cs4281_rates[0]) 210 211 static u_int8_t 212 cs4281_rate_to_rv(u_int32_t rate) 213 { 214 u_int32_t v; 215 216 for (v = 0; v < CS4281_NUM_RATES; v++) { 217 if (rate == cs4281_rates[v]) return v; 218 } 219 220 v = 1536000 / rate; 221 if (v > 255 || v < 32) v = 5; /* default to 8k */ 222 return v; 223 } 224 225 static u_int32_t 226 cs4281_rv_to_rate(u_int8_t rv) 227 { 228 u_int32_t r; 229 230 if (rv < CS4281_NUM_RATES) return cs4281_rates[rv]; 231 r = 1536000 / rv; 232 return r; 233 } 234 235 static inline u_int32_t 236 cs4281_format_to_dmr(u_int32_t format) 237 { 238 u_int32_t dmr = 0; 239 if (AFMT_8BIT & format) dmr |= CS4281PCI_DMR_SIZE8; 240 if (AFMT_CHANNEL(format) < 2) dmr |= CS4281PCI_DMR_MONO; 241 if (AFMT_BIGENDIAN & format) dmr |= CS4281PCI_DMR_BEND; 242 if (!(AFMT_SIGNED & format)) dmr |= CS4281PCI_DMR_USIGN; 243 return dmr; 244 } 245 246 static inline u_int32_t 247 cs4281_format_to_bps(u_int32_t format) 248 { 249 return ((AFMT_8BIT & format) ? 1 : 2) * 250 ((AFMT_CHANNEL(format) > 1) ? 2 : 1); 251 } 252 253 /* -------------------------------------------------------------------- */ 254 /* ac97 codec */ 255 256 static int 257 cs4281_rdcd(kobj_t obj, void *devinfo, int regno) 258 { 259 struct sc_info *sc = (struct sc_info *)devinfo; 260 int codecno; 261 262 codecno = regno >> 8; 263 regno &= 0xff; 264 265 /* Remove old state */ 266 cs4281_rd(sc, CS4281PCI_ACSDA); 267 268 /* Fill in AC97 register value request form */ 269 cs4281_wr(sc, CS4281PCI_ACCAD, regno); 270 cs4281_wr(sc, CS4281PCI_ACCDA, 0); 271 cs4281_wr(sc, CS4281PCI_ACCTL, CS4281PCI_ACCTL_ESYN | 272 CS4281PCI_ACCTL_VFRM | CS4281PCI_ACCTL_DCV | 273 CS4281PCI_ACCTL_CRW); 274 275 /* Wait for read to complete */ 276 if (cs4281_waitclr(sc, CS4281PCI_ACCTL, CS4281PCI_ACCTL_DCV, 250) == 0) { 277 device_printf(sc->dev, "cs4281_rdcd: DCV did not go\n"); 278 return -1; 279 } 280 281 /* Wait for valid status */ 282 if (cs4281_waitset(sc, CS4281PCI_ACSTS, CS4281PCI_ACSTS_VSTS, 250) == 0) { 283 device_printf(sc->dev,"cs4281_rdcd: VSTS did not come\n"); 284 return -1; 285 } 286 287 return cs4281_rd(sc, CS4281PCI_ACSDA); 288 } 289 290 static int 291 cs4281_wrcd(kobj_t obj, void *devinfo, int regno, u_int32_t data) 292 { 293 struct sc_info *sc = (struct sc_info *)devinfo; 294 int codecno; 295 296 codecno = regno >> 8; 297 regno &= 0xff; 298 299 cs4281_wr(sc, CS4281PCI_ACCAD, regno); 300 cs4281_wr(sc, CS4281PCI_ACCDA, data); 301 cs4281_wr(sc, CS4281PCI_ACCTL, CS4281PCI_ACCTL_ESYN | 302 CS4281PCI_ACCTL_VFRM | CS4281PCI_ACCTL_DCV); 303 304 if (cs4281_waitclr(sc, CS4281PCI_ACCTL, CS4281PCI_ACCTL_DCV, 250) == 0) { 305 device_printf(sc->dev,"cs4281_wrcd: DCV did not go\n"); 306 } 307 308 return 0; 309 } 310 311 static kobj_method_t cs4281_ac97_methods[] = { 312 KOBJMETHOD(ac97_read, cs4281_rdcd), 313 KOBJMETHOD(ac97_write, cs4281_wrcd), 314 KOBJMETHOD_END 315 }; 316 AC97_DECLARE(cs4281_ac97); 317 318 /* ------------------------------------------------------------------------- */ 319 /* shared rec/play channel interface */ 320 321 static void * 322 cs4281chan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir) 323 { 324 struct sc_info *sc = devinfo; 325 struct sc_chinfo *ch = (dir == PCMDIR_PLAY) ? &sc->pch : &sc->rch; 326 327 ch->buffer = b; 328 if (sndbuf_alloc(ch->buffer, sc->parent_dmat, 0, sc->bufsz) != 0) { 329 return NULL; 330 } 331 ch->parent = sc; 332 ch->channel = c; 333 334 ch->fmt = SND_FORMAT(AFMT_U8, 1, 0); 335 ch->spd = DSP_DEFAULT_SPEED; 336 ch->bps = 1; 337 ch->blksz = sndbuf_getsize(ch->buffer); 338 339 ch->dma_chan = (dir == PCMDIR_PLAY) ? CS4281_DMA_PLAY : CS4281_DMA_REC; 340 ch->dma_setup = 0; 341 342 adcdac_go(ch, 0); 343 adcdac_prog(ch); 344 345 return ch; 346 } 347 348 static u_int32_t 349 cs4281chan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize) 350 { 351 struct sc_chinfo *ch = data; 352 struct sc_info *sc = ch->parent; 353 u_int32_t go; 354 355 go = adcdac_go(ch, 0); 356 357 /* 2 interrupts are possible and used in buffer (half-empty,empty), 358 * hence factor of 2. */ 359 ch->blksz = MIN(blocksize, sc->bufsz / 2); 360 sndbuf_resize(ch->buffer, 2, ch->blksz); 361 ch->dma_setup = 0; 362 adcdac_prog(ch); 363 adcdac_go(ch, go); 364 365 DEB(printf("cs4281chan_setblocksize: blksz %d Setting %d\n", blocksize, ch->blksz)); 366 367 return ch->blksz; 368 } 369 370 static u_int32_t 371 cs4281chan_setspeed(kobj_t obj, void *data, u_int32_t speed) 372 { 373 struct sc_chinfo *ch = data; 374 struct sc_info *sc = ch->parent; 375 u_int32_t go, v, r; 376 377 go = adcdac_go(ch, 0); /* pause */ 378 r = (ch->dma_chan == CS4281_DMA_PLAY) ? CS4281PCI_DACSR : CS4281PCI_ADCSR; 379 v = cs4281_rate_to_rv(speed); 380 cs4281_wr(sc, r, v); 381 adcdac_go(ch, go); /* unpause */ 382 383 ch->spd = cs4281_rv_to_rate(v); 384 return ch->spd; 385 } 386 387 static int 388 cs4281chan_setformat(kobj_t obj, void *data, u_int32_t format) 389 { 390 struct sc_chinfo *ch = data; 391 struct sc_info *sc = ch->parent; 392 u_int32_t v, go; 393 394 go = adcdac_go(ch, 0); /* pause */ 395 396 if (ch->dma_chan == CS4281_DMA_PLAY) 397 v = CS4281PCI_DMR_TR_PLAY; 398 else 399 v = CS4281PCI_DMR_TR_REC; 400 v |= CS4281PCI_DMR_DMA | CS4281PCI_DMR_AUTO; 401 v |= cs4281_format_to_dmr(format); 402 cs4281_wr(sc, CS4281PCI_DMR(ch->dma_chan), v); 403 404 adcdac_go(ch, go); /* unpause */ 405 406 ch->fmt = format; 407 ch->bps = cs4281_format_to_bps(format); 408 ch->dma_setup = 0; 409 410 return 0; 411 } 412 413 static u_int32_t 414 cs4281chan_getptr(kobj_t obj, void *data) 415 { 416 struct sc_chinfo *ch = data; 417 struct sc_info *sc = ch->parent; 418 u_int32_t dba, dca, ptr; 419 int sz; 420 421 sz = sndbuf_getsize(ch->buffer); 422 dba = cs4281_rd(sc, CS4281PCI_DBA(ch->dma_chan)); 423 dca = cs4281_rd(sc, CS4281PCI_DCA(ch->dma_chan)); 424 ptr = (dca - dba + sz) % sz; 425 426 return ptr; 427 } 428 429 static int 430 cs4281chan_trigger(kobj_t obj, void *data, int go) 431 { 432 struct sc_chinfo *ch = data; 433 434 switch(go) { 435 case PCMTRIG_START: 436 adcdac_prog(ch); 437 adcdac_go(ch, 1); 438 break; 439 case PCMTRIG_STOP: 440 case PCMTRIG_ABORT: 441 adcdac_go(ch, 0); 442 break; 443 default: 444 break; 445 } 446 447 /* return 0 if ok */ 448 return 0; 449 } 450 451 static struct pcmchan_caps * 452 cs4281chan_getcaps(kobj_t obj, void *data) 453 { 454 return &cs4281_caps; 455 } 456 457 static kobj_method_t cs4281chan_methods[] = { 458 KOBJMETHOD(channel_init, cs4281chan_init), 459 KOBJMETHOD(channel_setformat, cs4281chan_setformat), 460 KOBJMETHOD(channel_setspeed, cs4281chan_setspeed), 461 KOBJMETHOD(channel_setblocksize, cs4281chan_setblocksize), 462 KOBJMETHOD(channel_trigger, cs4281chan_trigger), 463 KOBJMETHOD(channel_getptr, cs4281chan_getptr), 464 KOBJMETHOD(channel_getcaps, cs4281chan_getcaps), 465 KOBJMETHOD_END 466 }; 467 CHANNEL_DECLARE(cs4281chan); 468 469 /* -------------------------------------------------------------------- */ 470 /* ADC/DAC control */ 471 472 /* adcdac_go enables/disable DMA channel, returns non-zero if DMA was 473 * active before call */ 474 475 static u_int32_t 476 adcdac_go(struct sc_chinfo *ch, u_int32_t go) 477 { 478 struct sc_info *sc = ch->parent; 479 u_int32_t going; 480 481 going = !(cs4281_rd(sc, CS4281PCI_DCR(ch->dma_chan)) & CS4281PCI_DCR_MSK); 482 483 if (go) 484 cs4281_clr4(sc, CS4281PCI_DCR(ch->dma_chan), CS4281PCI_DCR_MSK); 485 else 486 cs4281_set4(sc, CS4281PCI_DCR(ch->dma_chan), CS4281PCI_DCR_MSK); 487 488 cs4281_wr(sc, CS4281PCI_HICR, CS4281PCI_HICR_EOI); 489 490 return going; 491 } 492 493 static void 494 adcdac_prog(struct sc_chinfo *ch) 495 { 496 struct sc_info *sc = ch->parent; 497 u_int32_t go; 498 499 if (!ch->dma_setup) { 500 go = adcdac_go(ch, 0); 501 cs4281_wr(sc, CS4281PCI_DBA(ch->dma_chan), 502 sndbuf_getbufaddr(ch->buffer)); 503 cs4281_wr(sc, CS4281PCI_DBC(ch->dma_chan), 504 sndbuf_getsize(ch->buffer) / ch->bps - 1); 505 ch->dma_setup = 1; 506 adcdac_go(ch, go); 507 } 508 } 509 510 /* -------------------------------------------------------------------- */ 511 /* The interrupt handler */ 512 513 static void 514 cs4281_intr(void *p) 515 { 516 struct sc_info *sc = (struct sc_info *)p; 517 u_int32_t hisr; 518 519 hisr = cs4281_rd(sc, CS4281PCI_HISR); 520 521 if (hisr == 0) return; 522 523 if (hisr & CS4281PCI_HISR_DMA(CS4281_DMA_PLAY)) { 524 chn_intr(sc->pch.channel); 525 cs4281_rd(sc, CS4281PCI_HDSR(CS4281_DMA_PLAY)); /* Clear interrupt */ 526 } 527 528 if (hisr & CS4281PCI_HISR_DMA(CS4281_DMA_REC)) { 529 chn_intr(sc->rch.channel); 530 cs4281_rd(sc, CS4281PCI_HDSR(CS4281_DMA_REC)); /* Clear interrupt */ 531 } 532 533 /* Signal End-of-Interrupt */ 534 cs4281_wr(sc, CS4281PCI_HICR, CS4281PCI_HICR_EOI); 535 } 536 537 /* -------------------------------------------------------------------- */ 538 /* power management related */ 539 540 static int 541 cs4281_power(struct sc_info *sc, int state) 542 { 543 544 switch (state) { 545 case 0: 546 /* Permit r/w access to all BA0 registers */ 547 cs4281_wr(sc, CS4281PCI_CWPR, CS4281PCI_CWPR_MAGIC); 548 /* Power on */ 549 cs4281_clr4(sc, CS4281PCI_EPPMC, CS4281PCI_EPPMC_FPDN); 550 break; 551 case 3: 552 /* Power off card and codec */ 553 cs4281_set4(sc, CS4281PCI_EPPMC, CS4281PCI_EPPMC_FPDN); 554 cs4281_clr4(sc, CS4281PCI_SPMC, CS4281PCI_SPMC_RSTN); 555 break; 556 } 557 558 DEB(printf("cs4281_power %d -> %d\n", sc->power, state)); 559 sc->power = state; 560 561 return 0; 562 } 563 564 static int 565 cs4281_init(struct sc_info *sc) 566 { 567 u_int32_t i, v; 568 569 /* (0) Blast clock register and serial port */ 570 cs4281_wr(sc, CS4281PCI_CLKCR1, 0); 571 cs4281_wr(sc, CS4281PCI_SERMC, 0); 572 573 /* (1) Make ESYN 0 to turn sync pulse on AC97 link */ 574 cs4281_wr(sc, CS4281PCI_ACCTL, 0); 575 DELAY(50); 576 577 /* (2) Effect Reset */ 578 cs4281_wr(sc, CS4281PCI_SPMC, 0); 579 DELAY(100); 580 cs4281_wr(sc, CS4281PCI_SPMC, CS4281PCI_SPMC_RSTN); 581 /* Wait 50ms for ABITCLK to become stable */ 582 DELAY(50000); 583 584 /* (3) Enable Sound System Clocks */ 585 cs4281_wr(sc, CS4281PCI_CLKCR1, CS4281PCI_CLKCR1_DLLP); 586 DELAY(50000); /* Wait for PLL to stabilize */ 587 cs4281_wr(sc, CS4281PCI_CLKCR1, 588 CS4281PCI_CLKCR1_DLLP | CS4281PCI_CLKCR1_SWCE); 589 590 /* (4) Power Up - this combination is essential. */ 591 cs4281_set4(sc, CS4281PCI_SSPM, 592 CS4281PCI_SSPM_ACLEN | CS4281PCI_SSPM_PSRCEN | 593 CS4281PCI_SSPM_CSRCEN | CS4281PCI_SSPM_MIXEN); 594 595 /* (5) Wait for clock stabilization */ 596 if (cs4281_waitset(sc, 597 CS4281PCI_CLKCR1, 598 CS4281PCI_CLKCR1_DLLRDY, 599 250) == 0) { 600 device_printf(sc->dev, "Clock stabilization failed\n"); 601 return -1; 602 } 603 604 /* (6) Enable ASYNC generation. */ 605 cs4281_wr(sc, CS4281PCI_ACCTL,CS4281PCI_ACCTL_ESYN); 606 607 /* Wait to allow AC97 to start generating clock bit */ 608 DELAY(50000); 609 610 /* Set AC97 timing */ 611 cs4281_wr(sc, CS4281PCI_SERMC, CS4281PCI_SERMC_PTC_AC97); 612 613 /* (7) Wait for AC97 ready signal */ 614 if (cs4281_waitset(sc, CS4281PCI_ACSTS, CS4281PCI_ACSTS_CRDY, 250) == 0) { 615 device_printf(sc->dev, "codec did not avail\n"); 616 return -1; 617 } 618 619 /* (8) Assert valid frame signal to begin sending commands to 620 * AC97 codec */ 621 cs4281_wr(sc, 622 CS4281PCI_ACCTL, 623 CS4281PCI_ACCTL_VFRM | CS4281PCI_ACCTL_ESYN); 624 625 /* (9) Wait for codec calibration */ 626 for(i = 0 ; i < 1000; i++) { 627 DELAY(10000); 628 v = cs4281_rdcd(0, sc, AC97_REG_POWER); 629 if ((v & 0x0f) == 0x0f) { 630 break; 631 } 632 } 633 if (i == 1000) { 634 device_printf(sc->dev, "codec failed to calibrate\n"); 635 return -1; 636 } 637 638 /* (10) Set AC97 timing */ 639 cs4281_wr(sc, CS4281PCI_SERMC, CS4281PCI_SERMC_PTC_AC97); 640 641 /* (11) Wait for valid data to arrive */ 642 if (cs4281_waitset(sc, 643 CS4281PCI_ACISV, 644 CS4281PCI_ACISV_ISV(3) | CS4281PCI_ACISV_ISV(4), 645 10000) == 0) { 646 device_printf(sc->dev, "cs4281 never got valid data\n"); 647 return -1; 648 } 649 650 /* (12) Start digital data transfer of audio data to codec */ 651 cs4281_wr(sc, 652 CS4281PCI_ACOSV, 653 CS4281PCI_ACOSV_SLV(3) | CS4281PCI_ACOSV_SLV(4)); 654 655 /* Set Master and headphone to max */ 656 cs4281_wrcd(0, sc, AC97_MIX_AUXOUT, 0); 657 cs4281_wrcd(0, sc, AC97_MIX_MASTER, 0); 658 659 /* Power on the DAC */ 660 v = cs4281_rdcd(0, sc, AC97_REG_POWER) & 0xfdff; 661 cs4281_wrcd(0, sc, AC97_REG_POWER, v); 662 663 /* Wait until DAC state ready */ 664 for(i = 0; i < 320; i++) { 665 DELAY(100); 666 v = cs4281_rdcd(0, sc, AC97_REG_POWER); 667 if (v & 0x02) break; 668 } 669 670 /* Power on the ADC */ 671 v = cs4281_rdcd(0, sc, AC97_REG_POWER) & 0xfeff; 672 cs4281_wrcd(0, sc, AC97_REG_POWER, v); 673 674 /* Wait until ADC state ready */ 675 for(i = 0; i < 320; i++) { 676 DELAY(100); 677 v = cs4281_rdcd(0, sc, AC97_REG_POWER); 678 if (v & 0x01) break; 679 } 680 681 /* FIFO configuration (driver is DMA orientated, implicit FIFO) */ 682 /* Play FIFO */ 683 684 v = CS4281PCI_FCR_RS(CS4281PCI_RPCM_PLAY_SLOT) | 685 CS4281PCI_FCR_LS(CS4281PCI_LPCM_PLAY_SLOT) | 686 CS4281PCI_FCR_SZ(CS4281_FIFO_SIZE)| 687 CS4281PCI_FCR_OF(0); 688 cs4281_wr(sc, CS4281PCI_FCR(CS4281_DMA_PLAY), v); 689 690 cs4281_wr(sc, CS4281PCI_FCR(CS4281_DMA_PLAY), v | CS4281PCI_FCR_FEN); 691 692 /* Record FIFO */ 693 v = CS4281PCI_FCR_RS(CS4281PCI_RPCM_REC_SLOT) | 694 CS4281PCI_FCR_LS(CS4281PCI_LPCM_REC_SLOT) | 695 CS4281PCI_FCR_SZ(CS4281_FIFO_SIZE)| 696 CS4281PCI_FCR_OF(CS4281_FIFO_SIZE + 1); 697 cs4281_wr(sc, CS4281PCI_FCR(CS4281_DMA_REC), v | CS4281PCI_FCR_PSH); 698 cs4281_wr(sc, CS4281PCI_FCR(CS4281_DMA_REC), v | CS4281PCI_FCR_FEN); 699 700 /* Match AC97 slots to FIFOs */ 701 v = CS4281PCI_SRCSA_PLSS(CS4281PCI_LPCM_PLAY_SLOT) | 702 CS4281PCI_SRCSA_PRSS(CS4281PCI_RPCM_PLAY_SLOT) | 703 CS4281PCI_SRCSA_CLSS(CS4281PCI_LPCM_REC_SLOT) | 704 CS4281PCI_SRCSA_CRSS(CS4281PCI_RPCM_REC_SLOT); 705 cs4281_wr(sc, CS4281PCI_SRCSA, v); 706 707 /* Set Auto-Initialize and set directions */ 708 cs4281_wr(sc, 709 CS4281PCI_DMR(CS4281_DMA_PLAY), 710 CS4281PCI_DMR_DMA | 711 CS4281PCI_DMR_AUTO | 712 CS4281PCI_DMR_TR_PLAY); 713 cs4281_wr(sc, 714 CS4281PCI_DMR(CS4281_DMA_REC), 715 CS4281PCI_DMR_DMA | 716 CS4281PCI_DMR_AUTO | 717 CS4281PCI_DMR_TR_REC); 718 719 /* Enable half and empty buffer interrupts keeping DMA paused */ 720 cs4281_wr(sc, 721 CS4281PCI_DCR(CS4281_DMA_PLAY), 722 CS4281PCI_DCR_TCIE | CS4281PCI_DCR_HTCIE | CS4281PCI_DCR_MSK); 723 cs4281_wr(sc, 724 CS4281PCI_DCR(CS4281_DMA_REC), 725 CS4281PCI_DCR_TCIE | CS4281PCI_DCR_HTCIE | CS4281PCI_DCR_MSK); 726 727 /* Enable Interrupts */ 728 cs4281_clr4(sc, 729 CS4281PCI_HIMR, 730 CS4281PCI_HIMR_DMAI | 731 CS4281PCI_HIMR_DMA(CS4281_DMA_PLAY) | 732 CS4281PCI_HIMR_DMA(CS4281_DMA_REC)); 733 734 /* Set playback volume */ 735 cs4281_wr(sc, CS4281PCI_PPLVC, 7); 736 cs4281_wr(sc, CS4281PCI_PPRVC, 7); 737 738 return 0; 739 } 740 741 /* -------------------------------------------------------------------- */ 742 /* Probe and attach the card */ 743 744 static int 745 cs4281_pci_probe(device_t dev) 746 { 747 char *s = NULL; 748 749 switch (pci_get_devid(dev)) { 750 case CS4281_PCI_ID: 751 s = "Crystal Semiconductor CS4281"; 752 break; 753 } 754 755 if (s) 756 device_set_desc(dev, s); 757 return s ? BUS_PROBE_DEFAULT : ENXIO; 758 } 759 760 static int 761 cs4281_pci_attach(device_t dev) 762 { 763 struct sc_info *sc; 764 struct ac97_info *codec = NULL; 765 char status[SND_STATUSLEN]; 766 767 sc = malloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO); 768 sc->dev = dev; 769 sc->type = pci_get_devid(dev); 770 771 pci_enable_busmaster(dev); 772 773 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 774 /* Reset the power state. */ 775 device_printf(dev, "chip is in D%d power mode " 776 "-- setting to D0\n", pci_get_powerstate(dev)); 777 778 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 779 } 780 781 sc->regid = PCIR_BAR(0); 782 sc->regtype = SYS_RES_MEMORY; 783 sc->reg = bus_alloc_resource_any(dev, sc->regtype, &sc->regid, RF_ACTIVE); 784 if (!sc->reg) { 785 sc->regtype = SYS_RES_IOPORT; 786 sc->reg = bus_alloc_resource_any(dev, sc->regtype, &sc->regid, 787 RF_ACTIVE); 788 if (!sc->reg) { 789 device_printf(dev, "unable to allocate register space\n"); 790 goto bad; 791 } 792 } 793 sc->st = rman_get_bustag(sc->reg); 794 sc->sh = rman_get_bushandle(sc->reg); 795 796 sc->memid = PCIR_BAR(1); 797 sc->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->memid, 798 RF_ACTIVE); 799 if (sc->mem == NULL) { 800 device_printf(dev, "unable to allocate fifo space\n"); 801 goto bad; 802 } 803 804 sc->irqid = 0; 805 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irqid, 806 RF_ACTIVE | RF_SHAREABLE); 807 if (!sc->irq) { 808 device_printf(dev, "unable to allocate interrupt\n"); 809 goto bad; 810 } 811 812 if (snd_setup_intr(dev, sc->irq, 0, cs4281_intr, sc, &sc->ih)) { 813 device_printf(dev, "unable to setup interrupt\n"); 814 goto bad; 815 } 816 817 sc->bufsz = pcm_getbuffersize(dev, 4096, CS4281_DEFAULT_BUFSZ, 65536); 818 819 if (bus_dma_tag_create(/*parent*/bus_get_dma_tag(dev), /*alignment*/2, 820 /*boundary*/0, 821 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 822 /*highaddr*/BUS_SPACE_MAXADDR, 823 /*filter*/NULL, /*filterarg*/NULL, 824 /*maxsize*/sc->bufsz, /*nsegments*/1, 825 /*maxsegz*/0x3ffff, 826 /*flags*/0, /*lockfunc*/NULL, /*lockarg*/NULL, 827 &sc->parent_dmat) != 0) { 828 device_printf(dev, "unable to create dma tag\n"); 829 goto bad; 830 } 831 832 /* power up */ 833 cs4281_power(sc, 0); 834 835 /* init chip */ 836 if (cs4281_init(sc) == -1) { 837 device_printf(dev, "unable to initialize the card\n"); 838 goto bad; 839 } 840 841 /* create/init mixer */ 842 codec = AC97_CREATE(dev, sc, cs4281_ac97); 843 if (codec == NULL) 844 goto bad; 845 846 mixer_init(dev, ac97_getmixerclass(), codec); 847 848 if (pcm_register(dev, sc, 1, 1)) 849 goto bad; 850 851 pcm_addchan(dev, PCMDIR_PLAY, &cs4281chan_class, sc); 852 pcm_addchan(dev, PCMDIR_REC, &cs4281chan_class, sc); 853 854 snprintf(status, SND_STATUSLEN, "at %s 0x%jx irq %jd %s", 855 (sc->regtype == SYS_RES_IOPORT)? "io" : "memory", 856 rman_get_start(sc->reg), rman_get_start(sc->irq),PCM_KLDSTRING(snd_cs4281)); 857 pcm_setstatus(dev, status); 858 859 return 0; 860 861 bad: 862 if (codec) 863 ac97_destroy(codec); 864 if (sc->reg) 865 bus_release_resource(dev, sc->regtype, sc->regid, sc->reg); 866 if (sc->mem) 867 bus_release_resource(dev, SYS_RES_MEMORY, sc->memid, sc->mem); 868 if (sc->ih) 869 bus_teardown_intr(dev, sc->irq, sc->ih); 870 if (sc->irq) 871 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); 872 if (sc->parent_dmat) 873 bus_dma_tag_destroy(sc->parent_dmat); 874 free(sc, M_DEVBUF); 875 876 return ENXIO; 877 } 878 879 static int 880 cs4281_pci_detach(device_t dev) 881 { 882 int r; 883 struct sc_info *sc; 884 885 r = pcm_unregister(dev); 886 if (r) 887 return r; 888 889 sc = pcm_getdevinfo(dev); 890 891 /* power off */ 892 cs4281_power(sc, 3); 893 894 bus_release_resource(dev, sc->regtype, sc->regid, sc->reg); 895 bus_release_resource(dev, SYS_RES_MEMORY, sc->memid, sc->mem); 896 bus_teardown_intr(dev, sc->irq, sc->ih); 897 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); 898 bus_dma_tag_destroy(sc->parent_dmat); 899 free(sc, M_DEVBUF); 900 901 return 0; 902 } 903 904 static int 905 cs4281_pci_suspend(device_t dev) 906 { 907 struct sc_info *sc; 908 909 sc = pcm_getdevinfo(dev); 910 911 sc->rch.dma_active = adcdac_go(&sc->rch, 0); 912 sc->pch.dma_active = adcdac_go(&sc->pch, 0); 913 914 cs4281_power(sc, 3); 915 916 return 0; 917 } 918 919 static int 920 cs4281_pci_resume(device_t dev) 921 { 922 struct sc_info *sc; 923 924 sc = pcm_getdevinfo(dev); 925 926 /* power up */ 927 cs4281_power(sc, 0); 928 929 /* initialize chip */ 930 if (cs4281_init(sc) == -1) { 931 device_printf(dev, "unable to reinitialize the card\n"); 932 return ENXIO; 933 } 934 935 /* restore mixer state */ 936 if (mixer_reinit(dev) == -1) { 937 device_printf(dev, "unable to reinitialize the mixer\n"); 938 return ENXIO; 939 } 940 941 /* restore chip state */ 942 cs4281chan_setspeed(NULL, &sc->rch, sc->rch.spd); 943 cs4281chan_setblocksize(NULL, &sc->rch, sc->rch.blksz); 944 cs4281chan_setformat(NULL, &sc->rch, sc->rch.fmt); 945 adcdac_go(&sc->rch, sc->rch.dma_active); 946 947 cs4281chan_setspeed(NULL, &sc->pch, sc->pch.spd); 948 cs4281chan_setblocksize(NULL, &sc->pch, sc->pch.blksz); 949 cs4281chan_setformat(NULL, &sc->pch, sc->pch.fmt); 950 adcdac_go(&sc->pch, sc->pch.dma_active); 951 952 return 0; 953 } 954 955 static device_method_t cs4281_methods[] = { 956 /* Device interface */ 957 DEVMETHOD(device_probe, cs4281_pci_probe), 958 DEVMETHOD(device_attach, cs4281_pci_attach), 959 DEVMETHOD(device_detach, cs4281_pci_detach), 960 DEVMETHOD(device_suspend, cs4281_pci_suspend), 961 DEVMETHOD(device_resume, cs4281_pci_resume), 962 { 0, 0 } 963 }; 964 965 static driver_t cs4281_driver = { 966 "pcm", 967 cs4281_methods, 968 PCM_SOFTC_SIZE, 969 }; 970 971 DRIVER_MODULE(snd_cs4281, pci, cs4281_driver, pcm_devclass, 0, 0); 972 MODULE_DEPEND(snd_cs4281, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 973 MODULE_VERSION(snd_cs4281, 1); 974