1 /*- 2 * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 #ifndef _HDAC_PRIVATE_H_ 30 #define _HDAC_PRIVATE_H_ 31 32 33 /**************************************************************************** 34 * Miscellaneous defines 35 ****************************************************************************/ 36 #define HDAC_DMA_ALIGNMENT 128 37 #define HDAC_CODEC_MAX 16 38 39 #define HDAC_MTX_NAME "hdac driver mutex" 40 41 /**************************************************************************** 42 * Helper Macros 43 ****************************************************************************/ 44 #define HDAC_READ_1(mem, offset) \ 45 bus_space_read_1((mem)->mem_tag, (mem)->mem_handle, (offset)) 46 #define HDAC_READ_2(mem, offset) \ 47 bus_space_read_2((mem)->mem_tag, (mem)->mem_handle, (offset)) 48 #define HDAC_READ_4(mem, offset) \ 49 bus_space_read_4((mem)->mem_tag, (mem)->mem_handle, (offset)) 50 #define HDAC_WRITE_1(mem, offset, value) \ 51 bus_space_write_1((mem)->mem_tag, (mem)->mem_handle, (offset), (value)) 52 #define HDAC_WRITE_2(mem, offset, value) \ 53 bus_space_write_2((mem)->mem_tag, (mem)->mem_handle, (offset), (value)) 54 #define HDAC_WRITE_4(mem, offset, value) \ 55 bus_space_write_4((mem)->mem_tag, (mem)->mem_handle, (offset), (value)) 56 57 #define HDAC_ISDCTL(sc, n) (_HDAC_ISDCTL((n), (sc)->num_iss, (sc)->num_oss)) 58 #define HDAC_ISDSTS(sc, n) (_HDAC_ISDSTS((n), (sc)->num_iss, (sc)->num_oss)) 59 #define HDAC_ISDPICB(sc, n) (_HDAC_ISDPICB((n), (sc)->num_iss, (sc)->num_oss)) 60 #define HDAC_ISDCBL(sc, n) (_HDAC_ISDCBL((n), (sc)->num_iss, (sc)->num_oss)) 61 #define HDAC_ISDLVI(sc, n) (_HDAC_ISDLVI((n), (sc)->num_iss, (sc)->num_oss)) 62 #define HDAC_ISDFIFOD(sc, n) (_HDAC_ISDFIFOD((n), (sc)->num_iss, (sc)->num_oss)) 63 #define HDAC_ISDFMT(sc, n) (_HDAC_ISDFMT((n), (sc)->num_iss, (sc)->num_oss)) 64 #define HDAC_ISDBDPL(sc, n) (_HDAC_ISDBDPL((n), (sc)->num_iss, (sc)->num_oss)) 65 #define HDAC_ISDBDPU(sc, n) (_HDAC_ISDBDPU((n), (sc)->num_iss, (sc)->num_oss)) 66 67 #define HDAC_OSDCTL(sc, n) (_HDAC_OSDCTL((n), (sc)->num_iss, (sc)->num_oss)) 68 #define HDAC_OSDSTS(sc, n) (_HDAC_OSDSTS((n), (sc)->num_iss, (sc)->num_oss)) 69 #define HDAC_OSDPICB(sc, n) (_HDAC_OSDPICB((n), (sc)->num_iss, (sc)->num_oss)) 70 #define HDAC_OSDCBL(sc, n) (_HDAC_OSDCBL((n), (sc)->num_iss, (sc)->num_oss)) 71 #define HDAC_OSDLVI(sc, n) (_HDAC_OSDLVI((n), (sc)->num_iss, (sc)->num_oss)) 72 #define HDAC_OSDFIFOD(sc, n) (_HDAC_OSDFIFOD((n), (sc)->num_iss, (sc)->num_oss)) 73 #define HDAC_OSDBDPL(sc, n) (_HDAC_OSDBDPL((n), (sc)->num_iss, (sc)->num_oss)) 74 #define HDAC_OSDBDPU(sc, n) (_HDAC_OSDBDPU((n), (sc)->num_iss, (sc)->num_oss)) 75 76 #define HDAC_BSDCTL(sc, n) (_HDAC_BSDCTL((n), (sc)->num_iss, (sc)->num_oss)) 77 #define HDAC_BSDSTS(sc, n) (_HDAC_BSDSTS((n), (sc)->num_iss, (sc)->num_oss)) 78 #define HDAC_BSDPICB(sc, n) (_HDAC_BSDPICB((n), (sc)->num_iss, (sc)->num_oss)) 79 #define HDAC_BSDCBL(sc, n) (_HDAC_BSDCBL((n), (sc)->num_iss, (sc)->num_oss)) 80 #define HDAC_BSDLVI(sc, n) (_HDAC_BSDLVI((n), (sc)->num_iss, (sc)->num_oss)) 81 #define HDAC_BSDFIFOD(sc, n) (_HDAC_BSDFIFOD((n), (sc)->num_iss, (sc)->num_oss)) 82 #define HDAC_BSDBDPL(sc, n) (_HDAC_BSDBDPL((n), (sc)->num_iss, (sc)->num_oss)) 83 #define HDAC_BSDBDPU(sc, n) (_HDAC_BSDBDPU((n), (sc)->num_iss, (sc)->num_oss)) 84 85 86 /**************************************************************************** 87 * Custom hdac malloc type 88 ****************************************************************************/ 89 MALLOC_DECLARE(M_HDAC); 90 91 /**************************************************************************** 92 * struct hdac_mem 93 * 94 * Holds the resources necessary to describe the physical memory associated 95 * with the device. 96 ****************************************************************************/ 97 struct hdac_mem { 98 struct resource *mem_res; 99 int mem_rid; 100 bus_space_tag_t mem_tag; 101 bus_space_handle_t mem_handle; 102 }; 103 104 /**************************************************************************** 105 * struct hdac_irq 106 * 107 * Holds the resources necessary to describe the irq associated with the 108 * device. 109 ****************************************************************************/ 110 struct hdac_irq { 111 struct resource *irq_res; 112 int irq_rid; 113 void *irq_handle; 114 }; 115 116 /**************************************************************************** 117 * struct hdac_dma 118 * 119 * This structure is used to hold all the information to manage the dma 120 * states. 121 ****************************************************************************/ 122 struct hdac_dma { 123 bus_dma_tag_t dma_tag; 124 bus_dmamap_t dma_map; 125 bus_addr_t dma_paddr; 126 bus_size_t dma_size; 127 caddr_t dma_vaddr; 128 }; 129 130 /**************************************************************************** 131 * struct hdac_rirb 132 * 133 * Hold a response from a verb sent to a codec received via the rirb. 134 ****************************************************************************/ 135 struct hdac_rirb { 136 uint32_t response; 137 uint32_t response_ex; 138 }; 139 140 #define HDAC_RIRB_RESPONSE_EX_SDATA_IN_MASK 0x0000000f 141 #define HDAC_RIRB_RESPONSE_EX_SDATA_IN_OFFSET 0 142 #define HDAC_RIRB_RESPONSE_EX_UNSOLICITED 0x00000010 143 144 #define HDAC_RIRB_RESPONSE_EX_SDATA_IN(response_ex) \ 145 (((response_ex) & HDAC_RIRB_RESPONSE_EX_SDATA_IN_MASK) >> \ 146 HDAC_RIRB_RESPONSE_EX_SDATA_IN_OFFSET) 147 148 /**************************************************************************** 149 * struct hdac_command_list 150 * 151 * This structure holds the list of verbs that are to be sent to the codec 152 * via the corb and the responses received via the rirb. It's allocated by 153 * the codec driver and is owned by it. 154 ****************************************************************************/ 155 struct hdac_command_list { 156 int num_commands; 157 uint32_t *verbs; 158 uint32_t *responses; 159 }; 160 161 typedef int nid_t; 162 163 struct hdac_softc; 164 struct hdac_bdle { 165 volatile uint32_t addrl; 166 volatile uint32_t addrh; 167 volatile uint32_t len; 168 volatile uint32_t ioc; 169 } __packed; 170 171 #define HDA_MAX_CONNS 32 172 #define HDA_MAX_NAMELEN 32 173 174 struct hdac_widget { 175 nid_t nid; 176 int type; 177 int enable; 178 int nconns, selconn; 179 int waspin; 180 uint32_t pflags; 181 int bindas; 182 int bindseqmask; 183 int ossdev; 184 uint32_t ossmask; 185 nid_t conns[HDA_MAX_CONNS]; 186 u_char connsenable[HDA_MAX_CONNS]; 187 char name[HDA_MAX_NAMELEN]; 188 struct hdac_devinfo *devinfo; 189 struct { 190 uint32_t widget_cap; 191 uint32_t outamp_cap; 192 uint32_t inamp_cap; 193 uint32_t supp_stream_formats; 194 uint32_t supp_pcm_size_rate; 195 uint32_t eapdbtl; 196 } param; 197 union { 198 struct { 199 uint32_t config; 200 uint32_t cap; 201 uint32_t ctrl; 202 } pin; 203 } wclass; 204 }; 205 206 struct hdac_audio_ctl { 207 struct hdac_widget *widget, *childwidget; 208 int enable; 209 int index, dir, ndir; 210 int mute, step, size, offset; 211 int left, right, forcemute; 212 uint32_t muted; 213 uint32_t ossmask, possmask; 214 }; 215 216 /* Association is a group of pins bound for some special function. */ 217 struct hdac_audio_as { 218 u_char enable; 219 u_char index; 220 u_char dir; 221 u_char pincnt; 222 u_char fakeredir; 223 u_char digital; 224 nid_t hpredir; 225 nid_t pins[16]; 226 nid_t dacs[16]; 227 int chan; 228 }; 229 230 struct hdac_pcm_devinfo { 231 device_t dev; 232 struct hdac_devinfo *devinfo; 233 int index; 234 int registered; 235 int play, rec; 236 u_char left[SOUND_MIXER_NRDEVICES]; 237 u_char right[SOUND_MIXER_NRDEVICES]; 238 int chan_size; 239 int chan_blkcnt; 240 u_char digital; 241 }; 242 243 /**************************************************************************** 244 * struct hdac_devinfo 245 * 246 * Holds all the parameters of a given codec function group. This is stored 247 * in the ivar of each child of the hdac bus 248 ****************************************************************************/ 249 struct hdac_devinfo { 250 uint8_t node_type; 251 nid_t nid; 252 nid_t startnode, endnode; 253 int nodecnt; 254 struct hdac_codec *codec; 255 struct hdac_widget *widget; 256 union { 257 struct { 258 uint32_t outamp_cap; 259 uint32_t inamp_cap; 260 uint32_t supp_stream_formats; 261 uint32_t supp_pcm_size_rate; 262 int ctlcnt, ascnt; 263 struct hdac_audio_ctl *ctl; 264 struct hdac_audio_as *as; 265 uint32_t quirks; 266 uint32_t gpio; 267 struct hdac_pcm_devinfo *devs; 268 int num_devs; 269 } audio; 270 /* XXX undefined: modem, hdmi. */ 271 } function; 272 }; 273 274 #define HDAC_CHN_RUNNING 0x00000001 275 #define HDAC_CHN_SUSPEND 0x00000002 276 277 struct hdac_chan { 278 struct snd_dbuf *b; 279 struct pcm_channel *c; 280 struct pcmchan_caps caps; 281 struct hdac_devinfo *devinfo; 282 struct hdac_pcm_devinfo *pdevinfo; 283 struct hdac_dma bdl_dma; 284 uint32_t spd, fmt, fmtlist[8], pcmrates[16]; 285 uint32_t supp_stream_formats, supp_pcm_size_rate; 286 uint32_t ptr, prevptr, blkcnt, blksz; 287 uint32_t *dmapos; 288 uint32_t flags; 289 int dir; 290 int off; 291 int sid; 292 int bit16, bit32; 293 int as; 294 nid_t io[16]; 295 }; 296 297 /**************************************************************************** 298 * struct hdac_codec 299 * 300 ****************************************************************************/ 301 struct hdac_codec { 302 int verbs_sent; 303 int responses_received; 304 nid_t cad; 305 uint16_t vendor_id; 306 uint16_t device_id; 307 uint8_t revision_id; 308 uint8_t stepping_id; 309 struct hdac_command_list *commands; 310 struct hdac_softc *sc; 311 struct hdac_devinfo *fgs; 312 int num_fgs; 313 }; 314 315 /**************************************************************************** 316 * struct hdac_softc 317 * 318 * This structure holds the current state of the hdac driver. 319 ****************************************************************************/ 320 321 #define HDAC_F_DMA_NOCACHE 0x00000001 322 #define HDAC_F_MSI 0x00000002 323 324 struct hdac_softc { 325 device_t dev; 326 device_t hdabus; 327 struct mtx *lock; 328 329 struct intr_config_hook intrhook; 330 331 struct hdac_mem mem; 332 struct hdac_irq irq; 333 uint32_t pci_subvendor; 334 335 uint32_t flags; 336 337 struct hdac_chan *chans; 338 int num_chans; 339 int num_iss; 340 int num_oss; 341 int num_bss; 342 int support_64bit; 343 int streamcnt; 344 345 int corb_size; 346 struct hdac_dma corb_dma; 347 int corb_wp; 348 349 int rirb_size; 350 struct hdac_dma rirb_dma; 351 int rirb_rp; 352 353 struct hdac_dma pos_dma; 354 355 bus_dma_tag_t chan_dmat; 356 357 /* 358 * Polling 359 */ 360 int polling; 361 int poll_ticks; 362 int poll_ival; 363 struct callout poll_hda; 364 struct callout poll_hdac; 365 struct callout poll_jack; 366 367 struct task unsolq_task; 368 369 #define HDAC_UNSOLQ_MAX 64 370 #define HDAC_UNSOLQ_READY 0 371 #define HDAC_UNSOLQ_BUSY 1 372 int unsolq_rp; 373 int unsolq_wp; 374 int unsolq_st; 375 uint32_t unsolq[HDAC_UNSOLQ_MAX]; 376 377 struct hdac_codec *codecs[HDAC_CODEC_MAX]; 378 }; 379 380 /**************************************************************************** 381 * struct hdac_command flags 382 ****************************************************************************/ 383 #define HDAC_COMMAND_FLAG_WAITOK 0x0000 384 #define HDAC_COMMAND_FLAG_NOWAIT 0x0001 385 386 #endif 387