1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2000 Katsurajima Naoto <raven@katsurajima.seya.yokohama.jp> 5 * Copyright (c) 2001 Cameron Grant <cg@freebsd.org> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #ifdef HAVE_KERNEL_OPTION_HEADERS 31 #include "opt_snd.h" 32 #endif 33 34 #include <dev/sound/pcm/sound.h> 35 #include <dev/sound/pcm/ac97.h> 36 #include <dev/sound/pci/ich.h> 37 38 #include <dev/pci/pcireg.h> 39 #include <dev/pci/pcivar.h> 40 41 /* -------------------------------------------------------------------- */ 42 43 #define ICH_TIMEOUT 1000 /* semaphore timeout polling count */ 44 #define ICH_DTBL_LENGTH 32 45 #define ICH_DEFAULT_BUFSZ 16384 46 #define ICH_MAX_BUFSZ 65536 47 #define ICH_MIN_BUFSZ 4096 48 #define ICH_DEFAULT_BLKCNT 2 49 #define ICH_MAX_BLKCNT 32 50 #define ICH_MIN_BLKCNT 2 51 #define ICH_MIN_BLKSZ 64 52 53 #define INTEL_VENDORID 0x8086 54 #define SIS_VENDORID 0x1039 55 #define NVIDIA_VENDORID 0x10de 56 #define AMD_VENDORID 0x1022 57 58 #define INTEL_82440MX 0x7195 59 #define INTEL_82801AA 0x2415 60 #define INTEL_82801AB 0x2425 61 #define INTEL_82801BA 0x2445 62 #define INTEL_82801CA 0x2485 63 #define INTEL_82801DB 0x24c5 /* ICH4 needs special handling */ 64 #define INTEL_82801EB 0x24d5 /* ICH5 needs to be treated as ICH4 */ 65 #define INTEL_6300ESB 0x25a6 /* 6300ESB needs to be treated as ICH4 */ 66 #define INTEL_82801FB 0x266e /* ICH6 needs to be treated as ICH4 */ 67 #define INTEL_82801GB 0x27de /* ICH7 needs to be treated as ICH4 */ 68 #define SIS_7012 0x7012 /* SiS 7012 needs special handling */ 69 #define NVIDIA_NFORCE 0x01b1 70 #define NVIDIA_NFORCE2 0x006a 71 #define NVIDIA_NFORCE2_400 0x008a 72 #define NVIDIA_NFORCE3 0x00da 73 #define NVIDIA_NFORCE3_250 0x00ea 74 #define NVIDIA_NFORCE4 0x0059 75 #define NVIDIA_NFORCE_410_MCP 0x026b 76 #define NVIDIA_NFORCE4_MCP 0x003a 77 #define AMD_768 0x7445 78 #define AMD_8111 0x746d 79 80 #define ICH_LOCK(sc) snd_mtxlock((sc)->ich_lock) 81 #define ICH_UNLOCK(sc) snd_mtxunlock((sc)->ich_lock) 82 #define ICH_LOCK_ASSERT(sc) snd_mtxassert((sc)->ich_lock) 83 84 #if 0 85 #define ICH_DEBUG(stmt) do { \ 86 stmt \ 87 } while (0) 88 #else 89 #define ICH_DEBUG(...) 90 #endif 91 92 #define ICH_CALIBRATE_DONE (1 << 0) 93 #define ICH_IGNORE_PCR (1 << 1) 94 #define ICH_IGNORE_RESET (1 << 2) 95 #define ICH_FIXED_RATE (1 << 3) 96 #define ICH_DMA_NOCACHE (1 << 4) 97 #define ICH_HIGH_LATENCY (1 << 5) 98 99 static const struct ich_type { 100 uint16_t vendor; 101 uint16_t devid; 102 uint32_t options; 103 #define PROBE_LOW 0x01 104 char *name; 105 } ich_devs[] = { 106 { INTEL_VENDORID, INTEL_82440MX, 0, 107 "Intel 440MX" }, 108 { INTEL_VENDORID, INTEL_82801AA, 0, 109 "Intel ICH (82801AA)" }, 110 { INTEL_VENDORID, INTEL_82801AB, 0, 111 "Intel ICH (82801AB)" }, 112 { INTEL_VENDORID, INTEL_82801BA, 0, 113 "Intel ICH2 (82801BA)" }, 114 { INTEL_VENDORID, INTEL_82801CA, 0, 115 "Intel ICH3 (82801CA)" }, 116 { INTEL_VENDORID, INTEL_82801DB, PROBE_LOW, 117 "Intel ICH4 (82801DB)" }, 118 { INTEL_VENDORID, INTEL_82801EB, PROBE_LOW, 119 "Intel ICH5 (82801EB)" }, 120 { INTEL_VENDORID, INTEL_6300ESB, PROBE_LOW, 121 "Intel 6300ESB" }, 122 { INTEL_VENDORID, INTEL_82801FB, PROBE_LOW, 123 "Intel ICH6 (82801FB)" }, 124 { INTEL_VENDORID, INTEL_82801GB, PROBE_LOW, 125 "Intel ICH7 (82801GB)" }, 126 { SIS_VENDORID, SIS_7012, 0, 127 "SiS 7012" }, 128 { NVIDIA_VENDORID, NVIDIA_NFORCE, 0, 129 "nVidia nForce" }, 130 { NVIDIA_VENDORID, NVIDIA_NFORCE2, 0, 131 "nVidia nForce2" }, 132 { NVIDIA_VENDORID, NVIDIA_NFORCE2_400, 0, 133 "nVidia nForce2 400" }, 134 { NVIDIA_VENDORID, NVIDIA_NFORCE3, 0, 135 "nVidia nForce3" }, 136 { NVIDIA_VENDORID, NVIDIA_NFORCE3_250, 0, 137 "nVidia nForce3 250" }, 138 { NVIDIA_VENDORID, NVIDIA_NFORCE4, 0, 139 "nVidia nForce4" }, 140 { NVIDIA_VENDORID, NVIDIA_NFORCE_410_MCP, 0, 141 "nVidia nForce 410 MCP" }, 142 { NVIDIA_VENDORID, NVIDIA_NFORCE4_MCP, 0, 143 "nVidia nForce 4 MCP" }, 144 { AMD_VENDORID, AMD_768, 0, 145 "AMD-768" }, 146 { AMD_VENDORID, AMD_8111, 0, 147 "AMD-8111" } 148 }; 149 150 /* buffer descriptor */ 151 struct ich_desc { 152 volatile uint32_t buffer; 153 volatile uint32_t length; 154 }; 155 156 struct sc_info; 157 158 /* channel registers */ 159 struct sc_chinfo { 160 uint32_t num:8, run:1, run_save:1; 161 uint32_t blksz, blkcnt, spd; 162 uint32_t regbase, spdreg; 163 uint32_t imask; 164 uint32_t civ; 165 166 struct snd_dbuf *buffer; 167 struct pcm_channel *channel; 168 struct sc_info *parent; 169 170 struct ich_desc *dtbl; 171 bus_addr_t desc_addr; 172 }; 173 174 /* device private data */ 175 struct sc_info { 176 device_t dev; 177 int hasvra, hasvrm, hasmic; 178 unsigned int chnum, bufsz, blkcnt; 179 int sample_size, swap_reg; 180 181 struct resource *nambar, *nabmbar, *irq; 182 int regtype, nambarid, nabmbarid, irqid; 183 bus_space_tag_t nambart, nabmbart; 184 bus_space_handle_t nambarh, nabmbarh; 185 bus_dma_tag_t dmat, chan_dmat; 186 bus_dmamap_t dtmap; 187 void *ih; 188 189 struct ac97_info *codec; 190 struct sc_chinfo ch[3]; 191 int ac97rate; 192 struct ich_desc *dtbl; 193 unsigned int dtbl_size; 194 bus_addr_t desc_addr; 195 struct intr_config_hook intrhook; 196 uint16_t vendor; 197 uint16_t devid; 198 uint32_t flags; 199 struct mtx *ich_lock; 200 }; 201 202 /* -------------------------------------------------------------------- */ 203 204 static uint32_t ich_fmt[] = { 205 SND_FORMAT(AFMT_S16_LE, 2, 0), 206 0 207 }; 208 static struct pcmchan_caps ich_vrcaps = {8000, 48000, ich_fmt, 0}; 209 static struct pcmchan_caps ich_caps = {48000, 48000, ich_fmt, 0}; 210 211 /* -------------------------------------------------------------------- */ 212 /* Hardware */ 213 static __inline uint32_t 214 ich_rd(struct sc_info *sc, int regno, int size) 215 { 216 switch (size) { 217 case 1: 218 return (bus_space_read_1(sc->nabmbart, sc->nabmbarh, regno)); 219 case 2: 220 return (bus_space_read_2(sc->nabmbart, sc->nabmbarh, regno)); 221 case 4: 222 return (bus_space_read_4(sc->nabmbart, sc->nabmbarh, regno)); 223 default: 224 return (0xffffffff); 225 } 226 } 227 228 static __inline void 229 ich_wr(struct sc_info *sc, int regno, uint32_t data, int size) 230 { 231 switch (size) { 232 case 1: 233 bus_space_write_1(sc->nabmbart, sc->nabmbarh, regno, data); 234 break; 235 case 2: 236 bus_space_write_2(sc->nabmbart, sc->nabmbarh, regno, data); 237 break; 238 case 4: 239 bus_space_write_4(sc->nabmbart, sc->nabmbarh, regno, data); 240 break; 241 } 242 } 243 244 /* ac97 codec */ 245 static int 246 ich_waitcd(void *devinfo) 247 { 248 struct sc_info *sc = (struct sc_info *)devinfo; 249 uint32_t data; 250 int i; 251 252 for (i = 0; i < ICH_TIMEOUT; i++) { 253 data = ich_rd(sc, ICH_REG_ACC_SEMA, 1); 254 if ((data & 0x01) == 0) 255 return (0); 256 DELAY(1); 257 } 258 if ((sc->flags & ICH_IGNORE_PCR) != 0) 259 return (0); 260 device_printf(sc->dev, "CODEC semaphore timeout\n"); 261 return (ETIMEDOUT); 262 } 263 264 static int 265 ich_rdcd(kobj_t obj, void *devinfo, int regno) 266 { 267 struct sc_info *sc = (struct sc_info *)devinfo; 268 269 regno &= 0xff; 270 ich_waitcd(sc); 271 272 return (bus_space_read_2(sc->nambart, sc->nambarh, regno)); 273 } 274 275 static int 276 ich_wrcd(kobj_t obj, void *devinfo, int regno, uint32_t data) 277 { 278 struct sc_info *sc = (struct sc_info *)devinfo; 279 280 regno &= 0xff; 281 ich_waitcd(sc); 282 bus_space_write_2(sc->nambart, sc->nambarh, regno, data); 283 284 return (0); 285 } 286 287 static kobj_method_t ich_ac97_methods[] = { 288 KOBJMETHOD(ac97_read, ich_rdcd), 289 KOBJMETHOD(ac97_write, ich_wrcd), 290 KOBJMETHOD_END 291 }; 292 AC97_DECLARE(ich_ac97); 293 294 /* -------------------------------------------------------------------- */ 295 /* common routines */ 296 297 static void 298 ich_filldtbl(struct sc_chinfo *ch) 299 { 300 struct sc_info *sc = ch->parent; 301 uint32_t base; 302 int i; 303 304 base = sndbuf_getbufaddr(ch->buffer); 305 if ((ch->blksz * ch->blkcnt) > sndbuf_getmaxsize(ch->buffer)) 306 ch->blksz = sndbuf_getmaxsize(ch->buffer) / ch->blkcnt; 307 if ((sndbuf_getblksz(ch->buffer) != ch->blksz || 308 sndbuf_getblkcnt(ch->buffer) != ch->blkcnt) && 309 sndbuf_resize(ch->buffer, ch->blkcnt, ch->blksz) != 0) 310 device_printf(sc->dev, "%s: failed blksz=%u blkcnt=%u\n", 311 __func__, ch->blksz, ch->blkcnt); 312 ch->blksz = sndbuf_getblksz(ch->buffer); 313 314 for (i = 0; i < ICH_DTBL_LENGTH; i++) { 315 ch->dtbl[i].buffer = base + (ch->blksz * (i % ch->blkcnt)); 316 ch->dtbl[i].length = ICH_BDC_IOC 317 | (ch->blksz / ch->parent->sample_size); 318 } 319 } 320 321 static int 322 ich_resetchan(struct sc_info *sc, int num) 323 { 324 int i, cr, regbase; 325 326 if (num == 0) 327 regbase = ICH_REG_PO_BASE; 328 else if (num == 1) 329 regbase = ICH_REG_PI_BASE; 330 else if (num == 2) 331 regbase = ICH_REG_MC_BASE; 332 else 333 return (ENXIO); 334 335 ich_wr(sc, regbase + ICH_REG_X_CR, 0, 1); 336 #if 1 337 /* This may result in no sound output on NForce 2 MBs, see PR 73987 */ 338 DELAY(100); 339 #else 340 (void)ich_rd(sc, regbase + ICH_REG_X_CR, 1); 341 #endif 342 ich_wr(sc, regbase + ICH_REG_X_CR, ICH_X_CR_RR, 1); 343 for (i = 0; i < ICH_TIMEOUT; i++) { 344 cr = ich_rd(sc, regbase + ICH_REG_X_CR, 1); 345 if (cr == 0) 346 return (0); 347 DELAY(1); 348 } 349 350 if (sc->flags & ICH_IGNORE_RESET) 351 return (0); 352 #if 0 353 else if (sc->vendor == NVIDIA_VENDORID) { 354 sc->flags |= ICH_IGNORE_RESET; 355 device_printf(sc->dev, "ignoring reset failure!\n"); 356 return (0); 357 } 358 #endif 359 360 device_printf(sc->dev, "cannot reset channel %d\n", num); 361 return (ENXIO); 362 } 363 364 /* -------------------------------------------------------------------- */ 365 /* channel interface */ 366 367 static void * 368 ichchan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir) 369 { 370 struct sc_info *sc = devinfo; 371 struct sc_chinfo *ch; 372 unsigned int num; 373 374 ICH_LOCK(sc); 375 num = sc->chnum++; 376 ch = &sc->ch[num]; 377 ch->num = num; 378 ch->buffer = b; 379 ch->channel = c; 380 ch->parent = sc; 381 ch->run = 0; 382 ch->dtbl = sc->dtbl + (ch->num * ICH_DTBL_LENGTH); 383 ch->desc_addr = sc->desc_addr + 384 (ch->num * ICH_DTBL_LENGTH * sizeof(struct ich_desc)); 385 ch->blkcnt = sc->blkcnt; 386 ch->blksz = sc->bufsz / ch->blkcnt; 387 388 switch(ch->num) { 389 case 0: /* play */ 390 KASSERT(dir == PCMDIR_PLAY, ("wrong direction")); 391 ch->regbase = ICH_REG_PO_BASE; 392 ch->spdreg = (sc->hasvra) ? AC97_REGEXT_FDACRATE : 0; 393 ch->imask = ICH_GLOB_STA_POINT; 394 break; 395 396 case 1: /* record */ 397 KASSERT(dir == PCMDIR_REC, ("wrong direction")); 398 ch->regbase = ICH_REG_PI_BASE; 399 ch->spdreg = (sc->hasvra) ? AC97_REGEXT_LADCRATE : 0; 400 ch->imask = ICH_GLOB_STA_PIINT; 401 break; 402 403 case 2: /* mic */ 404 KASSERT(dir == PCMDIR_REC, ("wrong direction")); 405 ch->regbase = ICH_REG_MC_BASE; 406 ch->spdreg = (sc->hasvrm) ? AC97_REGEXT_MADCRATE : 0; 407 ch->imask = ICH_GLOB_STA_MINT; 408 break; 409 410 default: 411 return (NULL); 412 } 413 414 if (sc->flags & ICH_FIXED_RATE) 415 ch->spdreg = 0; 416 417 ICH_UNLOCK(sc); 418 if (sndbuf_alloc(ch->buffer, sc->chan_dmat, 419 ((sc->flags & ICH_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0), 420 sc->bufsz) != 0) 421 return (NULL); 422 423 ICH_LOCK(sc); 424 ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (uint32_t)(ch->desc_addr), 4); 425 ICH_UNLOCK(sc); 426 427 return (ch); 428 } 429 430 static int 431 ichchan_setformat(kobj_t obj, void *data, uint32_t format) 432 { 433 434 ICH_DEBUG( 435 struct sc_chinfo *ch = data; 436 struct sc_info *sc = ch->parent; 437 if (!(sc->flags & ICH_CALIBRATE_DONE)) 438 device_printf(sc->dev, 439 "WARNING: %s() called before calibration!\n", 440 __func__); 441 ); 442 443 return (0); 444 } 445 446 static uint32_t 447 ichchan_setspeed(kobj_t obj, void *data, uint32_t speed) 448 { 449 struct sc_chinfo *ch = data; 450 struct sc_info *sc = ch->parent; 451 452 ICH_DEBUG( 453 if (!(sc->flags & ICH_CALIBRATE_DONE)) 454 device_printf(sc->dev, 455 "WARNING: %s() called before calibration!\n", 456 __func__); 457 ); 458 459 if (ch->spdreg) { 460 int r, ac97rate; 461 462 ICH_LOCK(sc); 463 if (sc->ac97rate <= 32000 || sc->ac97rate >= 64000) 464 sc->ac97rate = 48000; 465 ac97rate = sc->ac97rate; 466 ICH_UNLOCK(sc); 467 r = (speed * 48000) / ac97rate; 468 /* 469 * Cast the return value of ac97_setrate() to uint64 so that 470 * the math don't overflow into the negative range. 471 */ 472 ch->spd = ((uint64_t)ac97_setrate(sc->codec, ch->spdreg, r) * 473 ac97rate) / 48000; 474 } else { 475 ch->spd = 48000; 476 } 477 return (ch->spd); 478 } 479 480 static uint32_t 481 ichchan_setblocksize(kobj_t obj, void *data, uint32_t blocksize) 482 { 483 struct sc_chinfo *ch = data; 484 struct sc_info *sc = ch->parent; 485 486 ICH_DEBUG( 487 if (!(sc->flags & ICH_CALIBRATE_DONE)) 488 device_printf(sc->dev, 489 "WARNING: %s() called before calibration!\n", 490 __func__); 491 ); 492 493 if (sc->flags & ICH_HIGH_LATENCY) 494 blocksize = sndbuf_getmaxsize(ch->buffer) / ch->blkcnt; 495 496 if (blocksize < ICH_MIN_BLKSZ) 497 blocksize = ICH_MIN_BLKSZ; 498 blocksize &= ~(ICH_MIN_BLKSZ - 1); 499 ch->blksz = blocksize; 500 ich_filldtbl(ch); 501 ICH_LOCK(sc); 502 ich_wr(sc, ch->regbase + ICH_REG_X_LVI, ch->blkcnt - 1, 1); 503 ICH_UNLOCK(sc); 504 505 return (ch->blksz); 506 } 507 508 static int 509 ichchan_trigger(kobj_t obj, void *data, int go) 510 { 511 struct sc_chinfo *ch = data; 512 struct sc_info *sc = ch->parent; 513 514 ICH_DEBUG( 515 if (!(sc->flags & ICH_CALIBRATE_DONE)) 516 device_printf(sc->dev, 517 "WARNING: %s() called before calibration!\n", 518 __func__); 519 ); 520 521 switch (go) { 522 case PCMTRIG_START: 523 ch->run = 1; 524 ICH_LOCK(sc); 525 ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (uint32_t)(ch->desc_addr), 4); 526 ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RPBM | ICH_X_CR_LVBIE | ICH_X_CR_IOCE, 1); 527 ICH_UNLOCK(sc); 528 break; 529 case PCMTRIG_STOP: 530 case PCMTRIG_ABORT: 531 ICH_LOCK(sc); 532 ich_resetchan(sc, ch->num); 533 ICH_UNLOCK(sc); 534 ch->run = 0; 535 break; 536 default: 537 break; 538 } 539 return (0); 540 } 541 542 static uint32_t 543 ichchan_getptr(kobj_t obj, void *data) 544 { 545 struct sc_chinfo *ch = data; 546 struct sc_info *sc = ch->parent; 547 uint32_t pos; 548 549 ICH_DEBUG( 550 if (!(sc->flags & ICH_CALIBRATE_DONE)) 551 device_printf(sc->dev, 552 "WARNING: %s() called before calibration!\n", 553 __func__); 554 ); 555 556 ICH_LOCK(sc); 557 ch->civ = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1) % ch->blkcnt; 558 ICH_UNLOCK(sc); 559 560 pos = ch->civ * ch->blksz; 561 562 return (pos); 563 } 564 565 static struct pcmchan_caps * 566 ichchan_getcaps(kobj_t obj, void *data) 567 { 568 struct sc_chinfo *ch = data; 569 570 ICH_DEBUG( 571 struct sc_info *sc = ch->parent; 572 573 if (!(sc->flags & ICH_CALIBRATE_DONE)) 574 device_printf(ch->parent->dev, 575 "WARNING: %s() called before calibration!\n", 576 __func__); 577 ); 578 579 return ((ch->spdreg) ? &ich_vrcaps : &ich_caps); 580 } 581 582 static kobj_method_t ichchan_methods[] = { 583 KOBJMETHOD(channel_init, ichchan_init), 584 KOBJMETHOD(channel_setformat, ichchan_setformat), 585 KOBJMETHOD(channel_setspeed, ichchan_setspeed), 586 KOBJMETHOD(channel_setblocksize, ichchan_setblocksize), 587 KOBJMETHOD(channel_trigger, ichchan_trigger), 588 KOBJMETHOD(channel_getptr, ichchan_getptr), 589 KOBJMETHOD(channel_getcaps, ichchan_getcaps), 590 KOBJMETHOD_END 591 }; 592 CHANNEL_DECLARE(ichchan); 593 594 /* -------------------------------------------------------------------- */ 595 /* The interrupt handler */ 596 597 static void 598 ich_intr(void *p) 599 { 600 struct sc_info *sc = (struct sc_info *)p; 601 struct sc_chinfo *ch; 602 uint32_t cbi, lbi, lvi, st, gs; 603 int i; 604 605 ICH_LOCK(sc); 606 607 ICH_DEBUG( 608 if (!(sc->flags & ICH_CALIBRATE_DONE)) 609 device_printf(sc->dev, 610 "WARNING: %s() called before calibration!\n", 611 __func__); 612 ); 613 614 gs = ich_rd(sc, ICH_REG_GLOB_STA, 4) & ICH_GLOB_STA_IMASK; 615 if (gs & (ICH_GLOB_STA_PRES | ICH_GLOB_STA_SRES)) { 616 /* Clear resume interrupt(s) - nothing doing with them */ 617 ich_wr(sc, ICH_REG_GLOB_STA, gs, 4); 618 } 619 gs &= ~(ICH_GLOB_STA_PRES | ICH_GLOB_STA_SRES); 620 621 for (i = 0; i < 3; i++) { 622 ch = &sc->ch[i]; 623 if ((ch->imask & gs) == 0) 624 continue; 625 gs &= ~ch->imask; 626 st = ich_rd(sc, ch->regbase + 627 ((sc->swap_reg) ? ICH_REG_X_PICB : ICH_REG_X_SR), 628 2); 629 st &= ICH_X_SR_FIFOE | ICH_X_SR_BCIS | ICH_X_SR_LVBCI; 630 if (st & (ICH_X_SR_BCIS | ICH_X_SR_LVBCI)) { 631 /* block complete - update buffer */ 632 if (ch->run) { 633 ICH_UNLOCK(sc); 634 chn_intr(ch->channel); 635 ICH_LOCK(sc); 636 } 637 lvi = ich_rd(sc, ch->regbase + ICH_REG_X_LVI, 1); 638 cbi = ch->civ % ch->blkcnt; 639 if (cbi == 0) 640 cbi = ch->blkcnt - 1; 641 else 642 cbi--; 643 lbi = lvi % ch->blkcnt; 644 if (cbi >= lbi) 645 lvi += cbi - lbi; 646 else 647 lvi += cbi + ch->blkcnt - lbi; 648 lvi %= ICH_DTBL_LENGTH; 649 ich_wr(sc, ch->regbase + ICH_REG_X_LVI, lvi, 1); 650 } 651 /* clear status bit */ 652 ich_wr(sc, ch->regbase + 653 ((sc->swap_reg) ? ICH_REG_X_PICB : ICH_REG_X_SR), 654 st, 2); 655 } 656 ICH_UNLOCK(sc); 657 if (gs != 0) { 658 device_printf(sc->dev, 659 "Unhandled interrupt, gs_intr = %x\n", gs); 660 } 661 } 662 663 /* ------------------------------------------------------------------------- */ 664 /* Sysctl to control ac97 speed (some boards appear to end up using 665 * XTAL_IN rather than BIT_CLK for link timing). 666 */ 667 668 static int 669 ich_initsys(struct sc_info* sc) 670 { 671 /* XXX: this should move to a device specific sysctl "dev.pcm.X.yyy" 672 via device_get_sysctl_*() as discussed on multimedia@ in msg-id 673 <861wujij2q.fsf@xps.des.no> */ 674 SYSCTL_ADD_INT(device_get_sysctl_ctx(sc->dev), 675 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), 676 OID_AUTO, "ac97rate", CTLFLAG_RW, 677 &sc->ac97rate, 48000, 678 "AC97 link rate (default = 48000)"); 679 680 return (0); 681 } 682 683 static void 684 ich_setstatus(struct sc_info *sc) 685 { 686 char status[SND_STATUSLEN]; 687 688 snprintf(status, SND_STATUSLEN, 689 "at io 0x%jx, 0x%jx irq %jd bufsz %u %s", 690 rman_get_start(sc->nambar), rman_get_start(sc->nabmbar), 691 rman_get_start(sc->irq), sc->bufsz,PCM_KLDSTRING(snd_ich)); 692 693 if (bootverbose && (sc->flags & ICH_DMA_NOCACHE)) 694 device_printf(sc->dev, 695 "PCI Master abort workaround enabled\n"); 696 697 pcm_setstatus(sc->dev, status); 698 } 699 700 /* -------------------------------------------------------------------- */ 701 /* Calibrate card to determine the clock source. The source maybe a 702 * function of the ac97 codec initialization code (to be investigated). 703 */ 704 705 static void 706 ich_calibrate(void *arg) 707 { 708 struct sc_info *sc; 709 struct sc_chinfo *ch; 710 struct timeval t1, t2; 711 uint8_t ociv, nciv; 712 uint32_t wait_us, actual_48k_rate, oblkcnt; 713 714 sc = (struct sc_info *)arg; 715 ICH_LOCK(sc); 716 ch = &sc->ch[1]; 717 718 if (sc->intrhook.ich_func != NULL) { 719 config_intrhook_disestablish(&sc->intrhook); 720 sc->intrhook.ich_func = NULL; 721 } 722 723 /* 724 * Grab audio from input for fixed interval and compare how 725 * much we actually get with what we expect. Interval needs 726 * to be sufficiently short that no interrupts are 727 * generated. 728 */ 729 730 KASSERT(ch->regbase == ICH_REG_PI_BASE, ("wrong direction")); 731 732 oblkcnt = ch->blkcnt; 733 ch->blkcnt = 2; 734 sc->flags |= ICH_CALIBRATE_DONE; 735 ICH_UNLOCK(sc); 736 ichchan_setblocksize(0, ch, sndbuf_getmaxsize(ch->buffer) >> 1); 737 ICH_LOCK(sc); 738 sc->flags &= ~ICH_CALIBRATE_DONE; 739 740 /* 741 * our data format is stereo, 16 bit so each sample is 4 bytes. 742 * assuming we get 48000 samples per second, we get 192000 bytes/sec. 743 * we're going to start recording with interrupts disabled and measure 744 * the time taken for one block to complete. we know the block size, 745 * we know the time in microseconds, we calculate the sample rate: 746 * 747 * actual_rate [bps] = bytes / (time [s] * 4) 748 * actual_rate [bps] = (bytes * 1000000) / (time [us] * 4) 749 * actual_rate [Hz] = (bytes * 250000) / time [us] 750 */ 751 752 /* prepare */ 753 ociv = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1); 754 nciv = ociv; 755 ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (uint32_t)(ch->desc_addr), 4); 756 757 /* start */ 758 microtime(&t1); 759 ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RPBM, 1); 760 761 /* wait */ 762 do { 763 microtime(&t2); 764 if (t2.tv_sec - t1.tv_sec > 1) 765 break; 766 nciv = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1); 767 } while (nciv == ociv); 768 769 /* stop */ 770 ich_wr(sc, ch->regbase + ICH_REG_X_CR, 0, 1); 771 772 /* reset */ 773 DELAY(100); 774 ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RR, 1); 775 ch->blkcnt = oblkcnt; 776 777 /* turn time delta into us */ 778 wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + t2.tv_usec - t1.tv_usec; 779 780 if (nciv == ociv) { 781 device_printf(sc->dev, "ac97 link rate calibration timed out after %d us\n", wait_us); 782 sc->flags |= ICH_CALIBRATE_DONE; 783 ICH_UNLOCK(sc); 784 ich_setstatus(sc); 785 return; 786 } 787 788 /* Just in case the timecounter screwed. It is possible, really. */ 789 if (wait_us > 0) 790 actual_48k_rate = ((uint64_t)ch->blksz * 250000) / wait_us; 791 else 792 actual_48k_rate = 48000; 793 794 if (actual_48k_rate < 47500 || actual_48k_rate > 48500) { 795 sc->ac97rate = actual_48k_rate; 796 } else { 797 sc->ac97rate = 48000; 798 } 799 800 if (bootverbose || sc->ac97rate != 48000) { 801 device_printf(sc->dev, "measured ac97 link rate at %d Hz", actual_48k_rate); 802 if (sc->ac97rate != actual_48k_rate) 803 printf(", will use %d Hz", sc->ac97rate); 804 printf("\n"); 805 } 806 sc->flags |= ICH_CALIBRATE_DONE; 807 ICH_UNLOCK(sc); 808 809 ich_setstatus(sc); 810 811 return; 812 } 813 814 /* -------------------------------------------------------------------- */ 815 /* Probe and attach the card */ 816 817 static void 818 ich_setmap(void *arg, bus_dma_segment_t *segs, int nseg, int error) 819 { 820 struct sc_info *sc = (struct sc_info *)arg; 821 sc->desc_addr = segs->ds_addr; 822 return; 823 } 824 825 static int 826 ich_init(struct sc_info *sc) 827 { 828 uint32_t stat; 829 830 ich_wr(sc, ICH_REG_GLOB_CNT, ICH_GLOB_CTL_COLD, 4); 831 DELAY(600000); 832 stat = ich_rd(sc, ICH_REG_GLOB_STA, 4); 833 834 if ((stat & ICH_GLOB_STA_PCR) == 0) { 835 /* ICH4/ICH5 may fail when busmastering is enabled. Continue */ 836 if (sc->vendor == INTEL_VENDORID && ( 837 sc->devid == INTEL_82801DB || sc->devid == INTEL_82801EB || 838 sc->devid == INTEL_6300ESB || sc->devid == INTEL_82801FB || 839 sc->devid == INTEL_82801GB)) { 840 sc->flags |= ICH_IGNORE_PCR; 841 device_printf(sc->dev, "primary codec not ready!\n"); 842 } 843 } 844 845 #if 0 846 ich_wr(sc, ICH_REG_GLOB_CNT, ICH_GLOB_CTL_COLD | ICH_GLOB_CTL_PRES, 4); 847 #else 848 ich_wr(sc, ICH_REG_GLOB_CNT, ICH_GLOB_CTL_COLD, 4); 849 #endif 850 851 if (ich_resetchan(sc, 0) || ich_resetchan(sc, 1)) 852 return (ENXIO); 853 if (sc->hasmic && ich_resetchan(sc, 2)) 854 return (ENXIO); 855 856 return (0); 857 } 858 859 static int 860 ich_pci_probe(device_t dev) 861 { 862 int i; 863 uint16_t devid, vendor; 864 865 vendor = pci_get_vendor(dev); 866 devid = pci_get_device(dev); 867 for (i = 0; i < sizeof(ich_devs)/sizeof(ich_devs[0]); i++) { 868 if (vendor == ich_devs[i].vendor && 869 devid == ich_devs[i].devid) { 870 device_set_desc(dev, ich_devs[i].name); 871 /* allow a better driver to override us */ 872 if ((ich_devs[i].options & PROBE_LOW) != 0) 873 return (BUS_PROBE_LOW_PRIORITY); 874 return (BUS_PROBE_DEFAULT); 875 } 876 } 877 return (ENXIO); 878 } 879 880 static int 881 ich_pci_attach(device_t dev) 882 { 883 uint32_t subdev; 884 uint16_t extcaps; 885 uint16_t devid, vendor; 886 struct sc_info *sc; 887 int i; 888 889 sc = malloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO); 890 sc->ich_lock = snd_mtxcreate(device_get_nameunit(dev), "snd_ich softc"); 891 sc->dev = dev; 892 893 vendor = sc->vendor = pci_get_vendor(dev); 894 devid = sc->devid = pci_get_device(dev); 895 subdev = (pci_get_subdevice(dev) << 16) | pci_get_subvendor(dev); 896 /* 897 * The SiS 7012 register set isn't quite like the standard ich. 898 * There really should be a general "quirks" mechanism. 899 */ 900 if (vendor == SIS_VENDORID && devid == SIS_7012) { 901 sc->swap_reg = 1; 902 sc->sample_size = 1; 903 } else { 904 sc->swap_reg = 0; 905 sc->sample_size = 2; 906 } 907 908 /* 909 * Intel 440MX Errata #36 910 * - AC97 Soft Audio and Soft Modem Master Abort Errata 911 * 912 * http://www.intel.com/design/chipsets/specupdt/245051.htm 913 */ 914 if (vendor == INTEL_VENDORID && devid == INTEL_82440MX) 915 sc->flags |= ICH_DMA_NOCACHE; 916 917 /* 918 * Enable bus master. On ich4/5 this may prevent the detection of 919 * the primary codec becoming ready in ich_init(). 920 */ 921 pci_enable_busmaster(dev); 922 923 /* 924 * By default, ich4 has NAMBAR and NABMBAR i/o spaces as 925 * read-only. Need to enable "legacy support", by poking into 926 * pci config space. The driver should use MMBAR and MBBAR, 927 * but doing so will mess things up here. ich4 has enough new 928 * features it warrants it's own driver. 929 */ 930 if (vendor == INTEL_VENDORID && (devid == INTEL_82801DB || 931 devid == INTEL_82801EB || devid == INTEL_6300ESB || 932 devid == INTEL_82801FB || devid == INTEL_82801GB)) { 933 sc->nambarid = PCIR_MMBAR; 934 sc->nabmbarid = PCIR_MBBAR; 935 sc->regtype = SYS_RES_MEMORY; 936 pci_write_config(dev, PCIR_ICH_LEGACY, ICH_LEGACY_ENABLE, 1); 937 } else { 938 sc->nambarid = PCIR_NAMBAR; 939 sc->nabmbarid = PCIR_NABMBAR; 940 sc->regtype = SYS_RES_IOPORT; 941 } 942 943 sc->nambar = bus_alloc_resource_any(dev, sc->regtype, 944 &sc->nambarid, RF_ACTIVE); 945 sc->nabmbar = bus_alloc_resource_any(dev, sc->regtype, 946 &sc->nabmbarid, RF_ACTIVE); 947 948 if (!sc->nambar || !sc->nabmbar) { 949 device_printf(dev, "unable to map IO port space\n"); 950 goto bad; 951 } 952 953 sc->nambart = rman_get_bustag(sc->nambar); 954 sc->nambarh = rman_get_bushandle(sc->nambar); 955 sc->nabmbart = rman_get_bustag(sc->nabmbar); 956 sc->nabmbarh = rman_get_bushandle(sc->nabmbar); 957 958 sc->bufsz = pcm_getbuffersize(dev, 959 ICH_MIN_BUFSZ, ICH_DEFAULT_BUFSZ, ICH_MAX_BUFSZ); 960 961 if (resource_int_value(device_get_name(dev), 962 device_get_unit(dev), "blocksize", &i) == 0 && i > 0) { 963 sc->blkcnt = sc->bufsz / i; 964 i = 0; 965 while (sc->blkcnt >> i) 966 i++; 967 sc->blkcnt = 1 << (i - 1); 968 if (sc->blkcnt < ICH_MIN_BLKCNT) 969 sc->blkcnt = ICH_MIN_BLKCNT; 970 else if (sc->blkcnt > ICH_MAX_BLKCNT) 971 sc->blkcnt = ICH_MAX_BLKCNT; 972 } else 973 sc->blkcnt = ICH_DEFAULT_BLKCNT; 974 975 if (resource_int_value(device_get_name(dev), 976 device_get_unit(dev), "highlatency", &i) == 0 && i != 0) { 977 sc->flags |= ICH_HIGH_LATENCY; 978 sc->blkcnt = ICH_MIN_BLKCNT; 979 } 980 981 if (resource_int_value(device_get_name(dev), 982 device_get_unit(dev), "fixedrate", &i) == 0 && i != 0) 983 sc->flags |= ICH_FIXED_RATE; 984 985 if (resource_int_value(device_get_name(dev), 986 device_get_unit(dev), "micchannel_enabled", &i) == 0 && i != 0) 987 sc->hasmic = 1; 988 989 sc->irqid = 0; 990 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irqid, 991 RF_ACTIVE | RF_SHAREABLE); 992 if (!sc->irq || snd_setup_intr(dev, sc->irq, INTR_MPSAFE, ich_intr, 993 sc, &sc->ih)) { 994 device_printf(dev, "unable to map interrupt\n"); 995 goto bad; 996 } 997 998 if (ich_init(sc)) { 999 device_printf(dev, "unable to initialize the card\n"); 1000 goto bad; 1001 } 1002 1003 sc->codec = AC97_CREATE(dev, sc, ich_ac97); 1004 if (sc->codec == NULL) 1005 goto bad; 1006 1007 /* 1008 * Turn on inverted external amplifier sense flags for few 1009 * 'special' boards. 1010 */ 1011 switch (subdev) { 1012 case 0x202f161f: /* Gateway 7326GZ */ 1013 case 0x203a161f: /* Gateway 4028GZ */ 1014 case 0x203e161f: /* Gateway 3520GZ/M210 */ 1015 case 0x204c161f: /* Kvazar-Micro Senator 3592XT */ 1016 case 0x8144104d: /* Sony VAIO PCG-TR* */ 1017 case 0x8197104d: /* Sony S1XP */ 1018 case 0x81c0104d: /* Sony VAIO type T */ 1019 case 0x81c5104d: /* Sony VAIO VGN B1VP/B1XP */ 1020 case 0x3089103c: /* Compaq Presario B3800 */ 1021 case 0x309a103c: /* HP Compaq nx4300 */ 1022 case 0x82131033: /* NEC VersaPro VJ10F/BH */ 1023 case 0x82be1033: /* NEC VersaPro VJ12F/CH */ 1024 ac97_setflags(sc->codec, ac97_getflags(sc->codec) | AC97_F_EAPD_INV); 1025 break; 1026 default: 1027 break; 1028 } 1029 1030 mixer_init(dev, ac97_getmixerclass(), sc->codec); 1031 1032 /* check and set VRA function */ 1033 extcaps = ac97_getextcaps(sc->codec); 1034 sc->hasvra = extcaps & AC97_EXTCAP_VRA; 1035 sc->hasvrm = extcaps & AC97_EXTCAP_VRM; 1036 sc->hasmic = (sc->hasmic != 0 && 1037 (ac97_getcaps(sc->codec) & AC97_CAP_MICCHANNEL)) ? 1 : 0; 1038 ac97_setextmode(sc->codec, sc->hasvra | sc->hasvrm); 1039 1040 sc->dtbl_size = sizeof(struct ich_desc) * ICH_DTBL_LENGTH * 1041 ((sc->hasmic) ? 3 : 2); 1042 1043 /* BDL tag */ 1044 if (bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0, 1045 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1046 sc->dtbl_size, 1, 0x3ffff, 0, NULL, NULL, &sc->dmat) != 0) { 1047 device_printf(dev, "unable to create dma tag\n"); 1048 goto bad; 1049 } 1050 1051 /* PCM channel tag */ 1052 if (bus_dma_tag_create(bus_get_dma_tag(dev), ICH_MIN_BLKSZ, 0, 1053 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1054 sc->bufsz, 1, 0x3ffff, 0, NULL, NULL, &sc->chan_dmat) != 0) { 1055 device_printf(dev, "unable to create dma tag\n"); 1056 goto bad; 1057 } 1058 1059 if (bus_dmamem_alloc(sc->dmat, (void **)&sc->dtbl, BUS_DMA_NOWAIT | 1060 ((sc->flags & ICH_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0), 1061 &sc->dtmap)) 1062 goto bad; 1063 1064 if (bus_dmamap_load(sc->dmat, sc->dtmap, sc->dtbl, sc->dtbl_size, 1065 ich_setmap, sc, 0)) 1066 goto bad; 1067 1068 if (pcm_register(dev, sc, 1, (sc->hasmic) ? 2 : 1)) 1069 goto bad; 1070 1071 pcm_addchan(dev, PCMDIR_PLAY, &ichchan_class, sc); /* play */ 1072 pcm_addchan(dev, PCMDIR_REC, &ichchan_class, sc); /* record */ 1073 if (sc->hasmic) 1074 pcm_addchan(dev, PCMDIR_REC, &ichchan_class, sc); /* record mic */ 1075 1076 if (sc->flags & ICH_FIXED_RATE) { 1077 sc->flags |= ICH_CALIBRATE_DONE; 1078 ich_setstatus(sc); 1079 } else { 1080 ich_initsys(sc); 1081 1082 sc->intrhook.ich_func = ich_calibrate; 1083 sc->intrhook.ich_arg = sc; 1084 if (cold == 0 || 1085 config_intrhook_establish(&sc->intrhook) != 0) { 1086 sc->intrhook.ich_func = NULL; 1087 ich_calibrate(sc); 1088 } 1089 } 1090 1091 return (0); 1092 1093 bad: 1094 if (sc->codec) 1095 ac97_destroy(sc->codec); 1096 if (sc->ih) 1097 bus_teardown_intr(dev, sc->irq, sc->ih); 1098 if (sc->irq) 1099 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); 1100 if (sc->nambar) 1101 bus_release_resource(dev, sc->regtype, 1102 sc->nambarid, sc->nambar); 1103 if (sc->nabmbar) 1104 bus_release_resource(dev, sc->regtype, 1105 sc->nabmbarid, sc->nabmbar); 1106 if (sc->dtmap) 1107 bus_dmamap_unload(sc->dmat, sc->dtmap); 1108 if (sc->dtbl) 1109 bus_dmamem_free(sc->dmat, sc->dtbl, sc->dtmap); 1110 if (sc->chan_dmat) 1111 bus_dma_tag_destroy(sc->chan_dmat); 1112 if (sc->dmat) 1113 bus_dma_tag_destroy(sc->dmat); 1114 if (sc->ich_lock) 1115 snd_mtxfree(sc->ich_lock); 1116 free(sc, M_DEVBUF); 1117 return (ENXIO); 1118 } 1119 1120 static int 1121 ich_pci_detach(device_t dev) 1122 { 1123 struct sc_info *sc; 1124 int r; 1125 1126 r = pcm_unregister(dev); 1127 if (r) 1128 return (r); 1129 sc = pcm_getdevinfo(dev); 1130 1131 bus_teardown_intr(dev, sc->irq, sc->ih); 1132 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); 1133 bus_release_resource(dev, sc->regtype, sc->nambarid, sc->nambar); 1134 bus_release_resource(dev, sc->regtype, sc->nabmbarid, sc->nabmbar); 1135 bus_dmamap_unload(sc->dmat, sc->dtmap); 1136 bus_dmamem_free(sc->dmat, sc->dtbl, sc->dtmap); 1137 bus_dma_tag_destroy(sc->chan_dmat); 1138 bus_dma_tag_destroy(sc->dmat); 1139 snd_mtxfree(sc->ich_lock); 1140 free(sc, M_DEVBUF); 1141 return (0); 1142 } 1143 1144 static void 1145 ich_pci_codec_reset(struct sc_info *sc) 1146 { 1147 int i; 1148 uint32_t control; 1149 1150 control = ich_rd(sc, ICH_REG_GLOB_CNT, 4); 1151 control &= ~(ICH_GLOB_CTL_SHUT); 1152 control |= (control & ICH_GLOB_CTL_COLD) ? 1153 ICH_GLOB_CTL_WARM : ICH_GLOB_CTL_COLD; 1154 ich_wr(sc, ICH_REG_GLOB_CNT, control, 4); 1155 1156 for (i = 500000; i; i--) { 1157 if (ich_rd(sc, ICH_REG_GLOB_STA, 4) & ICH_GLOB_STA_PCR) 1158 break; /* or ICH_SCR? */ 1159 DELAY(1); 1160 } 1161 1162 if (i <= 0) 1163 printf("%s: time out\n", __func__); 1164 } 1165 1166 static int 1167 ich_pci_suspend(device_t dev) 1168 { 1169 struct sc_info *sc; 1170 int i; 1171 1172 sc = pcm_getdevinfo(dev); 1173 ICH_LOCK(sc); 1174 for (i = 0 ; i < 3; i++) { 1175 sc->ch[i].run_save = sc->ch[i].run; 1176 if (sc->ch[i].run) { 1177 ICH_UNLOCK(sc); 1178 ichchan_trigger(0, &sc->ch[i], PCMTRIG_ABORT); 1179 ICH_LOCK(sc); 1180 } 1181 } 1182 ICH_UNLOCK(sc); 1183 return (0); 1184 } 1185 1186 static int 1187 ich_pci_resume(device_t dev) 1188 { 1189 struct sc_info *sc; 1190 int err, i; 1191 1192 sc = pcm_getdevinfo(dev); 1193 1194 ICH_LOCK(sc); 1195 /* Reinit audio device */ 1196 err = ich_init(sc); 1197 if (err != 0) { 1198 device_printf(dev, "unable to reinitialize the card\n"); 1199 ICH_UNLOCK(sc); 1200 return (err); 1201 } 1202 /* Reinit mixer */ 1203 ich_pci_codec_reset(sc); 1204 ICH_UNLOCK(sc); 1205 ac97_setextmode(sc->codec, sc->hasvra | sc->hasvrm); 1206 if (mixer_reinit(dev) == -1) { 1207 device_printf(dev, "unable to reinitialize the mixer\n"); 1208 return (ENXIO); 1209 } 1210 /* Re-start DMA engines */ 1211 for (i = 0 ; i < 3; i++) { 1212 struct sc_chinfo *ch = &sc->ch[i]; 1213 if (sc->ch[i].run_save) { 1214 ichchan_setblocksize(0, ch, ch->blksz); 1215 ichchan_setspeed(0, ch, ch->spd); 1216 ichchan_trigger(0, ch, PCMTRIG_START); 1217 } 1218 } 1219 return (0); 1220 } 1221 1222 static device_method_t ich_methods[] = { 1223 /* Device interface */ 1224 DEVMETHOD(device_probe, ich_pci_probe), 1225 DEVMETHOD(device_attach, ich_pci_attach), 1226 DEVMETHOD(device_detach, ich_pci_detach), 1227 DEVMETHOD(device_suspend, ich_pci_suspend), 1228 DEVMETHOD(device_resume, ich_pci_resume), 1229 { 0, 0 } 1230 }; 1231 1232 static driver_t ich_driver = { 1233 "pcm", 1234 ich_methods, 1235 PCM_SOFTC_SIZE, 1236 }; 1237 1238 DRIVER_MODULE(snd_ich, pci, ich_driver, 0, 0); 1239 MODULE_DEPEND(snd_ich, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 1240 MODULE_VERSION(snd_ich, 1); 1241