1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2000 Katsurajima Naoto <raven@katsurajima.seya.yokohama.jp> 5 * Copyright (c) 2001 Cameron Grant <cg@freebsd.org> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #ifdef HAVE_KERNEL_OPTION_HEADERS 31 #include "opt_snd.h" 32 #endif 33 34 #include <dev/sound/pcm/sound.h> 35 #include <dev/sound/pcm/ac97.h> 36 #include <dev/sound/pci/ich.h> 37 38 #include <dev/pci/pcireg.h> 39 #include <dev/pci/pcivar.h> 40 41 SND_DECLARE_FILE("$FreeBSD$"); 42 43 /* -------------------------------------------------------------------- */ 44 45 #define ICH_TIMEOUT 1000 /* semaphore timeout polling count */ 46 #define ICH_DTBL_LENGTH 32 47 #define ICH_DEFAULT_BUFSZ 16384 48 #define ICH_MAX_BUFSZ 65536 49 #define ICH_MIN_BUFSZ 4096 50 #define ICH_DEFAULT_BLKCNT 2 51 #define ICH_MAX_BLKCNT 32 52 #define ICH_MIN_BLKCNT 2 53 #define ICH_MIN_BLKSZ 64 54 55 #define INTEL_VENDORID 0x8086 56 #define SIS_VENDORID 0x1039 57 #define NVIDIA_VENDORID 0x10de 58 #define AMD_VENDORID 0x1022 59 60 #define INTEL_82440MX 0x7195 61 #define INTEL_82801AA 0x2415 62 #define INTEL_82801AB 0x2425 63 #define INTEL_82801BA 0x2445 64 #define INTEL_82801CA 0x2485 65 #define INTEL_82801DB 0x24c5 /* ICH4 needs special handling */ 66 #define INTEL_82801EB 0x24d5 /* ICH5 needs to be treated as ICH4 */ 67 #define INTEL_6300ESB 0x25a6 /* 6300ESB needs to be treated as ICH4 */ 68 #define INTEL_82801FB 0x266e /* ICH6 needs to be treated as ICH4 */ 69 #define INTEL_82801GB 0x27de /* ICH7 needs to be treated as ICH4 */ 70 #define SIS_7012 0x7012 /* SiS 7012 needs special handling */ 71 #define NVIDIA_NFORCE 0x01b1 72 #define NVIDIA_NFORCE2 0x006a 73 #define NVIDIA_NFORCE2_400 0x008a 74 #define NVIDIA_NFORCE3 0x00da 75 #define NVIDIA_NFORCE3_250 0x00ea 76 #define NVIDIA_NFORCE4 0x0059 77 #define NVIDIA_NFORCE_410_MCP 0x026b 78 #define NVIDIA_NFORCE4_MCP 0x003a 79 #define AMD_768 0x7445 80 #define AMD_8111 0x746d 81 82 #define ICH_LOCK(sc) snd_mtxlock((sc)->ich_lock) 83 #define ICH_UNLOCK(sc) snd_mtxunlock((sc)->ich_lock) 84 #define ICH_LOCK_ASSERT(sc) snd_mtxassert((sc)->ich_lock) 85 86 #if 0 87 #define ICH_DEBUG(stmt) do { \ 88 stmt \ 89 } while (0) 90 #else 91 #define ICH_DEBUG(...) 92 #endif 93 94 #define ICH_CALIBRATE_DONE (1 << 0) 95 #define ICH_IGNORE_PCR (1 << 1) 96 #define ICH_IGNORE_RESET (1 << 2) 97 #define ICH_FIXED_RATE (1 << 3) 98 #define ICH_DMA_NOCACHE (1 << 4) 99 #define ICH_HIGH_LATENCY (1 << 5) 100 101 static const struct ich_type { 102 uint16_t vendor; 103 uint16_t devid; 104 uint32_t options; 105 #define PROBE_LOW 0x01 106 char *name; 107 } ich_devs[] = { 108 { INTEL_VENDORID, INTEL_82440MX, 0, 109 "Intel 440MX" }, 110 { INTEL_VENDORID, INTEL_82801AA, 0, 111 "Intel ICH (82801AA)" }, 112 { INTEL_VENDORID, INTEL_82801AB, 0, 113 "Intel ICH (82801AB)" }, 114 { INTEL_VENDORID, INTEL_82801BA, 0, 115 "Intel ICH2 (82801BA)" }, 116 { INTEL_VENDORID, INTEL_82801CA, 0, 117 "Intel ICH3 (82801CA)" }, 118 { INTEL_VENDORID, INTEL_82801DB, PROBE_LOW, 119 "Intel ICH4 (82801DB)" }, 120 { INTEL_VENDORID, INTEL_82801EB, PROBE_LOW, 121 "Intel ICH5 (82801EB)" }, 122 { INTEL_VENDORID, INTEL_6300ESB, PROBE_LOW, 123 "Intel 6300ESB" }, 124 { INTEL_VENDORID, INTEL_82801FB, PROBE_LOW, 125 "Intel ICH6 (82801FB)" }, 126 { INTEL_VENDORID, INTEL_82801GB, PROBE_LOW, 127 "Intel ICH7 (82801GB)" }, 128 { SIS_VENDORID, SIS_7012, 0, 129 "SiS 7012" }, 130 { NVIDIA_VENDORID, NVIDIA_NFORCE, 0, 131 "nVidia nForce" }, 132 { NVIDIA_VENDORID, NVIDIA_NFORCE2, 0, 133 "nVidia nForce2" }, 134 { NVIDIA_VENDORID, NVIDIA_NFORCE2_400, 0, 135 "nVidia nForce2 400" }, 136 { NVIDIA_VENDORID, NVIDIA_NFORCE3, 0, 137 "nVidia nForce3" }, 138 { NVIDIA_VENDORID, NVIDIA_NFORCE3_250, 0, 139 "nVidia nForce3 250" }, 140 { NVIDIA_VENDORID, NVIDIA_NFORCE4, 0, 141 "nVidia nForce4" }, 142 { NVIDIA_VENDORID, NVIDIA_NFORCE_410_MCP, 0, 143 "nVidia nForce 410 MCP" }, 144 { NVIDIA_VENDORID, NVIDIA_NFORCE4_MCP, 0, 145 "nVidia nForce 4 MCP" }, 146 { AMD_VENDORID, AMD_768, 0, 147 "AMD-768" }, 148 { AMD_VENDORID, AMD_8111, 0, 149 "AMD-8111" } 150 }; 151 152 /* buffer descriptor */ 153 struct ich_desc { 154 volatile uint32_t buffer; 155 volatile uint32_t length; 156 }; 157 158 struct sc_info; 159 160 /* channel registers */ 161 struct sc_chinfo { 162 uint32_t num:8, run:1, run_save:1; 163 uint32_t blksz, blkcnt, spd; 164 uint32_t regbase, spdreg; 165 uint32_t imask; 166 uint32_t civ; 167 168 struct snd_dbuf *buffer; 169 struct pcm_channel *channel; 170 struct sc_info *parent; 171 172 struct ich_desc *dtbl; 173 bus_addr_t desc_addr; 174 }; 175 176 /* device private data */ 177 struct sc_info { 178 device_t dev; 179 int hasvra, hasvrm, hasmic; 180 unsigned int chnum, bufsz, blkcnt; 181 int sample_size, swap_reg; 182 183 struct resource *nambar, *nabmbar, *irq; 184 int regtype, nambarid, nabmbarid, irqid; 185 bus_space_tag_t nambart, nabmbart; 186 bus_space_handle_t nambarh, nabmbarh; 187 bus_dma_tag_t dmat, chan_dmat; 188 bus_dmamap_t dtmap; 189 void *ih; 190 191 struct ac97_info *codec; 192 struct sc_chinfo ch[3]; 193 int ac97rate; 194 struct ich_desc *dtbl; 195 unsigned int dtbl_size; 196 bus_addr_t desc_addr; 197 struct intr_config_hook intrhook; 198 uint16_t vendor; 199 uint16_t devid; 200 uint32_t flags; 201 struct mtx *ich_lock; 202 }; 203 204 /* -------------------------------------------------------------------- */ 205 206 static uint32_t ich_fmt[] = { 207 SND_FORMAT(AFMT_S16_LE, 2, 0), 208 0 209 }; 210 static struct pcmchan_caps ich_vrcaps = {8000, 48000, ich_fmt, 0}; 211 static struct pcmchan_caps ich_caps = {48000, 48000, ich_fmt, 0}; 212 213 /* -------------------------------------------------------------------- */ 214 /* Hardware */ 215 static __inline uint32_t 216 ich_rd(struct sc_info *sc, int regno, int size) 217 { 218 switch (size) { 219 case 1: 220 return (bus_space_read_1(sc->nabmbart, sc->nabmbarh, regno)); 221 case 2: 222 return (bus_space_read_2(sc->nabmbart, sc->nabmbarh, regno)); 223 case 4: 224 return (bus_space_read_4(sc->nabmbart, sc->nabmbarh, regno)); 225 default: 226 return (0xffffffff); 227 } 228 } 229 230 static __inline void 231 ich_wr(struct sc_info *sc, int regno, uint32_t data, int size) 232 { 233 switch (size) { 234 case 1: 235 bus_space_write_1(sc->nabmbart, sc->nabmbarh, regno, data); 236 break; 237 case 2: 238 bus_space_write_2(sc->nabmbart, sc->nabmbarh, regno, data); 239 break; 240 case 4: 241 bus_space_write_4(sc->nabmbart, sc->nabmbarh, regno, data); 242 break; 243 } 244 } 245 246 /* ac97 codec */ 247 static int 248 ich_waitcd(void *devinfo) 249 { 250 struct sc_info *sc = (struct sc_info *)devinfo; 251 uint32_t data; 252 int i; 253 254 for (i = 0; i < ICH_TIMEOUT; i++) { 255 data = ich_rd(sc, ICH_REG_ACC_SEMA, 1); 256 if ((data & 0x01) == 0) 257 return (0); 258 DELAY(1); 259 } 260 if ((sc->flags & ICH_IGNORE_PCR) != 0) 261 return (0); 262 device_printf(sc->dev, "CODEC semaphore timeout\n"); 263 return (ETIMEDOUT); 264 } 265 266 static int 267 ich_rdcd(kobj_t obj, void *devinfo, int regno) 268 { 269 struct sc_info *sc = (struct sc_info *)devinfo; 270 271 regno &= 0xff; 272 ich_waitcd(sc); 273 274 return (bus_space_read_2(sc->nambart, sc->nambarh, regno)); 275 } 276 277 static int 278 ich_wrcd(kobj_t obj, void *devinfo, int regno, uint32_t data) 279 { 280 struct sc_info *sc = (struct sc_info *)devinfo; 281 282 regno &= 0xff; 283 ich_waitcd(sc); 284 bus_space_write_2(sc->nambart, sc->nambarh, regno, data); 285 286 return (0); 287 } 288 289 static kobj_method_t ich_ac97_methods[] = { 290 KOBJMETHOD(ac97_read, ich_rdcd), 291 KOBJMETHOD(ac97_write, ich_wrcd), 292 KOBJMETHOD_END 293 }; 294 AC97_DECLARE(ich_ac97); 295 296 /* -------------------------------------------------------------------- */ 297 /* common routines */ 298 299 static void 300 ich_filldtbl(struct sc_chinfo *ch) 301 { 302 struct sc_info *sc = ch->parent; 303 uint32_t base; 304 int i; 305 306 base = sndbuf_getbufaddr(ch->buffer); 307 if ((ch->blksz * ch->blkcnt) > sndbuf_getmaxsize(ch->buffer)) 308 ch->blksz = sndbuf_getmaxsize(ch->buffer) / ch->blkcnt; 309 if ((sndbuf_getblksz(ch->buffer) != ch->blksz || 310 sndbuf_getblkcnt(ch->buffer) != ch->blkcnt) && 311 sndbuf_resize(ch->buffer, ch->blkcnt, ch->blksz) != 0) 312 device_printf(sc->dev, "%s: failed blksz=%u blkcnt=%u\n", 313 __func__, ch->blksz, ch->blkcnt); 314 ch->blksz = sndbuf_getblksz(ch->buffer); 315 316 for (i = 0; i < ICH_DTBL_LENGTH; i++) { 317 ch->dtbl[i].buffer = base + (ch->blksz * (i % ch->blkcnt)); 318 ch->dtbl[i].length = ICH_BDC_IOC 319 | (ch->blksz / ch->parent->sample_size); 320 } 321 } 322 323 static int 324 ich_resetchan(struct sc_info *sc, int num) 325 { 326 int i, cr, regbase; 327 328 if (num == 0) 329 regbase = ICH_REG_PO_BASE; 330 else if (num == 1) 331 regbase = ICH_REG_PI_BASE; 332 else if (num == 2) 333 regbase = ICH_REG_MC_BASE; 334 else 335 return (ENXIO); 336 337 ich_wr(sc, regbase + ICH_REG_X_CR, 0, 1); 338 #if 1 339 /* This may result in no sound output on NForce 2 MBs, see PR 73987 */ 340 DELAY(100); 341 #else 342 (void)ich_rd(sc, regbase + ICH_REG_X_CR, 1); 343 #endif 344 ich_wr(sc, regbase + ICH_REG_X_CR, ICH_X_CR_RR, 1); 345 for (i = 0; i < ICH_TIMEOUT; i++) { 346 cr = ich_rd(sc, regbase + ICH_REG_X_CR, 1); 347 if (cr == 0) 348 return (0); 349 DELAY(1); 350 } 351 352 if (sc->flags & ICH_IGNORE_RESET) 353 return (0); 354 #if 0 355 else if (sc->vendor == NVIDIA_VENDORID) { 356 sc->flags |= ICH_IGNORE_RESET; 357 device_printf(sc->dev, "ignoring reset failure!\n"); 358 return (0); 359 } 360 #endif 361 362 device_printf(sc->dev, "cannot reset channel %d\n", num); 363 return (ENXIO); 364 } 365 366 /* -------------------------------------------------------------------- */ 367 /* channel interface */ 368 369 static void * 370 ichchan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir) 371 { 372 struct sc_info *sc = devinfo; 373 struct sc_chinfo *ch; 374 unsigned int num; 375 376 ICH_LOCK(sc); 377 num = sc->chnum++; 378 ch = &sc->ch[num]; 379 ch->num = num; 380 ch->buffer = b; 381 ch->channel = c; 382 ch->parent = sc; 383 ch->run = 0; 384 ch->dtbl = sc->dtbl + (ch->num * ICH_DTBL_LENGTH); 385 ch->desc_addr = sc->desc_addr + 386 (ch->num * ICH_DTBL_LENGTH * sizeof(struct ich_desc)); 387 ch->blkcnt = sc->blkcnt; 388 ch->blksz = sc->bufsz / ch->blkcnt; 389 390 switch(ch->num) { 391 case 0: /* play */ 392 KASSERT(dir == PCMDIR_PLAY, ("wrong direction")); 393 ch->regbase = ICH_REG_PO_BASE; 394 ch->spdreg = (sc->hasvra) ? AC97_REGEXT_FDACRATE : 0; 395 ch->imask = ICH_GLOB_STA_POINT; 396 break; 397 398 case 1: /* record */ 399 KASSERT(dir == PCMDIR_REC, ("wrong direction")); 400 ch->regbase = ICH_REG_PI_BASE; 401 ch->spdreg = (sc->hasvra) ? AC97_REGEXT_LADCRATE : 0; 402 ch->imask = ICH_GLOB_STA_PIINT; 403 break; 404 405 case 2: /* mic */ 406 KASSERT(dir == PCMDIR_REC, ("wrong direction")); 407 ch->regbase = ICH_REG_MC_BASE; 408 ch->spdreg = (sc->hasvrm) ? AC97_REGEXT_MADCRATE : 0; 409 ch->imask = ICH_GLOB_STA_MINT; 410 break; 411 412 default: 413 return (NULL); 414 } 415 416 if (sc->flags & ICH_FIXED_RATE) 417 ch->spdreg = 0; 418 419 ICH_UNLOCK(sc); 420 if (sndbuf_alloc(ch->buffer, sc->chan_dmat, 421 ((sc->flags & ICH_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0), 422 sc->bufsz) != 0) 423 return (NULL); 424 425 ICH_LOCK(sc); 426 ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (uint32_t)(ch->desc_addr), 4); 427 ICH_UNLOCK(sc); 428 429 return (ch); 430 } 431 432 static int 433 ichchan_setformat(kobj_t obj, void *data, uint32_t format) 434 { 435 436 ICH_DEBUG( 437 struct sc_chinfo *ch = data; 438 struct sc_info *sc = ch->parent; 439 if (!(sc->flags & ICH_CALIBRATE_DONE)) 440 device_printf(sc->dev, 441 "WARNING: %s() called before calibration!\n", 442 __func__); 443 ); 444 445 return (0); 446 } 447 448 static uint32_t 449 ichchan_setspeed(kobj_t obj, void *data, uint32_t speed) 450 { 451 struct sc_chinfo *ch = data; 452 struct sc_info *sc = ch->parent; 453 454 ICH_DEBUG( 455 if (!(sc->flags & ICH_CALIBRATE_DONE)) 456 device_printf(sc->dev, 457 "WARNING: %s() called before calibration!\n", 458 __func__); 459 ); 460 461 if (ch->spdreg) { 462 int r, ac97rate; 463 464 ICH_LOCK(sc); 465 if (sc->ac97rate <= 32000 || sc->ac97rate >= 64000) 466 sc->ac97rate = 48000; 467 ac97rate = sc->ac97rate; 468 ICH_UNLOCK(sc); 469 r = (speed * 48000) / ac97rate; 470 /* 471 * Cast the return value of ac97_setrate() to uint64 so that 472 * the math don't overflow into the negative range. 473 */ 474 ch->spd = ((uint64_t)ac97_setrate(sc->codec, ch->spdreg, r) * 475 ac97rate) / 48000; 476 } else { 477 ch->spd = 48000; 478 } 479 return (ch->spd); 480 } 481 482 static uint32_t 483 ichchan_setblocksize(kobj_t obj, void *data, uint32_t blocksize) 484 { 485 struct sc_chinfo *ch = data; 486 struct sc_info *sc = ch->parent; 487 488 ICH_DEBUG( 489 if (!(sc->flags & ICH_CALIBRATE_DONE)) 490 device_printf(sc->dev, 491 "WARNING: %s() called before calibration!\n", 492 __func__); 493 ); 494 495 if (sc->flags & ICH_HIGH_LATENCY) 496 blocksize = sndbuf_getmaxsize(ch->buffer) / ch->blkcnt; 497 498 if (blocksize < ICH_MIN_BLKSZ) 499 blocksize = ICH_MIN_BLKSZ; 500 blocksize &= ~(ICH_MIN_BLKSZ - 1); 501 ch->blksz = blocksize; 502 ich_filldtbl(ch); 503 ICH_LOCK(sc); 504 ich_wr(sc, ch->regbase + ICH_REG_X_LVI, ch->blkcnt - 1, 1); 505 ICH_UNLOCK(sc); 506 507 return (ch->blksz); 508 } 509 510 static int 511 ichchan_trigger(kobj_t obj, void *data, int go) 512 { 513 struct sc_chinfo *ch = data; 514 struct sc_info *sc = ch->parent; 515 516 ICH_DEBUG( 517 if (!(sc->flags & ICH_CALIBRATE_DONE)) 518 device_printf(sc->dev, 519 "WARNING: %s() called before calibration!\n", 520 __func__); 521 ); 522 523 switch (go) { 524 case PCMTRIG_START: 525 ch->run = 1; 526 ICH_LOCK(sc); 527 ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (uint32_t)(ch->desc_addr), 4); 528 ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RPBM | ICH_X_CR_LVBIE | ICH_X_CR_IOCE, 1); 529 ICH_UNLOCK(sc); 530 break; 531 case PCMTRIG_STOP: 532 case PCMTRIG_ABORT: 533 ICH_LOCK(sc); 534 ich_resetchan(sc, ch->num); 535 ICH_UNLOCK(sc); 536 ch->run = 0; 537 break; 538 default: 539 break; 540 } 541 return (0); 542 } 543 544 static uint32_t 545 ichchan_getptr(kobj_t obj, void *data) 546 { 547 struct sc_chinfo *ch = data; 548 struct sc_info *sc = ch->parent; 549 uint32_t pos; 550 551 ICH_DEBUG( 552 if (!(sc->flags & ICH_CALIBRATE_DONE)) 553 device_printf(sc->dev, 554 "WARNING: %s() called before calibration!\n", 555 __func__); 556 ); 557 558 ICH_LOCK(sc); 559 ch->civ = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1) % ch->blkcnt; 560 ICH_UNLOCK(sc); 561 562 pos = ch->civ * ch->blksz; 563 564 return (pos); 565 } 566 567 static struct pcmchan_caps * 568 ichchan_getcaps(kobj_t obj, void *data) 569 { 570 struct sc_chinfo *ch = data; 571 572 ICH_DEBUG( 573 struct sc_info *sc = ch->parent; 574 575 if (!(sc->flags & ICH_CALIBRATE_DONE)) 576 device_printf(ch->parent->dev, 577 "WARNING: %s() called before calibration!\n", 578 __func__); 579 ); 580 581 return ((ch->spdreg) ? &ich_vrcaps : &ich_caps); 582 } 583 584 static kobj_method_t ichchan_methods[] = { 585 KOBJMETHOD(channel_init, ichchan_init), 586 KOBJMETHOD(channel_setformat, ichchan_setformat), 587 KOBJMETHOD(channel_setspeed, ichchan_setspeed), 588 KOBJMETHOD(channel_setblocksize, ichchan_setblocksize), 589 KOBJMETHOD(channel_trigger, ichchan_trigger), 590 KOBJMETHOD(channel_getptr, ichchan_getptr), 591 KOBJMETHOD(channel_getcaps, ichchan_getcaps), 592 KOBJMETHOD_END 593 }; 594 CHANNEL_DECLARE(ichchan); 595 596 /* -------------------------------------------------------------------- */ 597 /* The interrupt handler */ 598 599 static void 600 ich_intr(void *p) 601 { 602 struct sc_info *sc = (struct sc_info *)p; 603 struct sc_chinfo *ch; 604 uint32_t cbi, lbi, lvi, st, gs; 605 int i; 606 607 ICH_LOCK(sc); 608 609 ICH_DEBUG( 610 if (!(sc->flags & ICH_CALIBRATE_DONE)) 611 device_printf(sc->dev, 612 "WARNING: %s() called before calibration!\n", 613 __func__); 614 ); 615 616 gs = ich_rd(sc, ICH_REG_GLOB_STA, 4) & ICH_GLOB_STA_IMASK; 617 if (gs & (ICH_GLOB_STA_PRES | ICH_GLOB_STA_SRES)) { 618 /* Clear resume interrupt(s) - nothing doing with them */ 619 ich_wr(sc, ICH_REG_GLOB_STA, gs, 4); 620 } 621 gs &= ~(ICH_GLOB_STA_PRES | ICH_GLOB_STA_SRES); 622 623 for (i = 0; i < 3; i++) { 624 ch = &sc->ch[i]; 625 if ((ch->imask & gs) == 0) 626 continue; 627 gs &= ~ch->imask; 628 st = ich_rd(sc, ch->regbase + 629 ((sc->swap_reg) ? ICH_REG_X_PICB : ICH_REG_X_SR), 630 2); 631 st &= ICH_X_SR_FIFOE | ICH_X_SR_BCIS | ICH_X_SR_LVBCI; 632 if (st & (ICH_X_SR_BCIS | ICH_X_SR_LVBCI)) { 633 /* block complete - update buffer */ 634 if (ch->run) { 635 ICH_UNLOCK(sc); 636 chn_intr(ch->channel); 637 ICH_LOCK(sc); 638 } 639 lvi = ich_rd(sc, ch->regbase + ICH_REG_X_LVI, 1); 640 cbi = ch->civ % ch->blkcnt; 641 if (cbi == 0) 642 cbi = ch->blkcnt - 1; 643 else 644 cbi--; 645 lbi = lvi % ch->blkcnt; 646 if (cbi >= lbi) 647 lvi += cbi - lbi; 648 else 649 lvi += cbi + ch->blkcnt - lbi; 650 lvi %= ICH_DTBL_LENGTH; 651 ich_wr(sc, ch->regbase + ICH_REG_X_LVI, lvi, 1); 652 } 653 /* clear status bit */ 654 ich_wr(sc, ch->regbase + 655 ((sc->swap_reg) ? ICH_REG_X_PICB : ICH_REG_X_SR), 656 st, 2); 657 } 658 ICH_UNLOCK(sc); 659 if (gs != 0) { 660 device_printf(sc->dev, 661 "Unhandled interrupt, gs_intr = %x\n", gs); 662 } 663 } 664 665 /* ------------------------------------------------------------------------- */ 666 /* Sysctl to control ac97 speed (some boards appear to end up using 667 * XTAL_IN rather than BIT_CLK for link timing). 668 */ 669 670 static int 671 ich_initsys(struct sc_info* sc) 672 { 673 /* XXX: this should move to a device specific sysctl "dev.pcm.X.yyy" 674 via device_get_sysctl_*() as discussed on multimedia@ in msg-id 675 <861wujij2q.fsf@xps.des.no> */ 676 SYSCTL_ADD_INT(device_get_sysctl_ctx(sc->dev), 677 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), 678 OID_AUTO, "ac97rate", CTLFLAG_RW, 679 &sc->ac97rate, 48000, 680 "AC97 link rate (default = 48000)"); 681 682 return (0); 683 } 684 685 static void 686 ich_setstatus(struct sc_info *sc) 687 { 688 char status[SND_STATUSLEN]; 689 690 snprintf(status, SND_STATUSLEN, 691 "at io 0x%jx, 0x%jx irq %jd bufsz %u %s", 692 rman_get_start(sc->nambar), rman_get_start(sc->nabmbar), 693 rman_get_start(sc->irq), sc->bufsz,PCM_KLDSTRING(snd_ich)); 694 695 if (bootverbose && (sc->flags & ICH_DMA_NOCACHE)) 696 device_printf(sc->dev, 697 "PCI Master abort workaround enabled\n"); 698 699 pcm_setstatus(sc->dev, status); 700 } 701 702 /* -------------------------------------------------------------------- */ 703 /* Calibrate card to determine the clock source. The source maybe a 704 * function of the ac97 codec initialization code (to be investigated). 705 */ 706 707 static void 708 ich_calibrate(void *arg) 709 { 710 struct sc_info *sc; 711 struct sc_chinfo *ch; 712 struct timeval t1, t2; 713 uint8_t ociv, nciv; 714 uint32_t wait_us, actual_48k_rate, oblkcnt; 715 716 sc = (struct sc_info *)arg; 717 ICH_LOCK(sc); 718 ch = &sc->ch[1]; 719 720 if (sc->intrhook.ich_func != NULL) { 721 config_intrhook_disestablish(&sc->intrhook); 722 sc->intrhook.ich_func = NULL; 723 } 724 725 /* 726 * Grab audio from input for fixed interval and compare how 727 * much we actually get with what we expect. Interval needs 728 * to be sufficiently short that no interrupts are 729 * generated. 730 */ 731 732 KASSERT(ch->regbase == ICH_REG_PI_BASE, ("wrong direction")); 733 734 oblkcnt = ch->blkcnt; 735 ch->blkcnt = 2; 736 sc->flags |= ICH_CALIBRATE_DONE; 737 ICH_UNLOCK(sc); 738 ichchan_setblocksize(0, ch, sndbuf_getmaxsize(ch->buffer) >> 1); 739 ICH_LOCK(sc); 740 sc->flags &= ~ICH_CALIBRATE_DONE; 741 742 /* 743 * our data format is stereo, 16 bit so each sample is 4 bytes. 744 * assuming we get 48000 samples per second, we get 192000 bytes/sec. 745 * we're going to start recording with interrupts disabled and measure 746 * the time taken for one block to complete. we know the block size, 747 * we know the time in microseconds, we calculate the sample rate: 748 * 749 * actual_rate [bps] = bytes / (time [s] * 4) 750 * actual_rate [bps] = (bytes * 1000000) / (time [us] * 4) 751 * actual_rate [Hz] = (bytes * 250000) / time [us] 752 */ 753 754 /* prepare */ 755 ociv = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1); 756 nciv = ociv; 757 ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (uint32_t)(ch->desc_addr), 4); 758 759 /* start */ 760 microtime(&t1); 761 ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RPBM, 1); 762 763 /* wait */ 764 do { 765 microtime(&t2); 766 if (t2.tv_sec - t1.tv_sec > 1) 767 break; 768 nciv = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1); 769 } while (nciv == ociv); 770 771 /* stop */ 772 ich_wr(sc, ch->regbase + ICH_REG_X_CR, 0, 1); 773 774 /* reset */ 775 DELAY(100); 776 ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RR, 1); 777 ch->blkcnt = oblkcnt; 778 779 /* turn time delta into us */ 780 wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + t2.tv_usec - t1.tv_usec; 781 782 if (nciv == ociv) { 783 device_printf(sc->dev, "ac97 link rate calibration timed out after %d us\n", wait_us); 784 sc->flags |= ICH_CALIBRATE_DONE; 785 ICH_UNLOCK(sc); 786 ich_setstatus(sc); 787 return; 788 } 789 790 /* Just in case the timecounter screwed. It is possible, really. */ 791 if (wait_us > 0) 792 actual_48k_rate = ((uint64_t)ch->blksz * 250000) / wait_us; 793 else 794 actual_48k_rate = 48000; 795 796 if (actual_48k_rate < 47500 || actual_48k_rate > 48500) { 797 sc->ac97rate = actual_48k_rate; 798 } else { 799 sc->ac97rate = 48000; 800 } 801 802 if (bootverbose || sc->ac97rate != 48000) { 803 device_printf(sc->dev, "measured ac97 link rate at %d Hz", actual_48k_rate); 804 if (sc->ac97rate != actual_48k_rate) 805 printf(", will use %d Hz", sc->ac97rate); 806 printf("\n"); 807 } 808 sc->flags |= ICH_CALIBRATE_DONE; 809 ICH_UNLOCK(sc); 810 811 ich_setstatus(sc); 812 813 return; 814 } 815 816 /* -------------------------------------------------------------------- */ 817 /* Probe and attach the card */ 818 819 static void 820 ich_setmap(void *arg, bus_dma_segment_t *segs, int nseg, int error) 821 { 822 struct sc_info *sc = (struct sc_info *)arg; 823 sc->desc_addr = segs->ds_addr; 824 return; 825 } 826 827 static int 828 ich_init(struct sc_info *sc) 829 { 830 uint32_t stat; 831 832 ich_wr(sc, ICH_REG_GLOB_CNT, ICH_GLOB_CTL_COLD, 4); 833 DELAY(600000); 834 stat = ich_rd(sc, ICH_REG_GLOB_STA, 4); 835 836 if ((stat & ICH_GLOB_STA_PCR) == 0) { 837 /* ICH4/ICH5 may fail when busmastering is enabled. Continue */ 838 if (sc->vendor == INTEL_VENDORID && ( 839 sc->devid == INTEL_82801DB || sc->devid == INTEL_82801EB || 840 sc->devid == INTEL_6300ESB || sc->devid == INTEL_82801FB || 841 sc->devid == INTEL_82801GB)) { 842 sc->flags |= ICH_IGNORE_PCR; 843 device_printf(sc->dev, "primary codec not ready!\n"); 844 } 845 } 846 847 #if 0 848 ich_wr(sc, ICH_REG_GLOB_CNT, ICH_GLOB_CTL_COLD | ICH_GLOB_CTL_PRES, 4); 849 #else 850 ich_wr(sc, ICH_REG_GLOB_CNT, ICH_GLOB_CTL_COLD, 4); 851 #endif 852 853 if (ich_resetchan(sc, 0) || ich_resetchan(sc, 1)) 854 return (ENXIO); 855 if (sc->hasmic && ich_resetchan(sc, 2)) 856 return (ENXIO); 857 858 return (0); 859 } 860 861 static int 862 ich_pci_probe(device_t dev) 863 { 864 int i; 865 uint16_t devid, vendor; 866 867 vendor = pci_get_vendor(dev); 868 devid = pci_get_device(dev); 869 for (i = 0; i < sizeof(ich_devs)/sizeof(ich_devs[0]); i++) { 870 if (vendor == ich_devs[i].vendor && 871 devid == ich_devs[i].devid) { 872 device_set_desc(dev, ich_devs[i].name); 873 /* allow a better driver to override us */ 874 if ((ich_devs[i].options & PROBE_LOW) != 0) 875 return (BUS_PROBE_LOW_PRIORITY); 876 return (BUS_PROBE_DEFAULT); 877 } 878 } 879 return (ENXIO); 880 } 881 882 static int 883 ich_pci_attach(device_t dev) 884 { 885 uint32_t subdev; 886 uint16_t extcaps; 887 uint16_t devid, vendor; 888 struct sc_info *sc; 889 int i; 890 891 sc = malloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO); 892 sc->ich_lock = snd_mtxcreate(device_get_nameunit(dev), "snd_ich softc"); 893 sc->dev = dev; 894 895 vendor = sc->vendor = pci_get_vendor(dev); 896 devid = sc->devid = pci_get_device(dev); 897 subdev = (pci_get_subdevice(dev) << 16) | pci_get_subvendor(dev); 898 /* 899 * The SiS 7012 register set isn't quite like the standard ich. 900 * There really should be a general "quirks" mechanism. 901 */ 902 if (vendor == SIS_VENDORID && devid == SIS_7012) { 903 sc->swap_reg = 1; 904 sc->sample_size = 1; 905 } else { 906 sc->swap_reg = 0; 907 sc->sample_size = 2; 908 } 909 910 /* 911 * Intel 440MX Errata #36 912 * - AC97 Soft Audio and Soft Modem Master Abort Errata 913 * 914 * http://www.intel.com/design/chipsets/specupdt/245051.htm 915 */ 916 if (vendor == INTEL_VENDORID && devid == INTEL_82440MX) 917 sc->flags |= ICH_DMA_NOCACHE; 918 919 /* 920 * Enable bus master. On ich4/5 this may prevent the detection of 921 * the primary codec becoming ready in ich_init(). 922 */ 923 pci_enable_busmaster(dev); 924 925 /* 926 * By default, ich4 has NAMBAR and NABMBAR i/o spaces as 927 * read-only. Need to enable "legacy support", by poking into 928 * pci config space. The driver should use MMBAR and MBBAR, 929 * but doing so will mess things up here. ich4 has enough new 930 * features it warrants it's own driver. 931 */ 932 if (vendor == INTEL_VENDORID && (devid == INTEL_82801DB || 933 devid == INTEL_82801EB || devid == INTEL_6300ESB || 934 devid == INTEL_82801FB || devid == INTEL_82801GB)) { 935 sc->nambarid = PCIR_MMBAR; 936 sc->nabmbarid = PCIR_MBBAR; 937 sc->regtype = SYS_RES_MEMORY; 938 pci_write_config(dev, PCIR_ICH_LEGACY, ICH_LEGACY_ENABLE, 1); 939 } else { 940 sc->nambarid = PCIR_NAMBAR; 941 sc->nabmbarid = PCIR_NABMBAR; 942 sc->regtype = SYS_RES_IOPORT; 943 } 944 945 sc->nambar = bus_alloc_resource_any(dev, sc->regtype, 946 &sc->nambarid, RF_ACTIVE); 947 sc->nabmbar = bus_alloc_resource_any(dev, sc->regtype, 948 &sc->nabmbarid, RF_ACTIVE); 949 950 if (!sc->nambar || !sc->nabmbar) { 951 device_printf(dev, "unable to map IO port space\n"); 952 goto bad; 953 } 954 955 sc->nambart = rman_get_bustag(sc->nambar); 956 sc->nambarh = rman_get_bushandle(sc->nambar); 957 sc->nabmbart = rman_get_bustag(sc->nabmbar); 958 sc->nabmbarh = rman_get_bushandle(sc->nabmbar); 959 960 sc->bufsz = pcm_getbuffersize(dev, 961 ICH_MIN_BUFSZ, ICH_DEFAULT_BUFSZ, ICH_MAX_BUFSZ); 962 963 if (resource_int_value(device_get_name(dev), 964 device_get_unit(dev), "blocksize", &i) == 0 && i > 0) { 965 sc->blkcnt = sc->bufsz / i; 966 i = 0; 967 while (sc->blkcnt >> i) 968 i++; 969 sc->blkcnt = 1 << (i - 1); 970 if (sc->blkcnt < ICH_MIN_BLKCNT) 971 sc->blkcnt = ICH_MIN_BLKCNT; 972 else if (sc->blkcnt > ICH_MAX_BLKCNT) 973 sc->blkcnt = ICH_MAX_BLKCNT; 974 } else 975 sc->blkcnt = ICH_DEFAULT_BLKCNT; 976 977 if (resource_int_value(device_get_name(dev), 978 device_get_unit(dev), "highlatency", &i) == 0 && i != 0) { 979 sc->flags |= ICH_HIGH_LATENCY; 980 sc->blkcnt = ICH_MIN_BLKCNT; 981 } 982 983 if (resource_int_value(device_get_name(dev), 984 device_get_unit(dev), "fixedrate", &i) == 0 && i != 0) 985 sc->flags |= ICH_FIXED_RATE; 986 987 if (resource_int_value(device_get_name(dev), 988 device_get_unit(dev), "micchannel_enabled", &i) == 0 && i != 0) 989 sc->hasmic = 1; 990 991 sc->irqid = 0; 992 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irqid, 993 RF_ACTIVE | RF_SHAREABLE); 994 if (!sc->irq || snd_setup_intr(dev, sc->irq, INTR_MPSAFE, ich_intr, 995 sc, &sc->ih)) { 996 device_printf(dev, "unable to map interrupt\n"); 997 goto bad; 998 } 999 1000 if (ich_init(sc)) { 1001 device_printf(dev, "unable to initialize the card\n"); 1002 goto bad; 1003 } 1004 1005 sc->codec = AC97_CREATE(dev, sc, ich_ac97); 1006 if (sc->codec == NULL) 1007 goto bad; 1008 1009 /* 1010 * Turn on inverted external amplifier sense flags for few 1011 * 'special' boards. 1012 */ 1013 switch (subdev) { 1014 case 0x202f161f: /* Gateway 7326GZ */ 1015 case 0x203a161f: /* Gateway 4028GZ */ 1016 case 0x203e161f: /* Gateway 3520GZ/M210 */ 1017 case 0x204c161f: /* Kvazar-Micro Senator 3592XT */ 1018 case 0x8144104d: /* Sony VAIO PCG-TR* */ 1019 case 0x8197104d: /* Sony S1XP */ 1020 case 0x81c0104d: /* Sony VAIO type T */ 1021 case 0x81c5104d: /* Sony VAIO VGN B1VP/B1XP */ 1022 case 0x3089103c: /* Compaq Presario B3800 */ 1023 case 0x309a103c: /* HP Compaq nx4300 */ 1024 case 0x82131033: /* NEC VersaPro VJ10F/BH */ 1025 case 0x82be1033: /* NEC VersaPro VJ12F/CH */ 1026 ac97_setflags(sc->codec, ac97_getflags(sc->codec) | AC97_F_EAPD_INV); 1027 break; 1028 default: 1029 break; 1030 } 1031 1032 mixer_init(dev, ac97_getmixerclass(), sc->codec); 1033 1034 /* check and set VRA function */ 1035 extcaps = ac97_getextcaps(sc->codec); 1036 sc->hasvra = extcaps & AC97_EXTCAP_VRA; 1037 sc->hasvrm = extcaps & AC97_EXTCAP_VRM; 1038 sc->hasmic = (sc->hasmic != 0 && 1039 (ac97_getcaps(sc->codec) & AC97_CAP_MICCHANNEL)) ? 1 : 0; 1040 ac97_setextmode(sc->codec, sc->hasvra | sc->hasvrm); 1041 1042 sc->dtbl_size = sizeof(struct ich_desc) * ICH_DTBL_LENGTH * 1043 ((sc->hasmic) ? 3 : 2); 1044 1045 /* BDL tag */ 1046 if (bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0, 1047 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1048 sc->dtbl_size, 1, 0x3ffff, 0, NULL, NULL, &sc->dmat) != 0) { 1049 device_printf(dev, "unable to create dma tag\n"); 1050 goto bad; 1051 } 1052 1053 /* PCM channel tag */ 1054 if (bus_dma_tag_create(bus_get_dma_tag(dev), ICH_MIN_BLKSZ, 0, 1055 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1056 sc->bufsz, 1, 0x3ffff, 0, NULL, NULL, &sc->chan_dmat) != 0) { 1057 device_printf(dev, "unable to create dma tag\n"); 1058 goto bad; 1059 } 1060 1061 if (bus_dmamem_alloc(sc->dmat, (void **)&sc->dtbl, BUS_DMA_NOWAIT | 1062 ((sc->flags & ICH_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0), 1063 &sc->dtmap)) 1064 goto bad; 1065 1066 if (bus_dmamap_load(sc->dmat, sc->dtmap, sc->dtbl, sc->dtbl_size, 1067 ich_setmap, sc, 0)) 1068 goto bad; 1069 1070 if (pcm_register(dev, sc, 1, (sc->hasmic) ? 2 : 1)) 1071 goto bad; 1072 1073 pcm_addchan(dev, PCMDIR_PLAY, &ichchan_class, sc); /* play */ 1074 pcm_addchan(dev, PCMDIR_REC, &ichchan_class, sc); /* record */ 1075 if (sc->hasmic) 1076 pcm_addchan(dev, PCMDIR_REC, &ichchan_class, sc); /* record mic */ 1077 1078 if (sc->flags & ICH_FIXED_RATE) { 1079 sc->flags |= ICH_CALIBRATE_DONE; 1080 ich_setstatus(sc); 1081 } else { 1082 ich_initsys(sc); 1083 1084 sc->intrhook.ich_func = ich_calibrate; 1085 sc->intrhook.ich_arg = sc; 1086 if (cold == 0 || 1087 config_intrhook_establish(&sc->intrhook) != 0) { 1088 sc->intrhook.ich_func = NULL; 1089 ich_calibrate(sc); 1090 } 1091 } 1092 1093 return (0); 1094 1095 bad: 1096 if (sc->codec) 1097 ac97_destroy(sc->codec); 1098 if (sc->ih) 1099 bus_teardown_intr(dev, sc->irq, sc->ih); 1100 if (sc->irq) 1101 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); 1102 if (sc->nambar) 1103 bus_release_resource(dev, sc->regtype, 1104 sc->nambarid, sc->nambar); 1105 if (sc->nabmbar) 1106 bus_release_resource(dev, sc->regtype, 1107 sc->nabmbarid, sc->nabmbar); 1108 if (sc->dtmap) 1109 bus_dmamap_unload(sc->dmat, sc->dtmap); 1110 if (sc->dtbl) 1111 bus_dmamem_free(sc->dmat, sc->dtbl, sc->dtmap); 1112 if (sc->chan_dmat) 1113 bus_dma_tag_destroy(sc->chan_dmat); 1114 if (sc->dmat) 1115 bus_dma_tag_destroy(sc->dmat); 1116 if (sc->ich_lock) 1117 snd_mtxfree(sc->ich_lock); 1118 free(sc, M_DEVBUF); 1119 return (ENXIO); 1120 } 1121 1122 static int 1123 ich_pci_detach(device_t dev) 1124 { 1125 struct sc_info *sc; 1126 int r; 1127 1128 r = pcm_unregister(dev); 1129 if (r) 1130 return (r); 1131 sc = pcm_getdevinfo(dev); 1132 1133 bus_teardown_intr(dev, sc->irq, sc->ih); 1134 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); 1135 bus_release_resource(dev, sc->regtype, sc->nambarid, sc->nambar); 1136 bus_release_resource(dev, sc->regtype, sc->nabmbarid, sc->nabmbar); 1137 bus_dmamap_unload(sc->dmat, sc->dtmap); 1138 bus_dmamem_free(sc->dmat, sc->dtbl, sc->dtmap); 1139 bus_dma_tag_destroy(sc->chan_dmat); 1140 bus_dma_tag_destroy(sc->dmat); 1141 snd_mtxfree(sc->ich_lock); 1142 free(sc, M_DEVBUF); 1143 return (0); 1144 } 1145 1146 static void 1147 ich_pci_codec_reset(struct sc_info *sc) 1148 { 1149 int i; 1150 uint32_t control; 1151 1152 control = ich_rd(sc, ICH_REG_GLOB_CNT, 4); 1153 control &= ~(ICH_GLOB_CTL_SHUT); 1154 control |= (control & ICH_GLOB_CTL_COLD) ? 1155 ICH_GLOB_CTL_WARM : ICH_GLOB_CTL_COLD; 1156 ich_wr(sc, ICH_REG_GLOB_CNT, control, 4); 1157 1158 for (i = 500000; i; i--) { 1159 if (ich_rd(sc, ICH_REG_GLOB_STA, 4) & ICH_GLOB_STA_PCR) 1160 break; /* or ICH_SCR? */ 1161 DELAY(1); 1162 } 1163 1164 if (i <= 0) 1165 printf("%s: time out\n", __func__); 1166 } 1167 1168 static int 1169 ich_pci_suspend(device_t dev) 1170 { 1171 struct sc_info *sc; 1172 int i; 1173 1174 sc = pcm_getdevinfo(dev); 1175 ICH_LOCK(sc); 1176 for (i = 0 ; i < 3; i++) { 1177 sc->ch[i].run_save = sc->ch[i].run; 1178 if (sc->ch[i].run) { 1179 ICH_UNLOCK(sc); 1180 ichchan_trigger(0, &sc->ch[i], PCMTRIG_ABORT); 1181 ICH_LOCK(sc); 1182 } 1183 } 1184 ICH_UNLOCK(sc); 1185 return (0); 1186 } 1187 1188 static int 1189 ich_pci_resume(device_t dev) 1190 { 1191 struct sc_info *sc; 1192 int err, i; 1193 1194 sc = pcm_getdevinfo(dev); 1195 1196 ICH_LOCK(sc); 1197 /* Reinit audio device */ 1198 err = ich_init(sc); 1199 if (err != 0) { 1200 device_printf(dev, "unable to reinitialize the card\n"); 1201 ICH_UNLOCK(sc); 1202 return (err); 1203 } 1204 /* Reinit mixer */ 1205 ich_pci_codec_reset(sc); 1206 ICH_UNLOCK(sc); 1207 ac97_setextmode(sc->codec, sc->hasvra | sc->hasvrm); 1208 if (mixer_reinit(dev) == -1) { 1209 device_printf(dev, "unable to reinitialize the mixer\n"); 1210 return (ENXIO); 1211 } 1212 /* Re-start DMA engines */ 1213 for (i = 0 ; i < 3; i++) { 1214 struct sc_chinfo *ch = &sc->ch[i]; 1215 if (sc->ch[i].run_save) { 1216 ichchan_setblocksize(0, ch, ch->blksz); 1217 ichchan_setspeed(0, ch, ch->spd); 1218 ichchan_trigger(0, ch, PCMTRIG_START); 1219 } 1220 } 1221 return (0); 1222 } 1223 1224 static device_method_t ich_methods[] = { 1225 /* Device interface */ 1226 DEVMETHOD(device_probe, ich_pci_probe), 1227 DEVMETHOD(device_attach, ich_pci_attach), 1228 DEVMETHOD(device_detach, ich_pci_detach), 1229 DEVMETHOD(device_suspend, ich_pci_suspend), 1230 DEVMETHOD(device_resume, ich_pci_resume), 1231 { 0, 0 } 1232 }; 1233 1234 static driver_t ich_driver = { 1235 "pcm", 1236 ich_methods, 1237 PCM_SOFTC_SIZE, 1238 }; 1239 1240 DRIVER_MODULE(snd_ich, pci, ich_driver, 0, 0); 1241 MODULE_DEPEND(snd_ich, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 1242 MODULE_VERSION(snd_ich, 1); 1243