1 /*- 2 * Copyright (c) 2000 Katsurajima Naoto <raven@katsurajima.seya.yokohama.jp> 3 * Copyright (c) 2001 Cameron Grant <cg@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <dev/sound/pcm/sound.h> 29 #include <dev/sound/pcm/ac97.h> 30 #include <dev/sound/pci/ich.h> 31 32 #include <dev/pci/pcireg.h> 33 #include <dev/pci/pcivar.h> 34 35 SND_DECLARE_FILE("$FreeBSD$"); 36 37 /* -------------------------------------------------------------------- */ 38 39 #define ICH_TIMEOUT 1000 /* semaphore timeout polling count */ 40 #define ICH_DTBL_LENGTH 32 41 #define ICH_DEFAULT_BUFSZ 16384 42 #define ICH_MAX_BUFSZ 65536 43 #define ICH_MIN_BUFSZ 4096 44 #define ICH_DEFAULT_BLKCNT 2 45 #define ICH_MAX_BLKCNT 32 46 #define ICH_MIN_BLKCNT 2 47 48 #define INTEL_VENDORID 0x8086 49 #define SIS_VENDORID 0x1039 50 #define NVIDIA_VENDORID 0x10de 51 #define AMD_VENDORID 0x1022 52 53 #define INTEL_82440MX 0x7195 54 #define INTEL_82801AA 0x2415 55 #define INTEL_82801AB 0x2425 56 #define INTEL_82801BA 0x2445 57 #define INTEL_82801CA 0x2485 58 #define INTEL_82801DB 0x24c5 /* ICH4 needs special handling */ 59 #define INTEL_82801EB 0x24d5 /* ICH5 needs to be treated as ICH4 */ 60 #define INTEL_6300ESB 0x25a6 /* 6300ESB needs to be treated as ICH4 */ 61 #define INTEL_82801FB 0x266e /* ICH6 needs to be treated as ICH4 */ 62 #define INTEL_82801GB 0x27de /* ICH7 needs to be treated as ICH4 */ 63 #define SIS_7012 0x7012 /* SiS 7012 needs special handling */ 64 #define NVIDIA_NFORCE 0x01b1 65 #define NVIDIA_NFORCE2 0x006a 66 #define NVIDIA_NFORCE2_400 0x008a 67 #define NVIDIA_NFORCE3 0x00da 68 #define NVIDIA_NFORCE3_250 0x00ea 69 #define NVIDIA_NFORCE4 0x0059 70 #define NVIDIA_NFORCE_410_MCP 0x026b 71 #define NVIDIA_NFORCE4_MCP 0x003a 72 #define AMD_768 0x7445 73 #define AMD_8111 0x746d 74 75 #define ICH_LOCK(sc) snd_mtxlock((sc)->ich_lock) 76 #define ICH_UNLOCK(sc) snd_mtxunlock((sc)->ich_lock) 77 #define ICH_LOCK_ASSERT(sc) snd_mtxassert((sc)->ich_lock) 78 79 #if 0 80 #define ICH_DEBUG(stmt) do { \ 81 stmt \ 82 } while(0) 83 #else 84 #define ICH_DEBUG(stmt) 85 #endif 86 87 static const struct ich_type { 88 uint16_t vendor; 89 uint16_t devid; 90 uint32_t options; 91 #define PROBE_LOW 0x01 92 char *name; 93 } ich_devs[] = { 94 { INTEL_VENDORID, INTEL_82440MX, 0, 95 "Intel 440MX" }, 96 { INTEL_VENDORID, INTEL_82801AA, 0, 97 "Intel ICH (82801AA)" }, 98 { INTEL_VENDORID, INTEL_82801AB, 0, 99 "Intel ICH (82801AB)" }, 100 { INTEL_VENDORID, INTEL_82801BA, 0, 101 "Intel ICH2 (82801BA)" }, 102 { INTEL_VENDORID, INTEL_82801CA, 0, 103 "Intel ICH3 (82801CA)" }, 104 { INTEL_VENDORID, INTEL_82801DB, PROBE_LOW, 105 "Intel ICH4 (82801DB)" }, 106 { INTEL_VENDORID, INTEL_82801EB, PROBE_LOW, 107 "Intel ICH5 (82801EB)" }, 108 { INTEL_VENDORID, INTEL_6300ESB, PROBE_LOW, 109 "Intel 6300ESB" }, 110 { INTEL_VENDORID, INTEL_82801FB, PROBE_LOW, 111 "Intel ICH6 (82801FB)" }, 112 { INTEL_VENDORID, INTEL_82801GB, PROBE_LOW, 113 "Intel ICH7 (82801GB)" }, 114 { SIS_VENDORID, SIS_7012, 0, 115 "SiS 7012" }, 116 { NVIDIA_VENDORID, NVIDIA_NFORCE, 0, 117 "nVidia nForce" }, 118 { NVIDIA_VENDORID, NVIDIA_NFORCE2, 0, 119 "nVidia nForce2" }, 120 { NVIDIA_VENDORID, NVIDIA_NFORCE2_400, 0, 121 "nVidia nForce2 400" }, 122 { NVIDIA_VENDORID, NVIDIA_NFORCE3, 0, 123 "nVidia nForce3" }, 124 { NVIDIA_VENDORID, NVIDIA_NFORCE3_250, 0, 125 "nVidia nForce3 250" }, 126 { NVIDIA_VENDORID, NVIDIA_NFORCE4, 0, 127 "nVidia nForce4" }, 128 { NVIDIA_VENDORID, NVIDIA_NFORCE_410_MCP, 0, 129 "nVidia nForce 410 MCP" }, 130 { NVIDIA_VENDORID, NVIDIA_NFORCE4_MCP, 0, 131 "nVidia nForce 4 MCP" }, 132 { AMD_VENDORID, AMD_768, 0, 133 "AMD-768" }, 134 { AMD_VENDORID, AMD_8111, 0, 135 "AMD-8111" } 136 }; 137 138 /* buffer descriptor */ 139 struct ich_desc { 140 volatile uint32_t buffer; 141 volatile uint32_t length; 142 }; 143 144 struct sc_info; 145 146 /* channel registers */ 147 struct sc_chinfo { 148 uint32_t num:8, run:1, run_save:1; 149 uint32_t blksz, blkcnt, spd; 150 uint32_t regbase, spdreg; 151 uint32_t imask; 152 uint32_t civ; 153 154 struct snd_dbuf *buffer; 155 struct pcm_channel *channel; 156 struct sc_info *parent; 157 158 struct ich_desc *dtbl; 159 bus_addr_t desc_addr; 160 }; 161 162 /* device private data */ 163 struct sc_info { 164 device_t dev; 165 int hasvra, hasvrm, hasmic; 166 unsigned int chnum, bufsz, blkcnt; 167 int sample_size, swap_reg, fixedrate; 168 169 struct resource *nambar, *nabmbar, *irq; 170 int regtype, nambarid, nabmbarid, irqid; 171 bus_space_tag_t nambart, nabmbart; 172 bus_space_handle_t nambarh, nabmbarh; 173 bus_dma_tag_t dmat; 174 bus_dmamap_t dtmap; 175 void *ih; 176 177 struct ac97_info *codec; 178 struct sc_chinfo ch[3]; 179 int ac97rate, calibrated; 180 struct ich_desc *dtbl; 181 bus_addr_t desc_addr; 182 struct intr_config_hook intrhook; 183 int use_intrhook; 184 uint16_t vendor; 185 uint16_t devid; 186 uint32_t flags; 187 #define IGNORE_PCR 0x01 188 struct mtx *ich_lock; 189 }; 190 191 /* -------------------------------------------------------------------- */ 192 193 static uint32_t ich_fmt[] = { 194 AFMT_STEREO | AFMT_S16_LE, 195 0 196 }; 197 static struct pcmchan_caps ich_vrcaps = {8000, 48000, ich_fmt, 0}; 198 static struct pcmchan_caps ich_caps = {48000, 48000, ich_fmt, 0}; 199 200 /* -------------------------------------------------------------------- */ 201 /* Hardware */ 202 static __inline uint32_t 203 ich_rd(struct sc_info *sc, int regno, int size) 204 { 205 switch (size) { 206 case 1: 207 return (bus_space_read_1(sc->nabmbart, sc->nabmbarh, regno)); 208 case 2: 209 return (bus_space_read_2(sc->nabmbart, sc->nabmbarh, regno)); 210 case 4: 211 return (bus_space_read_4(sc->nabmbart, sc->nabmbarh, regno)); 212 default: 213 return (0xffffffff); 214 } 215 } 216 217 static __inline void 218 ich_wr(struct sc_info *sc, int regno, uint32_t data, int size) 219 { 220 switch (size) { 221 case 1: 222 bus_space_write_1(sc->nabmbart, sc->nabmbarh, regno, data); 223 break; 224 case 2: 225 bus_space_write_2(sc->nabmbart, sc->nabmbarh, regno, data); 226 break; 227 case 4: 228 bus_space_write_4(sc->nabmbart, sc->nabmbarh, regno, data); 229 break; 230 } 231 } 232 233 /* ac97 codec */ 234 static int 235 ich_waitcd(void *devinfo) 236 { 237 struct sc_info *sc = (struct sc_info *)devinfo; 238 uint32_t data; 239 int i; 240 241 for (i = 0; i < ICH_TIMEOUT; i++) { 242 data = ich_rd(sc, ICH_REG_ACC_SEMA, 1); 243 if ((data & 0x01) == 0) 244 return (0); 245 DELAY(1); 246 } 247 if ((sc->flags & IGNORE_PCR) != 0) 248 return (0); 249 device_printf(sc->dev, "CODEC semaphore timeout\n"); 250 return (ETIMEDOUT); 251 } 252 253 static int 254 ich_rdcd(kobj_t obj, void *devinfo, int regno) 255 { 256 struct sc_info *sc = (struct sc_info *)devinfo; 257 258 regno &= 0xff; 259 ich_waitcd(sc); 260 261 return (bus_space_read_2(sc->nambart, sc->nambarh, regno)); 262 } 263 264 static int 265 ich_wrcd(kobj_t obj, void *devinfo, int regno, uint16_t data) 266 { 267 struct sc_info *sc = (struct sc_info *)devinfo; 268 269 regno &= 0xff; 270 ich_waitcd(sc); 271 bus_space_write_2(sc->nambart, sc->nambarh, regno, data); 272 273 return (0); 274 } 275 276 static kobj_method_t ich_ac97_methods[] = { 277 KOBJMETHOD(ac97_read, ich_rdcd), 278 KOBJMETHOD(ac97_write, ich_wrcd), 279 { 0, 0 } 280 }; 281 AC97_DECLARE(ich_ac97); 282 283 /* -------------------------------------------------------------------- */ 284 /* common routines */ 285 286 static void 287 ich_filldtbl(struct sc_chinfo *ch) 288 { 289 struct sc_info *sc = ch->parent; 290 uint32_t base; 291 int i; 292 293 base = sndbuf_getbufaddr(ch->buffer); 294 if ((ch->blksz * ch->blkcnt) > sndbuf_getmaxsize(ch->buffer)) 295 ch->blksz = sndbuf_getmaxsize(ch->buffer) / ch->blkcnt; 296 if ((sndbuf_getblksz(ch->buffer) != ch->blksz || 297 sndbuf_getblkcnt(ch->buffer) != ch->blkcnt) && 298 sndbuf_resize(ch->buffer, ch->blkcnt, ch->blksz) != 0) 299 device_printf(sc->dev, "%s: failed blksz=%u blkcnt=%u\n", 300 __func__, ch->blksz, ch->blkcnt); 301 ch->blksz = sndbuf_getblksz(ch->buffer); 302 303 for (i = 0; i < ICH_DTBL_LENGTH; i++) { 304 ch->dtbl[i].buffer = base + (ch->blksz * (i % ch->blkcnt)); 305 ch->dtbl[i].length = ICH_BDC_IOC 306 | (ch->blksz / ch->parent->sample_size); 307 } 308 } 309 310 static int 311 ich_resetchan(struct sc_info *sc, int num) 312 { 313 int i, cr, regbase; 314 315 if (num == 0) 316 regbase = ICH_REG_PO_BASE; 317 else if (num == 1) 318 regbase = ICH_REG_PI_BASE; 319 else if (num == 2) 320 regbase = ICH_REG_MC_BASE; 321 else 322 return (ENXIO); 323 324 ich_wr(sc, regbase + ICH_REG_X_CR, 0, 1); 325 #if 1 326 /* This may result in no sound output on NForce 2 MBs, see PR 73987 */ 327 DELAY(100); 328 #else 329 (void)ich_rd(sc, regbase + ICH_REG_X_CR, 1); 330 #endif 331 ich_wr(sc, regbase + ICH_REG_X_CR, ICH_X_CR_RR, 1); 332 for (i = 0; i < ICH_TIMEOUT; i++) { 333 cr = ich_rd(sc, regbase + ICH_REG_X_CR, 1); 334 if (cr == 0) 335 return (0); 336 } 337 338 device_printf(sc->dev, "cannot reset channel %d\n", num); 339 return (ENXIO); 340 } 341 342 /* -------------------------------------------------------------------- */ 343 /* channel interface */ 344 345 static void * 346 ichchan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir) 347 { 348 struct sc_info *sc = devinfo; 349 struct sc_chinfo *ch; 350 unsigned int num; 351 352 ICH_LOCK(sc); 353 num = sc->chnum++; 354 ch = &sc->ch[num]; 355 ch->num = num; 356 ch->buffer = b; 357 ch->channel = c; 358 ch->parent = sc; 359 ch->run = 0; 360 ch->dtbl = sc->dtbl + (ch->num * ICH_DTBL_LENGTH); 361 ch->desc_addr = sc->desc_addr + (ch->num * ICH_DTBL_LENGTH) * 362 sizeof(struct ich_desc); 363 ch->blkcnt = sc->blkcnt; 364 ch->blksz = sc->bufsz / ch->blkcnt; 365 366 switch(ch->num) { 367 case 0: /* play */ 368 KASSERT(dir == PCMDIR_PLAY, ("wrong direction")); 369 ch->regbase = ICH_REG_PO_BASE; 370 ch->spdreg = (sc->hasvra) ? AC97_REGEXT_FDACRATE : 0; 371 ch->imask = ICH_GLOB_STA_POINT; 372 break; 373 374 case 1: /* record */ 375 KASSERT(dir == PCMDIR_REC, ("wrong direction")); 376 ch->regbase = ICH_REG_PI_BASE; 377 ch->spdreg = (sc->hasvra) ? AC97_REGEXT_LADCRATE : 0; 378 ch->imask = ICH_GLOB_STA_PIINT; 379 break; 380 381 case 2: /* mic */ 382 KASSERT(dir == PCMDIR_REC, ("wrong direction")); 383 ch->regbase = ICH_REG_MC_BASE; 384 ch->spdreg = (sc->hasvrm) ? AC97_REGEXT_MADCRATE : 0; 385 ch->imask = ICH_GLOB_STA_MINT; 386 break; 387 388 default: 389 return (NULL); 390 } 391 392 if (sc->fixedrate != 0) 393 ch->spdreg = 0; 394 395 ICH_UNLOCK(sc); 396 if (sndbuf_alloc(ch->buffer, sc->dmat, sc->bufsz) != 0) 397 return (NULL); 398 399 ICH_LOCK(sc); 400 ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (uint32_t)(ch->desc_addr), 4); 401 ICH_UNLOCK(sc); 402 403 return (ch); 404 } 405 406 static int 407 ichchan_setformat(kobj_t obj, void *data, uint32_t format) 408 { 409 410 ICH_DEBUG( 411 struct sc_chinfo *ch = data; 412 struct sc_info *sc = ch->parent; 413 if (sc->calibrated == 0) 414 device_printf(sc->dev, 415 "WARNING: %s() called before calibration!\n", 416 __func__); 417 ); 418 419 return (0); 420 } 421 422 static int 423 ichchan_setspeed(kobj_t obj, void *data, uint32_t speed) 424 { 425 struct sc_chinfo *ch = data; 426 struct sc_info *sc = ch->parent; 427 428 ICH_DEBUG( 429 if (sc->calibrated == 0) 430 device_printf(sc->dev, 431 "WARNING: %s() called before calibration!\n", 432 __func__); 433 ); 434 435 if (ch->spdreg) { 436 int r, ac97rate; 437 438 ICH_LOCK(sc); 439 if (sc->ac97rate <= 32000 || sc->ac97rate >= 64000) 440 sc->ac97rate = 48000; 441 ac97rate = sc->ac97rate; 442 ICH_UNLOCK(sc); 443 r = (speed * 48000) / ac97rate; 444 /* 445 * Cast the return value of ac97_setrate() to uint64 so that 446 * the math don't overflow into the negative range. 447 */ 448 ch->spd = ((uint64_t)ac97_setrate(sc->codec, ch->spdreg, r) * 449 ac97rate) / 48000; 450 } else { 451 ch->spd = 48000; 452 } 453 return (ch->spd); 454 } 455 456 static int 457 ichchan_setblocksize(kobj_t obj, void *data, uint32_t blocksize) 458 { 459 struct sc_chinfo *ch = data; 460 struct sc_info *sc = ch->parent; 461 462 ICH_DEBUG( 463 if (sc->calibrated == 0) 464 device_printf(sc->dev, 465 "WARNING: %s() called before calibration!\n", 466 __func__); 467 ); 468 469 ch->blksz = blocksize; 470 ich_filldtbl(ch); 471 ICH_LOCK(sc); 472 ich_wr(sc, ch->regbase + ICH_REG_X_LVI, ch->blkcnt - 1, 1); 473 ICH_UNLOCK(sc); 474 475 return (ch->blksz); 476 } 477 478 static int 479 ichchan_trigger(kobj_t obj, void *data, int go) 480 { 481 struct sc_chinfo *ch = data; 482 struct sc_info *sc = ch->parent; 483 484 ICH_DEBUG( 485 if (sc->calibrated == 0) 486 device_printf(sc->dev, 487 "WARNING: %s() called before calibration!\n", 488 __func__); 489 ); 490 491 switch (go) { 492 case PCMTRIG_START: 493 ch->run = 1; 494 ICH_LOCK(sc); 495 ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (uint32_t)(ch->desc_addr), 4); 496 ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RPBM | ICH_X_CR_LVBIE | ICH_X_CR_IOCE, 1); 497 ICH_UNLOCK(sc); 498 break; 499 500 case PCMTRIG_ABORT: 501 ICH_LOCK(sc); 502 ich_resetchan(sc, ch->num); 503 ICH_UNLOCK(sc); 504 ch->run = 0; 505 break; 506 } 507 return (0); 508 } 509 510 static int 511 ichchan_getptr(kobj_t obj, void *data) 512 { 513 struct sc_chinfo *ch = data; 514 struct sc_info *sc = ch->parent; 515 uint32_t pos; 516 517 ICH_DEBUG( 518 if (sc->calibrated == 0) 519 device_printf(sc->dev, 520 "WARNING: %s() called before calibration!\n", 521 __func__); 522 ); 523 524 ICH_LOCK(sc); 525 ch->civ = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1) % ch->blkcnt; 526 ICH_UNLOCK(sc); 527 528 pos = ch->civ * ch->blksz; 529 530 return (pos); 531 } 532 533 static struct pcmchan_caps * 534 ichchan_getcaps(kobj_t obj, void *data) 535 { 536 struct sc_chinfo *ch = data; 537 538 ICH_DEBUG( 539 struct sc_info *sc = ch->parent; 540 541 if (sc->calibrated == 0) 542 device_printf(ch->parent->dev, 543 "WARNING: %s() called before calibration!\n", 544 __func__); 545 ); 546 547 return ((ch->spdreg) ? &ich_vrcaps : &ich_caps); 548 } 549 550 static kobj_method_t ichchan_methods[] = { 551 KOBJMETHOD(channel_init, ichchan_init), 552 KOBJMETHOD(channel_setformat, ichchan_setformat), 553 KOBJMETHOD(channel_setspeed, ichchan_setspeed), 554 KOBJMETHOD(channel_setblocksize, ichchan_setblocksize), 555 KOBJMETHOD(channel_trigger, ichchan_trigger), 556 KOBJMETHOD(channel_getptr, ichchan_getptr), 557 KOBJMETHOD(channel_getcaps, ichchan_getcaps), 558 { 0, 0 } 559 }; 560 CHANNEL_DECLARE(ichchan); 561 562 /* -------------------------------------------------------------------- */ 563 /* The interrupt handler */ 564 565 static void 566 ich_intr(void *p) 567 { 568 struct sc_info *sc = (struct sc_info *)p; 569 struct sc_chinfo *ch; 570 uint32_t cbi, lbi, lvi, st, gs; 571 int i; 572 573 ICH_LOCK(sc); 574 575 ICH_DEBUG( 576 if (sc->calibrated == 0) 577 device_printf(sc->dev, 578 "WARNING: %s() called before calibration!\n", 579 __func__); 580 ); 581 582 gs = ich_rd(sc, ICH_REG_GLOB_STA, 4) & ICH_GLOB_STA_IMASK; 583 if (gs & (ICH_GLOB_STA_PRES | ICH_GLOB_STA_SRES)) { 584 /* Clear resume interrupt(s) - nothing doing with them */ 585 ich_wr(sc, ICH_REG_GLOB_STA, gs, 4); 586 } 587 gs &= ~(ICH_GLOB_STA_PRES | ICH_GLOB_STA_SRES); 588 589 for (i = 0; i < 3; i++) { 590 ch = &sc->ch[i]; 591 if ((ch->imask & gs) == 0) 592 continue; 593 gs &= ~ch->imask; 594 st = ich_rd(sc, ch->regbase + 595 ((sc->swap_reg) ? ICH_REG_X_PICB : ICH_REG_X_SR), 596 2); 597 st &= ICH_X_SR_FIFOE | ICH_X_SR_BCIS | ICH_X_SR_LVBCI; 598 if (st & (ICH_X_SR_BCIS | ICH_X_SR_LVBCI)) { 599 /* block complete - update buffer */ 600 if (ch->run) { 601 ICH_UNLOCK(sc); 602 chn_intr(ch->channel); 603 ICH_LOCK(sc); 604 } 605 lvi = ich_rd(sc, ch->regbase + ICH_REG_X_LVI, 1); 606 cbi = ch->civ % ch->blkcnt; 607 if (cbi == 0) 608 cbi = ch->blkcnt - 1; 609 else 610 cbi--; 611 lbi = lvi % ch->blkcnt; 612 if (cbi >= lbi) 613 lvi += cbi - lbi; 614 else 615 lvi += cbi + ch->blkcnt - lbi; 616 lvi %= ICH_DTBL_LENGTH; 617 ich_wr(sc, ch->regbase + ICH_REG_X_LVI, lvi, 1); 618 619 } 620 /* clear status bit */ 621 ich_wr(sc, ch->regbase + 622 ((sc->swap_reg) ? ICH_REG_X_PICB : ICH_REG_X_SR), 623 st, 2); 624 } 625 ICH_UNLOCK(sc); 626 if (gs != 0) { 627 device_printf(sc->dev, 628 "Unhandled interrupt, gs_intr = %x\n", gs); 629 } 630 } 631 632 /* ------------------------------------------------------------------------- */ 633 /* Sysctl to control ac97 speed (some boards appear to end up using 634 * XTAL_IN rather than BIT_CLK for link timing). 635 */ 636 637 static int 638 ich_initsys(struct sc_info* sc) 639 { 640 #ifdef SND_DYNSYSCTL 641 /* XXX: this should move to a device specific sysctl "dev.pcm.X.yyy" 642 via device_get_sysctl_*() as discussed on multimedia@ in msg-id 643 <861wujij2q.fsf@xps.des.no> */ 644 SYSCTL_ADD_INT(device_get_sysctl_ctx(sc->dev), 645 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), 646 OID_AUTO, "ac97rate", CTLFLAG_RW, 647 &sc->ac97rate, 48000, 648 "AC97 link rate (default = 48000)"); 649 #endif /* SND_DYNSYSCTL */ 650 return (0); 651 } 652 653 static void 654 ich_setstatus(struct sc_info *sc) 655 { 656 char status[SND_STATUSLEN]; 657 658 snprintf(status, SND_STATUSLEN, 659 "at io 0x%lx, 0x%lx irq %ld bufsz %u %s", 660 rman_get_start(sc->nambar), rman_get_start(sc->nabmbar), 661 rman_get_start(sc->irq), sc->bufsz,PCM_KLDSTRING(snd_ich)); 662 663 pcm_setstatus(sc->dev, status); 664 } 665 666 /* -------------------------------------------------------------------- */ 667 /* Calibrate card to determine the clock source. The source maybe a 668 * function of the ac97 codec initialization code (to be investigated). 669 */ 670 671 static void 672 ich_calibrate(void *arg) 673 { 674 struct sc_info *sc; 675 struct sc_chinfo *ch; 676 struct timeval t1, t2; 677 uint8_t ociv, nciv; 678 uint32_t wait_us, actual_48k_rate, oblkcnt; 679 680 sc = (struct sc_info *)arg; 681 ICH_LOCK(sc); 682 ch = &sc->ch[1]; 683 684 if (sc->use_intrhook) 685 config_intrhook_disestablish(&sc->intrhook); 686 687 /* 688 * Grab audio from input for fixed interval and compare how 689 * much we actually get with what we expect. Interval needs 690 * to be sufficiently short that no interrupts are 691 * generated. 692 */ 693 694 KASSERT(ch->regbase == ICH_REG_PI_BASE, ("wrong direction")); 695 696 oblkcnt = ch->blkcnt; 697 ch->blkcnt = 2; 698 sc->calibrated = 1; 699 ICH_UNLOCK(sc); 700 ichchan_setblocksize(0, ch, sndbuf_getmaxsize(ch->buffer) >> 1); 701 ICH_LOCK(sc); 702 sc->calibrated = 0; 703 704 /* 705 * our data format is stereo, 16 bit so each sample is 4 bytes. 706 * assuming we get 48000 samples per second, we get 192000 bytes/sec. 707 * we're going to start recording with interrupts disabled and measure 708 * the time taken for one block to complete. we know the block size, 709 * we know the time in microseconds, we calculate the sample rate: 710 * 711 * actual_rate [bps] = bytes / (time [s] * 4) 712 * actual_rate [bps] = (bytes * 1000000) / (time [us] * 4) 713 * actual_rate [Hz] = (bytes * 250000) / time [us] 714 */ 715 716 /* prepare */ 717 ociv = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1); 718 nciv = ociv; 719 ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (uint32_t)(ch->desc_addr), 4); 720 721 /* start */ 722 microtime(&t1); 723 ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RPBM, 1); 724 725 /* wait */ 726 do { 727 microtime(&t2); 728 if (t2.tv_sec - t1.tv_sec > 1) 729 break; 730 nciv = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1); 731 } while (nciv == ociv); 732 733 /* stop */ 734 ich_wr(sc, ch->regbase + ICH_REG_X_CR, 0, 1); 735 736 /* reset */ 737 DELAY(100); 738 ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RR, 1); 739 ch->blkcnt = oblkcnt; 740 741 /* turn time delta into us */ 742 wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + t2.tv_usec - t1.tv_usec; 743 744 if (nciv == ociv) { 745 device_printf(sc->dev, "ac97 link rate calibration timed out after %d us\n", wait_us); 746 sc->calibrated = 1; 747 ICH_UNLOCK(sc); 748 ich_setstatus(sc); 749 return; 750 } 751 752 actual_48k_rate = ((uint64_t)ch->blksz * 250000) / wait_us; 753 754 if (actual_48k_rate < 47500 || actual_48k_rate > 48500) { 755 sc->ac97rate = actual_48k_rate; 756 } else { 757 sc->ac97rate = 48000; 758 } 759 760 if (bootverbose || sc->ac97rate != 48000) { 761 device_printf(sc->dev, "measured ac97 link rate at %d Hz", actual_48k_rate); 762 if (sc->ac97rate != actual_48k_rate) 763 printf(", will use %d Hz", sc->ac97rate); 764 printf("\n"); 765 } 766 sc->calibrated = 1; 767 ICH_UNLOCK(sc); 768 769 ich_setstatus(sc); 770 771 return; 772 } 773 774 /* -------------------------------------------------------------------- */ 775 /* Probe and attach the card */ 776 777 static void 778 ich_setmap(void *arg, bus_dma_segment_t *segs, int nseg, int error) 779 { 780 struct sc_info *sc = (struct sc_info *)arg; 781 sc->desc_addr = segs->ds_addr; 782 return; 783 } 784 785 static int 786 ich_init(struct sc_info *sc) 787 { 788 uint32_t stat; 789 790 ich_wr(sc, ICH_REG_GLOB_CNT, ICH_GLOB_CTL_COLD, 4); 791 DELAY(600000); 792 stat = ich_rd(sc, ICH_REG_GLOB_STA, 4); 793 794 if ((stat & ICH_GLOB_STA_PCR) == 0) { 795 /* ICH4/ICH5 may fail when busmastering is enabled. Continue */ 796 if (sc->vendor == INTEL_VENDORID && ( 797 sc->devid == INTEL_82801DB || sc->devid == INTEL_82801EB || 798 sc->devid == INTEL_6300ESB || sc->devid == INTEL_82801FB || 799 sc->devid == INTEL_82801GB)) { 800 sc->flags |= IGNORE_PCR; 801 device_printf(sc->dev, "primary codec not ready!\n"); 802 } 803 } 804 805 #if 0 806 ich_wr(sc, ICH_REG_GLOB_CNT, ICH_GLOB_CTL_COLD | ICH_GLOB_CTL_PRES, 4); 807 #else 808 ich_wr(sc, ICH_REG_GLOB_CNT, ICH_GLOB_CTL_COLD, 4); 809 #endif 810 811 if (ich_resetchan(sc, 0) || ich_resetchan(sc, 1)) 812 return (ENXIO); 813 if (sc->hasmic && ich_resetchan(sc, 2)) 814 return (ENXIO); 815 816 return (0); 817 } 818 819 static int 820 ich_pci_probe(device_t dev) 821 { 822 int i; 823 uint16_t devid, vendor; 824 825 vendor = pci_get_vendor(dev); 826 devid = pci_get_device(dev); 827 for (i = 0; i < sizeof(ich_devs)/sizeof(ich_devs[0]); i++) { 828 if (vendor == ich_devs[i].vendor && 829 devid == ich_devs[i].devid) { 830 device_set_desc(dev, ich_devs[i].name); 831 /* allow a better driver to override us */ 832 if ((ich_devs[i].options & PROBE_LOW) != 0) 833 return (BUS_PROBE_LOW_PRIORITY); 834 return (BUS_PROBE_DEFAULT); 835 } 836 } 837 return (ENXIO); 838 } 839 840 static int 841 ich_pci_attach(device_t dev) 842 { 843 uint32_t subdev; 844 uint16_t extcaps; 845 uint16_t devid, vendor; 846 struct sc_info *sc; 847 int i; 848 849 if ((sc = malloc(sizeof(*sc), M_DEVBUF, M_NOWAIT | M_ZERO)) == NULL) { 850 device_printf(dev, "cannot allocate softc\n"); 851 return (ENXIO); 852 } 853 854 sc->ich_lock = snd_mtxcreate(device_get_nameunit(dev), "sound softc"); 855 sc->dev = dev; 856 857 vendor = sc->vendor = pci_get_vendor(dev); 858 devid = sc->devid = pci_get_device(dev); 859 subdev = (pci_get_subdevice(dev) << 16) | pci_get_subvendor(dev); 860 /* 861 * The SiS 7012 register set isn't quite like the standard ich. 862 * There really should be a general "quirks" mechanism. 863 */ 864 if (vendor == SIS_VENDORID && devid == SIS_7012) { 865 sc->swap_reg = 1; 866 sc->sample_size = 1; 867 } else { 868 sc->swap_reg = 0; 869 sc->sample_size = 2; 870 } 871 872 /* 873 * Enable bus master. On ich4/5 this may prevent the detection of 874 * the primary codec becoming ready in ich_init(). 875 */ 876 pci_enable_busmaster(dev); 877 878 /* 879 * By default, ich4 has NAMBAR and NABMBAR i/o spaces as 880 * read-only. Need to enable "legacy support", by poking into 881 * pci config space. The driver should use MMBAR and MBBAR, 882 * but doing so will mess things up here. ich4 has enough new 883 * features it warrants it's own driver. 884 */ 885 if (vendor == INTEL_VENDORID && (devid == INTEL_82801DB || 886 devid == INTEL_82801EB || devid == INTEL_6300ESB || 887 devid == INTEL_82801FB || devid == INTEL_82801GB)) { 888 sc->nambarid = PCIR_MMBAR; 889 sc->nabmbarid = PCIR_MBBAR; 890 sc->regtype = SYS_RES_MEMORY; 891 pci_write_config(dev, PCIR_ICH_LEGACY, ICH_LEGACY_ENABLE, 1); 892 } else { 893 sc->nambarid = PCIR_NAMBAR; 894 sc->nabmbarid = PCIR_NABMBAR; 895 sc->regtype = SYS_RES_IOPORT; 896 } 897 898 sc->nambar = bus_alloc_resource_any(dev, sc->regtype, 899 &sc->nambarid, RF_ACTIVE); 900 sc->nabmbar = bus_alloc_resource_any(dev, sc->regtype, 901 &sc->nabmbarid, RF_ACTIVE); 902 903 if (!sc->nambar || !sc->nabmbar) { 904 device_printf(dev, "unable to map IO port space\n"); 905 goto bad; 906 } 907 908 sc->nambart = rman_get_bustag(sc->nambar); 909 sc->nambarh = rman_get_bushandle(sc->nambar); 910 sc->nabmbart = rman_get_bustag(sc->nabmbar); 911 sc->nabmbarh = rman_get_bushandle(sc->nabmbar); 912 913 sc->bufsz = pcm_getbuffersize(dev, 914 ICH_MIN_BUFSZ, ICH_DEFAULT_BUFSZ, ICH_MAX_BUFSZ); 915 916 if (resource_int_value(device_get_name(sc->dev), 917 device_get_unit(sc->dev), "blocksize", &i) == 0 && i > 0) { 918 sc->blkcnt = sc->bufsz / i; 919 i = 0; 920 while (sc->blkcnt >> i) 921 i++; 922 sc->blkcnt = 1 << (i - 1); 923 if (sc->blkcnt < ICH_MIN_BLKCNT) 924 sc->blkcnt = ICH_MIN_BLKCNT; 925 else if (sc->blkcnt > ICH_MAX_BLKCNT) 926 sc->blkcnt = ICH_MAX_BLKCNT; 927 } else 928 sc->blkcnt = ICH_DEFAULT_BLKCNT; 929 930 if (resource_int_value(device_get_name(sc->dev), 931 device_get_unit(sc->dev), "fixedrate", &i) == 0 && 932 i != 0) 933 sc->fixedrate = 1; 934 else 935 sc->fixedrate = 0; 936 937 if (bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0, 938 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, 939 NULL, NULL, sc->bufsz, 1, 0x3ffff, 0, 940 NULL, NULL, &sc->dmat) != 0) { 941 device_printf(dev, "unable to create dma tag\n"); 942 goto bad; 943 } 944 945 sc->irqid = 0; 946 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irqid, 947 RF_ACTIVE | RF_SHAREABLE); 948 if (!sc->irq || snd_setup_intr(dev, sc->irq, INTR_MPSAFE, ich_intr, sc, &sc->ih)) { 949 device_printf(dev, "unable to map interrupt\n"); 950 goto bad; 951 } 952 953 if (ich_init(sc)) { 954 device_printf(dev, "unable to initialize the card\n"); 955 goto bad; 956 } 957 958 if (bus_dmamem_alloc(sc->dmat, (void **)&sc->dtbl, 959 BUS_DMA_NOWAIT, &sc->dtmap)) 960 goto bad; 961 962 if (bus_dmamap_load(sc->dmat, sc->dtmap, sc->dtbl, 963 sizeof(struct ich_desc) * ICH_DTBL_LENGTH * 3, 964 ich_setmap, sc, 0)) 965 goto bad; 966 967 sc->codec = AC97_CREATE(dev, sc, ich_ac97); 968 if (sc->codec == NULL) 969 goto bad; 970 971 /* 972 * Turn on inverted external amplifier sense flags for few 973 * 'special' boards. 974 */ 975 switch (subdev) { 976 case 0x202f161f: /* Gateway 7326GZ */ 977 case 0x203a161f: /* Gateway 4028GZ */ 978 case 0x204c161f: /* Kvazar-Micro Senator 3592XT */ 979 case 0x8144104d: /* Sony VAIO PCG-TR* */ 980 case 0x8197104d: /* Sony S1XP */ 981 case 0x81c0104d: /* Sony VAIO type T */ 982 case 0x81c5104d: /* Sony VAIO VGN B1VP/B1XP */ 983 case 0x3089103c: /* Compaq Presario B3800 */ 984 case 0x309a103c: /* HP Compaq nx4300 */ 985 case 0x82131033: /* NEC VersaPro VJ10F/BH */ 986 case 0x82be1033: /* NEC VersaPro VJ12F/CH */ 987 ac97_setflags(sc->codec, ac97_getflags(sc->codec) | AC97_F_EAPD_INV); 988 break; 989 default: 990 break; 991 } 992 993 mixer_init(dev, ac97_getmixerclass(), sc->codec); 994 995 /* check and set VRA function */ 996 extcaps = ac97_getextcaps(sc->codec); 997 sc->hasvra = extcaps & AC97_EXTCAP_VRA; 998 sc->hasvrm = extcaps & AC97_EXTCAP_VRM; 999 sc->hasmic = ac97_getcaps(sc->codec) & AC97_CAP_MICCHANNEL; 1000 ac97_setextmode(sc->codec, sc->hasvra | sc->hasvrm); 1001 1002 if (pcm_register(dev, sc, 1, (sc->hasmic) ? 2 : 1)) 1003 goto bad; 1004 1005 pcm_addchan(dev, PCMDIR_PLAY, &ichchan_class, sc); /* play */ 1006 pcm_addchan(dev, PCMDIR_REC, &ichchan_class, sc); /* record */ 1007 if (sc->hasmic) 1008 pcm_addchan(dev, PCMDIR_REC, &ichchan_class, sc); /* record mic */ 1009 1010 if (sc->fixedrate == 0) { 1011 ich_initsys(sc); 1012 1013 sc->intrhook.ich_func = ich_calibrate; 1014 sc->intrhook.ich_arg = sc; 1015 sc->use_intrhook = 1; 1016 if (config_intrhook_establish(&sc->intrhook) != 0) { 1017 device_printf(dev, "Cannot establish calibration hook, will calibrate now\n"); 1018 sc->use_intrhook = 0; 1019 ich_calibrate(sc); 1020 } 1021 } else { 1022 sc->calibrated = 1; 1023 ich_setstatus(sc); 1024 } 1025 1026 return (0); 1027 1028 bad: 1029 if (sc->codec) 1030 ac97_destroy(sc->codec); 1031 if (sc->ih) 1032 bus_teardown_intr(dev, sc->irq, sc->ih); 1033 if (sc->irq) 1034 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); 1035 if (sc->nambar) 1036 bus_release_resource(dev, sc->regtype, 1037 sc->nambarid, sc->nambar); 1038 if (sc->nabmbar) 1039 bus_release_resource(dev, sc->regtype, 1040 sc->nabmbarid, sc->nabmbar); 1041 if (sc->dtmap) 1042 bus_dmamap_unload(sc->dmat, sc->dtmap); 1043 if (sc->dmat) 1044 bus_dma_tag_destroy(sc->dmat); 1045 if (sc->ich_lock) 1046 snd_mtxfree(sc->ich_lock); 1047 free(sc, M_DEVBUF); 1048 return (ENXIO); 1049 } 1050 1051 static int 1052 ich_pci_detach(device_t dev) 1053 { 1054 struct sc_info *sc; 1055 int r; 1056 1057 r = pcm_unregister(dev); 1058 if (r) 1059 return (r); 1060 sc = pcm_getdevinfo(dev); 1061 1062 bus_teardown_intr(dev, sc->irq, sc->ih); 1063 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq); 1064 bus_release_resource(dev, sc->regtype, sc->nambarid, sc->nambar); 1065 bus_release_resource(dev, sc->regtype, sc->nabmbarid, sc->nabmbar); 1066 bus_dmamap_unload(sc->dmat, sc->dtmap); 1067 bus_dma_tag_destroy(sc->dmat); 1068 snd_mtxfree(sc->ich_lock); 1069 free(sc, M_DEVBUF); 1070 return (0); 1071 } 1072 1073 static void 1074 ich_pci_codec_reset(struct sc_info *sc) 1075 { 1076 int i; 1077 uint32_t control; 1078 1079 control = ich_rd(sc, ICH_REG_GLOB_CNT, 4); 1080 control &= ~(ICH_GLOB_CTL_SHUT); 1081 control |= (control & ICH_GLOB_CTL_COLD) ? 1082 ICH_GLOB_CTL_WARM : ICH_GLOB_CTL_COLD; 1083 ich_wr(sc, ICH_REG_GLOB_CNT, control, 4); 1084 1085 for (i = 500000; i; i--) { 1086 if (ich_rd(sc, ICH_REG_GLOB_STA, 4) & ICH_GLOB_STA_PCR) 1087 break; /* or ICH_SCR? */ 1088 DELAY(1); 1089 } 1090 1091 if (i <= 0) 1092 printf("%s: time out\n", __func__); 1093 } 1094 1095 static int 1096 ich_pci_suspend(device_t dev) 1097 { 1098 struct sc_info *sc; 1099 int i; 1100 1101 sc = pcm_getdevinfo(dev); 1102 ICH_LOCK(sc); 1103 for (i = 0 ; i < 3; i++) { 1104 sc->ch[i].run_save = sc->ch[i].run; 1105 if (sc->ch[i].run) { 1106 ICH_UNLOCK(sc); 1107 ichchan_trigger(0, &sc->ch[i], PCMTRIG_ABORT); 1108 ICH_LOCK(sc); 1109 } 1110 } 1111 ICH_UNLOCK(sc); 1112 return (0); 1113 } 1114 1115 static int 1116 ich_pci_resume(device_t dev) 1117 { 1118 struct sc_info *sc; 1119 int i; 1120 1121 sc = pcm_getdevinfo(dev); 1122 1123 if (sc->regtype == SYS_RES_IOPORT) 1124 pci_enable_io(dev, SYS_RES_IOPORT); 1125 else 1126 pci_enable_io(dev, SYS_RES_MEMORY); 1127 pci_enable_busmaster(dev); 1128 1129 ICH_LOCK(sc); 1130 /* Reinit audio device */ 1131 if (ich_init(sc) == -1) { 1132 device_printf(dev, "unable to reinitialize the card\n"); 1133 ICH_UNLOCK(sc); 1134 return (ENXIO); 1135 } 1136 /* Reinit mixer */ 1137 ich_pci_codec_reset(sc); 1138 ICH_UNLOCK(sc); 1139 ac97_setextmode(sc->codec, sc->hasvra | sc->hasvrm); 1140 if (mixer_reinit(dev) == -1) { 1141 device_printf(dev, "unable to reinitialize the mixer\n"); 1142 return (ENXIO); 1143 } 1144 /* Re-start DMA engines */ 1145 for (i = 0 ; i < 3; i++) { 1146 struct sc_chinfo *ch = &sc->ch[i]; 1147 if (sc->ch[i].run_save) { 1148 ichchan_setblocksize(0, ch, ch->blksz); 1149 ichchan_setspeed(0, ch, ch->spd); 1150 ichchan_trigger(0, ch, PCMTRIG_START); 1151 } 1152 } 1153 return (0); 1154 } 1155 1156 static device_method_t ich_methods[] = { 1157 /* Device interface */ 1158 DEVMETHOD(device_probe, ich_pci_probe), 1159 DEVMETHOD(device_attach, ich_pci_attach), 1160 DEVMETHOD(device_detach, ich_pci_detach), 1161 DEVMETHOD(device_suspend, ich_pci_suspend), 1162 DEVMETHOD(device_resume, ich_pci_resume), 1163 { 0, 0 } 1164 }; 1165 1166 static driver_t ich_driver = { 1167 "pcm", 1168 ich_methods, 1169 PCM_SOFTC_SIZE, 1170 }; 1171 1172 DRIVER_MODULE(snd_ich, pci, ich_driver, pcm_devclass, 0, 0); 1173 MODULE_DEPEND(snd_ich, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 1174 MODULE_VERSION(snd_ich, 1); 1175