1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 1999 Cameron Grant <cg@freebsd.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #ifdef HAVE_KERNEL_OPTION_HEADERS 30 #include "opt_snd.h" 31 #endif 32 33 #include <dev/sound/pcm/sound.h> 34 #include <dev/sound/pcm/ac97.h> 35 #include <dev/sound/pci/t4dwave.h> 36 37 #include <dev/pci/pcireg.h> 38 #include <dev/pci/pcivar.h> 39 40 SND_DECLARE_FILE("$FreeBSD$"); 41 42 /* -------------------------------------------------------------------- */ 43 44 #define TDX_PCI_ID 0x20001023 45 #define TNX_PCI_ID 0x20011023 46 #define ALI_PCI_ID 0x545110b9 47 #define SPA_PCI_ID 0x70181039 48 49 #define TR_DEFAULT_BUFSZ 0x1000 50 /* For ALi M5451 the DMA transfer size appears to be fixed to 64k. */ 51 #define ALI_BUFSZ 0x10000 52 #define TR_BUFALGN 0x8 53 #define TR_TIMEOUT_CDC 0xffff 54 #define TR_MAXHWCH 64 55 #define ALI_MAXHWCH 32 56 #define TR_MAXPLAYCH 4 57 #define ALI_MAXPLAYCH 1 58 /* 59 * Though, it's not clearly documented in the 4DWAVE datasheet, the 60 * DX and NX chips can't handle DMA addresses located above 1GB as the 61 * LBA (loop begin address) register which holds the DMA base address 62 * is 32-bit, but the two MSBs are used for other purposes. 63 */ 64 #define TR_MAXADDR ((1U << 30) - 1) 65 #define ALI_MAXADDR ((1U << 31) - 1) 66 67 struct tr_info; 68 69 /* channel registers */ 70 struct tr_chinfo { 71 u_int32_t cso, alpha, fms, fmc, ec; 72 u_int32_t lba; 73 u_int32_t eso, delta; 74 u_int32_t rvol, cvol; 75 u_int32_t gvsel, pan, vol, ctrl; 76 u_int32_t active:1, was_active:1; 77 int index, bufhalf; 78 struct snd_dbuf *buffer; 79 struct pcm_channel *channel; 80 struct tr_info *parent; 81 }; 82 83 struct tr_rchinfo { 84 u_int32_t delta; 85 u_int32_t active:1, was_active:1; 86 struct snd_dbuf *buffer; 87 struct pcm_channel *channel; 88 struct tr_info *parent; 89 }; 90 91 /* device private data */ 92 struct tr_info { 93 u_int32_t type; 94 u_int32_t rev; 95 96 bus_space_tag_t st; 97 bus_space_handle_t sh; 98 bus_dma_tag_t parent_dmat; 99 100 struct resource *reg, *irq; 101 int regtype, regid, irqid; 102 void *ih; 103 104 struct mtx *lock; 105 106 u_int32_t hwchns; 107 u_int32_t playchns; 108 unsigned int bufsz; 109 110 struct tr_chinfo chinfo[TR_MAXPLAYCH]; 111 struct tr_rchinfo recchinfo; 112 }; 113 114 /* -------------------------------------------------------------------- */ 115 116 static u_int32_t tr_recfmt[] = { 117 SND_FORMAT(AFMT_U8, 1, 0), 118 SND_FORMAT(AFMT_U8, 2, 0), 119 SND_FORMAT(AFMT_S8, 1, 0), 120 SND_FORMAT(AFMT_S8, 2, 0), 121 SND_FORMAT(AFMT_S16_LE, 1, 0), 122 SND_FORMAT(AFMT_S16_LE, 2, 0), 123 SND_FORMAT(AFMT_U16_LE, 1, 0), 124 SND_FORMAT(AFMT_U16_LE, 2, 0), 125 0 126 }; 127 static struct pcmchan_caps tr_reccaps = {4000, 48000, tr_recfmt, 0}; 128 129 static u_int32_t tr_playfmt[] = { 130 SND_FORMAT(AFMT_U8, 1, 0), 131 SND_FORMAT(AFMT_U8, 2, 0), 132 SND_FORMAT(AFMT_S8, 1, 0), 133 SND_FORMAT(AFMT_S8, 2, 0), 134 SND_FORMAT(AFMT_S16_LE, 1, 0), 135 SND_FORMAT(AFMT_S16_LE, 2, 0), 136 SND_FORMAT(AFMT_U16_LE, 1, 0), 137 SND_FORMAT(AFMT_U16_LE, 2, 0), 138 0 139 }; 140 static struct pcmchan_caps tr_playcaps = {4000, 48000, tr_playfmt, 0}; 141 142 /* -------------------------------------------------------------------- */ 143 144 /* Hardware */ 145 146 static u_int32_t 147 tr_rd(struct tr_info *tr, int regno, int size) 148 { 149 switch(size) { 150 case 1: 151 return bus_space_read_1(tr->st, tr->sh, regno); 152 case 2: 153 return bus_space_read_2(tr->st, tr->sh, regno); 154 case 4: 155 return bus_space_read_4(tr->st, tr->sh, regno); 156 default: 157 return 0xffffffff; 158 } 159 } 160 161 static void 162 tr_wr(struct tr_info *tr, int regno, u_int32_t data, int size) 163 { 164 switch(size) { 165 case 1: 166 bus_space_write_1(tr->st, tr->sh, regno, data); 167 break; 168 case 2: 169 bus_space_write_2(tr->st, tr->sh, regno, data); 170 break; 171 case 4: 172 bus_space_write_4(tr->st, tr->sh, regno, data); 173 break; 174 } 175 } 176 177 /* -------------------------------------------------------------------- */ 178 /* ac97 codec */ 179 180 static int 181 tr_rdcd(kobj_t obj, void *devinfo, int regno) 182 { 183 struct tr_info *tr = (struct tr_info *)devinfo; 184 int i, j, treg, trw; 185 186 switch (tr->type) { 187 case SPA_PCI_ID: 188 treg=SPA_REG_CODECRD; 189 trw=SPA_CDC_RWSTAT; 190 break; 191 case ALI_PCI_ID: 192 if (tr->rev > 0x01) 193 treg=TDX_REG_CODECWR; 194 else 195 treg=TDX_REG_CODECRD; 196 trw=TDX_CDC_RWSTAT; 197 break; 198 case TDX_PCI_ID: 199 treg=TDX_REG_CODECRD; 200 trw=TDX_CDC_RWSTAT; 201 break; 202 case TNX_PCI_ID: 203 treg=(regno & 0x100)? TNX_REG_CODEC2RD : TNX_REG_CODEC1RD; 204 trw=TNX_CDC_RWSTAT; 205 break; 206 default: 207 printf("!!! tr_rdcd defaulted !!!\n"); 208 return -1; 209 } 210 211 i = j = 0; 212 213 regno &= 0x7f; 214 snd_mtxlock(tr->lock); 215 if (tr->type == ALI_PCI_ID) { 216 u_int32_t chk1, chk2; 217 j = trw; 218 for (i = TR_TIMEOUT_CDC; (i > 0) && (j & trw); i--) 219 j = tr_rd(tr, treg, 4); 220 if (i > 0) { 221 chk1 = tr_rd(tr, 0xc8, 4); 222 chk2 = tr_rd(tr, 0xc8, 4); 223 for (i = TR_TIMEOUT_CDC; (i > 0) && (chk1 == chk2); 224 i--) 225 chk2 = tr_rd(tr, 0xc8, 4); 226 } 227 } 228 if (tr->type != ALI_PCI_ID || i > 0) { 229 tr_wr(tr, treg, regno | trw, 4); 230 j=trw; 231 for (i=TR_TIMEOUT_CDC; (i > 0) && (j & trw); i--) 232 j=tr_rd(tr, treg, 4); 233 } 234 snd_mtxunlock(tr->lock); 235 if (i == 0) printf("codec timeout during read of register %x\n", regno); 236 return (j >> TR_CDC_DATA) & 0xffff; 237 } 238 239 static int 240 tr_wrcd(kobj_t obj, void *devinfo, int regno, u_int32_t data) 241 { 242 struct tr_info *tr = (struct tr_info *)devinfo; 243 int i, j, treg, trw; 244 245 switch (tr->type) { 246 case SPA_PCI_ID: 247 treg=SPA_REG_CODECWR; 248 trw=SPA_CDC_RWSTAT; 249 break; 250 case ALI_PCI_ID: 251 case TDX_PCI_ID: 252 treg=TDX_REG_CODECWR; 253 trw=TDX_CDC_RWSTAT; 254 break; 255 case TNX_PCI_ID: 256 treg=TNX_REG_CODECWR; 257 trw=TNX_CDC_RWSTAT | ((regno & 0x100)? TNX_CDC_SEC : 0); 258 break; 259 default: 260 printf("!!! tr_wrcd defaulted !!!"); 261 return -1; 262 } 263 264 i = 0; 265 266 regno &= 0x7f; 267 #if 0 268 printf("tr_wrcd: reg %x was %x", regno, tr_rdcd(devinfo, regno)); 269 #endif 270 j=trw; 271 snd_mtxlock(tr->lock); 272 if (tr->type == ALI_PCI_ID) { 273 j = trw; 274 for (i = TR_TIMEOUT_CDC; (i > 0) && (j & trw); i--) 275 j = tr_rd(tr, treg, 4); 276 if (i > 0) { 277 u_int32_t chk1, chk2; 278 chk1 = tr_rd(tr, 0xc8, 4); 279 chk2 = tr_rd(tr, 0xc8, 4); 280 for (i = TR_TIMEOUT_CDC; (i > 0) && (chk1 == chk2); 281 i--) 282 chk2 = tr_rd(tr, 0xc8, 4); 283 } 284 } 285 if (tr->type != ALI_PCI_ID || i > 0) { 286 for (i=TR_TIMEOUT_CDC; (i>0) && (j & trw); i--) 287 j=tr_rd(tr, treg, 4); 288 if (tr->type == ALI_PCI_ID && tr->rev > 0x01) 289 trw |= 0x0100; 290 tr_wr(tr, treg, (data << TR_CDC_DATA) | regno | trw, 4); 291 } 292 #if 0 293 printf(" - wrote %x, now %x\n", data, tr_rdcd(devinfo, regno)); 294 #endif 295 snd_mtxunlock(tr->lock); 296 if (i==0) printf("codec timeout writing %x, data %x\n", regno, data); 297 return (i > 0)? 0 : -1; 298 } 299 300 static kobj_method_t tr_ac97_methods[] = { 301 KOBJMETHOD(ac97_read, tr_rdcd), 302 KOBJMETHOD(ac97_write, tr_wrcd), 303 KOBJMETHOD_END 304 }; 305 AC97_DECLARE(tr_ac97); 306 307 /* -------------------------------------------------------------------- */ 308 /* playback channel interrupts */ 309 310 #if 0 311 static u_int32_t 312 tr_testint(struct tr_chinfo *ch) 313 { 314 struct tr_info *tr = ch->parent; 315 int bank, chan; 316 317 bank = (ch->index & 0x20) ? 1 : 0; 318 chan = ch->index & 0x1f; 319 return tr_rd(tr, bank? TR_REG_ADDRINTB : TR_REG_ADDRINTA, 4) & (1 << chan); 320 } 321 #endif 322 323 static void 324 tr_clrint(struct tr_chinfo *ch) 325 { 326 struct tr_info *tr = ch->parent; 327 int bank, chan; 328 329 bank = (ch->index & 0x20) ? 1 : 0; 330 chan = ch->index & 0x1f; 331 tr_wr(tr, bank? TR_REG_ADDRINTB : TR_REG_ADDRINTA, 1 << chan, 4); 332 } 333 334 static void 335 tr_enaint(struct tr_chinfo *ch, int enable) 336 { 337 struct tr_info *tr = ch->parent; 338 u_int32_t i, reg; 339 int bank, chan; 340 341 snd_mtxlock(tr->lock); 342 bank = (ch->index & 0x20) ? 1 : 0; 343 chan = ch->index & 0x1f; 344 reg = bank? TR_REG_INTENB : TR_REG_INTENA; 345 346 i = tr_rd(tr, reg, 4); 347 i &= ~(1 << chan); 348 i |= (enable? 1 : 0) << chan; 349 350 tr_clrint(ch); 351 tr_wr(tr, reg, i, 4); 352 snd_mtxunlock(tr->lock); 353 } 354 355 /* playback channels */ 356 357 static void 358 tr_selch(struct tr_chinfo *ch) 359 { 360 struct tr_info *tr = ch->parent; 361 int i; 362 363 i = tr_rd(tr, TR_REG_CIR, 4); 364 i &= ~TR_CIR_MASK; 365 i |= ch->index & 0x3f; 366 tr_wr(tr, TR_REG_CIR, i, 4); 367 } 368 369 static void 370 tr_startch(struct tr_chinfo *ch) 371 { 372 struct tr_info *tr = ch->parent; 373 int bank, chan; 374 375 bank = (ch->index & 0x20) ? 1 : 0; 376 chan = ch->index & 0x1f; 377 tr_wr(tr, bank? TR_REG_STARTB : TR_REG_STARTA, 1 << chan, 4); 378 } 379 380 static void 381 tr_stopch(struct tr_chinfo *ch) 382 { 383 struct tr_info *tr = ch->parent; 384 int bank, chan; 385 386 bank = (ch->index & 0x20) ? 1 : 0; 387 chan = ch->index & 0x1f; 388 tr_wr(tr, bank? TR_REG_STOPB : TR_REG_STOPA, 1 << chan, 4); 389 } 390 391 static void 392 tr_wrch(struct tr_chinfo *ch) 393 { 394 struct tr_info *tr = ch->parent; 395 u_int32_t cr[TR_CHN_REGS], i; 396 397 ch->gvsel &= 0x00000001; 398 ch->fmc &= 0x00000003; 399 ch->fms &= 0x0000000f; 400 ch->ctrl &= 0x0000000f; 401 ch->pan &= 0x0000007f; 402 ch->rvol &= 0x0000007f; 403 ch->cvol &= 0x0000007f; 404 ch->vol &= 0x000000ff; 405 ch->ec &= 0x00000fff; 406 ch->alpha &= 0x00000fff; 407 ch->delta &= 0x0000ffff; 408 if (tr->type == ALI_PCI_ID) 409 ch->lba &= ALI_MAXADDR; 410 else 411 ch->lba &= TR_MAXADDR; 412 413 cr[1]=ch->lba; 414 cr[3]=(ch->fmc<<14) | (ch->rvol<<7) | (ch->cvol); 415 cr[4]=(ch->gvsel<<31) | (ch->pan<<24) | (ch->vol<<16) | (ch->ctrl<<12) | (ch->ec); 416 417 switch (tr->type) { 418 case SPA_PCI_ID: 419 case ALI_PCI_ID: 420 case TDX_PCI_ID: 421 ch->cso &= 0x0000ffff; 422 ch->eso &= 0x0000ffff; 423 cr[0]=(ch->cso<<16) | (ch->alpha<<4) | (ch->fms); 424 cr[2]=(ch->eso<<16) | (ch->delta); 425 break; 426 case TNX_PCI_ID: 427 ch->cso &= 0x00ffffff; 428 ch->eso &= 0x00ffffff; 429 cr[0]=((ch->delta & 0xff)<<24) | (ch->cso); 430 cr[2]=((ch->delta>>8)<<24) | (ch->eso); 431 cr[3]|=(ch->alpha<<20) | (ch->fms<<16) | (ch->fmc<<14); 432 break; 433 } 434 snd_mtxlock(tr->lock); 435 tr_selch(ch); 436 for (i=0; i<TR_CHN_REGS; i++) 437 tr_wr(tr, TR_REG_CHNBASE+(i<<2), cr[i], 4); 438 snd_mtxunlock(tr->lock); 439 } 440 441 static void 442 tr_rdch(struct tr_chinfo *ch) 443 { 444 struct tr_info *tr = ch->parent; 445 u_int32_t cr[5], i; 446 447 snd_mtxlock(tr->lock); 448 tr_selch(ch); 449 for (i=0; i<5; i++) 450 cr[i]=tr_rd(tr, TR_REG_CHNBASE+(i<<2), 4); 451 snd_mtxunlock(tr->lock); 452 453 454 if (tr->type == ALI_PCI_ID) 455 ch->lba=(cr[1] & ALI_MAXADDR); 456 else 457 ch->lba=(cr[1] & TR_MAXADDR); 458 ch->fmc= (cr[3] & 0x0000c000) >> 14; 459 ch->rvol= (cr[3] & 0x00003f80) >> 7; 460 ch->cvol= (cr[3] & 0x0000007f); 461 ch->gvsel= (cr[4] & 0x80000000) >> 31; 462 ch->pan= (cr[4] & 0x7f000000) >> 24; 463 ch->vol= (cr[4] & 0x00ff0000) >> 16; 464 ch->ctrl= (cr[4] & 0x0000f000) >> 12; 465 ch->ec= (cr[4] & 0x00000fff); 466 switch(tr->type) { 467 case SPA_PCI_ID: 468 case ALI_PCI_ID: 469 case TDX_PCI_ID: 470 ch->cso= (cr[0] & 0xffff0000) >> 16; 471 ch->alpha= (cr[0] & 0x0000fff0) >> 4; 472 ch->fms= (cr[0] & 0x0000000f); 473 ch->eso= (cr[2] & 0xffff0000) >> 16; 474 ch->delta= (cr[2] & 0x0000ffff); 475 break; 476 case TNX_PCI_ID: 477 ch->cso= (cr[0] & 0x00ffffff); 478 ch->eso= (cr[2] & 0x00ffffff); 479 ch->delta= ((cr[2] & 0xff000000) >> 16) | ((cr[0] & 0xff000000) >> 24); 480 ch->alpha= (cr[3] & 0xfff00000) >> 20; 481 ch->fms= (cr[3] & 0x000f0000) >> 16; 482 break; 483 } 484 } 485 486 static u_int32_t 487 tr_fmttobits(u_int32_t fmt) 488 { 489 u_int32_t bits; 490 491 bits = 0; 492 bits |= (fmt & AFMT_SIGNED)? 0x2 : 0; 493 bits |= (AFMT_CHANNEL(fmt) > 1)? 0x4 : 0; 494 bits |= (fmt & AFMT_16BIT)? 0x8 : 0; 495 496 return bits; 497 } 498 499 /* -------------------------------------------------------------------- */ 500 /* channel interface */ 501 502 static void * 503 trpchan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir) 504 { 505 struct tr_info *tr = devinfo; 506 struct tr_chinfo *ch; 507 508 KASSERT(dir == PCMDIR_PLAY, ("trpchan_init: bad direction")); 509 ch = &tr->chinfo[tr->playchns]; 510 ch->index = tr->playchns++; 511 ch->buffer = b; 512 ch->parent = tr; 513 ch->channel = c; 514 if (sndbuf_alloc(ch->buffer, tr->parent_dmat, 0, tr->bufsz) != 0) 515 return NULL; 516 517 return ch; 518 } 519 520 static int 521 trpchan_setformat(kobj_t obj, void *data, u_int32_t format) 522 { 523 struct tr_chinfo *ch = data; 524 525 ch->ctrl = tr_fmttobits(format) | 0x01; 526 527 return 0; 528 } 529 530 static u_int32_t 531 trpchan_setspeed(kobj_t obj, void *data, u_int32_t speed) 532 { 533 struct tr_chinfo *ch = data; 534 535 ch->delta = (speed << 12) / 48000; 536 return (ch->delta * 48000) >> 12; 537 } 538 539 static u_int32_t 540 trpchan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize) 541 { 542 struct tr_chinfo *ch = data; 543 544 sndbuf_resize(ch->buffer, 2, blocksize); 545 return blocksize; 546 } 547 548 static int 549 trpchan_trigger(kobj_t obj, void *data, int go) 550 { 551 struct tr_chinfo *ch = data; 552 553 if (!PCMTRIG_COMMON(go)) 554 return 0; 555 556 if (go == PCMTRIG_START) { 557 ch->fmc = 3; 558 ch->fms = 0; 559 ch->ec = 0; 560 ch->alpha = 0; 561 ch->lba = sndbuf_getbufaddr(ch->buffer); 562 ch->cso = 0; 563 ch->eso = (sndbuf_getsize(ch->buffer) / sndbuf_getalign(ch->buffer)) - 1; 564 ch->rvol = ch->cvol = 0x7f; 565 ch->gvsel = 0; 566 ch->pan = 0; 567 ch->vol = 0; 568 ch->bufhalf = 0; 569 tr_wrch(ch); 570 tr_enaint(ch, 1); 571 tr_startch(ch); 572 ch->active = 1; 573 } else { 574 tr_stopch(ch); 575 ch->active = 0; 576 } 577 578 return 0; 579 } 580 581 static u_int32_t 582 trpchan_getptr(kobj_t obj, void *data) 583 { 584 struct tr_chinfo *ch = data; 585 586 tr_rdch(ch); 587 return ch->cso * sndbuf_getalign(ch->buffer); 588 } 589 590 static struct pcmchan_caps * 591 trpchan_getcaps(kobj_t obj, void *data) 592 { 593 return &tr_playcaps; 594 } 595 596 static kobj_method_t trpchan_methods[] = { 597 KOBJMETHOD(channel_init, trpchan_init), 598 KOBJMETHOD(channel_setformat, trpchan_setformat), 599 KOBJMETHOD(channel_setspeed, trpchan_setspeed), 600 KOBJMETHOD(channel_setblocksize, trpchan_setblocksize), 601 KOBJMETHOD(channel_trigger, trpchan_trigger), 602 KOBJMETHOD(channel_getptr, trpchan_getptr), 603 KOBJMETHOD(channel_getcaps, trpchan_getcaps), 604 KOBJMETHOD_END 605 }; 606 CHANNEL_DECLARE(trpchan); 607 608 /* -------------------------------------------------------------------- */ 609 /* rec channel interface */ 610 611 static void * 612 trrchan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir) 613 { 614 struct tr_info *tr = devinfo; 615 struct tr_rchinfo *ch; 616 617 KASSERT(dir == PCMDIR_REC, ("trrchan_init: bad direction")); 618 ch = &tr->recchinfo; 619 ch->buffer = b; 620 ch->parent = tr; 621 ch->channel = c; 622 if (sndbuf_alloc(ch->buffer, tr->parent_dmat, 0, tr->bufsz) != 0) 623 return NULL; 624 625 return ch; 626 } 627 628 static int 629 trrchan_setformat(kobj_t obj, void *data, u_int32_t format) 630 { 631 struct tr_rchinfo *ch = data; 632 struct tr_info *tr = ch->parent; 633 u_int32_t i, bits; 634 635 bits = tr_fmttobits(format); 636 /* set # of samples between interrupts */ 637 i = (sndbuf_runsz(ch->buffer) >> ((bits & 0x08)? 1 : 0)) - 1; 638 tr_wr(tr, TR_REG_SBBL, i | (i << 16), 4); 639 /* set sample format */ 640 i = 0x18 | (bits << 4); 641 tr_wr(tr, TR_REG_SBCTRL, i, 1); 642 643 return 0; 644 } 645 646 static u_int32_t 647 trrchan_setspeed(kobj_t obj, void *data, u_int32_t speed) 648 { 649 struct tr_rchinfo *ch = data; 650 struct tr_info *tr = ch->parent; 651 652 /* setup speed */ 653 ch->delta = (48000 << 12) / speed; 654 tr_wr(tr, TR_REG_SBDELTA, ch->delta, 2); 655 656 /* return closest possible speed */ 657 return (48000 << 12) / ch->delta; 658 } 659 660 static u_int32_t 661 trrchan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize) 662 { 663 struct tr_rchinfo *ch = data; 664 665 sndbuf_resize(ch->buffer, 2, blocksize); 666 667 return blocksize; 668 } 669 670 static int 671 trrchan_trigger(kobj_t obj, void *data, int go) 672 { 673 struct tr_rchinfo *ch = data; 674 struct tr_info *tr = ch->parent; 675 u_int32_t i; 676 677 if (!PCMTRIG_COMMON(go)) 678 return 0; 679 680 if (go == PCMTRIG_START) { 681 /* set up dma mode regs */ 682 tr_wr(tr, TR_REG_DMAR15, 0, 1); 683 i = tr_rd(tr, TR_REG_DMAR11, 1) & 0x03; 684 tr_wr(tr, TR_REG_DMAR11, i | 0x54, 1); 685 /* set up base address */ 686 tr_wr(tr, TR_REG_DMAR0, sndbuf_getbufaddr(ch->buffer), 4); 687 /* set up buffer size */ 688 i = tr_rd(tr, TR_REG_DMAR4, 4) & ~0x00ffffff; 689 tr_wr(tr, TR_REG_DMAR4, i | (sndbuf_runsz(ch->buffer) - 1), 4); 690 /* start */ 691 tr_wr(tr, TR_REG_SBCTRL, tr_rd(tr, TR_REG_SBCTRL, 1) | 1, 1); 692 ch->active = 1; 693 } else { 694 tr_wr(tr, TR_REG_SBCTRL, tr_rd(tr, TR_REG_SBCTRL, 1) & ~7, 1); 695 ch->active = 0; 696 } 697 698 /* return 0 if ok */ 699 return 0; 700 } 701 702 static u_int32_t 703 trrchan_getptr(kobj_t obj, void *data) 704 { 705 struct tr_rchinfo *ch = data; 706 struct tr_info *tr = ch->parent; 707 708 /* return current byte offset of channel */ 709 return tr_rd(tr, TR_REG_DMAR0, 4) - sndbuf_getbufaddr(ch->buffer); 710 } 711 712 static struct pcmchan_caps * 713 trrchan_getcaps(kobj_t obj, void *data) 714 { 715 return &tr_reccaps; 716 } 717 718 static kobj_method_t trrchan_methods[] = { 719 KOBJMETHOD(channel_init, trrchan_init), 720 KOBJMETHOD(channel_setformat, trrchan_setformat), 721 KOBJMETHOD(channel_setspeed, trrchan_setspeed), 722 KOBJMETHOD(channel_setblocksize, trrchan_setblocksize), 723 KOBJMETHOD(channel_trigger, trrchan_trigger), 724 KOBJMETHOD(channel_getptr, trrchan_getptr), 725 KOBJMETHOD(channel_getcaps, trrchan_getcaps), 726 KOBJMETHOD_END 727 }; 728 CHANNEL_DECLARE(trrchan); 729 730 /* -------------------------------------------------------------------- */ 731 /* The interrupt handler */ 732 733 static void 734 tr_intr(void *p) 735 { 736 struct tr_info *tr = (struct tr_info *)p; 737 struct tr_chinfo *ch; 738 u_int32_t active, mask, bufhalf, chnum, intsrc; 739 int tmp; 740 741 intsrc = tr_rd(tr, TR_REG_MISCINT, 4); 742 if (intsrc & TR_INT_ADDR) { 743 chnum = 0; 744 while (chnum < tr->hwchns) { 745 mask = 0x00000001; 746 active = tr_rd(tr, (chnum < 32)? TR_REG_ADDRINTA : TR_REG_ADDRINTB, 4); 747 bufhalf = tr_rd(tr, (chnum < 32)? TR_REG_CSPF_A : TR_REG_CSPF_B, 4); 748 if (active) { 749 do { 750 if (active & mask) { 751 tmp = (bufhalf & mask)? 1 : 0; 752 if (chnum < tr->playchns) { 753 ch = &tr->chinfo[chnum]; 754 /* printf("%d @ %d, ", chnum, trpchan_getptr(NULL, ch)); */ 755 if (ch->bufhalf != tmp) { 756 chn_intr(ch->channel); 757 ch->bufhalf = tmp; 758 } 759 } 760 } 761 chnum++; 762 mask <<= 1; 763 } while (chnum & 31); 764 } else 765 chnum += 32; 766 767 tr_wr(tr, (chnum <= 32)? TR_REG_ADDRINTA : TR_REG_ADDRINTB, active, 4); 768 } 769 } 770 if (intsrc & TR_INT_SB) { 771 chn_intr(tr->recchinfo.channel); 772 tr_rd(tr, TR_REG_SBR9, 1); 773 tr_rd(tr, TR_REG_SBR10, 1); 774 } 775 } 776 777 /* -------------------------------------------------------------------- */ 778 779 /* 780 * Probe and attach the card 781 */ 782 783 static int 784 tr_init(struct tr_info *tr) 785 { 786 switch (tr->type) { 787 case SPA_PCI_ID: 788 tr_wr(tr, SPA_REG_GPIO, 0, 4); 789 tr_wr(tr, SPA_REG_CODECST, SPA_RST_OFF, 4); 790 break; 791 case TDX_PCI_ID: 792 tr_wr(tr, TDX_REG_CODECST, TDX_CDC_ON, 4); 793 break; 794 case TNX_PCI_ID: 795 tr_wr(tr, TNX_REG_CODECST, TNX_CDC_ON, 4); 796 break; 797 } 798 799 tr_wr(tr, TR_REG_CIR, TR_CIR_MIDENA | TR_CIR_ADDRENA, 4); 800 return 0; 801 } 802 803 static int 804 tr_pci_probe(device_t dev) 805 { 806 switch (pci_get_devid(dev)) { 807 case SPA_PCI_ID: 808 device_set_desc(dev, "SiS 7018"); 809 return BUS_PROBE_DEFAULT; 810 case ALI_PCI_ID: 811 device_set_desc(dev, "Acer Labs M5451"); 812 return BUS_PROBE_DEFAULT; 813 case TDX_PCI_ID: 814 device_set_desc(dev, "Trident 4DWave DX"); 815 return BUS_PROBE_DEFAULT; 816 case TNX_PCI_ID: 817 device_set_desc(dev, "Trident 4DWave NX"); 818 return BUS_PROBE_DEFAULT; 819 } 820 821 return ENXIO; 822 } 823 824 static int 825 tr_pci_attach(device_t dev) 826 { 827 struct tr_info *tr; 828 struct ac97_info *codec = NULL; 829 bus_addr_t lowaddr; 830 int i, dacn; 831 char status[SND_STATUSLEN]; 832 #ifdef __sparc64__ 833 device_t *children; 834 int nchildren; 835 u_int32_t data; 836 #endif 837 838 tr = malloc(sizeof(*tr), M_DEVBUF, M_WAITOK | M_ZERO); 839 tr->type = pci_get_devid(dev); 840 tr->rev = pci_get_revid(dev); 841 tr->lock = snd_mtxcreate(device_get_nameunit(dev), "snd_t4dwave softc"); 842 843 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 844 "dac", &i) == 0) { 845 if (i < 1) 846 dacn = 1; 847 else if (i > TR_MAXPLAYCH) 848 dacn = TR_MAXPLAYCH; 849 else 850 dacn = i; 851 } else { 852 switch (tr->type) { 853 case ALI_PCI_ID: 854 dacn = ALI_MAXPLAYCH; 855 break; 856 default: 857 dacn = TR_MAXPLAYCH; 858 break; 859 } 860 } 861 862 pci_enable_busmaster(dev); 863 864 tr->regid = PCIR_BAR(0); 865 tr->regtype = SYS_RES_IOPORT; 866 tr->reg = bus_alloc_resource_any(dev, tr->regtype, &tr->regid, 867 RF_ACTIVE); 868 if (tr->reg) { 869 tr->st = rman_get_bustag(tr->reg); 870 tr->sh = rman_get_bushandle(tr->reg); 871 } else { 872 device_printf(dev, "unable to map register space\n"); 873 goto bad; 874 } 875 876 if (tr_init(tr) == -1) { 877 device_printf(dev, "unable to initialize the card\n"); 878 goto bad; 879 } 880 tr->playchns = 0; 881 882 codec = AC97_CREATE(dev, tr, tr_ac97); 883 if (codec == NULL) goto bad; 884 if (mixer_init(dev, ac97_getmixerclass(), codec) == -1) goto bad; 885 886 tr->irqid = 0; 887 tr->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &tr->irqid, 888 RF_ACTIVE | RF_SHAREABLE); 889 if (!tr->irq || snd_setup_intr(dev, tr->irq, 0, tr_intr, tr, &tr->ih)) { 890 device_printf(dev, "unable to map interrupt\n"); 891 goto bad; 892 } 893 894 if (tr->type == ALI_PCI_ID) { 895 /* 896 * The M5451 generates 31 bit of DMA and in order to do 897 * 32-bit DMA, the 31st bit can be set via its accompanying 898 * ISA bridge. Note that we can't predict whether bus_dma(9) 899 * will actually supply us with a 32-bit buffer and even when 900 * using a low address of BUS_SPACE_MAXADDR_32BIT for both 901 * we might end up with the play buffer being in the 32-bit 902 * range while the record buffer isn't or vice versa. So we 903 * limit enabling the 31st bit to sparc64, where the IOMMU 904 * guarantees that we're using a 32-bit address (and in turn 905 * requires it). 906 */ 907 lowaddr = ALI_MAXADDR; 908 #ifdef __sparc64__ 909 if (device_get_children(device_get_parent(dev), &children, 910 &nchildren) == 0) { 911 for (i = 0; i < nchildren; i++) { 912 if (pci_get_devid(children[i]) == 0x153310b9) { 913 lowaddr = BUS_SPACE_MAXADDR_32BIT; 914 data = pci_read_config(children[i], 915 0x7e, 1); 916 if (bootverbose) 917 device_printf(dev, 918 "M1533 0x7e: 0x%x -> ", 919 data); 920 data |= 0x1; 921 if (bootverbose) 922 printf("0x%x\n", data); 923 pci_write_config(children[i], 0x7e, 924 data, 1); 925 break; 926 } 927 } 928 } 929 free(children, M_TEMP); 930 #endif 931 tr->hwchns = ALI_MAXHWCH; 932 tr->bufsz = ALI_BUFSZ; 933 } else { 934 lowaddr = TR_MAXADDR; 935 tr->hwchns = TR_MAXHWCH; 936 tr->bufsz = pcm_getbuffersize(dev, 4096, TR_DEFAULT_BUFSZ, 937 65536); 938 } 939 940 if (bus_dma_tag_create(/*parent*/bus_get_dma_tag(dev), 941 /*alignment*/TR_BUFALGN, 942 /*boundary*/0, 943 /*lowaddr*/lowaddr, 944 /*highaddr*/BUS_SPACE_MAXADDR, 945 /*filter*/NULL, /*filterarg*/NULL, 946 /*maxsize*/tr->bufsz, /*nsegments*/1, /*maxsegz*/tr->bufsz, 947 /*flags*/0, /*lockfunc*/busdma_lock_mutex, 948 /*lockarg*/&Giant, &tr->parent_dmat) != 0) { 949 device_printf(dev, "unable to create dma tag\n"); 950 goto bad; 951 } 952 953 snprintf(status, 64, "at io 0x%jx irq %jd %s", 954 rman_get_start(tr->reg), rman_get_start(tr->irq),PCM_KLDSTRING(snd_t4dwave)); 955 956 if (pcm_register(dev, tr, dacn, 1)) 957 goto bad; 958 pcm_addchan(dev, PCMDIR_REC, &trrchan_class, tr); 959 for (i = 0; i < dacn; i++) 960 pcm_addchan(dev, PCMDIR_PLAY, &trpchan_class, tr); 961 pcm_setstatus(dev, status); 962 963 return 0; 964 965 bad: 966 if (codec) ac97_destroy(codec); 967 if (tr->reg) bus_release_resource(dev, tr->regtype, tr->regid, tr->reg); 968 if (tr->ih) bus_teardown_intr(dev, tr->irq, tr->ih); 969 if (tr->irq) bus_release_resource(dev, SYS_RES_IRQ, tr->irqid, tr->irq); 970 if (tr->parent_dmat) bus_dma_tag_destroy(tr->parent_dmat); 971 if (tr->lock) snd_mtxfree(tr->lock); 972 free(tr, M_DEVBUF); 973 return ENXIO; 974 } 975 976 static int 977 tr_pci_detach(device_t dev) 978 { 979 int r; 980 struct tr_info *tr; 981 982 r = pcm_unregister(dev); 983 if (r) 984 return r; 985 986 tr = pcm_getdevinfo(dev); 987 bus_release_resource(dev, tr->regtype, tr->regid, tr->reg); 988 bus_teardown_intr(dev, tr->irq, tr->ih); 989 bus_release_resource(dev, SYS_RES_IRQ, tr->irqid, tr->irq); 990 bus_dma_tag_destroy(tr->parent_dmat); 991 snd_mtxfree(tr->lock); 992 free(tr, M_DEVBUF); 993 994 return 0; 995 } 996 997 static int 998 tr_pci_suspend(device_t dev) 999 { 1000 int i; 1001 struct tr_info *tr; 1002 1003 tr = pcm_getdevinfo(dev); 1004 1005 for (i = 0; i < tr->playchns; i++) { 1006 tr->chinfo[i].was_active = tr->chinfo[i].active; 1007 if (tr->chinfo[i].active) { 1008 trpchan_trigger(NULL, &tr->chinfo[i], PCMTRIG_STOP); 1009 } 1010 } 1011 1012 tr->recchinfo.was_active = tr->recchinfo.active; 1013 if (tr->recchinfo.active) { 1014 trrchan_trigger(NULL, &tr->recchinfo, PCMTRIG_STOP); 1015 } 1016 1017 return 0; 1018 } 1019 1020 static int 1021 tr_pci_resume(device_t dev) 1022 { 1023 int i; 1024 struct tr_info *tr; 1025 1026 tr = pcm_getdevinfo(dev); 1027 1028 if (tr_init(tr) == -1) { 1029 device_printf(dev, "unable to initialize the card\n"); 1030 return ENXIO; 1031 } 1032 1033 if (mixer_reinit(dev) == -1) { 1034 device_printf(dev, "unable to initialize the mixer\n"); 1035 return ENXIO; 1036 } 1037 1038 for (i = 0; i < tr->playchns; i++) { 1039 if (tr->chinfo[i].was_active) { 1040 trpchan_trigger(NULL, &tr->chinfo[i], PCMTRIG_START); 1041 } 1042 } 1043 1044 if (tr->recchinfo.was_active) { 1045 trrchan_trigger(NULL, &tr->recchinfo, PCMTRIG_START); 1046 } 1047 1048 return 0; 1049 } 1050 1051 static device_method_t tr_methods[] = { 1052 /* Device interface */ 1053 DEVMETHOD(device_probe, tr_pci_probe), 1054 DEVMETHOD(device_attach, tr_pci_attach), 1055 DEVMETHOD(device_detach, tr_pci_detach), 1056 DEVMETHOD(device_suspend, tr_pci_suspend), 1057 DEVMETHOD(device_resume, tr_pci_resume), 1058 { 0, 0 } 1059 }; 1060 1061 static driver_t tr_driver = { 1062 "pcm", 1063 tr_methods, 1064 PCM_SOFTC_SIZE, 1065 }; 1066 1067 DRIVER_MODULE(snd_t4dwave, pci, tr_driver, pcm_devclass, 0, 0); 1068 MODULE_DEPEND(snd_t4dwave, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 1069 MODULE_VERSION(snd_t4dwave, 1); 1070