1 /*- 2 * SPDX-License-Identifier: BSD-4-Clause 3 * 4 * Copyright (c) 1997, 1998, 1999 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD. 37 * Manuals, sample driver and firmware source kits are available 38 * from http://www.alteon.com/support/openkits. 39 * 40 * Written by Bill Paul <wpaul@ctr.columbia.edu> 41 * Electrical Engineering Department 42 * Columbia University, New York City 43 */ 44 45 /* 46 * The Alteon Networks Tigon chip contains an embedded R4000 CPU, 47 * gigabit MAC, dual DMA channels and a PCI interface unit. NICs 48 * using the Tigon may have anywhere from 512K to 2MB of SRAM. The 49 * Tigon supports hardware IP, TCP and UCP checksumming, multicast 50 * filtering and jumbo (9014 byte) frames. The hardware is largely 51 * controlled by firmware, which must be loaded into the NIC during 52 * initialization. 53 * 54 * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware 55 * revision, which supports new features such as extended commands, 56 * extended jumbo receive ring desciptors and a mini receive ring. 57 * 58 * Alteon Networks is to be commended for releasing such a vast amount 59 * of development material for the Tigon NIC without requiring an NDA 60 * (although they really should have done it a long time ago). With 61 * any luck, the other vendors will finally wise up and follow Alteon's 62 * stellar example. 63 * 64 * The firmware for the Tigon 1 and 2 NICs is compiled directly into 65 * this driver by #including it as a C header file. This bloats the 66 * driver somewhat, but it's the easiest method considering that the 67 * driver code and firmware code need to be kept in sync. The source 68 * for the firmware is not provided with the FreeBSD distribution since 69 * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3. 70 * 71 * The following people deserve special thanks: 72 * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board 73 * for testing 74 * - Raymond Lee of Netgear, for providing a pair of Netgear 75 * GA620 Tigon 2 boards for testing 76 * - Ulf Zimmermann, for bringing the GA260 to my attention and 77 * convincing me to write this driver. 78 * - Andrew Gallatin for providing FreeBSD/Alpha support. 79 */ 80 81 #include <sys/cdefs.h> 82 __FBSDID("$FreeBSD$"); 83 84 #include "opt_ti.h" 85 86 #include <sys/param.h> 87 #include <sys/systm.h> 88 #include <sys/sockio.h> 89 #include <sys/mbuf.h> 90 #include <sys/malloc.h> 91 #include <sys/kernel.h> 92 #include <sys/module.h> 93 #include <sys/socket.h> 94 #include <sys/queue.h> 95 #include <sys/conf.h> 96 #include <sys/sf_buf.h> 97 98 #include <net/if.h> 99 #include <net/if_var.h> 100 #include <net/if_arp.h> 101 #include <net/ethernet.h> 102 #include <net/if_dl.h> 103 #include <net/if_media.h> 104 #include <net/if_types.h> 105 #include <net/if_vlan_var.h> 106 107 #include <net/bpf.h> 108 109 #include <netinet/in_systm.h> 110 #include <netinet/in.h> 111 #include <netinet/ip.h> 112 113 #include <machine/bus.h> 114 #include <machine/resource.h> 115 #include <sys/bus.h> 116 #include <sys/rman.h> 117 118 #ifdef TI_SF_BUF_JUMBO 119 #include <vm/vm.h> 120 #include <vm/vm_page.h> 121 #endif 122 123 #include <dev/pci/pcireg.h> 124 #include <dev/pci/pcivar.h> 125 126 #include <sys/tiio.h> 127 #include <dev/ti/if_tireg.h> 128 #include <dev/ti/ti_fw.h> 129 #include <dev/ti/ti_fw2.h> 130 131 #include <sys/sysctl.h> 132 133 #define TI_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 134 /* 135 * We can only turn on header splitting if we're using extended receive 136 * BDs. 137 */ 138 #if defined(TI_JUMBO_HDRSPLIT) && !defined(TI_SF_BUF_JUMBO) 139 #error "options TI_JUMBO_HDRSPLIT requires TI_SF_BUF_JUMBO" 140 #endif /* TI_JUMBO_HDRSPLIT && !TI_SF_BUF_JUMBO */ 141 142 typedef enum { 143 TI_SWAP_HTON, 144 TI_SWAP_NTOH 145 } ti_swap_type; 146 147 /* 148 * Various supported device vendors/types and their names. 149 */ 150 151 static const struct ti_type ti_devs[] = { 152 { ALT_VENDORID, ALT_DEVICEID_ACENIC, 153 "Alteon AceNIC 1000baseSX Gigabit Ethernet" }, 154 { ALT_VENDORID, ALT_DEVICEID_ACENIC_COPPER, 155 "Alteon AceNIC 1000baseT Gigabit Ethernet" }, 156 { TC_VENDORID, TC_DEVICEID_3C985, 157 "3Com 3c985-SX Gigabit Ethernet" }, 158 { NG_VENDORID, NG_DEVICEID_GA620, 159 "Netgear GA620 1000baseSX Gigabit Ethernet" }, 160 { NG_VENDORID, NG_DEVICEID_GA620T, 161 "Netgear GA620 1000baseT Gigabit Ethernet" }, 162 { SGI_VENDORID, SGI_DEVICEID_TIGON, 163 "Silicon Graphics Gigabit Ethernet" }, 164 { DEC_VENDORID, DEC_DEVICEID_FARALLON_PN9000SX, 165 "Farallon PN9000SX Gigabit Ethernet" }, 166 { 0, 0, NULL } 167 }; 168 169 170 static d_open_t ti_open; 171 static d_close_t ti_close; 172 static d_ioctl_t ti_ioctl2; 173 174 static struct cdevsw ti_cdevsw = { 175 .d_version = D_VERSION, 176 .d_flags = 0, 177 .d_open = ti_open, 178 .d_close = ti_close, 179 .d_ioctl = ti_ioctl2, 180 .d_name = "ti", 181 }; 182 183 static int ti_probe(device_t); 184 static int ti_attach(device_t); 185 static int ti_detach(device_t); 186 static void ti_txeof(struct ti_softc *); 187 static void ti_rxeof(struct ti_softc *); 188 189 static int ti_encap(struct ti_softc *, struct mbuf **); 190 191 static void ti_intr(void *); 192 static void ti_start(struct ifnet *); 193 static void ti_start_locked(struct ifnet *); 194 static int ti_ioctl(struct ifnet *, u_long, caddr_t); 195 static uint64_t ti_get_counter(struct ifnet *, ift_counter); 196 static void ti_init(void *); 197 static void ti_init_locked(void *); 198 static void ti_init2(struct ti_softc *); 199 static void ti_stop(struct ti_softc *); 200 static void ti_watchdog(void *); 201 static int ti_shutdown(device_t); 202 static int ti_ifmedia_upd(struct ifnet *); 203 static int ti_ifmedia_upd_locked(struct ti_softc *); 204 static void ti_ifmedia_sts(struct ifnet *, struct ifmediareq *); 205 206 static uint32_t ti_eeprom_putbyte(struct ti_softc *, int); 207 static uint8_t ti_eeprom_getbyte(struct ti_softc *, int, uint8_t *); 208 static int ti_read_eeprom(struct ti_softc *, caddr_t, int, int); 209 210 static void ti_add_mcast(struct ti_softc *, struct ether_addr *); 211 static void ti_del_mcast(struct ti_softc *, struct ether_addr *); 212 static void ti_setmulti(struct ti_softc *); 213 214 static void ti_mem_read(struct ti_softc *, uint32_t, uint32_t, void *); 215 static void ti_mem_write(struct ti_softc *, uint32_t, uint32_t, void *); 216 static void ti_mem_zero(struct ti_softc *, uint32_t, uint32_t); 217 static int ti_copy_mem(struct ti_softc *, uint32_t, uint32_t, caddr_t, int, 218 int); 219 static int ti_copy_scratch(struct ti_softc *, uint32_t, uint32_t, caddr_t, 220 int, int, int); 221 static int ti_bcopy_swap(const void *, void *, size_t, ti_swap_type); 222 static void ti_loadfw(struct ti_softc *); 223 static void ti_cmd(struct ti_softc *, struct ti_cmd_desc *); 224 static void ti_cmd_ext(struct ti_softc *, struct ti_cmd_desc *, caddr_t, int); 225 static void ti_handle_events(struct ti_softc *); 226 static void ti_dma_map_addr(void *, bus_dma_segment_t *, int, int); 227 static int ti_dma_alloc(struct ti_softc *); 228 static void ti_dma_free(struct ti_softc *); 229 static int ti_dma_ring_alloc(struct ti_softc *, bus_size_t, bus_size_t, 230 bus_dma_tag_t *, uint8_t **, bus_dmamap_t *, bus_addr_t *, const char *); 231 static void ti_dma_ring_free(struct ti_softc *, bus_dma_tag_t *, uint8_t **, 232 bus_dmamap_t, bus_addr_t *); 233 static int ti_newbuf_std(struct ti_softc *, int); 234 static int ti_newbuf_mini(struct ti_softc *, int); 235 static int ti_newbuf_jumbo(struct ti_softc *, int, struct mbuf *); 236 static int ti_init_rx_ring_std(struct ti_softc *); 237 static void ti_free_rx_ring_std(struct ti_softc *); 238 static int ti_init_rx_ring_jumbo(struct ti_softc *); 239 static void ti_free_rx_ring_jumbo(struct ti_softc *); 240 static int ti_init_rx_ring_mini(struct ti_softc *); 241 static void ti_free_rx_ring_mini(struct ti_softc *); 242 static void ti_free_tx_ring(struct ti_softc *); 243 static int ti_init_tx_ring(struct ti_softc *); 244 static void ti_discard_std(struct ti_softc *, int); 245 #ifndef TI_SF_BUF_JUMBO 246 static void ti_discard_jumbo(struct ti_softc *, int); 247 #endif 248 static void ti_discard_mini(struct ti_softc *, int); 249 250 static int ti_64bitslot_war(struct ti_softc *); 251 static int ti_chipinit(struct ti_softc *); 252 static int ti_gibinit(struct ti_softc *); 253 254 #ifdef TI_JUMBO_HDRSPLIT 255 static __inline void ti_hdr_split(struct mbuf *top, int hdr_len, int pkt_len, 256 int idx); 257 #endif /* TI_JUMBO_HDRSPLIT */ 258 259 static void ti_sysctl_node(struct ti_softc *); 260 261 static device_method_t ti_methods[] = { 262 /* Device interface */ 263 DEVMETHOD(device_probe, ti_probe), 264 DEVMETHOD(device_attach, ti_attach), 265 DEVMETHOD(device_detach, ti_detach), 266 DEVMETHOD(device_shutdown, ti_shutdown), 267 { 0, 0 } 268 }; 269 270 static driver_t ti_driver = { 271 "ti", 272 ti_methods, 273 sizeof(struct ti_softc) 274 }; 275 276 static devclass_t ti_devclass; 277 278 DRIVER_MODULE(ti, pci, ti_driver, ti_devclass, 0, 0); 279 MODULE_DEPEND(ti, pci, 1, 1, 1); 280 MODULE_DEPEND(ti, ether, 1, 1, 1); 281 282 /* 283 * Send an instruction or address to the EEPROM, check for ACK. 284 */ 285 static uint32_t 286 ti_eeprom_putbyte(struct ti_softc *sc, int byte) 287 { 288 int i, ack = 0; 289 290 /* 291 * Make sure we're in TX mode. 292 */ 293 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 294 295 /* 296 * Feed in each bit and stobe the clock. 297 */ 298 for (i = 0x80; i; i >>= 1) { 299 if (byte & i) { 300 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 301 } else { 302 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 303 } 304 DELAY(1); 305 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 306 DELAY(1); 307 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 308 } 309 310 /* 311 * Turn off TX mode. 312 */ 313 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 314 315 /* 316 * Check for ack. 317 */ 318 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 319 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN; 320 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 321 322 return (ack); 323 } 324 325 /* 326 * Read a byte of data stored in the EEPROM at address 'addr.' 327 * We have to send two address bytes since the EEPROM can hold 328 * more than 256 bytes of data. 329 */ 330 static uint8_t 331 ti_eeprom_getbyte(struct ti_softc *sc, int addr, uint8_t *dest) 332 { 333 int i; 334 uint8_t byte = 0; 335 336 EEPROM_START; 337 338 /* 339 * Send write control code to EEPROM. 340 */ 341 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 342 device_printf(sc->ti_dev, 343 "failed to send write command, status: %x\n", 344 CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 345 return (1); 346 } 347 348 /* 349 * Send first byte of address of byte we want to read. 350 */ 351 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) { 352 device_printf(sc->ti_dev, "failed to send address, status: %x\n", 353 CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 354 return (1); 355 } 356 /* 357 * Send second byte address of byte we want to read. 358 */ 359 if (ti_eeprom_putbyte(sc, addr & 0xFF)) { 360 device_printf(sc->ti_dev, "failed to send address, status: %x\n", 361 CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 362 return (1); 363 } 364 365 EEPROM_STOP; 366 EEPROM_START; 367 /* 368 * Send read control code to EEPROM. 369 */ 370 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 371 device_printf(sc->ti_dev, 372 "failed to send read command, status: %x\n", 373 CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 374 return (1); 375 } 376 377 /* 378 * Start reading bits from EEPROM. 379 */ 380 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 381 for (i = 0x80; i; i >>= 1) { 382 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 383 DELAY(1); 384 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN) 385 byte |= i; 386 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 387 DELAY(1); 388 } 389 390 EEPROM_STOP; 391 392 /* 393 * No ACK generated for read, so just return byte. 394 */ 395 396 *dest = byte; 397 398 return (0); 399 } 400 401 /* 402 * Read a sequence of bytes from the EEPROM. 403 */ 404 static int 405 ti_read_eeprom(struct ti_softc *sc, caddr_t dest, int off, int cnt) 406 { 407 int err = 0, i; 408 uint8_t byte = 0; 409 410 for (i = 0; i < cnt; i++) { 411 err = ti_eeprom_getbyte(sc, off + i, &byte); 412 if (err) 413 break; 414 *(dest + i) = byte; 415 } 416 417 return (err ? 1 : 0); 418 } 419 420 /* 421 * NIC memory read function. 422 * Can be used to copy data from NIC local memory. 423 */ 424 static void 425 ti_mem_read(struct ti_softc *sc, uint32_t addr, uint32_t len, void *buf) 426 { 427 int segptr, segsize, cnt; 428 char *ptr; 429 430 segptr = addr; 431 cnt = len; 432 ptr = buf; 433 434 while (cnt) { 435 if (cnt < TI_WINLEN) 436 segsize = cnt; 437 else 438 segsize = TI_WINLEN - (segptr % TI_WINLEN); 439 CSR_WRITE_4(sc, TI_WINBASE, rounddown2(segptr, TI_WINLEN)); 440 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle, 441 TI_WINDOW + (segptr & (TI_WINLEN - 1)), (uint32_t *)ptr, 442 segsize / 4); 443 ptr += segsize; 444 segptr += segsize; 445 cnt -= segsize; 446 } 447 } 448 449 450 /* 451 * NIC memory write function. 452 * Can be used to copy data into NIC local memory. 453 */ 454 static void 455 ti_mem_write(struct ti_softc *sc, uint32_t addr, uint32_t len, void *buf) 456 { 457 int segptr, segsize, cnt; 458 char *ptr; 459 460 segptr = addr; 461 cnt = len; 462 ptr = buf; 463 464 while (cnt) { 465 if (cnt < TI_WINLEN) 466 segsize = cnt; 467 else 468 segsize = TI_WINLEN - (segptr % TI_WINLEN); 469 CSR_WRITE_4(sc, TI_WINBASE, rounddown2(segptr, TI_WINLEN)); 470 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 471 TI_WINDOW + (segptr & (TI_WINLEN - 1)), (uint32_t *)ptr, 472 segsize / 4); 473 ptr += segsize; 474 segptr += segsize; 475 cnt -= segsize; 476 } 477 } 478 479 /* 480 * NIC memory read function. 481 * Can be used to clear a section of NIC local memory. 482 */ 483 static void 484 ti_mem_zero(struct ti_softc *sc, uint32_t addr, uint32_t len) 485 { 486 int segptr, segsize, cnt; 487 488 segptr = addr; 489 cnt = len; 490 491 while (cnt) { 492 if (cnt < TI_WINLEN) 493 segsize = cnt; 494 else 495 segsize = TI_WINLEN - (segptr % TI_WINLEN); 496 CSR_WRITE_4(sc, TI_WINBASE, rounddown2(segptr, TI_WINLEN)); 497 bus_space_set_region_4(sc->ti_btag, sc->ti_bhandle, 498 TI_WINDOW + (segptr & (TI_WINLEN - 1)), 0, segsize / 4); 499 segptr += segsize; 500 cnt -= segsize; 501 } 502 } 503 504 static int 505 ti_copy_mem(struct ti_softc *sc, uint32_t tigon_addr, uint32_t len, 506 caddr_t buf, int useraddr, int readdata) 507 { 508 int segptr, segsize, cnt; 509 caddr_t ptr; 510 uint32_t origwin; 511 int resid, segresid; 512 int first_pass; 513 514 TI_LOCK_ASSERT(sc); 515 516 /* 517 * At the moment, we don't handle non-aligned cases, we just bail. 518 * If this proves to be a problem, it will be fixed. 519 */ 520 if (readdata == 0 && (tigon_addr & 0x3) != 0) { 521 device_printf(sc->ti_dev, "%s: tigon address %#x isn't " 522 "word-aligned\n", __func__, tigon_addr); 523 device_printf(sc->ti_dev, "%s: unaligned writes aren't " 524 "yet supported\n", __func__); 525 return (EINVAL); 526 } 527 528 segptr = tigon_addr & ~0x3; 529 segresid = tigon_addr - segptr; 530 531 /* 532 * This is the non-aligned amount left over that we'll need to 533 * copy. 534 */ 535 resid = len & 0x3; 536 537 /* Add in the left over amount at the front of the buffer */ 538 resid += segresid; 539 540 cnt = len & ~0x3; 541 /* 542 * If resid + segresid is >= 4, add multiples of 4 to the count and 543 * decrease the residual by that much. 544 */ 545 cnt += resid & ~0x3; 546 resid -= resid & ~0x3; 547 548 ptr = buf; 549 550 first_pass = 1; 551 552 /* 553 * Save the old window base value. 554 */ 555 origwin = CSR_READ_4(sc, TI_WINBASE); 556 557 while (cnt) { 558 bus_size_t ti_offset; 559 560 if (cnt < TI_WINLEN) 561 segsize = cnt; 562 else 563 segsize = TI_WINLEN - (segptr % TI_WINLEN); 564 CSR_WRITE_4(sc, TI_WINBASE, rounddown2(segptr, TI_WINLEN)); 565 566 ti_offset = TI_WINDOW + (segptr & (TI_WINLEN -1)); 567 568 if (readdata) { 569 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle, 570 ti_offset, (uint32_t *)sc->ti_membuf, segsize >> 2); 571 if (useraddr) { 572 /* 573 * Yeah, this is a little on the kludgy 574 * side, but at least this code is only 575 * used for debugging. 576 */ 577 ti_bcopy_swap(sc->ti_membuf, sc->ti_membuf2, 578 segsize, TI_SWAP_NTOH); 579 580 TI_UNLOCK(sc); 581 if (first_pass) { 582 copyout(&sc->ti_membuf2[segresid], ptr, 583 segsize - segresid); 584 first_pass = 0; 585 } else 586 copyout(sc->ti_membuf2, ptr, segsize); 587 TI_LOCK(sc); 588 } else { 589 if (first_pass) { 590 591 ti_bcopy_swap(sc->ti_membuf, 592 sc->ti_membuf2, segsize, 593 TI_SWAP_NTOH); 594 TI_UNLOCK(sc); 595 bcopy(&sc->ti_membuf2[segresid], ptr, 596 segsize - segresid); 597 TI_LOCK(sc); 598 first_pass = 0; 599 } else 600 ti_bcopy_swap(sc->ti_membuf, ptr, 601 segsize, TI_SWAP_NTOH); 602 } 603 604 } else { 605 if (useraddr) { 606 TI_UNLOCK(sc); 607 copyin(ptr, sc->ti_membuf2, segsize); 608 TI_LOCK(sc); 609 ti_bcopy_swap(sc->ti_membuf2, sc->ti_membuf, 610 segsize, TI_SWAP_HTON); 611 } else 612 ti_bcopy_swap(ptr, sc->ti_membuf, segsize, 613 TI_SWAP_HTON); 614 615 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 616 ti_offset, (uint32_t *)sc->ti_membuf, segsize >> 2); 617 } 618 segptr += segsize; 619 ptr += segsize; 620 cnt -= segsize; 621 } 622 623 /* 624 * Handle leftover, non-word-aligned bytes. 625 */ 626 if (resid != 0) { 627 uint32_t tmpval, tmpval2; 628 bus_size_t ti_offset; 629 630 /* 631 * Set the segment pointer. 632 */ 633 CSR_WRITE_4(sc, TI_WINBASE, rounddown2(segptr, TI_WINLEN)); 634 635 ti_offset = TI_WINDOW + (segptr & (TI_WINLEN - 1)); 636 637 /* 638 * First, grab whatever is in our source/destination. 639 * We'll obviously need this for reads, but also for 640 * writes, since we'll be doing read/modify/write. 641 */ 642 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle, 643 ti_offset, &tmpval, 1); 644 645 /* 646 * Next, translate this from little-endian to big-endian 647 * (at least on i386 boxes). 648 */ 649 tmpval2 = ntohl(tmpval); 650 651 if (readdata) { 652 /* 653 * If we're reading, just copy the leftover number 654 * of bytes from the host byte order buffer to 655 * the user's buffer. 656 */ 657 if (useraddr) { 658 TI_UNLOCK(sc); 659 copyout(&tmpval2, ptr, resid); 660 TI_LOCK(sc); 661 } else 662 bcopy(&tmpval2, ptr, resid); 663 } else { 664 /* 665 * If we're writing, first copy the bytes to be 666 * written into the network byte order buffer, 667 * leaving the rest of the buffer with whatever was 668 * originally in there. Then, swap the bytes 669 * around into host order and write them out. 670 * 671 * XXX KDM the read side of this has been verified 672 * to work, but the write side of it has not been 673 * verified. So user beware. 674 */ 675 if (useraddr) { 676 TI_UNLOCK(sc); 677 copyin(ptr, &tmpval2, resid); 678 TI_LOCK(sc); 679 } else 680 bcopy(ptr, &tmpval2, resid); 681 682 tmpval = htonl(tmpval2); 683 684 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 685 ti_offset, &tmpval, 1); 686 } 687 } 688 689 CSR_WRITE_4(sc, TI_WINBASE, origwin); 690 691 return (0); 692 } 693 694 static int 695 ti_copy_scratch(struct ti_softc *sc, uint32_t tigon_addr, uint32_t len, 696 caddr_t buf, int useraddr, int readdata, int cpu) 697 { 698 uint32_t segptr; 699 int cnt; 700 uint32_t tmpval, tmpval2; 701 caddr_t ptr; 702 703 TI_LOCK_ASSERT(sc); 704 705 /* 706 * At the moment, we don't handle non-aligned cases, we just bail. 707 * If this proves to be a problem, it will be fixed. 708 */ 709 if (tigon_addr & 0x3) { 710 device_printf(sc->ti_dev, "%s: tigon address %#x " 711 "isn't word-aligned\n", __func__, tigon_addr); 712 return (EINVAL); 713 } 714 715 if (len & 0x3) { 716 device_printf(sc->ti_dev, "%s: transfer length %d " 717 "isn't word-aligned\n", __func__, len); 718 return (EINVAL); 719 } 720 721 segptr = tigon_addr; 722 cnt = len; 723 ptr = buf; 724 725 while (cnt) { 726 CSR_WRITE_4(sc, CPU_REG(TI_SRAM_ADDR, cpu), segptr); 727 728 if (readdata) { 729 tmpval2 = CSR_READ_4(sc, CPU_REG(TI_SRAM_DATA, cpu)); 730 731 tmpval = ntohl(tmpval2); 732 733 /* 734 * Note: I've used this debugging interface 735 * extensively with Alteon's 12.3.15 firmware, 736 * compiled with GCC 2.7.2.1 and binutils 2.9.1. 737 * 738 * When you compile the firmware without 739 * optimization, which is necessary sometimes in 740 * order to properly step through it, you sometimes 741 * read out a bogus value of 0xc0017c instead of 742 * whatever was supposed to be in that scratchpad 743 * location. That value is on the stack somewhere, 744 * but I've never been able to figure out what was 745 * causing the problem. 746 * 747 * The address seems to pop up in random places, 748 * often not in the same place on two subsequent 749 * reads. 750 * 751 * In any case, the underlying data doesn't seem 752 * to be affected, just the value read out. 753 * 754 * KDM, 3/7/2000 755 */ 756 757 if (tmpval2 == 0xc0017c) 758 device_printf(sc->ti_dev, "found 0xc0017c at " 759 "%#x (tmpval2)\n", segptr); 760 761 if (tmpval == 0xc0017c) 762 device_printf(sc->ti_dev, "found 0xc0017c at " 763 "%#x (tmpval)\n", segptr); 764 765 if (useraddr) 766 copyout(&tmpval, ptr, 4); 767 else 768 bcopy(&tmpval, ptr, 4); 769 } else { 770 if (useraddr) 771 copyin(ptr, &tmpval2, 4); 772 else 773 bcopy(ptr, &tmpval2, 4); 774 775 tmpval = htonl(tmpval2); 776 777 CSR_WRITE_4(sc, CPU_REG(TI_SRAM_DATA, cpu), tmpval); 778 } 779 780 cnt -= 4; 781 segptr += 4; 782 ptr += 4; 783 } 784 785 return (0); 786 } 787 788 static int 789 ti_bcopy_swap(const void *src, void *dst, size_t len, ti_swap_type swap_type) 790 { 791 const uint8_t *tmpsrc; 792 uint8_t *tmpdst; 793 size_t tmplen; 794 795 if (len & 0x3) { 796 printf("ti_bcopy_swap: length %zd isn't 32-bit aligned\n", len); 797 return (-1); 798 } 799 800 tmpsrc = src; 801 tmpdst = dst; 802 tmplen = len; 803 804 while (tmplen) { 805 if (swap_type == TI_SWAP_NTOH) 806 *(uint32_t *)tmpdst = ntohl(*(const uint32_t *)tmpsrc); 807 else 808 *(uint32_t *)tmpdst = htonl(*(const uint32_t *)tmpsrc); 809 tmpsrc += 4; 810 tmpdst += 4; 811 tmplen -= 4; 812 } 813 814 return (0); 815 } 816 817 /* 818 * Load firmware image into the NIC. Check that the firmware revision 819 * is acceptable and see if we want the firmware for the Tigon 1 or 820 * Tigon 2. 821 */ 822 static void 823 ti_loadfw(struct ti_softc *sc) 824 { 825 826 TI_LOCK_ASSERT(sc); 827 828 switch (sc->ti_hwrev) { 829 case TI_HWREV_TIGON: 830 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR || 831 tigonFwReleaseMinor != TI_FIRMWARE_MINOR || 832 tigonFwReleaseFix != TI_FIRMWARE_FIX) { 833 device_printf(sc->ti_dev, "firmware revision mismatch; " 834 "want %d.%d.%d, got %d.%d.%d\n", 835 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 836 TI_FIRMWARE_FIX, tigonFwReleaseMajor, 837 tigonFwReleaseMinor, tigonFwReleaseFix); 838 return; 839 } 840 ti_mem_write(sc, tigonFwTextAddr, tigonFwTextLen, tigonFwText); 841 ti_mem_write(sc, tigonFwDataAddr, tigonFwDataLen, tigonFwData); 842 ti_mem_write(sc, tigonFwRodataAddr, tigonFwRodataLen, 843 tigonFwRodata); 844 ti_mem_zero(sc, tigonFwBssAddr, tigonFwBssLen); 845 ti_mem_zero(sc, tigonFwSbssAddr, tigonFwSbssLen); 846 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr); 847 break; 848 case TI_HWREV_TIGON_II: 849 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR || 850 tigon2FwReleaseMinor != TI_FIRMWARE_MINOR || 851 tigon2FwReleaseFix != TI_FIRMWARE_FIX) { 852 device_printf(sc->ti_dev, "firmware revision mismatch; " 853 "want %d.%d.%d, got %d.%d.%d\n", 854 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 855 TI_FIRMWARE_FIX, tigon2FwReleaseMajor, 856 tigon2FwReleaseMinor, tigon2FwReleaseFix); 857 return; 858 } 859 ti_mem_write(sc, tigon2FwTextAddr, tigon2FwTextLen, 860 tigon2FwText); 861 ti_mem_write(sc, tigon2FwDataAddr, tigon2FwDataLen, 862 tigon2FwData); 863 ti_mem_write(sc, tigon2FwRodataAddr, tigon2FwRodataLen, 864 tigon2FwRodata); 865 ti_mem_zero(sc, tigon2FwBssAddr, tigon2FwBssLen); 866 ti_mem_zero(sc, tigon2FwSbssAddr, tigon2FwSbssLen); 867 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr); 868 break; 869 default: 870 device_printf(sc->ti_dev, 871 "can't load firmware: unknown hardware rev\n"); 872 break; 873 } 874 } 875 876 /* 877 * Send the NIC a command via the command ring. 878 */ 879 static void 880 ti_cmd(struct ti_softc *sc, struct ti_cmd_desc *cmd) 881 { 882 int index; 883 884 index = sc->ti_cmd_saved_prodidx; 885 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(uint32_t *)(cmd)); 886 TI_INC(index, TI_CMD_RING_CNT); 887 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 888 sc->ti_cmd_saved_prodidx = index; 889 } 890 891 /* 892 * Send the NIC an extended command. The 'len' parameter specifies the 893 * number of command slots to include after the initial command. 894 */ 895 static void 896 ti_cmd_ext(struct ti_softc *sc, struct ti_cmd_desc *cmd, caddr_t arg, int len) 897 { 898 int index; 899 int i; 900 901 index = sc->ti_cmd_saved_prodidx; 902 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(uint32_t *)(cmd)); 903 TI_INC(index, TI_CMD_RING_CNT); 904 for (i = 0; i < len; i++) { 905 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), 906 *(uint32_t *)(&arg[i * 4])); 907 TI_INC(index, TI_CMD_RING_CNT); 908 } 909 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 910 sc->ti_cmd_saved_prodidx = index; 911 } 912 913 /* 914 * Handle events that have triggered interrupts. 915 */ 916 static void 917 ti_handle_events(struct ti_softc *sc) 918 { 919 struct ti_event_desc *e; 920 921 if (sc->ti_rdata.ti_event_ring == NULL) 922 return; 923 924 bus_dmamap_sync(sc->ti_cdata.ti_event_ring_tag, 925 sc->ti_cdata.ti_event_ring_map, BUS_DMASYNC_POSTREAD); 926 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) { 927 e = &sc->ti_rdata.ti_event_ring[sc->ti_ev_saved_considx]; 928 switch (TI_EVENT_EVENT(e)) { 929 case TI_EV_LINKSTAT_CHANGED: 930 sc->ti_linkstat = TI_EVENT_CODE(e); 931 if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) { 932 if_link_state_change(sc->ti_ifp, LINK_STATE_UP); 933 sc->ti_ifp->if_baudrate = IF_Mbps(100); 934 if (bootverbose) 935 device_printf(sc->ti_dev, 936 "10/100 link up\n"); 937 } else if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) { 938 if_link_state_change(sc->ti_ifp, LINK_STATE_UP); 939 sc->ti_ifp->if_baudrate = IF_Gbps(1UL); 940 if (bootverbose) 941 device_printf(sc->ti_dev, 942 "gigabit link up\n"); 943 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) { 944 if_link_state_change(sc->ti_ifp, 945 LINK_STATE_DOWN); 946 sc->ti_ifp->if_baudrate = 0; 947 if (bootverbose) 948 device_printf(sc->ti_dev, 949 "link down\n"); 950 } 951 break; 952 case TI_EV_ERROR: 953 if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_INVAL_CMD) 954 device_printf(sc->ti_dev, "invalid command\n"); 955 else if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_UNIMP_CMD) 956 device_printf(sc->ti_dev, "unknown command\n"); 957 else if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_BADCFG) 958 device_printf(sc->ti_dev, "bad config data\n"); 959 break; 960 case TI_EV_FIRMWARE_UP: 961 ti_init2(sc); 962 break; 963 case TI_EV_STATS_UPDATED: 964 case TI_EV_RESET_JUMBO_RING: 965 case TI_EV_MCAST_UPDATED: 966 /* Who cares. */ 967 break; 968 default: 969 device_printf(sc->ti_dev, "unknown event: %d\n", 970 TI_EVENT_EVENT(e)); 971 break; 972 } 973 /* Advance the consumer index. */ 974 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT); 975 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx); 976 } 977 bus_dmamap_sync(sc->ti_cdata.ti_event_ring_tag, 978 sc->ti_cdata.ti_event_ring_map, BUS_DMASYNC_PREREAD); 979 } 980 981 struct ti_dmamap_arg { 982 bus_addr_t ti_busaddr; 983 }; 984 985 static void 986 ti_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 987 { 988 struct ti_dmamap_arg *ctx; 989 990 if (error) 991 return; 992 993 KASSERT(nseg == 1, ("%s: %d segments returned!", __func__, nseg)); 994 995 ctx = arg; 996 ctx->ti_busaddr = segs->ds_addr; 997 } 998 999 static int 1000 ti_dma_ring_alloc(struct ti_softc *sc, bus_size_t alignment, bus_size_t maxsize, 1001 bus_dma_tag_t *tag, uint8_t **ring, bus_dmamap_t *map, bus_addr_t *paddr, 1002 const char *msg) 1003 { 1004 struct ti_dmamap_arg ctx; 1005 int error; 1006 1007 error = bus_dma_tag_create(sc->ti_cdata.ti_parent_tag, 1008 alignment, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 1009 NULL, maxsize, 1, maxsize, 0, NULL, NULL, tag); 1010 if (error != 0) { 1011 device_printf(sc->ti_dev, 1012 "could not create %s dma tag\n", msg); 1013 return (error); 1014 } 1015 /* Allocate DMA'able memory for ring. */ 1016 error = bus_dmamem_alloc(*tag, (void **)ring, 1017 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, map); 1018 if (error != 0) { 1019 device_printf(sc->ti_dev, 1020 "could not allocate DMA'able memory for %s\n", msg); 1021 return (error); 1022 } 1023 /* Load the address of the ring. */ 1024 ctx.ti_busaddr = 0; 1025 error = bus_dmamap_load(*tag, *map, *ring, maxsize, ti_dma_map_addr, 1026 &ctx, BUS_DMA_NOWAIT); 1027 if (error != 0) { 1028 device_printf(sc->ti_dev, 1029 "could not load DMA'able memory for %s\n", msg); 1030 return (error); 1031 } 1032 *paddr = ctx.ti_busaddr; 1033 return (0); 1034 } 1035 1036 static void 1037 ti_dma_ring_free(struct ti_softc *sc, bus_dma_tag_t *tag, uint8_t **ring, 1038 bus_dmamap_t map, bus_addr_t *paddr) 1039 { 1040 1041 if (*paddr != 0) { 1042 bus_dmamap_unload(*tag, map); 1043 *paddr = 0; 1044 } 1045 if (*ring != NULL) { 1046 bus_dmamem_free(*tag, *ring, map); 1047 *ring = NULL; 1048 } 1049 if (*tag) { 1050 bus_dma_tag_destroy(*tag); 1051 *tag = NULL; 1052 } 1053 } 1054 1055 static int 1056 ti_dma_alloc(struct ti_softc *sc) 1057 { 1058 bus_addr_t lowaddr; 1059 int i, error; 1060 1061 lowaddr = BUS_SPACE_MAXADDR; 1062 if (sc->ti_dac == 0) 1063 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1064 1065 error = bus_dma_tag_create(bus_get_dma_tag(sc->ti_dev), 1, 0, lowaddr, 1066 BUS_SPACE_MAXADDR, NULL, NULL, BUS_SPACE_MAXSIZE_32BIT, 0, 1067 BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL, 1068 &sc->ti_cdata.ti_parent_tag); 1069 if (error != 0) { 1070 device_printf(sc->ti_dev, 1071 "could not allocate parent dma tag\n"); 1072 return (ENOMEM); 1073 } 1074 1075 error = ti_dma_ring_alloc(sc, TI_RING_ALIGN, sizeof(struct ti_gib), 1076 &sc->ti_cdata.ti_gib_tag, (uint8_t **)&sc->ti_rdata.ti_info, 1077 &sc->ti_cdata.ti_gib_map, &sc->ti_rdata.ti_info_paddr, "GIB"); 1078 if (error) 1079 return (error); 1080 1081 /* Producer/consumer status */ 1082 error = ti_dma_ring_alloc(sc, TI_RING_ALIGN, sizeof(struct ti_status), 1083 &sc->ti_cdata.ti_status_tag, (uint8_t **)&sc->ti_rdata.ti_status, 1084 &sc->ti_cdata.ti_status_map, &sc->ti_rdata.ti_status_paddr, 1085 "event ring"); 1086 if (error) 1087 return (error); 1088 1089 /* Event ring */ 1090 error = ti_dma_ring_alloc(sc, TI_RING_ALIGN, TI_EVENT_RING_SZ, 1091 &sc->ti_cdata.ti_event_ring_tag, 1092 (uint8_t **)&sc->ti_rdata.ti_event_ring, 1093 &sc->ti_cdata.ti_event_ring_map, &sc->ti_rdata.ti_event_ring_paddr, 1094 "event ring"); 1095 if (error) 1096 return (error); 1097 1098 /* Command ring lives in shared memory so no need to create DMA area. */ 1099 1100 /* Standard RX ring */ 1101 error = ti_dma_ring_alloc(sc, TI_RING_ALIGN, TI_STD_RX_RING_SZ, 1102 &sc->ti_cdata.ti_rx_std_ring_tag, 1103 (uint8_t **)&sc->ti_rdata.ti_rx_std_ring, 1104 &sc->ti_cdata.ti_rx_std_ring_map, 1105 &sc->ti_rdata.ti_rx_std_ring_paddr, "RX ring"); 1106 if (error) 1107 return (error); 1108 1109 /* Jumbo RX ring */ 1110 error = ti_dma_ring_alloc(sc, TI_JUMBO_RING_ALIGN, TI_JUMBO_RX_RING_SZ, 1111 &sc->ti_cdata.ti_rx_jumbo_ring_tag, 1112 (uint8_t **)&sc->ti_rdata.ti_rx_jumbo_ring, 1113 &sc->ti_cdata.ti_rx_jumbo_ring_map, 1114 &sc->ti_rdata.ti_rx_jumbo_ring_paddr, "jumbo RX ring"); 1115 if (error) 1116 return (error); 1117 1118 /* RX return ring */ 1119 error = ti_dma_ring_alloc(sc, TI_RING_ALIGN, TI_RX_RETURN_RING_SZ, 1120 &sc->ti_cdata.ti_rx_return_ring_tag, 1121 (uint8_t **)&sc->ti_rdata.ti_rx_return_ring, 1122 &sc->ti_cdata.ti_rx_return_ring_map, 1123 &sc->ti_rdata.ti_rx_return_ring_paddr, "RX return ring"); 1124 if (error) 1125 return (error); 1126 1127 /* Create DMA tag for standard RX mbufs. */ 1128 error = bus_dma_tag_create(sc->ti_cdata.ti_parent_tag, 1, 0, 1129 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1, 1130 MCLBYTES, 0, NULL, NULL, &sc->ti_cdata.ti_rx_std_tag); 1131 if (error) { 1132 device_printf(sc->ti_dev, "could not allocate RX dma tag\n"); 1133 return (error); 1134 } 1135 1136 /* Create DMA tag for jumbo RX mbufs. */ 1137 #ifdef TI_SF_BUF_JUMBO 1138 /* 1139 * The VM system will take care of providing aligned pages. Alignment 1140 * is set to 1 here so that busdma resources won't be wasted. 1141 */ 1142 error = bus_dma_tag_create(sc->ti_cdata.ti_parent_tag, 1, 0, 1143 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, PAGE_SIZE * 4, 4, 1144 PAGE_SIZE, 0, NULL, NULL, &sc->ti_cdata.ti_rx_jumbo_tag); 1145 #else 1146 error = bus_dma_tag_create(sc->ti_cdata.ti_parent_tag, 1, 0, 1147 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MJUM9BYTES, 1, 1148 MJUM9BYTES, 0, NULL, NULL, &sc->ti_cdata.ti_rx_jumbo_tag); 1149 #endif 1150 if (error) { 1151 device_printf(sc->ti_dev, 1152 "could not allocate jumbo RX dma tag\n"); 1153 return (error); 1154 } 1155 1156 /* Create DMA tag for TX mbufs. */ 1157 error = bus_dma_tag_create(sc->ti_cdata.ti_parent_tag, 1, 1158 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1159 MCLBYTES * TI_MAXTXSEGS, TI_MAXTXSEGS, MCLBYTES, 0, NULL, NULL, 1160 &sc->ti_cdata.ti_tx_tag); 1161 if (error) { 1162 device_printf(sc->ti_dev, "could not allocate TX dma tag\n"); 1163 return (ENOMEM); 1164 } 1165 1166 /* Create DMA maps for RX buffers. */ 1167 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 1168 error = bus_dmamap_create(sc->ti_cdata.ti_rx_std_tag, 0, 1169 &sc->ti_cdata.ti_rx_std_maps[i]); 1170 if (error) { 1171 device_printf(sc->ti_dev, 1172 "could not create DMA map for RX\n"); 1173 return (error); 1174 } 1175 } 1176 error = bus_dmamap_create(sc->ti_cdata.ti_rx_std_tag, 0, 1177 &sc->ti_cdata.ti_rx_std_sparemap); 1178 if (error) { 1179 device_printf(sc->ti_dev, 1180 "could not create spare DMA map for RX\n"); 1181 return (error); 1182 } 1183 1184 /* Create DMA maps for jumbo RX buffers. */ 1185 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 1186 error = bus_dmamap_create(sc->ti_cdata.ti_rx_jumbo_tag, 0, 1187 &sc->ti_cdata.ti_rx_jumbo_maps[i]); 1188 if (error) { 1189 device_printf(sc->ti_dev, 1190 "could not create DMA map for jumbo RX\n"); 1191 return (error); 1192 } 1193 } 1194 error = bus_dmamap_create(sc->ti_cdata.ti_rx_jumbo_tag, 0, 1195 &sc->ti_cdata.ti_rx_jumbo_sparemap); 1196 if (error) { 1197 device_printf(sc->ti_dev, 1198 "could not create spare DMA map for jumbo RX\n"); 1199 return (error); 1200 } 1201 1202 /* Create DMA maps for TX buffers. */ 1203 for (i = 0; i < TI_TX_RING_CNT; i++) { 1204 error = bus_dmamap_create(sc->ti_cdata.ti_tx_tag, 0, 1205 &sc->ti_cdata.ti_txdesc[i].tx_dmamap); 1206 if (error) { 1207 device_printf(sc->ti_dev, 1208 "could not create DMA map for TX\n"); 1209 return (ENOMEM); 1210 } 1211 } 1212 1213 /* Mini ring and TX ring is not available on Tigon 1. */ 1214 if (sc->ti_hwrev == TI_HWREV_TIGON) 1215 return (0); 1216 1217 /* TX ring */ 1218 error = ti_dma_ring_alloc(sc, TI_RING_ALIGN, TI_TX_RING_SZ, 1219 &sc->ti_cdata.ti_tx_ring_tag, (uint8_t **)&sc->ti_rdata.ti_tx_ring, 1220 &sc->ti_cdata.ti_tx_ring_map, &sc->ti_rdata.ti_tx_ring_paddr, 1221 "TX ring"); 1222 if (error) 1223 return (error); 1224 1225 /* Mini RX ring */ 1226 error = ti_dma_ring_alloc(sc, TI_RING_ALIGN, TI_MINI_RX_RING_SZ, 1227 &sc->ti_cdata.ti_rx_mini_ring_tag, 1228 (uint8_t **)&sc->ti_rdata.ti_rx_mini_ring, 1229 &sc->ti_cdata.ti_rx_mini_ring_map, 1230 &sc->ti_rdata.ti_rx_mini_ring_paddr, "mini RX ring"); 1231 if (error) 1232 return (error); 1233 1234 /* Create DMA tag for mini RX mbufs. */ 1235 error = bus_dma_tag_create(sc->ti_cdata.ti_parent_tag, 1, 0, 1236 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MHLEN, 1, 1237 MHLEN, 0, NULL, NULL, &sc->ti_cdata.ti_rx_mini_tag); 1238 if (error) { 1239 device_printf(sc->ti_dev, 1240 "could not allocate mini RX dma tag\n"); 1241 return (error); 1242 } 1243 1244 /* Create DMA maps for mini RX buffers. */ 1245 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 1246 error = bus_dmamap_create(sc->ti_cdata.ti_rx_mini_tag, 0, 1247 &sc->ti_cdata.ti_rx_mini_maps[i]); 1248 if (error) { 1249 device_printf(sc->ti_dev, 1250 "could not create DMA map for mini RX\n"); 1251 return (error); 1252 } 1253 } 1254 error = bus_dmamap_create(sc->ti_cdata.ti_rx_mini_tag, 0, 1255 &sc->ti_cdata.ti_rx_mini_sparemap); 1256 if (error) { 1257 device_printf(sc->ti_dev, 1258 "could not create spare DMA map for mini RX\n"); 1259 return (error); 1260 } 1261 1262 return (0); 1263 } 1264 1265 static void 1266 ti_dma_free(struct ti_softc *sc) 1267 { 1268 int i; 1269 1270 /* Destroy DMA maps for RX buffers. */ 1271 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 1272 if (sc->ti_cdata.ti_rx_std_maps[i]) { 1273 bus_dmamap_destroy(sc->ti_cdata.ti_rx_std_tag, 1274 sc->ti_cdata.ti_rx_std_maps[i]); 1275 sc->ti_cdata.ti_rx_std_maps[i] = NULL; 1276 } 1277 } 1278 if (sc->ti_cdata.ti_rx_std_sparemap) { 1279 bus_dmamap_destroy(sc->ti_cdata.ti_rx_std_tag, 1280 sc->ti_cdata.ti_rx_std_sparemap); 1281 sc->ti_cdata.ti_rx_std_sparemap = NULL; 1282 } 1283 if (sc->ti_cdata.ti_rx_std_tag) { 1284 bus_dma_tag_destroy(sc->ti_cdata.ti_rx_std_tag); 1285 sc->ti_cdata.ti_rx_std_tag = NULL; 1286 } 1287 1288 /* Destroy DMA maps for jumbo RX buffers. */ 1289 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 1290 if (sc->ti_cdata.ti_rx_jumbo_maps[i]) { 1291 bus_dmamap_destroy(sc->ti_cdata.ti_rx_jumbo_tag, 1292 sc->ti_cdata.ti_rx_jumbo_maps[i]); 1293 sc->ti_cdata.ti_rx_jumbo_maps[i] = NULL; 1294 } 1295 } 1296 if (sc->ti_cdata.ti_rx_jumbo_sparemap) { 1297 bus_dmamap_destroy(sc->ti_cdata.ti_rx_jumbo_tag, 1298 sc->ti_cdata.ti_rx_jumbo_sparemap); 1299 sc->ti_cdata.ti_rx_jumbo_sparemap = NULL; 1300 } 1301 if (sc->ti_cdata.ti_rx_jumbo_tag) { 1302 bus_dma_tag_destroy(sc->ti_cdata.ti_rx_jumbo_tag); 1303 sc->ti_cdata.ti_rx_jumbo_tag = NULL; 1304 } 1305 1306 /* Destroy DMA maps for mini RX buffers. */ 1307 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 1308 if (sc->ti_cdata.ti_rx_mini_maps[i]) { 1309 bus_dmamap_destroy(sc->ti_cdata.ti_rx_mini_tag, 1310 sc->ti_cdata.ti_rx_mini_maps[i]); 1311 sc->ti_cdata.ti_rx_mini_maps[i] = NULL; 1312 } 1313 } 1314 if (sc->ti_cdata.ti_rx_mini_sparemap) { 1315 bus_dmamap_destroy(sc->ti_cdata.ti_rx_mini_tag, 1316 sc->ti_cdata.ti_rx_mini_sparemap); 1317 sc->ti_cdata.ti_rx_mini_sparemap = NULL; 1318 } 1319 if (sc->ti_cdata.ti_rx_mini_tag) { 1320 bus_dma_tag_destroy(sc->ti_cdata.ti_rx_mini_tag); 1321 sc->ti_cdata.ti_rx_mini_tag = NULL; 1322 } 1323 1324 /* Destroy DMA maps for TX buffers. */ 1325 for (i = 0; i < TI_TX_RING_CNT; i++) { 1326 if (sc->ti_cdata.ti_txdesc[i].tx_dmamap) { 1327 bus_dmamap_destroy(sc->ti_cdata.ti_tx_tag, 1328 sc->ti_cdata.ti_txdesc[i].tx_dmamap); 1329 sc->ti_cdata.ti_txdesc[i].tx_dmamap = NULL; 1330 } 1331 } 1332 if (sc->ti_cdata.ti_tx_tag) { 1333 bus_dma_tag_destroy(sc->ti_cdata.ti_tx_tag); 1334 sc->ti_cdata.ti_tx_tag = NULL; 1335 } 1336 1337 /* Destroy standard RX ring. */ 1338 ti_dma_ring_free(sc, &sc->ti_cdata.ti_rx_std_ring_tag, 1339 (void *)&sc->ti_rdata.ti_rx_std_ring, 1340 sc->ti_cdata.ti_rx_std_ring_map, 1341 &sc->ti_rdata.ti_rx_std_ring_paddr); 1342 /* Destroy jumbo RX ring. */ 1343 ti_dma_ring_free(sc, &sc->ti_cdata.ti_rx_jumbo_ring_tag, 1344 (void *)&sc->ti_rdata.ti_rx_jumbo_ring, 1345 sc->ti_cdata.ti_rx_jumbo_ring_map, 1346 &sc->ti_rdata.ti_rx_jumbo_ring_paddr); 1347 /* Destroy mini RX ring. */ 1348 ti_dma_ring_free(sc, &sc->ti_cdata.ti_rx_mini_ring_tag, 1349 (void *)&sc->ti_rdata.ti_rx_mini_ring, 1350 sc->ti_cdata.ti_rx_mini_ring_map, 1351 &sc->ti_rdata.ti_rx_mini_ring_paddr); 1352 /* Destroy RX return ring. */ 1353 ti_dma_ring_free(sc, &sc->ti_cdata.ti_rx_return_ring_tag, 1354 (void *)&sc->ti_rdata.ti_rx_return_ring, 1355 sc->ti_cdata.ti_rx_return_ring_map, 1356 &sc->ti_rdata.ti_rx_return_ring_paddr); 1357 /* Destroy TX ring. */ 1358 ti_dma_ring_free(sc, &sc->ti_cdata.ti_tx_ring_tag, 1359 (void *)&sc->ti_rdata.ti_tx_ring, sc->ti_cdata.ti_tx_ring_map, 1360 &sc->ti_rdata.ti_tx_ring_paddr); 1361 /* Destroy status block. */ 1362 ti_dma_ring_free(sc, &sc->ti_cdata.ti_status_tag, 1363 (void *)&sc->ti_rdata.ti_status, sc->ti_cdata.ti_status_map, 1364 &sc->ti_rdata.ti_status_paddr); 1365 /* Destroy event ring. */ 1366 ti_dma_ring_free(sc, &sc->ti_cdata.ti_event_ring_tag, 1367 (void *)&sc->ti_rdata.ti_event_ring, 1368 sc->ti_cdata.ti_event_ring_map, &sc->ti_rdata.ti_event_ring_paddr); 1369 /* Destroy GIB */ 1370 ti_dma_ring_free(sc, &sc->ti_cdata.ti_gib_tag, 1371 (void *)&sc->ti_rdata.ti_info, sc->ti_cdata.ti_gib_map, 1372 &sc->ti_rdata.ti_info_paddr); 1373 1374 /* Destroy the parent tag. */ 1375 if (sc->ti_cdata.ti_parent_tag) { 1376 bus_dma_tag_destroy(sc->ti_cdata.ti_parent_tag); 1377 sc->ti_cdata.ti_parent_tag = NULL; 1378 } 1379 } 1380 1381 /* 1382 * Intialize a standard receive ring descriptor. 1383 */ 1384 static int 1385 ti_newbuf_std(struct ti_softc *sc, int i) 1386 { 1387 bus_dmamap_t map; 1388 bus_dma_segment_t segs[1]; 1389 struct mbuf *m; 1390 struct ti_rx_desc *r; 1391 int error, nsegs; 1392 1393 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1394 if (m == NULL) 1395 return (ENOBUFS); 1396 m->m_len = m->m_pkthdr.len = MCLBYTES; 1397 m_adj(m, ETHER_ALIGN); 1398 1399 error = bus_dmamap_load_mbuf_sg(sc->ti_cdata.ti_rx_std_tag, 1400 sc->ti_cdata.ti_rx_std_sparemap, m, segs, &nsegs, 0); 1401 if (error != 0) { 1402 m_freem(m); 1403 return (error); 1404 } 1405 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1406 1407 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) { 1408 bus_dmamap_sync(sc->ti_cdata.ti_rx_std_tag, 1409 sc->ti_cdata.ti_rx_std_maps[i], BUS_DMASYNC_POSTREAD); 1410 bus_dmamap_unload(sc->ti_cdata.ti_rx_std_tag, 1411 sc->ti_cdata.ti_rx_std_maps[i]); 1412 } 1413 1414 map = sc->ti_cdata.ti_rx_std_maps[i]; 1415 sc->ti_cdata.ti_rx_std_maps[i] = sc->ti_cdata.ti_rx_std_sparemap; 1416 sc->ti_cdata.ti_rx_std_sparemap = map; 1417 sc->ti_cdata.ti_rx_std_chain[i] = m; 1418 1419 r = &sc->ti_rdata.ti_rx_std_ring[i]; 1420 ti_hostaddr64(&r->ti_addr, segs[0].ds_addr); 1421 r->ti_len = segs[0].ds_len; 1422 r->ti_type = TI_BDTYPE_RECV_BD; 1423 r->ti_flags = 0; 1424 r->ti_vlan_tag = 0; 1425 r->ti_tcp_udp_cksum = 0; 1426 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM) 1427 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 1428 r->ti_idx = i; 1429 1430 bus_dmamap_sync(sc->ti_cdata.ti_rx_std_tag, 1431 sc->ti_cdata.ti_rx_std_maps[i], BUS_DMASYNC_PREREAD); 1432 return (0); 1433 } 1434 1435 /* 1436 * Intialize a mini receive ring descriptor. This only applies to 1437 * the Tigon 2. 1438 */ 1439 static int 1440 ti_newbuf_mini(struct ti_softc *sc, int i) 1441 { 1442 bus_dmamap_t map; 1443 bus_dma_segment_t segs[1]; 1444 struct mbuf *m; 1445 struct ti_rx_desc *r; 1446 int error, nsegs; 1447 1448 MGETHDR(m, M_NOWAIT, MT_DATA); 1449 if (m == NULL) 1450 return (ENOBUFS); 1451 m->m_len = m->m_pkthdr.len = MHLEN; 1452 m_adj(m, ETHER_ALIGN); 1453 1454 error = bus_dmamap_load_mbuf_sg(sc->ti_cdata.ti_rx_mini_tag, 1455 sc->ti_cdata.ti_rx_mini_sparemap, m, segs, &nsegs, 0); 1456 if (error != 0) { 1457 m_freem(m); 1458 return (error); 1459 } 1460 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1461 1462 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) { 1463 bus_dmamap_sync(sc->ti_cdata.ti_rx_mini_tag, 1464 sc->ti_cdata.ti_rx_mini_maps[i], BUS_DMASYNC_POSTREAD); 1465 bus_dmamap_unload(sc->ti_cdata.ti_rx_mini_tag, 1466 sc->ti_cdata.ti_rx_mini_maps[i]); 1467 } 1468 1469 map = sc->ti_cdata.ti_rx_mini_maps[i]; 1470 sc->ti_cdata.ti_rx_mini_maps[i] = sc->ti_cdata.ti_rx_mini_sparemap; 1471 sc->ti_cdata.ti_rx_mini_sparemap = map; 1472 sc->ti_cdata.ti_rx_mini_chain[i] = m; 1473 1474 r = &sc->ti_rdata.ti_rx_mini_ring[i]; 1475 ti_hostaddr64(&r->ti_addr, segs[0].ds_addr); 1476 r->ti_len = segs[0].ds_len; 1477 r->ti_type = TI_BDTYPE_RECV_BD; 1478 r->ti_flags = TI_BDFLAG_MINI_RING; 1479 r->ti_vlan_tag = 0; 1480 r->ti_tcp_udp_cksum = 0; 1481 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM) 1482 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 1483 r->ti_idx = i; 1484 1485 bus_dmamap_sync(sc->ti_cdata.ti_rx_mini_tag, 1486 sc->ti_cdata.ti_rx_mini_maps[i], BUS_DMASYNC_PREREAD); 1487 return (0); 1488 } 1489 1490 #ifndef TI_SF_BUF_JUMBO 1491 1492 /* 1493 * Initialize a jumbo receive ring descriptor. This allocates 1494 * a jumbo buffer from the pool managed internally by the driver. 1495 */ 1496 static int 1497 ti_newbuf_jumbo(struct ti_softc *sc, int i, struct mbuf *dummy) 1498 { 1499 bus_dmamap_t map; 1500 bus_dma_segment_t segs[1]; 1501 struct mbuf *m; 1502 struct ti_rx_desc *r; 1503 int error, nsegs; 1504 1505 (void)dummy; 1506 1507 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES); 1508 if (m == NULL) 1509 return (ENOBUFS); 1510 m->m_len = m->m_pkthdr.len = MJUM9BYTES; 1511 m_adj(m, ETHER_ALIGN); 1512 1513 error = bus_dmamap_load_mbuf_sg(sc->ti_cdata.ti_rx_jumbo_tag, 1514 sc->ti_cdata.ti_rx_jumbo_sparemap, m, segs, &nsegs, 0); 1515 if (error != 0) { 1516 m_freem(m); 1517 return (error); 1518 } 1519 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1520 1521 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) { 1522 bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_tag, 1523 sc->ti_cdata.ti_rx_jumbo_maps[i], BUS_DMASYNC_POSTREAD); 1524 bus_dmamap_unload(sc->ti_cdata.ti_rx_jumbo_tag, 1525 sc->ti_cdata.ti_rx_jumbo_maps[i]); 1526 } 1527 1528 map = sc->ti_cdata.ti_rx_jumbo_maps[i]; 1529 sc->ti_cdata.ti_rx_jumbo_maps[i] = sc->ti_cdata.ti_rx_jumbo_sparemap; 1530 sc->ti_cdata.ti_rx_jumbo_sparemap = map; 1531 sc->ti_cdata.ti_rx_jumbo_chain[i] = m; 1532 1533 r = &sc->ti_rdata.ti_rx_jumbo_ring[i]; 1534 ti_hostaddr64(&r->ti_addr, segs[0].ds_addr); 1535 r->ti_len = segs[0].ds_len; 1536 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 1537 r->ti_flags = TI_BDFLAG_JUMBO_RING; 1538 r->ti_vlan_tag = 0; 1539 r->ti_tcp_udp_cksum = 0; 1540 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM) 1541 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 1542 r->ti_idx = i; 1543 1544 bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_tag, 1545 sc->ti_cdata.ti_rx_jumbo_maps[i], BUS_DMASYNC_PREREAD); 1546 return (0); 1547 } 1548 1549 #else 1550 1551 #if (PAGE_SIZE == 4096) 1552 #define NPAYLOAD 2 1553 #else 1554 #define NPAYLOAD 1 1555 #endif 1556 1557 #define TCP_HDR_LEN (52 + sizeof(struct ether_header)) 1558 #define UDP_HDR_LEN (28 + sizeof(struct ether_header)) 1559 #define NFS_HDR_LEN (UDP_HDR_LEN) 1560 static int HDR_LEN = TCP_HDR_LEN; 1561 1562 /* 1563 * Initialize a jumbo receive ring descriptor. This allocates 1564 * a jumbo buffer from the pool managed internally by the driver. 1565 */ 1566 static int 1567 ti_newbuf_jumbo(struct ti_softc *sc, int idx, struct mbuf *m_old) 1568 { 1569 bus_dmamap_t map; 1570 struct mbuf *cur, *m_new = NULL; 1571 struct mbuf *m[3] = {NULL, NULL, NULL}; 1572 struct ti_rx_desc_ext *r; 1573 vm_page_t frame; 1574 /* 1 extra buf to make nobufs easy*/ 1575 struct sf_buf *sf[3] = {NULL, NULL, NULL}; 1576 int i; 1577 bus_dma_segment_t segs[4]; 1578 int nsegs; 1579 1580 if (m_old != NULL) { 1581 m_new = m_old; 1582 cur = m_old->m_next; 1583 for (i = 0; i <= NPAYLOAD; i++){ 1584 m[i] = cur; 1585 cur = cur->m_next; 1586 } 1587 } else { 1588 /* Allocate the mbufs. */ 1589 MGETHDR(m_new, M_NOWAIT, MT_DATA); 1590 if (m_new == NULL) { 1591 device_printf(sc->ti_dev, "mbuf allocation failed " 1592 "-- packet dropped!\n"); 1593 goto nobufs; 1594 } 1595 MGET(m[NPAYLOAD], M_NOWAIT, MT_DATA); 1596 if (m[NPAYLOAD] == NULL) { 1597 device_printf(sc->ti_dev, "cluster mbuf allocation " 1598 "failed -- packet dropped!\n"); 1599 goto nobufs; 1600 } 1601 if (!(MCLGET(m[NPAYLOAD], M_NOWAIT))) { 1602 device_printf(sc->ti_dev, "mbuf allocation failed " 1603 "-- packet dropped!\n"); 1604 goto nobufs; 1605 } 1606 m[NPAYLOAD]->m_len = MCLBYTES; 1607 1608 for (i = 0; i < NPAYLOAD; i++){ 1609 MGET(m[i], M_NOWAIT, MT_DATA); 1610 if (m[i] == NULL) { 1611 device_printf(sc->ti_dev, "mbuf allocation " 1612 "failed -- packet dropped!\n"); 1613 goto nobufs; 1614 } 1615 frame = vm_page_alloc(NULL, 0, 1616 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | 1617 VM_ALLOC_WIRED); 1618 if (frame == NULL) { 1619 device_printf(sc->ti_dev, "buffer allocation " 1620 "failed -- packet dropped!\n"); 1621 printf(" index %d page %d\n", idx, i); 1622 goto nobufs; 1623 } 1624 sf[i] = sf_buf_alloc(frame, SFB_NOWAIT); 1625 if (sf[i] == NULL) { 1626 vm_page_unwire_noq(frame); 1627 vm_page_free(frame); 1628 device_printf(sc->ti_dev, "buffer allocation " 1629 "failed -- packet dropped!\n"); 1630 printf(" index %d page %d\n", idx, i); 1631 goto nobufs; 1632 } 1633 } 1634 for (i = 0; i < NPAYLOAD; i++){ 1635 /* Attach the buffer to the mbuf. */ 1636 m[i]->m_data = (void *)sf_buf_kva(sf[i]); 1637 m[i]->m_len = PAGE_SIZE; 1638 MEXTADD(m[i], sf_buf_kva(sf[i]), PAGE_SIZE, 1639 sf_mext_free, (void*)sf_buf_kva(sf[i]), sf[i], 1640 0, EXT_DISPOSABLE); 1641 m[i]->m_next = m[i+1]; 1642 } 1643 /* link the buffers to the header */ 1644 m_new->m_next = m[0]; 1645 m_new->m_data += ETHER_ALIGN; 1646 if (sc->ti_hdrsplit) 1647 m_new->m_len = MHLEN - ETHER_ALIGN; 1648 else 1649 m_new->m_len = HDR_LEN; 1650 m_new->m_pkthdr.len = NPAYLOAD * PAGE_SIZE + m_new->m_len; 1651 } 1652 1653 /* Set up the descriptor. */ 1654 r = &sc->ti_rdata.ti_rx_jumbo_ring[idx]; 1655 sc->ti_cdata.ti_rx_jumbo_chain[idx] = m_new; 1656 map = sc->ti_cdata.ti_rx_jumbo_maps[i]; 1657 if (bus_dmamap_load_mbuf_sg(sc->ti_cdata.ti_rx_jumbo_tag, map, m_new, 1658 segs, &nsegs, 0)) 1659 return (ENOBUFS); 1660 if ((nsegs < 1) || (nsegs > 4)) 1661 return (ENOBUFS); 1662 ti_hostaddr64(&r->ti_addr0, segs[0].ds_addr); 1663 r->ti_len0 = m_new->m_len; 1664 1665 ti_hostaddr64(&r->ti_addr1, segs[1].ds_addr); 1666 r->ti_len1 = PAGE_SIZE; 1667 1668 ti_hostaddr64(&r->ti_addr2, segs[2].ds_addr); 1669 r->ti_len2 = m[1]->m_ext.ext_size; /* could be PAGE_SIZE or MCLBYTES */ 1670 1671 if (PAGE_SIZE == 4096) { 1672 ti_hostaddr64(&r->ti_addr3, segs[3].ds_addr); 1673 r->ti_len3 = MCLBYTES; 1674 } else { 1675 r->ti_len3 = 0; 1676 } 1677 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 1678 1679 r->ti_flags = TI_BDFLAG_JUMBO_RING|TI_RCB_FLAG_USE_EXT_RX_BD; 1680 1681 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM) 1682 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM|TI_BDFLAG_IP_CKSUM; 1683 1684 r->ti_idx = idx; 1685 1686 bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_tag, map, BUS_DMASYNC_PREREAD); 1687 return (0); 1688 1689 nobufs: 1690 1691 /* 1692 * Warning! : 1693 * This can only be called before the mbufs are strung together. 1694 * If the mbufs are strung together, m_freem() will free the chain, 1695 * so that the later mbufs will be freed multiple times. 1696 */ 1697 if (m_new) 1698 m_freem(m_new); 1699 1700 for (i = 0; i < 3; i++) { 1701 if (m[i]) 1702 m_freem(m[i]); 1703 if (sf[i]) 1704 sf_mext_free((void *)sf_buf_kva(sf[i]), sf[i]); 1705 } 1706 return (ENOBUFS); 1707 } 1708 #endif 1709 1710 /* 1711 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 1712 * that's 1MB or memory, which is a lot. For now, we fill only the first 1713 * 256 ring entries and hope that our CPU is fast enough to keep up with 1714 * the NIC. 1715 */ 1716 static int 1717 ti_init_rx_ring_std(struct ti_softc *sc) 1718 { 1719 int i; 1720 struct ti_cmd_desc cmd; 1721 1722 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 1723 if (ti_newbuf_std(sc, i) != 0) 1724 return (ENOBUFS); 1725 } 1726 1727 sc->ti_std = TI_STD_RX_RING_CNT - 1; 1728 TI_UPDATE_STDPROD(sc, TI_STD_RX_RING_CNT - 1); 1729 1730 return (0); 1731 } 1732 1733 static void 1734 ti_free_rx_ring_std(struct ti_softc *sc) 1735 { 1736 bus_dmamap_t map; 1737 int i; 1738 1739 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 1740 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) { 1741 map = sc->ti_cdata.ti_rx_std_maps[i]; 1742 bus_dmamap_sync(sc->ti_cdata.ti_rx_std_tag, map, 1743 BUS_DMASYNC_POSTREAD); 1744 bus_dmamap_unload(sc->ti_cdata.ti_rx_std_tag, map); 1745 m_freem(sc->ti_cdata.ti_rx_std_chain[i]); 1746 sc->ti_cdata.ti_rx_std_chain[i] = NULL; 1747 } 1748 } 1749 bzero(sc->ti_rdata.ti_rx_std_ring, TI_STD_RX_RING_SZ); 1750 bus_dmamap_sync(sc->ti_cdata.ti_rx_std_ring_tag, 1751 sc->ti_cdata.ti_rx_std_ring_map, BUS_DMASYNC_PREWRITE); 1752 } 1753 1754 static int 1755 ti_init_rx_ring_jumbo(struct ti_softc *sc) 1756 { 1757 struct ti_cmd_desc cmd; 1758 int i; 1759 1760 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 1761 if (ti_newbuf_jumbo(sc, i, NULL) != 0) 1762 return (ENOBUFS); 1763 } 1764 1765 sc->ti_jumbo = TI_JUMBO_RX_RING_CNT - 1; 1766 TI_UPDATE_JUMBOPROD(sc, TI_JUMBO_RX_RING_CNT - 1); 1767 1768 return (0); 1769 } 1770 1771 static void 1772 ti_free_rx_ring_jumbo(struct ti_softc *sc) 1773 { 1774 bus_dmamap_t map; 1775 int i; 1776 1777 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 1778 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) { 1779 map = sc->ti_cdata.ti_rx_jumbo_maps[i]; 1780 bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_tag, map, 1781 BUS_DMASYNC_POSTREAD); 1782 bus_dmamap_unload(sc->ti_cdata.ti_rx_jumbo_tag, map); 1783 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]); 1784 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL; 1785 } 1786 } 1787 bzero(sc->ti_rdata.ti_rx_jumbo_ring, TI_JUMBO_RX_RING_SZ); 1788 bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_ring_tag, 1789 sc->ti_cdata.ti_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE); 1790 } 1791 1792 static int 1793 ti_init_rx_ring_mini(struct ti_softc *sc) 1794 { 1795 int i; 1796 1797 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 1798 if (ti_newbuf_mini(sc, i) != 0) 1799 return (ENOBUFS); 1800 } 1801 1802 sc->ti_mini = TI_MINI_RX_RING_CNT - 1; 1803 TI_UPDATE_MINIPROD(sc, TI_MINI_RX_RING_CNT - 1); 1804 1805 return (0); 1806 } 1807 1808 static void 1809 ti_free_rx_ring_mini(struct ti_softc *sc) 1810 { 1811 bus_dmamap_t map; 1812 int i; 1813 1814 if (sc->ti_rdata.ti_rx_mini_ring == NULL) 1815 return; 1816 1817 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 1818 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) { 1819 map = sc->ti_cdata.ti_rx_mini_maps[i]; 1820 bus_dmamap_sync(sc->ti_cdata.ti_rx_mini_tag, map, 1821 BUS_DMASYNC_POSTREAD); 1822 bus_dmamap_unload(sc->ti_cdata.ti_rx_mini_tag, map); 1823 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]); 1824 sc->ti_cdata.ti_rx_mini_chain[i] = NULL; 1825 } 1826 } 1827 bzero(sc->ti_rdata.ti_rx_mini_ring, TI_MINI_RX_RING_SZ); 1828 bus_dmamap_sync(sc->ti_cdata.ti_rx_mini_ring_tag, 1829 sc->ti_cdata.ti_rx_mini_ring_map, BUS_DMASYNC_PREWRITE); 1830 } 1831 1832 static void 1833 ti_free_tx_ring(struct ti_softc *sc) 1834 { 1835 struct ti_txdesc *txd; 1836 int i; 1837 1838 if (sc->ti_rdata.ti_tx_ring == NULL) 1839 return; 1840 1841 for (i = 0; i < TI_TX_RING_CNT; i++) { 1842 txd = &sc->ti_cdata.ti_txdesc[i]; 1843 if (txd->tx_m != NULL) { 1844 bus_dmamap_sync(sc->ti_cdata.ti_tx_tag, txd->tx_dmamap, 1845 BUS_DMASYNC_POSTWRITE); 1846 bus_dmamap_unload(sc->ti_cdata.ti_tx_tag, 1847 txd->tx_dmamap); 1848 m_freem(txd->tx_m); 1849 txd->tx_m = NULL; 1850 } 1851 } 1852 bzero(sc->ti_rdata.ti_tx_ring, TI_TX_RING_SZ); 1853 bus_dmamap_sync(sc->ti_cdata.ti_tx_ring_tag, 1854 sc->ti_cdata.ti_tx_ring_map, BUS_DMASYNC_PREWRITE); 1855 } 1856 1857 static int 1858 ti_init_tx_ring(struct ti_softc *sc) 1859 { 1860 struct ti_txdesc *txd; 1861 int i; 1862 1863 STAILQ_INIT(&sc->ti_cdata.ti_txfreeq); 1864 STAILQ_INIT(&sc->ti_cdata.ti_txbusyq); 1865 for (i = 0; i < TI_TX_RING_CNT; i++) { 1866 txd = &sc->ti_cdata.ti_txdesc[i]; 1867 STAILQ_INSERT_TAIL(&sc->ti_cdata.ti_txfreeq, txd, tx_q); 1868 } 1869 sc->ti_txcnt = 0; 1870 sc->ti_tx_saved_considx = 0; 1871 sc->ti_tx_saved_prodidx = 0; 1872 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0); 1873 return (0); 1874 } 1875 1876 /* 1877 * The Tigon 2 firmware has a new way to add/delete multicast addresses, 1878 * but we have to support the old way too so that Tigon 1 cards will 1879 * work. 1880 */ 1881 static void 1882 ti_add_mcast(struct ti_softc *sc, struct ether_addr *addr) 1883 { 1884 struct ti_cmd_desc cmd; 1885 uint16_t *m; 1886 uint32_t ext[2] = {0, 0}; 1887 1888 m = (uint16_t *)&addr->octet[0]; 1889 1890 switch (sc->ti_hwrev) { 1891 case TI_HWREV_TIGON: 1892 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1893 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1894 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0); 1895 break; 1896 case TI_HWREV_TIGON_II: 1897 ext[0] = htons(m[0]); 1898 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1899 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2); 1900 break; 1901 default: 1902 device_printf(sc->ti_dev, "unknown hwrev\n"); 1903 break; 1904 } 1905 } 1906 1907 static void 1908 ti_del_mcast(struct ti_softc *sc, struct ether_addr *addr) 1909 { 1910 struct ti_cmd_desc cmd; 1911 uint16_t *m; 1912 uint32_t ext[2] = {0, 0}; 1913 1914 m = (uint16_t *)&addr->octet[0]; 1915 1916 switch (sc->ti_hwrev) { 1917 case TI_HWREV_TIGON: 1918 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1919 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1920 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0); 1921 break; 1922 case TI_HWREV_TIGON_II: 1923 ext[0] = htons(m[0]); 1924 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1925 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2); 1926 break; 1927 default: 1928 device_printf(sc->ti_dev, "unknown hwrev\n"); 1929 break; 1930 } 1931 } 1932 1933 /* 1934 * Configure the Tigon's multicast address filter. 1935 * 1936 * The actual multicast table management is a bit of a pain, thanks to 1937 * slight brain damage on the part of both Alteon and us. With our 1938 * multicast code, we are only alerted when the multicast address table 1939 * changes and at that point we only have the current list of addresses: 1940 * we only know the current state, not the previous state, so we don't 1941 * actually know what addresses were removed or added. The firmware has 1942 * state, but we can't get our grubby mits on it, and there is no 'delete 1943 * all multicast addresses' command. Hence, we have to maintain our own 1944 * state so we know what addresses have been programmed into the NIC at 1945 * any given time. 1946 */ 1947 static void 1948 ti_setmulti(struct ti_softc *sc) 1949 { 1950 struct ifnet *ifp; 1951 struct ifmultiaddr *ifma; 1952 struct ti_cmd_desc cmd; 1953 struct ti_mc_entry *mc; 1954 uint32_t intrs; 1955 1956 TI_LOCK_ASSERT(sc); 1957 1958 ifp = sc->ti_ifp; 1959 1960 if (ifp->if_flags & IFF_ALLMULTI) { 1961 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0); 1962 return; 1963 } else { 1964 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0); 1965 } 1966 1967 /* Disable interrupts. */ 1968 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR); 1969 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1970 1971 /* First, zot all the existing filters. */ 1972 while (SLIST_FIRST(&sc->ti_mc_listhead) != NULL) { 1973 mc = SLIST_FIRST(&sc->ti_mc_listhead); 1974 ti_del_mcast(sc, &mc->mc_addr); 1975 SLIST_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries); 1976 free(mc, M_DEVBUF); 1977 } 1978 1979 /* Now program new ones. */ 1980 if_maddr_rlock(ifp); 1981 CK_STAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1982 if (ifma->ifma_addr->sa_family != AF_LINK) 1983 continue; 1984 mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, M_NOWAIT); 1985 if (mc == NULL) { 1986 device_printf(sc->ti_dev, 1987 "no memory for mcast filter entry\n"); 1988 continue; 1989 } 1990 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1991 (char *)&mc->mc_addr, ETHER_ADDR_LEN); 1992 SLIST_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries); 1993 ti_add_mcast(sc, &mc->mc_addr); 1994 } 1995 if_maddr_runlock(ifp); 1996 1997 /* Re-enable interrupts. */ 1998 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); 1999 } 2000 2001 /* 2002 * Check to see if the BIOS has configured us for a 64 bit slot when 2003 * we aren't actually in one. If we detect this condition, we can work 2004 * around it on the Tigon 2 by setting a bit in the PCI state register, 2005 * but for the Tigon 1 we must give up and abort the interface attach. 2006 */ 2007 static int 2008 ti_64bitslot_war(struct ti_softc *sc) 2009 { 2010 2011 if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) { 2012 CSR_WRITE_4(sc, 0x600, 0); 2013 CSR_WRITE_4(sc, 0x604, 0); 2014 CSR_WRITE_4(sc, 0x600, 0x5555AAAA); 2015 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) { 2016 if (sc->ti_hwrev == TI_HWREV_TIGON) 2017 return (EINVAL); 2018 else { 2019 TI_SETBIT(sc, TI_PCI_STATE, 2020 TI_PCISTATE_32BIT_BUS); 2021 return (0); 2022 } 2023 } 2024 } 2025 2026 return (0); 2027 } 2028 2029 /* 2030 * Do endian, PCI and DMA initialization. Also check the on-board ROM 2031 * self-test results. 2032 */ 2033 static int 2034 ti_chipinit(struct ti_softc *sc) 2035 { 2036 uint32_t cacheline; 2037 uint32_t pci_writemax = 0; 2038 uint32_t hdrsplit; 2039 2040 /* Initialize link to down state. */ 2041 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN; 2042 2043 /* Set endianness before we access any non-PCI registers. */ 2044 #if 0 && BYTE_ORDER == BIG_ENDIAN 2045 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 2046 TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24)); 2047 #else 2048 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 2049 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24)); 2050 #endif 2051 2052 /* Check the ROM failed bit to see if self-tests passed. */ 2053 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) { 2054 device_printf(sc->ti_dev, "board self-diagnostics failed!\n"); 2055 return (ENODEV); 2056 } 2057 2058 /* Halt the CPU. */ 2059 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT); 2060 2061 /* Figure out the hardware revision. */ 2062 switch (CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) { 2063 case TI_REV_TIGON_I: 2064 sc->ti_hwrev = TI_HWREV_TIGON; 2065 break; 2066 case TI_REV_TIGON_II: 2067 sc->ti_hwrev = TI_HWREV_TIGON_II; 2068 break; 2069 default: 2070 device_printf(sc->ti_dev, "unsupported chip revision\n"); 2071 return (ENODEV); 2072 } 2073 2074 /* Do special setup for Tigon 2. */ 2075 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 2076 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT); 2077 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_512K); 2078 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS); 2079 } 2080 2081 /* 2082 * We don't have firmware source for the Tigon 1, so Tigon 1 boards 2083 * can't do header splitting. 2084 */ 2085 #ifdef TI_JUMBO_HDRSPLIT 2086 if (sc->ti_hwrev != TI_HWREV_TIGON) 2087 sc->ti_hdrsplit = 1; 2088 else 2089 device_printf(sc->ti_dev, 2090 "can't do header splitting on a Tigon I board\n"); 2091 #endif /* TI_JUMBO_HDRSPLIT */ 2092 2093 /* Set up the PCI state register. */ 2094 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD); 2095 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 2096 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT); 2097 } 2098 2099 /* Clear the read/write max DMA parameters. */ 2100 TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA| 2101 TI_PCISTATE_READ_MAXDMA)); 2102 2103 /* Get cache line size. */ 2104 cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF; 2105 2106 /* 2107 * If the system has set enabled the PCI memory write 2108 * and invalidate command in the command register, set 2109 * the write max parameter accordingly. This is necessary 2110 * to use MWI with the Tigon 2. 2111 */ 2112 if (CSR_READ_4(sc, TI_PCI_CMDSTAT) & PCIM_CMD_MWIEN) { 2113 switch (cacheline) { 2114 case 1: 2115 case 4: 2116 case 8: 2117 case 16: 2118 case 32: 2119 case 64: 2120 break; 2121 default: 2122 /* Disable PCI memory write and invalidate. */ 2123 if (bootverbose) 2124 device_printf(sc->ti_dev, "cache line size %d" 2125 " not supported; disabling PCI MWI\n", 2126 cacheline); 2127 CSR_WRITE_4(sc, TI_PCI_CMDSTAT, CSR_READ_4(sc, 2128 TI_PCI_CMDSTAT) & ~PCIM_CMD_MWIEN); 2129 break; 2130 } 2131 } 2132 2133 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax); 2134 2135 /* This sets the min dma param all the way up (0xff). */ 2136 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA); 2137 2138 if (sc->ti_hdrsplit) 2139 hdrsplit = TI_OPMODE_JUMBO_HDRSPLIT; 2140 else 2141 hdrsplit = 0; 2142 2143 /* Configure DMA variables. */ 2144 #if BYTE_ORDER == BIG_ENDIAN 2145 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD | 2146 TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD | 2147 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB | 2148 TI_OPMODE_DONT_FRAG_JUMBO | hdrsplit); 2149 #else /* BYTE_ORDER */ 2150 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA| 2151 TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO| 2152 TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB | hdrsplit); 2153 #endif /* BYTE_ORDER */ 2154 2155 /* 2156 * Only allow 1 DMA channel to be active at a time. 2157 * I don't think this is a good idea, but without it 2158 * the firmware racks up lots of nicDmaReadRingFull 2159 * errors. This is not compatible with hardware checksums. 2160 */ 2161 if ((sc->ti_ifp->if_capenable & (IFCAP_TXCSUM | IFCAP_RXCSUM)) == 0) 2162 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE); 2163 2164 /* Recommended settings from Tigon manual. */ 2165 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W); 2166 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W); 2167 2168 if (ti_64bitslot_war(sc)) { 2169 device_printf(sc->ti_dev, "bios thinks we're in a 64 bit slot, " 2170 "but we aren't"); 2171 return (EINVAL); 2172 } 2173 2174 return (0); 2175 } 2176 2177 /* 2178 * Initialize the general information block and firmware, and 2179 * start the CPU(s) running. 2180 */ 2181 static int 2182 ti_gibinit(struct ti_softc *sc) 2183 { 2184 struct ifnet *ifp; 2185 struct ti_rcb *rcb; 2186 int i; 2187 2188 TI_LOCK_ASSERT(sc); 2189 2190 ifp = sc->ti_ifp; 2191 2192 /* Disable interrupts for now. */ 2193 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2194 2195 /* Tell the chip where to find the general information block. */ 2196 CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 2197 (uint64_t)sc->ti_rdata.ti_info_paddr >> 32); 2198 CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, 2199 sc->ti_rdata.ti_info_paddr & 0xFFFFFFFF); 2200 2201 /* Load the firmware into SRAM. */ 2202 ti_loadfw(sc); 2203 2204 /* Set up the contents of the general info and ring control blocks. */ 2205 2206 /* Set up the event ring and producer pointer. */ 2207 bzero(sc->ti_rdata.ti_event_ring, TI_EVENT_RING_SZ); 2208 rcb = &sc->ti_rdata.ti_info->ti_ev_rcb; 2209 ti_hostaddr64(&rcb->ti_hostaddr, sc->ti_rdata.ti_event_ring_paddr); 2210 rcb->ti_flags = 0; 2211 ti_hostaddr64(&sc->ti_rdata.ti_info->ti_ev_prodidx_ptr, 2212 sc->ti_rdata.ti_status_paddr + 2213 offsetof(struct ti_status, ti_ev_prodidx_r)); 2214 sc->ti_ev_prodidx.ti_idx = 0; 2215 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0); 2216 sc->ti_ev_saved_considx = 0; 2217 2218 /* Set up the command ring and producer mailbox. */ 2219 rcb = &sc->ti_rdata.ti_info->ti_cmd_rcb; 2220 ti_hostaddr64(&rcb->ti_hostaddr, TI_GCR_NIC_ADDR(TI_GCR_CMDRING)); 2221 rcb->ti_flags = 0; 2222 rcb->ti_max_len = 0; 2223 for (i = 0; i < TI_CMD_RING_CNT; i++) { 2224 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0); 2225 } 2226 CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0); 2227 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0); 2228 sc->ti_cmd_saved_prodidx = 0; 2229 2230 /* 2231 * Assign the address of the stats refresh buffer. 2232 * We re-use the current stats buffer for this to 2233 * conserve memory. 2234 */ 2235 bzero(&sc->ti_rdata.ti_info->ti_stats, sizeof(struct ti_stats)); 2236 ti_hostaddr64(&sc->ti_rdata.ti_info->ti_refresh_stats_ptr, 2237 sc->ti_rdata.ti_info_paddr + offsetof(struct ti_gib, ti_stats)); 2238 2239 /* Set up the standard receive ring. */ 2240 rcb = &sc->ti_rdata.ti_info->ti_std_rx_rcb; 2241 ti_hostaddr64(&rcb->ti_hostaddr, sc->ti_rdata.ti_rx_std_ring_paddr); 2242 rcb->ti_max_len = TI_FRAMELEN; 2243 rcb->ti_flags = 0; 2244 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM) 2245 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 2246 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 2247 if (sc->ti_ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 2248 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 2249 2250 /* Set up the jumbo receive ring. */ 2251 rcb = &sc->ti_rdata.ti_info->ti_jumbo_rx_rcb; 2252 ti_hostaddr64(&rcb->ti_hostaddr, sc->ti_rdata.ti_rx_jumbo_ring_paddr); 2253 2254 #ifndef TI_SF_BUF_JUMBO 2255 rcb->ti_max_len = MJUM9BYTES - ETHER_ALIGN; 2256 rcb->ti_flags = 0; 2257 #else 2258 rcb->ti_max_len = PAGE_SIZE; 2259 rcb->ti_flags = TI_RCB_FLAG_USE_EXT_RX_BD; 2260 #endif 2261 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM) 2262 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 2263 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 2264 if (sc->ti_ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 2265 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 2266 2267 /* 2268 * Set up the mini ring. Only activated on the 2269 * Tigon 2 but the slot in the config block is 2270 * still there on the Tigon 1. 2271 */ 2272 rcb = &sc->ti_rdata.ti_info->ti_mini_rx_rcb; 2273 ti_hostaddr64(&rcb->ti_hostaddr, sc->ti_rdata.ti_rx_mini_ring_paddr); 2274 rcb->ti_max_len = MHLEN - ETHER_ALIGN; 2275 if (sc->ti_hwrev == TI_HWREV_TIGON) 2276 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED; 2277 else 2278 rcb->ti_flags = 0; 2279 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM) 2280 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 2281 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 2282 if (sc->ti_ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 2283 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 2284 2285 /* 2286 * Set up the receive return ring. 2287 */ 2288 rcb = &sc->ti_rdata.ti_info->ti_return_rcb; 2289 ti_hostaddr64(&rcb->ti_hostaddr, sc->ti_rdata.ti_rx_return_ring_paddr); 2290 rcb->ti_flags = 0; 2291 rcb->ti_max_len = TI_RETURN_RING_CNT; 2292 ti_hostaddr64(&sc->ti_rdata.ti_info->ti_return_prodidx_ptr, 2293 sc->ti_rdata.ti_status_paddr + 2294 offsetof(struct ti_status, ti_return_prodidx_r)); 2295 2296 /* 2297 * Set up the tx ring. Note: for the Tigon 2, we have the option 2298 * of putting the transmit ring in the host's address space and 2299 * letting the chip DMA it instead of leaving the ring in the NIC's 2300 * memory and accessing it through the shared memory region. We 2301 * do this for the Tigon 2, but it doesn't work on the Tigon 1, 2302 * so we have to revert to the shared memory scheme if we detect 2303 * a Tigon 1 chip. 2304 */ 2305 CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE); 2306 if (sc->ti_rdata.ti_tx_ring != NULL) 2307 bzero(sc->ti_rdata.ti_tx_ring, TI_TX_RING_SZ); 2308 rcb = &sc->ti_rdata.ti_info->ti_tx_rcb; 2309 if (sc->ti_hwrev == TI_HWREV_TIGON) 2310 rcb->ti_flags = 0; 2311 else 2312 rcb->ti_flags = TI_RCB_FLAG_HOST_RING; 2313 if (sc->ti_ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 2314 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 2315 if (sc->ti_ifp->if_capenable & IFCAP_TXCSUM) 2316 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 2317 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 2318 rcb->ti_max_len = TI_TX_RING_CNT; 2319 if (sc->ti_hwrev == TI_HWREV_TIGON) 2320 ti_hostaddr64(&rcb->ti_hostaddr, TI_TX_RING_BASE); 2321 else 2322 ti_hostaddr64(&rcb->ti_hostaddr, 2323 sc->ti_rdata.ti_tx_ring_paddr); 2324 ti_hostaddr64(&sc->ti_rdata.ti_info->ti_tx_considx_ptr, 2325 sc->ti_rdata.ti_status_paddr + 2326 offsetof(struct ti_status, ti_tx_considx_r)); 2327 2328 bus_dmamap_sync(sc->ti_cdata.ti_gib_tag, sc->ti_cdata.ti_gib_map, 2329 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2330 bus_dmamap_sync(sc->ti_cdata.ti_status_tag, sc->ti_cdata.ti_status_map, 2331 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2332 bus_dmamap_sync(sc->ti_cdata.ti_event_ring_tag, 2333 sc->ti_cdata.ti_event_ring_map, 2334 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2335 if (sc->ti_rdata.ti_tx_ring != NULL) 2336 bus_dmamap_sync(sc->ti_cdata.ti_tx_ring_tag, 2337 sc->ti_cdata.ti_tx_ring_map, BUS_DMASYNC_PREWRITE); 2338 2339 /* Set up tunables */ 2340 #if 0 2341 if (ifp->if_mtu > ETHERMTU + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN) 2342 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 2343 (sc->ti_rx_coal_ticks / 10)); 2344 else 2345 #endif 2346 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks); 2347 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks); 2348 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 2349 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds); 2350 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds); 2351 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio); 2352 2353 /* Turn interrupts on. */ 2354 CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0); 2355 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2356 2357 /* Start CPU. */ 2358 TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP)); 2359 2360 return (0); 2361 } 2362 2363 /* 2364 * Probe for a Tigon chip. Check the PCI vendor and device IDs 2365 * against our list and return its name if we find a match. 2366 */ 2367 static int 2368 ti_probe(device_t dev) 2369 { 2370 const struct ti_type *t; 2371 2372 t = ti_devs; 2373 2374 while (t->ti_name != NULL) { 2375 if ((pci_get_vendor(dev) == t->ti_vid) && 2376 (pci_get_device(dev) == t->ti_did)) { 2377 device_set_desc(dev, t->ti_name); 2378 return (BUS_PROBE_DEFAULT); 2379 } 2380 t++; 2381 } 2382 2383 return (ENXIO); 2384 } 2385 2386 static int 2387 ti_attach(device_t dev) 2388 { 2389 struct ifnet *ifp; 2390 struct ti_softc *sc; 2391 int error = 0, rid; 2392 u_char eaddr[6]; 2393 2394 sc = device_get_softc(dev); 2395 sc->ti_dev = dev; 2396 2397 mtx_init(&sc->ti_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 2398 MTX_DEF); 2399 callout_init_mtx(&sc->ti_watchdog, &sc->ti_mtx, 0); 2400 ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts); 2401 ifp = sc->ti_ifp = if_alloc(IFT_ETHER); 2402 if (ifp == NULL) { 2403 device_printf(dev, "can not if_alloc()\n"); 2404 error = ENOSPC; 2405 goto fail; 2406 } 2407 sc->ti_ifp->if_hwassist = TI_CSUM_FEATURES; 2408 sc->ti_ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_RXCSUM; 2409 sc->ti_ifp->if_capenable = sc->ti_ifp->if_capabilities; 2410 2411 /* 2412 * Map control/status registers. 2413 */ 2414 pci_enable_busmaster(dev); 2415 2416 rid = PCIR_BAR(0); 2417 sc->ti_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 2418 RF_ACTIVE); 2419 2420 if (sc->ti_res == NULL) { 2421 device_printf(dev, "couldn't map memory\n"); 2422 error = ENXIO; 2423 goto fail; 2424 } 2425 2426 sc->ti_btag = rman_get_bustag(sc->ti_res); 2427 sc->ti_bhandle = rman_get_bushandle(sc->ti_res); 2428 2429 /* Allocate interrupt */ 2430 rid = 0; 2431 2432 sc->ti_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 2433 RF_SHAREABLE | RF_ACTIVE); 2434 2435 if (sc->ti_irq == NULL) { 2436 device_printf(dev, "couldn't map interrupt\n"); 2437 error = ENXIO; 2438 goto fail; 2439 } 2440 2441 if (ti_chipinit(sc)) { 2442 device_printf(dev, "chip initialization failed\n"); 2443 error = ENXIO; 2444 goto fail; 2445 } 2446 2447 /* Zero out the NIC's on-board SRAM. */ 2448 ti_mem_zero(sc, 0x2000, 0x100000 - 0x2000); 2449 2450 /* Init again -- zeroing memory may have clobbered some registers. */ 2451 if (ti_chipinit(sc)) { 2452 device_printf(dev, "chip initialization failed\n"); 2453 error = ENXIO; 2454 goto fail; 2455 } 2456 2457 /* 2458 * Get station address from the EEPROM. Note: the manual states 2459 * that the MAC address is at offset 0x8c, however the data is 2460 * stored as two longwords (since that's how it's loaded into 2461 * the NIC). This means the MAC address is actually preceded 2462 * by two zero bytes. We need to skip over those. 2463 */ 2464 if (ti_read_eeprom(sc, eaddr, TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 2465 device_printf(dev, "failed to read station address\n"); 2466 error = ENXIO; 2467 goto fail; 2468 } 2469 2470 /* Allocate working area for memory dump. */ 2471 sc->ti_membuf = malloc(sizeof(uint8_t) * TI_WINLEN, M_DEVBUF, M_NOWAIT); 2472 sc->ti_membuf2 = malloc(sizeof(uint8_t) * TI_WINLEN, M_DEVBUF, 2473 M_NOWAIT); 2474 if (sc->ti_membuf == NULL || sc->ti_membuf2 == NULL) { 2475 device_printf(dev, "cannot allocate memory buffer\n"); 2476 error = ENOMEM; 2477 goto fail; 2478 } 2479 if ((error = ti_dma_alloc(sc)) != 0) 2480 goto fail; 2481 2482 /* 2483 * We really need a better way to tell a 1000baseTX card 2484 * from a 1000baseSX one, since in theory there could be 2485 * OEMed 1000baseTX cards from lame vendors who aren't 2486 * clever enough to change the PCI ID. For the moment 2487 * though, the AceNIC is the only copper card available. 2488 */ 2489 if (pci_get_vendor(dev) == ALT_VENDORID && 2490 pci_get_device(dev) == ALT_DEVICEID_ACENIC_COPPER) 2491 sc->ti_copper = 1; 2492 /* Ok, it's not the only copper card available. */ 2493 if (pci_get_vendor(dev) == NG_VENDORID && 2494 pci_get_device(dev) == NG_DEVICEID_GA620T) 2495 sc->ti_copper = 1; 2496 2497 /* Set default tunable values. */ 2498 ti_sysctl_node(sc); 2499 2500 /* Set up ifnet structure */ 2501 ifp->if_softc = sc; 2502 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2503 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2504 ifp->if_ioctl = ti_ioctl; 2505 ifp->if_start = ti_start; 2506 ifp->if_init = ti_init; 2507 ifp->if_get_counter = ti_get_counter; 2508 ifp->if_baudrate = IF_Gbps(1UL); 2509 ifp->if_snd.ifq_drv_maxlen = TI_TX_RING_CNT - 1; 2510 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 2511 IFQ_SET_READY(&ifp->if_snd); 2512 2513 /* Set up ifmedia support. */ 2514 if (sc->ti_copper) { 2515 /* 2516 * Copper cards allow manual 10/100 mode selection, 2517 * but not manual 1000baseTX mode selection. Why? 2518 * Because currently there's no way to specify the 2519 * master/slave setting through the firmware interface, 2520 * so Alteon decided to just bag it and handle it 2521 * via autonegotiation. 2522 */ 2523 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 2524 ifmedia_add(&sc->ifmedia, 2525 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 2526 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); 2527 ifmedia_add(&sc->ifmedia, 2528 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 2529 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_T, 0, NULL); 2530 ifmedia_add(&sc->ifmedia, 2531 IFM_ETHER|IFM_1000_T|IFM_FDX, 0, NULL); 2532 } else { 2533 /* Fiber cards don't support 10/100 modes. */ 2534 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 2535 ifmedia_add(&sc->ifmedia, 2536 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 2537 } 2538 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 2539 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO); 2540 2541 /* 2542 * We're assuming here that card initialization is a sequential 2543 * thing. If it isn't, multiple cards probing at the same time 2544 * could stomp on the list of softcs here. 2545 */ 2546 2547 /* Register the device */ 2548 sc->dev = make_dev(&ti_cdevsw, device_get_unit(dev), UID_ROOT, 2549 GID_OPERATOR, 0600, "ti%d", device_get_unit(dev)); 2550 sc->dev->si_drv1 = sc; 2551 2552 /* 2553 * Call MI attach routine. 2554 */ 2555 ether_ifattach(ifp, eaddr); 2556 2557 /* VLAN capability setup. */ 2558 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWCSUM | 2559 IFCAP_VLAN_HWTAGGING; 2560 ifp->if_capenable = ifp->if_capabilities; 2561 /* Tell the upper layer we support VLAN over-sized frames. */ 2562 ifp->if_hdrlen = sizeof(struct ether_vlan_header); 2563 2564 /* Driver supports link state tracking. */ 2565 ifp->if_capabilities |= IFCAP_LINKSTATE; 2566 ifp->if_capenable |= IFCAP_LINKSTATE; 2567 2568 /* Hook interrupt last to avoid having to lock softc */ 2569 error = bus_setup_intr(dev, sc->ti_irq, INTR_TYPE_NET|INTR_MPSAFE, 2570 NULL, ti_intr, sc, &sc->ti_intrhand); 2571 2572 if (error) { 2573 device_printf(dev, "couldn't set up irq\n"); 2574 goto fail; 2575 } 2576 2577 fail: 2578 if (error) 2579 ti_detach(dev); 2580 2581 return (error); 2582 } 2583 2584 /* 2585 * Shutdown hardware and free up resources. This can be called any 2586 * time after the mutex has been initialized. It is called in both 2587 * the error case in attach and the normal detach case so it needs 2588 * to be careful about only freeing resources that have actually been 2589 * allocated. 2590 */ 2591 static int 2592 ti_detach(device_t dev) 2593 { 2594 struct ti_softc *sc; 2595 struct ifnet *ifp; 2596 2597 sc = device_get_softc(dev); 2598 if (sc->dev) 2599 destroy_dev(sc->dev); 2600 KASSERT(mtx_initialized(&sc->ti_mtx), ("ti mutex not initialized")); 2601 ifp = sc->ti_ifp; 2602 if (device_is_attached(dev)) { 2603 ether_ifdetach(ifp); 2604 TI_LOCK(sc); 2605 ti_stop(sc); 2606 TI_UNLOCK(sc); 2607 } 2608 2609 /* These should only be active if attach succeeded */ 2610 callout_drain(&sc->ti_watchdog); 2611 bus_generic_detach(dev); 2612 ti_dma_free(sc); 2613 ifmedia_removeall(&sc->ifmedia); 2614 2615 if (sc->ti_intrhand) 2616 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 2617 if (sc->ti_irq) 2618 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 2619 if (sc->ti_res) { 2620 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0), 2621 sc->ti_res); 2622 } 2623 if (ifp) 2624 if_free(ifp); 2625 if (sc->ti_membuf) 2626 free(sc->ti_membuf, M_DEVBUF); 2627 if (sc->ti_membuf2) 2628 free(sc->ti_membuf2, M_DEVBUF); 2629 2630 mtx_destroy(&sc->ti_mtx); 2631 2632 return (0); 2633 } 2634 2635 #ifdef TI_JUMBO_HDRSPLIT 2636 /* 2637 * If hdr_len is 0, that means that header splitting wasn't done on 2638 * this packet for some reason. The two most likely reasons are that 2639 * the protocol isn't a supported protocol for splitting, or this 2640 * packet had a fragment offset that wasn't 0. 2641 * 2642 * The header length, if it is non-zero, will always be the length of 2643 * the headers on the packet, but that length could be longer than the 2644 * first mbuf. So we take the minimum of the two as the actual 2645 * length. 2646 */ 2647 static __inline void 2648 ti_hdr_split(struct mbuf *top, int hdr_len, int pkt_len, int idx) 2649 { 2650 int i = 0; 2651 int lengths[4] = {0, 0, 0, 0}; 2652 struct mbuf *m, *mp; 2653 2654 if (hdr_len != 0) 2655 top->m_len = min(hdr_len, top->m_len); 2656 pkt_len -= top->m_len; 2657 lengths[i++] = top->m_len; 2658 2659 mp = top; 2660 for (m = top->m_next; m && pkt_len; m = m->m_next) { 2661 m->m_len = m->m_ext.ext_size = min(m->m_len, pkt_len); 2662 pkt_len -= m->m_len; 2663 lengths[i++] = m->m_len; 2664 mp = m; 2665 } 2666 2667 #if 0 2668 if (hdr_len != 0) 2669 printf("got split packet: "); 2670 else 2671 printf("got non-split packet: "); 2672 2673 printf("%d,%d,%d,%d = %d\n", lengths[0], 2674 lengths[1], lengths[2], lengths[3], 2675 lengths[0] + lengths[1] + lengths[2] + 2676 lengths[3]); 2677 #endif 2678 2679 if (pkt_len) 2680 panic("header splitting didn't"); 2681 2682 if (m) { 2683 m_freem(m); 2684 mp->m_next = NULL; 2685 2686 } 2687 if (mp->m_next != NULL) 2688 panic("ti_hdr_split: last mbuf in chain should be null"); 2689 } 2690 #endif /* TI_JUMBO_HDRSPLIT */ 2691 2692 static void 2693 ti_discard_std(struct ti_softc *sc, int i) 2694 { 2695 2696 struct ti_rx_desc *r; 2697 2698 r = &sc->ti_rdata.ti_rx_std_ring[i]; 2699 r->ti_len = MCLBYTES - ETHER_ALIGN; 2700 r->ti_type = TI_BDTYPE_RECV_BD; 2701 r->ti_flags = 0; 2702 r->ti_vlan_tag = 0; 2703 r->ti_tcp_udp_cksum = 0; 2704 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM) 2705 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 2706 r->ti_idx = i; 2707 } 2708 2709 static void 2710 ti_discard_mini(struct ti_softc *sc, int i) 2711 { 2712 2713 struct ti_rx_desc *r; 2714 2715 r = &sc->ti_rdata.ti_rx_mini_ring[i]; 2716 r->ti_len = MHLEN - ETHER_ALIGN; 2717 r->ti_type = TI_BDTYPE_RECV_BD; 2718 r->ti_flags = TI_BDFLAG_MINI_RING; 2719 r->ti_vlan_tag = 0; 2720 r->ti_tcp_udp_cksum = 0; 2721 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM) 2722 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 2723 r->ti_idx = i; 2724 } 2725 2726 #ifndef TI_SF_BUF_JUMBO 2727 static void 2728 ti_discard_jumbo(struct ti_softc *sc, int i) 2729 { 2730 2731 struct ti_rx_desc *r; 2732 2733 r = &sc->ti_rdata.ti_rx_jumbo_ring[i]; 2734 r->ti_len = MJUM9BYTES - ETHER_ALIGN; 2735 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 2736 r->ti_flags = TI_BDFLAG_JUMBO_RING; 2737 r->ti_vlan_tag = 0; 2738 r->ti_tcp_udp_cksum = 0; 2739 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM) 2740 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 2741 r->ti_idx = i; 2742 } 2743 #endif 2744 2745 /* 2746 * Frame reception handling. This is called if there's a frame 2747 * on the receive return list. 2748 * 2749 * Note: we have to be able to handle three possibilities here: 2750 * 1) the frame is from the mini receive ring (can only happen) 2751 * on Tigon 2 boards) 2752 * 2) the frame is from the jumbo receive ring 2753 * 3) the frame is from the standard receive ring 2754 */ 2755 2756 static void 2757 ti_rxeof(struct ti_softc *sc) 2758 { 2759 struct ifnet *ifp; 2760 #ifdef TI_SF_BUF_JUMBO 2761 bus_dmamap_t map; 2762 #endif 2763 struct ti_cmd_desc cmd; 2764 int jumbocnt, minicnt, stdcnt, ti_len; 2765 2766 TI_LOCK_ASSERT(sc); 2767 2768 ifp = sc->ti_ifp; 2769 2770 bus_dmamap_sync(sc->ti_cdata.ti_rx_std_ring_tag, 2771 sc->ti_cdata.ti_rx_std_ring_map, BUS_DMASYNC_POSTWRITE); 2772 if (ifp->if_mtu > ETHERMTU + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN) 2773 bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_ring_tag, 2774 sc->ti_cdata.ti_rx_jumbo_ring_map, BUS_DMASYNC_POSTWRITE); 2775 if (sc->ti_rdata.ti_rx_mini_ring != NULL) 2776 bus_dmamap_sync(sc->ti_cdata.ti_rx_mini_ring_tag, 2777 sc->ti_cdata.ti_rx_mini_ring_map, BUS_DMASYNC_POSTWRITE); 2778 bus_dmamap_sync(sc->ti_cdata.ti_rx_return_ring_tag, 2779 sc->ti_cdata.ti_rx_return_ring_map, BUS_DMASYNC_POSTREAD); 2780 2781 jumbocnt = minicnt = stdcnt = 0; 2782 while (sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) { 2783 struct ti_rx_desc *cur_rx; 2784 uint32_t rxidx; 2785 struct mbuf *m = NULL; 2786 uint16_t vlan_tag = 0; 2787 int have_tag = 0; 2788 2789 cur_rx = 2790 &sc->ti_rdata.ti_rx_return_ring[sc->ti_rx_saved_considx]; 2791 rxidx = cur_rx->ti_idx; 2792 ti_len = cur_rx->ti_len; 2793 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT); 2794 2795 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) { 2796 have_tag = 1; 2797 vlan_tag = cur_rx->ti_vlan_tag; 2798 } 2799 2800 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) { 2801 jumbocnt++; 2802 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT); 2803 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx]; 2804 #ifndef TI_SF_BUF_JUMBO 2805 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 2806 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 2807 ti_discard_jumbo(sc, rxidx); 2808 continue; 2809 } 2810 if (ti_newbuf_jumbo(sc, rxidx, NULL) != 0) { 2811 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 2812 ti_discard_jumbo(sc, rxidx); 2813 continue; 2814 } 2815 m->m_len = ti_len; 2816 #else /* !TI_SF_BUF_JUMBO */ 2817 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL; 2818 map = sc->ti_cdata.ti_rx_jumbo_maps[rxidx]; 2819 bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_tag, map, 2820 BUS_DMASYNC_POSTREAD); 2821 bus_dmamap_unload(sc->ti_cdata.ti_rx_jumbo_tag, map); 2822 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 2823 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 2824 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 2825 continue; 2826 } 2827 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) == ENOBUFS) { 2828 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 2829 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 2830 continue; 2831 } 2832 #ifdef TI_JUMBO_HDRSPLIT 2833 if (sc->ti_hdrsplit) 2834 ti_hdr_split(m, TI_HOSTADDR(cur_rx->ti_addr), 2835 ti_len, rxidx); 2836 else 2837 #endif /* TI_JUMBO_HDRSPLIT */ 2838 m_adj(m, ti_len - m->m_pkthdr.len); 2839 #endif /* TI_SF_BUF_JUMBO */ 2840 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) { 2841 minicnt++; 2842 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT); 2843 m = sc->ti_cdata.ti_rx_mini_chain[rxidx]; 2844 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 2845 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 2846 ti_discard_mini(sc, rxidx); 2847 continue; 2848 } 2849 if (ti_newbuf_mini(sc, rxidx) != 0) { 2850 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 2851 ti_discard_mini(sc, rxidx); 2852 continue; 2853 } 2854 m->m_len = ti_len; 2855 } else { 2856 stdcnt++; 2857 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT); 2858 m = sc->ti_cdata.ti_rx_std_chain[rxidx]; 2859 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 2860 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 2861 ti_discard_std(sc, rxidx); 2862 continue; 2863 } 2864 if (ti_newbuf_std(sc, rxidx) != 0) { 2865 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 2866 ti_discard_std(sc, rxidx); 2867 continue; 2868 } 2869 m->m_len = ti_len; 2870 } 2871 2872 m->m_pkthdr.len = ti_len; 2873 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 2874 m->m_pkthdr.rcvif = ifp; 2875 2876 if (ifp->if_capenable & IFCAP_RXCSUM) { 2877 if (cur_rx->ti_flags & TI_BDFLAG_IP_CKSUM) { 2878 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2879 if ((cur_rx->ti_ip_cksum ^ 0xffff) == 0) 2880 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2881 } 2882 if (cur_rx->ti_flags & TI_BDFLAG_TCP_UDP_CKSUM) { 2883 m->m_pkthdr.csum_data = 2884 cur_rx->ti_tcp_udp_cksum; 2885 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID; 2886 } 2887 } 2888 2889 /* 2890 * If we received a packet with a vlan tag, 2891 * tag it before passing the packet upward. 2892 */ 2893 if (have_tag) { 2894 m->m_pkthdr.ether_vtag = vlan_tag; 2895 m->m_flags |= M_VLANTAG; 2896 } 2897 TI_UNLOCK(sc); 2898 (*ifp->if_input)(ifp, m); 2899 TI_LOCK(sc); 2900 } 2901 2902 bus_dmamap_sync(sc->ti_cdata.ti_rx_return_ring_tag, 2903 sc->ti_cdata.ti_rx_return_ring_map, BUS_DMASYNC_PREREAD); 2904 /* Only necessary on the Tigon 1. */ 2905 if (sc->ti_hwrev == TI_HWREV_TIGON) 2906 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 2907 sc->ti_rx_saved_considx); 2908 2909 if (stdcnt > 0) { 2910 bus_dmamap_sync(sc->ti_cdata.ti_rx_std_ring_tag, 2911 sc->ti_cdata.ti_rx_std_ring_map, BUS_DMASYNC_PREWRITE); 2912 TI_UPDATE_STDPROD(sc, sc->ti_std); 2913 } 2914 if (minicnt > 0) { 2915 bus_dmamap_sync(sc->ti_cdata.ti_rx_mini_ring_tag, 2916 sc->ti_cdata.ti_rx_mini_ring_map, BUS_DMASYNC_PREWRITE); 2917 TI_UPDATE_MINIPROD(sc, sc->ti_mini); 2918 } 2919 if (jumbocnt > 0) { 2920 bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_ring_tag, 2921 sc->ti_cdata.ti_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE); 2922 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo); 2923 } 2924 } 2925 2926 static void 2927 ti_txeof(struct ti_softc *sc) 2928 { 2929 struct ti_txdesc *txd; 2930 struct ti_tx_desc txdesc; 2931 struct ti_tx_desc *cur_tx = NULL; 2932 struct ifnet *ifp; 2933 int idx; 2934 2935 ifp = sc->ti_ifp; 2936 2937 txd = STAILQ_FIRST(&sc->ti_cdata.ti_txbusyq); 2938 if (txd == NULL) 2939 return; 2940 2941 if (sc->ti_rdata.ti_tx_ring != NULL) 2942 bus_dmamap_sync(sc->ti_cdata.ti_tx_ring_tag, 2943 sc->ti_cdata.ti_tx_ring_map, BUS_DMASYNC_POSTWRITE); 2944 /* 2945 * Go through our tx ring and free mbufs for those 2946 * frames that have been sent. 2947 */ 2948 for (idx = sc->ti_tx_saved_considx; idx != sc->ti_tx_considx.ti_idx; 2949 TI_INC(idx, TI_TX_RING_CNT)) { 2950 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2951 ti_mem_read(sc, TI_TX_RING_BASE + idx * sizeof(txdesc), 2952 sizeof(txdesc), &txdesc); 2953 cur_tx = &txdesc; 2954 } else 2955 cur_tx = &sc->ti_rdata.ti_tx_ring[idx]; 2956 sc->ti_txcnt--; 2957 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2958 if ((cur_tx->ti_flags & TI_BDFLAG_END) == 0) 2959 continue; 2960 bus_dmamap_sync(sc->ti_cdata.ti_tx_tag, txd->tx_dmamap, 2961 BUS_DMASYNC_POSTWRITE); 2962 bus_dmamap_unload(sc->ti_cdata.ti_tx_tag, txd->tx_dmamap); 2963 2964 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 2965 m_freem(txd->tx_m); 2966 txd->tx_m = NULL; 2967 STAILQ_REMOVE_HEAD(&sc->ti_cdata.ti_txbusyq, tx_q); 2968 STAILQ_INSERT_TAIL(&sc->ti_cdata.ti_txfreeq, txd, tx_q); 2969 txd = STAILQ_FIRST(&sc->ti_cdata.ti_txbusyq); 2970 } 2971 sc->ti_tx_saved_considx = idx; 2972 if (sc->ti_txcnt == 0) 2973 sc->ti_timer = 0; 2974 } 2975 2976 static void 2977 ti_intr(void *xsc) 2978 { 2979 struct ti_softc *sc; 2980 struct ifnet *ifp; 2981 2982 sc = xsc; 2983 TI_LOCK(sc); 2984 ifp = sc->ti_ifp; 2985 2986 /* Make sure this is really our interrupt. */ 2987 if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE)) { 2988 TI_UNLOCK(sc); 2989 return; 2990 } 2991 2992 /* Ack interrupt and stop others from occurring. */ 2993 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2994 2995 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 2996 bus_dmamap_sync(sc->ti_cdata.ti_status_tag, 2997 sc->ti_cdata.ti_status_map, BUS_DMASYNC_POSTREAD); 2998 /* Check RX return ring producer/consumer */ 2999 ti_rxeof(sc); 3000 3001 /* Check TX ring producer/consumer */ 3002 ti_txeof(sc); 3003 bus_dmamap_sync(sc->ti_cdata.ti_status_tag, 3004 sc->ti_cdata.ti_status_map, BUS_DMASYNC_PREREAD); 3005 } 3006 3007 ti_handle_events(sc); 3008 3009 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3010 /* Re-enable interrupts. */ 3011 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 3012 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3013 ti_start_locked(ifp); 3014 } 3015 3016 TI_UNLOCK(sc); 3017 } 3018 3019 static uint64_t 3020 ti_get_counter(struct ifnet *ifp, ift_counter cnt) 3021 { 3022 3023 switch (cnt) { 3024 case IFCOUNTER_COLLISIONS: 3025 { 3026 struct ti_softc *sc; 3027 struct ti_stats *s; 3028 uint64_t rv; 3029 3030 sc = if_getsoftc(ifp); 3031 s = &sc->ti_rdata.ti_info->ti_stats; 3032 3033 TI_LOCK(sc); 3034 bus_dmamap_sync(sc->ti_cdata.ti_gib_tag, 3035 sc->ti_cdata.ti_gib_map, BUS_DMASYNC_POSTREAD); 3036 rv = s->dot3StatsSingleCollisionFrames + 3037 s->dot3StatsMultipleCollisionFrames + 3038 s->dot3StatsExcessiveCollisions + 3039 s->dot3StatsLateCollisions; 3040 bus_dmamap_sync(sc->ti_cdata.ti_gib_tag, 3041 sc->ti_cdata.ti_gib_map, BUS_DMASYNC_PREREAD); 3042 TI_UNLOCK(sc); 3043 return (rv); 3044 } 3045 default: 3046 return (if_get_counter_default(ifp, cnt)); 3047 } 3048 } 3049 3050 /* 3051 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 3052 * pointers to descriptors. 3053 */ 3054 static int 3055 ti_encap(struct ti_softc *sc, struct mbuf **m_head) 3056 { 3057 struct ti_txdesc *txd; 3058 struct ti_tx_desc *f; 3059 struct ti_tx_desc txdesc; 3060 struct mbuf *m; 3061 bus_dma_segment_t txsegs[TI_MAXTXSEGS]; 3062 uint16_t csum_flags; 3063 int error, frag, i, nseg; 3064 3065 if ((txd = STAILQ_FIRST(&sc->ti_cdata.ti_txfreeq)) == NULL) 3066 return (ENOBUFS); 3067 3068 error = bus_dmamap_load_mbuf_sg(sc->ti_cdata.ti_tx_tag, txd->tx_dmamap, 3069 *m_head, txsegs, &nseg, 0); 3070 if (error == EFBIG) { 3071 m = m_defrag(*m_head, M_NOWAIT); 3072 if (m == NULL) { 3073 m_freem(*m_head); 3074 *m_head = NULL; 3075 return (ENOMEM); 3076 } 3077 *m_head = m; 3078 error = bus_dmamap_load_mbuf_sg(sc->ti_cdata.ti_tx_tag, 3079 txd->tx_dmamap, *m_head, txsegs, &nseg, 0); 3080 if (error) { 3081 m_freem(*m_head); 3082 *m_head = NULL; 3083 return (error); 3084 } 3085 } else if (error != 0) 3086 return (error); 3087 if (nseg == 0) { 3088 m_freem(*m_head); 3089 *m_head = NULL; 3090 return (EIO); 3091 } 3092 3093 if (sc->ti_txcnt + nseg >= TI_TX_RING_CNT) { 3094 bus_dmamap_unload(sc->ti_cdata.ti_tx_tag, txd->tx_dmamap); 3095 return (ENOBUFS); 3096 } 3097 bus_dmamap_sync(sc->ti_cdata.ti_tx_tag, txd->tx_dmamap, 3098 BUS_DMASYNC_PREWRITE); 3099 3100 m = *m_head; 3101 csum_flags = 0; 3102 if (m->m_pkthdr.csum_flags & CSUM_IP) 3103 csum_flags |= TI_BDFLAG_IP_CKSUM; 3104 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 3105 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 3106 3107 frag = sc->ti_tx_saved_prodidx; 3108 for (i = 0; i < nseg; i++) { 3109 if (sc->ti_hwrev == TI_HWREV_TIGON) { 3110 bzero(&txdesc, sizeof(txdesc)); 3111 f = &txdesc; 3112 } else 3113 f = &sc->ti_rdata.ti_tx_ring[frag]; 3114 ti_hostaddr64(&f->ti_addr, txsegs[i].ds_addr); 3115 f->ti_len = txsegs[i].ds_len; 3116 f->ti_flags = csum_flags; 3117 if (m->m_flags & M_VLANTAG) { 3118 f->ti_flags |= TI_BDFLAG_VLAN_TAG; 3119 f->ti_vlan_tag = m->m_pkthdr.ether_vtag; 3120 } else { 3121 f->ti_vlan_tag = 0; 3122 } 3123 3124 if (sc->ti_hwrev == TI_HWREV_TIGON) 3125 ti_mem_write(sc, TI_TX_RING_BASE + frag * 3126 sizeof(txdesc), sizeof(txdesc), &txdesc); 3127 TI_INC(frag, TI_TX_RING_CNT); 3128 } 3129 3130 sc->ti_tx_saved_prodidx = frag; 3131 /* set TI_BDFLAG_END on the last descriptor */ 3132 frag = (frag + TI_TX_RING_CNT - 1) % TI_TX_RING_CNT; 3133 if (sc->ti_hwrev == TI_HWREV_TIGON) { 3134 txdesc.ti_flags |= TI_BDFLAG_END; 3135 ti_mem_write(sc, TI_TX_RING_BASE + frag * sizeof(txdesc), 3136 sizeof(txdesc), &txdesc); 3137 } else 3138 sc->ti_rdata.ti_tx_ring[frag].ti_flags |= TI_BDFLAG_END; 3139 3140 STAILQ_REMOVE_HEAD(&sc->ti_cdata.ti_txfreeq, tx_q); 3141 STAILQ_INSERT_TAIL(&sc->ti_cdata.ti_txbusyq, txd, tx_q); 3142 txd->tx_m = m; 3143 sc->ti_txcnt += nseg; 3144 3145 return (0); 3146 } 3147 3148 static void 3149 ti_start(struct ifnet *ifp) 3150 { 3151 struct ti_softc *sc; 3152 3153 sc = ifp->if_softc; 3154 TI_LOCK(sc); 3155 ti_start_locked(ifp); 3156 TI_UNLOCK(sc); 3157 } 3158 3159 /* 3160 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3161 * to the mbuf data regions directly in the transmit descriptors. 3162 */ 3163 static void 3164 ti_start_locked(struct ifnet *ifp) 3165 { 3166 struct ti_softc *sc; 3167 struct mbuf *m_head = NULL; 3168 int enq = 0; 3169 3170 sc = ifp->if_softc; 3171 3172 for (; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 3173 sc->ti_txcnt < (TI_TX_RING_CNT - 16);) { 3174 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 3175 if (m_head == NULL) 3176 break; 3177 3178 /* 3179 * Pack the data into the transmit ring. If we 3180 * don't have room, set the OACTIVE flag and wait 3181 * for the NIC to drain the ring. 3182 */ 3183 if (ti_encap(sc, &m_head)) { 3184 if (m_head == NULL) 3185 break; 3186 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 3187 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3188 break; 3189 } 3190 3191 enq++; 3192 /* 3193 * If there's a BPF listener, bounce a copy of this frame 3194 * to him. 3195 */ 3196 ETHER_BPF_MTAP(ifp, m_head); 3197 } 3198 3199 if (enq > 0) { 3200 if (sc->ti_rdata.ti_tx_ring != NULL) 3201 bus_dmamap_sync(sc->ti_cdata.ti_tx_ring_tag, 3202 sc->ti_cdata.ti_tx_ring_map, BUS_DMASYNC_PREWRITE); 3203 /* Transmit */ 3204 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, sc->ti_tx_saved_prodidx); 3205 3206 /* 3207 * Set a timeout in case the chip goes out to lunch. 3208 */ 3209 sc->ti_timer = 5; 3210 } 3211 } 3212 3213 static void 3214 ti_init(void *xsc) 3215 { 3216 struct ti_softc *sc; 3217 3218 sc = xsc; 3219 TI_LOCK(sc); 3220 ti_init_locked(sc); 3221 TI_UNLOCK(sc); 3222 } 3223 3224 static void 3225 ti_init_locked(void *xsc) 3226 { 3227 struct ti_softc *sc = xsc; 3228 3229 if (sc->ti_ifp->if_drv_flags & IFF_DRV_RUNNING) 3230 return; 3231 3232 /* Cancel pending I/O and flush buffers. */ 3233 ti_stop(sc); 3234 3235 /* Init the gen info block, ring control blocks and firmware. */ 3236 if (ti_gibinit(sc)) { 3237 device_printf(sc->ti_dev, "initialization failure\n"); 3238 return; 3239 } 3240 } 3241 3242 static void ti_init2(struct ti_softc *sc) 3243 { 3244 struct ti_cmd_desc cmd; 3245 struct ifnet *ifp; 3246 uint8_t *ea; 3247 struct ifmedia *ifm; 3248 int tmp; 3249 3250 TI_LOCK_ASSERT(sc); 3251 3252 ifp = sc->ti_ifp; 3253 3254 /* Specify MTU and interface index. */ 3255 CSR_WRITE_4(sc, TI_GCR_IFINDEX, device_get_unit(sc->ti_dev)); 3256 CSR_WRITE_4(sc, TI_GCR_IFMTU, ifp->if_mtu + 3257 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 3258 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0); 3259 3260 /* Load our MAC address. */ 3261 ea = IF_LLADDR(sc->ti_ifp); 3262 CSR_WRITE_4(sc, TI_GCR_PAR0, (ea[0] << 8) | ea[1]); 3263 CSR_WRITE_4(sc, TI_GCR_PAR1, 3264 (ea[2] << 24) | (ea[3] << 16) | (ea[4] << 8) | ea[5]); 3265 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0); 3266 3267 /* Enable or disable promiscuous mode as needed. */ 3268 if (ifp->if_flags & IFF_PROMISC) { 3269 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0); 3270 } else { 3271 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0); 3272 } 3273 3274 /* Program multicast filter. */ 3275 ti_setmulti(sc); 3276 3277 /* 3278 * If this is a Tigon 1, we should tell the 3279 * firmware to use software packet filtering. 3280 */ 3281 if (sc->ti_hwrev == TI_HWREV_TIGON) { 3282 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0); 3283 } 3284 3285 /* Init RX ring. */ 3286 if (ti_init_rx_ring_std(sc) != 0) { 3287 /* XXX */ 3288 device_printf(sc->ti_dev, "no memory for std Rx buffers.\n"); 3289 return; 3290 } 3291 3292 /* Init jumbo RX ring. */ 3293 if (ifp->if_mtu > ETHERMTU + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN) { 3294 if (ti_init_rx_ring_jumbo(sc) != 0) { 3295 /* XXX */ 3296 device_printf(sc->ti_dev, 3297 "no memory for jumbo Rx buffers.\n"); 3298 return; 3299 } 3300 } 3301 3302 /* 3303 * If this is a Tigon 2, we can also configure the 3304 * mini ring. 3305 */ 3306 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 3307 if (ti_init_rx_ring_mini(sc) != 0) { 3308 /* XXX */ 3309 device_printf(sc->ti_dev, 3310 "no memory for mini Rx buffers.\n"); 3311 return; 3312 } 3313 } 3314 3315 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0); 3316 sc->ti_rx_saved_considx = 0; 3317 3318 /* Init TX ring. */ 3319 ti_init_tx_ring(sc); 3320 3321 /* Tell firmware we're alive. */ 3322 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0); 3323 3324 /* Enable host interrupts. */ 3325 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 3326 3327 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3328 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3329 callout_reset(&sc->ti_watchdog, hz, ti_watchdog, sc); 3330 3331 /* 3332 * Make sure to set media properly. We have to do this 3333 * here since we have to issue commands in order to set 3334 * the link negotiation and we can't issue commands until 3335 * the firmware is running. 3336 */ 3337 ifm = &sc->ifmedia; 3338 tmp = ifm->ifm_media; 3339 ifm->ifm_media = ifm->ifm_cur->ifm_media; 3340 ti_ifmedia_upd_locked(sc); 3341 ifm->ifm_media = tmp; 3342 } 3343 3344 /* 3345 * Set media options. 3346 */ 3347 static int 3348 ti_ifmedia_upd(struct ifnet *ifp) 3349 { 3350 struct ti_softc *sc; 3351 int error; 3352 3353 sc = ifp->if_softc; 3354 TI_LOCK(sc); 3355 error = ti_ifmedia_upd_locked(sc); 3356 TI_UNLOCK(sc); 3357 3358 return (error); 3359 } 3360 3361 static int 3362 ti_ifmedia_upd_locked(struct ti_softc *sc) 3363 { 3364 struct ifmedia *ifm; 3365 struct ti_cmd_desc cmd; 3366 uint32_t flowctl; 3367 3368 ifm = &sc->ifmedia; 3369 3370 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 3371 return (EINVAL); 3372 3373 flowctl = 0; 3374 3375 switch (IFM_SUBTYPE(ifm->ifm_media)) { 3376 case IFM_AUTO: 3377 /* 3378 * Transmit flow control doesn't work on the Tigon 1. 3379 */ 3380 flowctl = TI_GLNK_RX_FLOWCTL_Y; 3381 3382 /* 3383 * Transmit flow control can also cause problems on the 3384 * Tigon 2, apparently with both the copper and fiber 3385 * boards. The symptom is that the interface will just 3386 * hang. This was reproduced with Alteon 180 switches. 3387 */ 3388 #if 0 3389 if (sc->ti_hwrev != TI_HWREV_TIGON) 3390 flowctl |= TI_GLNK_TX_FLOWCTL_Y; 3391 #endif 3392 3393 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 3394 TI_GLNK_FULL_DUPLEX| flowctl | 3395 TI_GLNK_AUTONEGENB|TI_GLNK_ENB); 3396 3397 flowctl = TI_LNK_RX_FLOWCTL_Y; 3398 #if 0 3399 if (sc->ti_hwrev != TI_HWREV_TIGON) 3400 flowctl |= TI_LNK_TX_FLOWCTL_Y; 3401 #endif 3402 3403 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB| 3404 TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX| flowctl | 3405 TI_LNK_AUTONEGENB|TI_LNK_ENB); 3406 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 3407 TI_CMD_CODE_NEGOTIATE_BOTH, 0); 3408 break; 3409 case IFM_1000_SX: 3410 case IFM_1000_T: 3411 flowctl = TI_GLNK_RX_FLOWCTL_Y; 3412 #if 0 3413 if (sc->ti_hwrev != TI_HWREV_TIGON) 3414 flowctl |= TI_GLNK_TX_FLOWCTL_Y; 3415 #endif 3416 3417 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 3418 flowctl |TI_GLNK_ENB); 3419 CSR_WRITE_4(sc, TI_GCR_LINK, 0); 3420 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 3421 TI_SETBIT(sc, TI_GCR_GLINK, TI_GLNK_FULL_DUPLEX); 3422 } 3423 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 3424 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0); 3425 break; 3426 case IFM_100_FX: 3427 case IFM_10_FL: 3428 case IFM_100_TX: 3429 case IFM_10_T: 3430 flowctl = TI_LNK_RX_FLOWCTL_Y; 3431 #if 0 3432 if (sc->ti_hwrev != TI_HWREV_TIGON) 3433 flowctl |= TI_LNK_TX_FLOWCTL_Y; 3434 #endif 3435 3436 CSR_WRITE_4(sc, TI_GCR_GLINK, 0); 3437 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF|flowctl); 3438 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX || 3439 IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) { 3440 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB); 3441 } else { 3442 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB); 3443 } 3444 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 3445 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX); 3446 } else { 3447 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX); 3448 } 3449 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 3450 TI_CMD_CODE_NEGOTIATE_10_100, 0); 3451 break; 3452 } 3453 3454 return (0); 3455 } 3456 3457 /* 3458 * Report current media status. 3459 */ 3460 static void 3461 ti_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3462 { 3463 struct ti_softc *sc; 3464 uint32_t media = 0; 3465 3466 sc = ifp->if_softc; 3467 3468 TI_LOCK(sc); 3469 3470 ifmr->ifm_status = IFM_AVALID; 3471 ifmr->ifm_active = IFM_ETHER; 3472 3473 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) { 3474 TI_UNLOCK(sc); 3475 return; 3476 } 3477 3478 ifmr->ifm_status |= IFM_ACTIVE; 3479 3480 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) { 3481 media = CSR_READ_4(sc, TI_GCR_GLINK_STAT); 3482 if (sc->ti_copper) 3483 ifmr->ifm_active |= IFM_1000_T; 3484 else 3485 ifmr->ifm_active |= IFM_1000_SX; 3486 if (media & TI_GLNK_FULL_DUPLEX) 3487 ifmr->ifm_active |= IFM_FDX; 3488 else 3489 ifmr->ifm_active |= IFM_HDX; 3490 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) { 3491 media = CSR_READ_4(sc, TI_GCR_LINK_STAT); 3492 if (sc->ti_copper) { 3493 if (media & TI_LNK_100MB) 3494 ifmr->ifm_active |= IFM_100_TX; 3495 if (media & TI_LNK_10MB) 3496 ifmr->ifm_active |= IFM_10_T; 3497 } else { 3498 if (media & TI_LNK_100MB) 3499 ifmr->ifm_active |= IFM_100_FX; 3500 if (media & TI_LNK_10MB) 3501 ifmr->ifm_active |= IFM_10_FL; 3502 } 3503 if (media & TI_LNK_FULL_DUPLEX) 3504 ifmr->ifm_active |= IFM_FDX; 3505 if (media & TI_LNK_HALF_DUPLEX) 3506 ifmr->ifm_active |= IFM_HDX; 3507 } 3508 TI_UNLOCK(sc); 3509 } 3510 3511 static int 3512 ti_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 3513 { 3514 struct ti_softc *sc = ifp->if_softc; 3515 struct ifreq *ifr = (struct ifreq *) data; 3516 struct ti_cmd_desc cmd; 3517 int mask, error = 0; 3518 3519 switch (command) { 3520 case SIOCSIFMTU: 3521 TI_LOCK(sc); 3522 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > TI_JUMBO_MTU) 3523 error = EINVAL; 3524 else { 3525 ifp->if_mtu = ifr->ifr_mtu; 3526 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3527 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3528 ti_init_locked(sc); 3529 } 3530 } 3531 TI_UNLOCK(sc); 3532 break; 3533 case SIOCSIFFLAGS: 3534 TI_LOCK(sc); 3535 if (ifp->if_flags & IFF_UP) { 3536 /* 3537 * If only the state of the PROMISC flag changed, 3538 * then just use the 'set promisc mode' command 3539 * instead of reinitializing the entire NIC. Doing 3540 * a full re-init means reloading the firmware and 3541 * waiting for it to start up, which may take a 3542 * second or two. 3543 */ 3544 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 3545 ifp->if_flags & IFF_PROMISC && 3546 !(sc->ti_if_flags & IFF_PROMISC)) { 3547 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 3548 TI_CMD_CODE_PROMISC_ENB, 0); 3549 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING && 3550 !(ifp->if_flags & IFF_PROMISC) && 3551 sc->ti_if_flags & IFF_PROMISC) { 3552 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 3553 TI_CMD_CODE_PROMISC_DIS, 0); 3554 } else 3555 ti_init_locked(sc); 3556 } else { 3557 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3558 ti_stop(sc); 3559 } 3560 } 3561 sc->ti_if_flags = ifp->if_flags; 3562 TI_UNLOCK(sc); 3563 break; 3564 case SIOCADDMULTI: 3565 case SIOCDELMULTI: 3566 TI_LOCK(sc); 3567 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3568 ti_setmulti(sc); 3569 TI_UNLOCK(sc); 3570 break; 3571 case SIOCSIFMEDIA: 3572 case SIOCGIFMEDIA: 3573 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 3574 break; 3575 case SIOCSIFCAP: 3576 TI_LOCK(sc); 3577 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 3578 if ((mask & IFCAP_TXCSUM) != 0 && 3579 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 3580 ifp->if_capenable ^= IFCAP_TXCSUM; 3581 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 3582 ifp->if_hwassist |= TI_CSUM_FEATURES; 3583 else 3584 ifp->if_hwassist &= ~TI_CSUM_FEATURES; 3585 } 3586 if ((mask & IFCAP_RXCSUM) != 0 && 3587 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) 3588 ifp->if_capenable ^= IFCAP_RXCSUM; 3589 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 3590 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) 3591 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 3592 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 3593 (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0) 3594 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 3595 if ((mask & (IFCAP_TXCSUM | IFCAP_RXCSUM | 3596 IFCAP_VLAN_HWTAGGING)) != 0) { 3597 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3598 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3599 ti_init_locked(sc); 3600 } 3601 } 3602 TI_UNLOCK(sc); 3603 VLAN_CAPABILITIES(ifp); 3604 break; 3605 default: 3606 error = ether_ioctl(ifp, command, data); 3607 break; 3608 } 3609 3610 return (error); 3611 } 3612 3613 static int 3614 ti_open(struct cdev *dev, int flags, int fmt, struct thread *td) 3615 { 3616 struct ti_softc *sc; 3617 3618 sc = dev->si_drv1; 3619 if (sc == NULL) 3620 return (ENODEV); 3621 3622 TI_LOCK(sc); 3623 sc->ti_flags |= TI_FLAG_DEBUGING; 3624 TI_UNLOCK(sc); 3625 3626 return (0); 3627 } 3628 3629 static int 3630 ti_close(struct cdev *dev, int flag, int fmt, struct thread *td) 3631 { 3632 struct ti_softc *sc; 3633 3634 sc = dev->si_drv1; 3635 if (sc == NULL) 3636 return (ENODEV); 3637 3638 TI_LOCK(sc); 3639 sc->ti_flags &= ~TI_FLAG_DEBUGING; 3640 TI_UNLOCK(sc); 3641 3642 return (0); 3643 } 3644 3645 /* 3646 * This ioctl routine goes along with the Tigon character device. 3647 */ 3648 static int 3649 ti_ioctl2(struct cdev *dev, u_long cmd, caddr_t addr, int flag, 3650 struct thread *td) 3651 { 3652 struct ti_softc *sc; 3653 int error; 3654 3655 sc = dev->si_drv1; 3656 if (sc == NULL) 3657 return (ENODEV); 3658 3659 error = 0; 3660 3661 switch (cmd) { 3662 case TIIOCGETSTATS: 3663 { 3664 struct ti_stats *outstats; 3665 3666 outstats = (struct ti_stats *)addr; 3667 3668 TI_LOCK(sc); 3669 bus_dmamap_sync(sc->ti_cdata.ti_gib_tag, 3670 sc->ti_cdata.ti_gib_map, BUS_DMASYNC_POSTREAD); 3671 bcopy(&sc->ti_rdata.ti_info->ti_stats, outstats, 3672 sizeof(struct ti_stats)); 3673 bus_dmamap_sync(sc->ti_cdata.ti_gib_tag, 3674 sc->ti_cdata.ti_gib_map, BUS_DMASYNC_PREREAD); 3675 TI_UNLOCK(sc); 3676 break; 3677 } 3678 case TIIOCGETPARAMS: 3679 { 3680 struct ti_params *params; 3681 3682 params = (struct ti_params *)addr; 3683 3684 TI_LOCK(sc); 3685 params->ti_stat_ticks = sc->ti_stat_ticks; 3686 params->ti_rx_coal_ticks = sc->ti_rx_coal_ticks; 3687 params->ti_tx_coal_ticks = sc->ti_tx_coal_ticks; 3688 params->ti_rx_max_coal_bds = sc->ti_rx_max_coal_bds; 3689 params->ti_tx_max_coal_bds = sc->ti_tx_max_coal_bds; 3690 params->ti_tx_buf_ratio = sc->ti_tx_buf_ratio; 3691 params->param_mask = TI_PARAM_ALL; 3692 TI_UNLOCK(sc); 3693 break; 3694 } 3695 case TIIOCSETPARAMS: 3696 { 3697 struct ti_params *params; 3698 3699 params = (struct ti_params *)addr; 3700 3701 TI_LOCK(sc); 3702 if (params->param_mask & TI_PARAM_STAT_TICKS) { 3703 sc->ti_stat_ticks = params->ti_stat_ticks; 3704 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 3705 } 3706 3707 if (params->param_mask & TI_PARAM_RX_COAL_TICKS) { 3708 sc->ti_rx_coal_ticks = params->ti_rx_coal_ticks; 3709 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 3710 sc->ti_rx_coal_ticks); 3711 } 3712 3713 if (params->param_mask & TI_PARAM_TX_COAL_TICKS) { 3714 sc->ti_tx_coal_ticks = params->ti_tx_coal_ticks; 3715 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, 3716 sc->ti_tx_coal_ticks); 3717 } 3718 3719 if (params->param_mask & TI_PARAM_RX_COAL_BDS) { 3720 sc->ti_rx_max_coal_bds = params->ti_rx_max_coal_bds; 3721 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, 3722 sc->ti_rx_max_coal_bds); 3723 } 3724 3725 if (params->param_mask & TI_PARAM_TX_COAL_BDS) { 3726 sc->ti_tx_max_coal_bds = params->ti_tx_max_coal_bds; 3727 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, 3728 sc->ti_tx_max_coal_bds); 3729 } 3730 3731 if (params->param_mask & TI_PARAM_TX_BUF_RATIO) { 3732 sc->ti_tx_buf_ratio = params->ti_tx_buf_ratio; 3733 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, 3734 sc->ti_tx_buf_ratio); 3735 } 3736 TI_UNLOCK(sc); 3737 break; 3738 } 3739 case TIIOCSETTRACE: { 3740 ti_trace_type trace_type; 3741 3742 trace_type = *(ti_trace_type *)addr; 3743 3744 /* 3745 * Set tracing to whatever the user asked for. Setting 3746 * this register to 0 should have the effect of disabling 3747 * tracing. 3748 */ 3749 TI_LOCK(sc); 3750 CSR_WRITE_4(sc, TI_GCR_NIC_TRACING, trace_type); 3751 TI_UNLOCK(sc); 3752 break; 3753 } 3754 case TIIOCGETTRACE: { 3755 struct ti_trace_buf *trace_buf; 3756 uint32_t trace_start, cur_trace_ptr, trace_len; 3757 3758 trace_buf = (struct ti_trace_buf *)addr; 3759 3760 TI_LOCK(sc); 3761 trace_start = CSR_READ_4(sc, TI_GCR_NICTRACE_START); 3762 cur_trace_ptr = CSR_READ_4(sc, TI_GCR_NICTRACE_PTR); 3763 trace_len = CSR_READ_4(sc, TI_GCR_NICTRACE_LEN); 3764 #if 0 3765 if_printf(sc->ti_ifp, "trace_start = %#x, cur_trace_ptr = %#x, " 3766 "trace_len = %d\n", trace_start, 3767 cur_trace_ptr, trace_len); 3768 if_printf(sc->ti_ifp, "trace_buf->buf_len = %d\n", 3769 trace_buf->buf_len); 3770 #endif 3771 error = ti_copy_mem(sc, trace_start, min(trace_len, 3772 trace_buf->buf_len), (caddr_t)trace_buf->buf, 1, 1); 3773 if (error == 0) { 3774 trace_buf->fill_len = min(trace_len, 3775 trace_buf->buf_len); 3776 if (cur_trace_ptr < trace_start) 3777 trace_buf->cur_trace_ptr = 3778 trace_start - cur_trace_ptr; 3779 else 3780 trace_buf->cur_trace_ptr = 3781 cur_trace_ptr - trace_start; 3782 } else 3783 trace_buf->fill_len = 0; 3784 TI_UNLOCK(sc); 3785 break; 3786 } 3787 3788 /* 3789 * For debugging, five ioctls are needed: 3790 * ALT_ATTACH 3791 * ALT_READ_TG_REG 3792 * ALT_WRITE_TG_REG 3793 * ALT_READ_TG_MEM 3794 * ALT_WRITE_TG_MEM 3795 */ 3796 case ALT_ATTACH: 3797 /* 3798 * From what I can tell, Alteon's Solaris Tigon driver 3799 * only has one character device, so you have to attach 3800 * to the Tigon board you're interested in. This seems 3801 * like a not-so-good way to do things, since unless you 3802 * subsequently specify the unit number of the device 3803 * you're interested in every ioctl, you'll only be 3804 * able to debug one board at a time. 3805 */ 3806 break; 3807 case ALT_READ_TG_MEM: 3808 case ALT_WRITE_TG_MEM: 3809 { 3810 struct tg_mem *mem_param; 3811 uint32_t sram_end, scratch_end; 3812 3813 mem_param = (struct tg_mem *)addr; 3814 3815 if (sc->ti_hwrev == TI_HWREV_TIGON) { 3816 sram_end = TI_END_SRAM_I; 3817 scratch_end = TI_END_SCRATCH_I; 3818 } else { 3819 sram_end = TI_END_SRAM_II; 3820 scratch_end = TI_END_SCRATCH_II; 3821 } 3822 3823 /* 3824 * For now, we'll only handle accessing regular SRAM, 3825 * nothing else. 3826 */ 3827 TI_LOCK(sc); 3828 if (mem_param->tgAddr >= TI_BEG_SRAM && 3829 mem_param->tgAddr + mem_param->len <= sram_end) { 3830 /* 3831 * In this instance, we always copy to/from user 3832 * space, so the user space argument is set to 1. 3833 */ 3834 error = ti_copy_mem(sc, mem_param->tgAddr, 3835 mem_param->len, mem_param->userAddr, 1, 3836 cmd == ALT_READ_TG_MEM ? 1 : 0); 3837 } else if (mem_param->tgAddr >= TI_BEG_SCRATCH && 3838 mem_param->tgAddr <= scratch_end) { 3839 error = ti_copy_scratch(sc, mem_param->tgAddr, 3840 mem_param->len, mem_param->userAddr, 1, 3841 cmd == ALT_READ_TG_MEM ? 1 : 0, TI_PROCESSOR_A); 3842 } else if (mem_param->tgAddr >= TI_BEG_SCRATCH_B_DEBUG && 3843 mem_param->tgAddr <= TI_BEG_SCRATCH_B_DEBUG) { 3844 if (sc->ti_hwrev == TI_HWREV_TIGON) { 3845 if_printf(sc->ti_ifp, 3846 "invalid memory range for Tigon I\n"); 3847 error = EINVAL; 3848 break; 3849 } 3850 error = ti_copy_scratch(sc, mem_param->tgAddr - 3851 TI_SCRATCH_DEBUG_OFF, mem_param->len, 3852 mem_param->userAddr, 1, 3853 cmd == ALT_READ_TG_MEM ? 1 : 0, TI_PROCESSOR_B); 3854 } else { 3855 if_printf(sc->ti_ifp, "memory address %#x len %d is " 3856 "out of supported range\n", 3857 mem_param->tgAddr, mem_param->len); 3858 error = EINVAL; 3859 } 3860 TI_UNLOCK(sc); 3861 break; 3862 } 3863 case ALT_READ_TG_REG: 3864 case ALT_WRITE_TG_REG: 3865 { 3866 struct tg_reg *regs; 3867 uint32_t tmpval; 3868 3869 regs = (struct tg_reg *)addr; 3870 3871 /* 3872 * Make sure the address in question isn't out of range. 3873 */ 3874 if (regs->addr > TI_REG_MAX) { 3875 error = EINVAL; 3876 break; 3877 } 3878 TI_LOCK(sc); 3879 if (cmd == ALT_READ_TG_REG) { 3880 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle, 3881 regs->addr, &tmpval, 1); 3882 regs->data = ntohl(tmpval); 3883 #if 0 3884 if ((regs->addr == TI_CPU_STATE) 3885 || (regs->addr == TI_CPU_CTL_B)) { 3886 if_printf(sc->ti_ifp, "register %#x = %#x\n", 3887 regs->addr, tmpval); 3888 } 3889 #endif 3890 } else { 3891 tmpval = htonl(regs->data); 3892 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 3893 regs->addr, &tmpval, 1); 3894 } 3895 TI_UNLOCK(sc); 3896 break; 3897 } 3898 default: 3899 error = ENOTTY; 3900 break; 3901 } 3902 return (error); 3903 } 3904 3905 static void 3906 ti_watchdog(void *arg) 3907 { 3908 struct ti_softc *sc; 3909 struct ifnet *ifp; 3910 3911 sc = arg; 3912 TI_LOCK_ASSERT(sc); 3913 callout_reset(&sc->ti_watchdog, hz, ti_watchdog, sc); 3914 if (sc->ti_timer == 0 || --sc->ti_timer > 0) 3915 return; 3916 3917 /* 3918 * When we're debugging, the chip is often stopped for long periods 3919 * of time, and that would normally cause the watchdog timer to fire. 3920 * Since that impedes debugging, we don't want to do that. 3921 */ 3922 if (sc->ti_flags & TI_FLAG_DEBUGING) 3923 return; 3924 3925 ifp = sc->ti_ifp; 3926 if_printf(ifp, "watchdog timeout -- resetting\n"); 3927 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3928 ti_init_locked(sc); 3929 3930 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 3931 } 3932 3933 /* 3934 * Stop the adapter and free any mbufs allocated to the 3935 * RX and TX lists. 3936 */ 3937 static void 3938 ti_stop(struct ti_softc *sc) 3939 { 3940 struct ifnet *ifp; 3941 struct ti_cmd_desc cmd; 3942 3943 TI_LOCK_ASSERT(sc); 3944 3945 ifp = sc->ti_ifp; 3946 3947 /* Disable host interrupts. */ 3948 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 3949 /* 3950 * Tell firmware we're shutting down. 3951 */ 3952 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0); 3953 3954 /* Halt and reinitialize. */ 3955 if (ti_chipinit(sc) == 0) { 3956 ti_mem_zero(sc, 0x2000, 0x100000 - 0x2000); 3957 /* XXX ignore init errors. */ 3958 ti_chipinit(sc); 3959 } 3960 3961 /* Free the RX lists. */ 3962 ti_free_rx_ring_std(sc); 3963 3964 /* Free jumbo RX list. */ 3965 ti_free_rx_ring_jumbo(sc); 3966 3967 /* Free mini RX list. */ 3968 ti_free_rx_ring_mini(sc); 3969 3970 /* Free TX buffers. */ 3971 ti_free_tx_ring(sc); 3972 3973 sc->ti_ev_prodidx.ti_idx = 0; 3974 sc->ti_return_prodidx.ti_idx = 0; 3975 sc->ti_tx_considx.ti_idx = 0; 3976 sc->ti_tx_saved_considx = TI_TXCONS_UNSET; 3977 3978 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 3979 callout_stop(&sc->ti_watchdog); 3980 } 3981 3982 /* 3983 * Stop all chip I/O so that the kernel's probe routines don't 3984 * get confused by errant DMAs when rebooting. 3985 */ 3986 static int 3987 ti_shutdown(device_t dev) 3988 { 3989 struct ti_softc *sc; 3990 3991 sc = device_get_softc(dev); 3992 TI_LOCK(sc); 3993 ti_chipinit(sc); 3994 TI_UNLOCK(sc); 3995 3996 return (0); 3997 } 3998 3999 static void 4000 ti_sysctl_node(struct ti_softc *sc) 4001 { 4002 struct sysctl_ctx_list *ctx; 4003 struct sysctl_oid_list *child; 4004 char tname[32]; 4005 4006 ctx = device_get_sysctl_ctx(sc->ti_dev); 4007 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->ti_dev)); 4008 4009 /* Use DAC */ 4010 sc->ti_dac = 1; 4011 snprintf(tname, sizeof(tname), "dev.ti.%d.dac", 4012 device_get_unit(sc->ti_dev)); 4013 TUNABLE_INT_FETCH(tname, &sc->ti_dac); 4014 4015 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_coal_ticks", CTLFLAG_RW, 4016 &sc->ti_rx_coal_ticks, 0, "Receive coalcesced ticks"); 4017 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_max_coal_bds", CTLFLAG_RW, 4018 &sc->ti_rx_max_coal_bds, 0, "Receive max coalcesced BDs"); 4019 4020 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_coal_ticks", CTLFLAG_RW, 4021 &sc->ti_tx_coal_ticks, 0, "Send coalcesced ticks"); 4022 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_max_coal_bds", CTLFLAG_RW, 4023 &sc->ti_tx_max_coal_bds, 0, "Send max coalcesced BDs"); 4024 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_buf_ratio", CTLFLAG_RW, 4025 &sc->ti_tx_buf_ratio, 0, 4026 "Ratio of NIC memory devoted to TX buffer"); 4027 4028 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "stat_ticks", CTLFLAG_RW, 4029 &sc->ti_stat_ticks, 0, 4030 "Number of clock ticks for statistics update interval"); 4031 4032 /* Pull in device tunables. */ 4033 sc->ti_rx_coal_ticks = 170; 4034 resource_int_value(device_get_name(sc->ti_dev), 4035 device_get_unit(sc->ti_dev), "rx_coal_ticks", 4036 &sc->ti_rx_coal_ticks); 4037 sc->ti_rx_max_coal_bds = 64; 4038 resource_int_value(device_get_name(sc->ti_dev), 4039 device_get_unit(sc->ti_dev), "rx_max_coal_bds", 4040 &sc->ti_rx_max_coal_bds); 4041 4042 sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500; 4043 resource_int_value(device_get_name(sc->ti_dev), 4044 device_get_unit(sc->ti_dev), "tx_coal_ticks", 4045 &sc->ti_tx_coal_ticks); 4046 sc->ti_tx_max_coal_bds = 32; 4047 resource_int_value(device_get_name(sc->ti_dev), 4048 device_get_unit(sc->ti_dev), "tx_max_coal_bds", 4049 &sc->ti_tx_max_coal_bds); 4050 sc->ti_tx_buf_ratio = 21; 4051 resource_int_value(device_get_name(sc->ti_dev), 4052 device_get_unit(sc->ti_dev), "tx_buf_ratio", 4053 &sc->ti_tx_buf_ratio); 4054 4055 sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC; 4056 resource_int_value(device_get_name(sc->ti_dev), 4057 device_get_unit(sc->ti_dev), "stat_ticks", 4058 &sc->ti_stat_ticks); 4059 } 4060