1 /*- 2 * Copyright (C) 2006-2007 Semihalf, Piotr Kruszynski <ppk@semihalf.com> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 18 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 19 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 20 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 21 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 22 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 23 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 * 25 * $FreeBSD$ 26 */ 27 28 #ifndef _IF_TSEC_H 29 #define _IF_TSEC_H 30 31 #define TSEC_RX_NUM_DESC 256 32 #define TSEC_TX_NUM_DESC 256 33 34 /* Interrupt Coalescing types */ 35 #define TSEC_IC_RX 0 36 #define TSEC_IC_TX 1 37 38 /* eTSEC ID */ 39 #define TSEC_ETSEC_ID 0x0124 40 41 /* Frame sizes */ 42 #define TSEC_MIN_FRAME_SIZE 64 43 #define TSEC_MAX_FRAME_SIZE 9600 44 45 struct tsec_softc { 46 /* XXX MII bus requires that struct ifnet is first!!! */ 47 struct ifnet *tsec_ifp; 48 49 struct mtx transmit_lock; /* transmitter lock */ 50 struct mtx receive_lock; /* receiver lock */ 51 52 device_t dev; 53 device_t tsec_miibus; 54 struct mii_data *tsec_mii; /* MII media control */ 55 int tsec_link; 56 57 bus_dma_tag_t tsec_tx_dtag; /* TX descriptors tag */ 58 bus_dmamap_t tsec_tx_dmap; /* TX descriptors map */ 59 struct tsec_desc *tsec_tx_vaddr;/* vadress of TX descriptors */ 60 uint32_t tsec_tx_raddr; /* real adress of TX descriptors */ 61 62 bus_dma_tag_t tsec_rx_dtag; /* RX descriptors tag */ 63 bus_dmamap_t tsec_rx_dmap; /* RX descriptors map */ 64 struct tsec_desc *tsec_rx_vaddr; /* vadress of RX descriptors */ 65 uint32_t tsec_rx_raddr; /* real adress of RX descriptors */ 66 67 bus_dma_tag_t tsec_tx_mtag; /* TX mbufs tag */ 68 bus_dma_tag_t tsec_rx_mtag; /* TX mbufs tag */ 69 70 struct rx_data_type { 71 bus_dmamap_t map; /* mbuf map */ 72 struct mbuf *mbuf; 73 uint32_t paddr; /* DMA addres of buffer */ 74 } rx_data[TSEC_RX_NUM_DESC]; 75 76 uint32_t tx_cur_desc_cnt; 77 uint32_t tx_dirty_desc_cnt; 78 uint32_t rx_cur_desc_cnt; 79 80 struct resource *sc_rres; /* register resource */ 81 int sc_rrid; /* register rid */ 82 struct { 83 bus_space_tag_t bst; 84 bus_space_handle_t bsh; 85 } sc_bas; 86 87 struct resource *sc_transmit_ires; 88 void *sc_transmit_ihand; 89 int sc_transmit_irid; 90 struct resource *sc_receive_ires; 91 void *sc_receive_ihand; 92 int sc_receive_irid; 93 struct resource *sc_error_ires; 94 void *sc_error_ihand; 95 int sc_error_irid; 96 97 int tsec_if_flags; 98 int is_etsec; 99 100 /* Watchdog and MII tick related */ 101 struct callout tsec_callout; 102 int tsec_watchdog; 103 104 /* TX maps */ 105 bus_dmamap_t tx_map_data[TSEC_TX_NUM_DESC]; 106 107 /* unused TX maps data */ 108 uint32_t tx_map_unused_get_cnt; 109 uint32_t tx_map_unused_put_cnt; 110 bus_dmamap_t *tx_map_unused_data[TSEC_TX_NUM_DESC]; 111 112 /* used TX maps data */ 113 uint32_t tx_map_used_get_cnt; 114 uint32_t tx_map_used_put_cnt; 115 bus_dmamap_t *tx_map_used_data[TSEC_TX_NUM_DESC]; 116 117 /* mbufs in TX queue */ 118 uint32_t tx_mbuf_used_get_cnt; 119 uint32_t tx_mbuf_used_put_cnt; 120 struct mbuf *tx_mbuf_used_data[TSEC_TX_NUM_DESC]; 121 122 /* interrupt coalescing */ 123 struct mtx ic_lock; 124 uint32_t rx_ic_time; /* RW, valid values 0..65535 */ 125 uint32_t rx_ic_count; /* RW, valid values 0..255 */ 126 uint32_t tx_ic_time; 127 uint32_t tx_ic_count; 128 129 /* currently received frame */ 130 struct mbuf *frame; 131 }; 132 133 /* interface to get/put generic objects */ 134 #define TSEC_CNT_INIT(cnt, wrap) ((cnt) = ((wrap) - 1)) 135 136 #define TSEC_INC(count, wrap) (count = ((count) + 1) & ((wrap) - 1)) 137 138 #define TSEC_GET_GENERIC(hand, tab, count, wrap) \ 139 ((hand)->tab[TSEC_INC((hand)->count, wrap)]) 140 141 #define TSEC_PUT_GENERIC(hand, tab, count, wrap, val) \ 142 ((hand)->tab[TSEC_INC((hand)->count, wrap)] = val) 143 144 #define TSEC_BACK_GENERIC(sc, count, wrap) do { \ 145 if ((sc)->count > 0) \ 146 (sc)->count--; \ 147 else \ 148 (sc)->count = (wrap) - 1; \ 149 } while (0) 150 151 /* TX maps interface */ 152 #define TSEC_TX_MAP_CNT_INIT(sc) do { \ 153 TSEC_CNT_INIT((sc)->tx_map_unused_get_cnt, TSEC_TX_NUM_DESC); \ 154 TSEC_CNT_INIT((sc)->tx_map_unused_put_cnt, TSEC_TX_NUM_DESC); \ 155 TSEC_CNT_INIT((sc)->tx_map_used_get_cnt, TSEC_TX_NUM_DESC); \ 156 TSEC_CNT_INIT((sc)->tx_map_used_put_cnt, TSEC_TX_NUM_DESC); \ 157 } while (0) 158 159 /* interface to get/put unused TX maps */ 160 #define TSEC_ALLOC_TX_MAP(sc) \ 161 TSEC_GET_GENERIC(sc, tx_map_unused_data, tx_map_unused_get_cnt, \ 162 TSEC_TX_NUM_DESC) 163 164 #define TSEC_FREE_TX_MAP(sc, val) \ 165 TSEC_PUT_GENERIC(sc, tx_map_unused_data, tx_map_unused_put_cnt, \ 166 TSEC_TX_NUM_DESC, val) 167 168 /* interface to get/put used TX maps */ 169 #define TSEC_GET_TX_MAP(sc) \ 170 TSEC_GET_GENERIC(sc, tx_map_used_data, tx_map_used_get_cnt, \ 171 TSEC_TX_NUM_DESC) 172 173 #define TSEC_PUT_TX_MAP(sc, val) \ 174 TSEC_PUT_GENERIC(sc, tx_map_used_data, tx_map_used_put_cnt, \ 175 TSEC_TX_NUM_DESC, val) 176 177 /* interface to get/put TX mbufs in send queue */ 178 #define TSEC_TX_MBUF_CNT_INIT(sc) do { \ 179 TSEC_CNT_INIT((sc)->tx_mbuf_used_get_cnt, TSEC_TX_NUM_DESC); \ 180 TSEC_CNT_INIT((sc)->tx_mbuf_used_put_cnt, TSEC_TX_NUM_DESC); \ 181 } while (0) 182 183 #define TSEC_GET_TX_MBUF(sc) \ 184 TSEC_GET_GENERIC(sc, tx_mbuf_used_data, tx_mbuf_used_get_cnt, \ 185 TSEC_TX_NUM_DESC) 186 187 #define TSEC_PUT_TX_MBUF(sc, val) \ 188 TSEC_PUT_GENERIC(sc, tx_mbuf_used_data, tx_mbuf_used_put_cnt, \ 189 TSEC_TX_NUM_DESC, val) 190 191 #define TSEC_EMPTYQ_TX_MBUF(sc) \ 192 ((sc)->tx_mbuf_used_get_cnt == (sc)->tx_mbuf_used_put_cnt) 193 194 /* interface for manage tx tsec_desc */ 195 #define TSEC_TX_DESC_CNT_INIT(sc) do { \ 196 TSEC_CNT_INIT((sc)->tx_cur_desc_cnt, TSEC_TX_NUM_DESC); \ 197 TSEC_CNT_INIT((sc)->tx_dirty_desc_cnt, TSEC_TX_NUM_DESC); \ 198 } while (0) 199 200 #define TSEC_GET_CUR_TX_DESC(sc) \ 201 &TSEC_GET_GENERIC(sc, tsec_tx_vaddr, tx_cur_desc_cnt, \ 202 TSEC_TX_NUM_DESC) 203 204 #define TSEC_GET_DIRTY_TX_DESC(sc) \ 205 &TSEC_GET_GENERIC(sc, tsec_tx_vaddr, tx_dirty_desc_cnt, \ 206 TSEC_TX_NUM_DESC) 207 208 #define TSEC_BACK_DIRTY_TX_DESC(sc) \ 209 TSEC_BACK_GENERIC(sc, tx_dirty_desc_cnt, TSEC_TX_NUM_DESC) 210 211 #define TSEC_CUR_DIFF_DIRTY_TX_DESC(sc) \ 212 ((sc)->tx_cur_desc_cnt != (sc)->tx_dirty_desc_cnt) 213 214 #define TSEC_FREE_TX_DESC(sc) \ 215 (((sc)->tx_cur_desc_cnt < (sc)->tx_dirty_desc_cnt) ? \ 216 ((sc)->tx_dirty_desc_cnt - (sc)->tx_cur_desc_cnt - 1) \ 217 : \ 218 (TSEC_TX_NUM_DESC - (sc)->tx_cur_desc_cnt \ 219 + (sc)->tx_dirty_desc_cnt - 1)) 220 221 /* interface for manage rx tsec_desc */ 222 #define TSEC_RX_DESC_CNT_INIT(sc) do { \ 223 TSEC_CNT_INIT((sc)->rx_cur_desc_cnt, TSEC_RX_NUM_DESC); \ 224 } while (0) 225 226 #define TSEC_GET_CUR_RX_DESC(sc) \ 227 &TSEC_GET_GENERIC(sc, tsec_rx_vaddr, rx_cur_desc_cnt, \ 228 TSEC_RX_NUM_DESC) 229 230 #define TSEC_BACK_CUR_RX_DESC(sc) \ 231 TSEC_BACK_GENERIC(sc, rx_cur_desc_cnt, TSEC_RX_NUM_DESC) 232 233 #define TSEC_GET_CUR_RX_DESC_CNT(sc) \ 234 ((sc)->rx_cur_desc_cnt) 235 236 /* init all counters (for init only!) */ 237 #define TSEC_TX_RX_COUNTERS_INIT(sc) do { \ 238 TSEC_TX_MAP_CNT_INIT(sc); \ 239 TSEC_TX_MBUF_CNT_INIT(sc); \ 240 TSEC_TX_DESC_CNT_INIT(sc); \ 241 TSEC_RX_DESC_CNT_INIT(sc); \ 242 } while (0) 243 244 /* read/write bus functions */ 245 #define TSEC_READ(sc, reg) \ 246 bus_space_read_4((sc)->sc_bas.bst, (sc)->sc_bas.bsh, (reg)) 247 #define TSEC_WRITE(sc, reg, val) \ 248 bus_space_write_4((sc)->sc_bas.bst, (sc)->sc_bas.bsh, (reg), (val)) 249 250 /* Lock for transmitter */ 251 #define TSEC_TRANSMIT_LOCK(sc) do { \ 252 mtx_assert(&(sc)->receive_lock, MA_NOTOWNED); \ 253 mtx_lock(&(sc)->transmit_lock); \ 254 } while (0) 255 256 #define TSEC_TRANSMIT_UNLOCK(sc) mtx_unlock(&(sc)->transmit_lock) 257 #define TSEC_TRANSMIT_LOCK_ASSERT(sc) mtx_assert(&(sc)->transmit_lock, MA_OWNED) 258 259 /* Lock for receiver */ 260 #define TSEC_RECEIVE_LOCK(sc) do { \ 261 mtx_assert(&(sc)->transmit_lock, MA_NOTOWNED); \ 262 mtx_lock(&(sc)->receive_lock); \ 263 } while (0) 264 265 #define TSEC_RECEIVE_UNLOCK(sc) mtx_unlock(&(sc)->receive_lock) 266 #define TSEC_RECEIVE_LOCK_ASSERT(sc) mtx_assert(&(sc)->receive_lock, MA_OWNED) 267 268 /* Lock for interrupts coalescing */ 269 #define TSEC_IC_LOCK(sc) do { \ 270 mtx_assert(&(sc)->ic_lock, MA_NOTOWNED); \ 271 mtx_lock(&(sc)->ic_lock); \ 272 } while (0) 273 274 #define TSEC_IC_UNLOCK(sc) mtx_unlock(&(sc)->ic_lock) 275 #define TSEC_IC_LOCK_ASSERT(sc) mtx_assert(&(sc)->ic_lock, MA_OWNED) 276 277 /* Global tsec lock (with all locks) */ 278 #define TSEC_GLOBAL_LOCK(sc) do { \ 279 if ((mtx_owned(&(sc)->transmit_lock) ? 1 : 0) != \ 280 (mtx_owned(&(sc)->receive_lock) ? 1 : 0)) { \ 281 panic("tsec deadlock possibility detection!"); \ 282 } \ 283 mtx_lock(&(sc)->transmit_lock); \ 284 mtx_lock(&(sc)->receive_lock); \ 285 } while (0) 286 287 #define TSEC_GLOBAL_UNLOCK(sc) do { \ 288 TSEC_RECEIVE_UNLOCK(sc); \ 289 TSEC_TRANSMIT_UNLOCK(sc); \ 290 } while (0) 291 292 #define TSEC_GLOBAL_LOCK_ASSERT(sc) do { \ 293 TSEC_TRANSMIT_LOCK_ASSERT(sc); \ 294 TSEC_RECEIVE_LOCK_ASSERT(sc); \ 295 } while (0) 296 297 /* From global to {transmit,receive} */ 298 #define TSEC_GLOBAL_TO_TRANSMIT_LOCK(sc) do { \ 299 mtx_unlock(&(sc)->receive_lock);\ 300 } while (0) 301 302 #define TSEC_GLOBAL_TO_RECEIVE_LOCK(sc) do { \ 303 mtx_unlock(&(sc)->transmit_lock);\ 304 } while (0) 305 306 struct tsec_desc { 307 volatile uint16_t flags; /* descriptor flags */ 308 volatile uint16_t length; /* buffer length */ 309 volatile uint32_t bufptr; /* buffer pointer */ 310 }; 311 312 #define TSEC_READ_RETRY 10000 313 #define TSEC_READ_DELAY 100 314 315 /* Structures and defines for TCP/IP Off-load */ 316 struct tsec_tx_fcb { 317 volatile uint16_t flags; 318 volatile uint8_t l4_offset; 319 volatile uint8_t l3_offset; 320 volatile uint16_t ph_chsum; 321 volatile uint16_t vlan; 322 }; 323 324 struct tsec_rx_fcb { 325 volatile uint16_t flags; 326 volatile uint8_t rq_index; 327 volatile uint8_t protocol; 328 volatile uint16_t unused; 329 volatile uint16_t vlan; 330 }; 331 332 #define TSEC_CHECKSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 333 334 #define TSEC_TX_FCB_IP4 TSEC_TX_FCB_L3_IS_IP 335 #define TSEC_TX_FCB_IP6 (TSEC_TX_FCB_L3_IS_IP | TSEC_TX_FCB_L3_IS_IP6) 336 337 #define TSEC_TX_FCB_TCP TSEC_TX_FCB_L4_IS_TCP_UDP 338 #define TSEC_TX_FCB_UDP (TSEC_TX_FCB_L4_IS_TCP_UDP | TSEC_TX_FCB_L4_IS_UDP) 339 340 #define TSEC_RX_FCB_IP_CSUM_CHECKED(flags) \ 341 ((flags & (TSEC_RX_FCB_IP_FOUND | TSEC_RX_FCB_IP6_FOUND | \ 342 TSEC_RX_FCB_IP_CSUM | TSEC_RX_FCB_PARSE_ERROR)) \ 343 == (TSEC_RX_FCB_IP_FOUND | TSEC_RX_FCB_IP_CSUM)) 344 345 #define TSEC_RX_FCB_TCP_UDP_CSUM_CHECKED(flags) \ 346 ((flags & (TSEC_RX_FCB_TCP_UDP_FOUND | TSEC_RX_FCB_TCP_UDP_CSUM \ 347 | TSEC_RX_FCB_PARSE_ERROR)) \ 348 == (TSEC_RX_FCB_TCP_UDP_FOUND | TSEC_RX_FCB_TCP_UDP_CSUM)) 349 350 /* Prototypes */ 351 extern devclass_t tsec_devclass; 352 353 int tsec_attach(struct tsec_softc *sc); 354 int tsec_detach(struct tsec_softc *sc); 355 356 void tsec_error_intr(void *arg); 357 void tsec_receive_intr(void *arg); 358 void tsec_transmit_intr(void *arg); 359 360 int tsec_miibus_readreg(device_t dev, int phy, int reg); 361 void tsec_miibus_writereg(device_t dev, int phy, int reg, int value); 362 void tsec_miibus_statchg(device_t dev); 363 int tsec_resume(device_t dev); /* XXX */ 364 void tsec_shutdown(device_t dev); 365 int tsec_suspend(device_t dev); /* XXX */ 366 367 void tsec_get_hwaddr(struct tsec_softc *sc, uint8_t *addr); 368 369 #endif /* _IF_TSEC_H */ 370