1098ca2bdSWarner Losh /*-
24d846d26SWarner Losh * SPDX-License-Identifier: BSD-2-Clause
3718cf2ccSPedro F. Giffuni *
427d5dc18SMarcel Moolenaar * Copyright (c) 2003 Marcel Moolenaar
527d5dc18SMarcel Moolenaar * All rights reserved.
627d5dc18SMarcel Moolenaar *
727d5dc18SMarcel Moolenaar * Redistribution and use in source and binary forms, with or without
827d5dc18SMarcel Moolenaar * modification, are permitted provided that the following conditions
927d5dc18SMarcel Moolenaar * are met:
1027d5dc18SMarcel Moolenaar *
1127d5dc18SMarcel Moolenaar * 1. Redistributions of source code must retain the above copyright
1227d5dc18SMarcel Moolenaar * notice, this list of conditions and the following disclaimer.
1327d5dc18SMarcel Moolenaar * 2. Redistributions in binary form must reproduce the above copyright
1427d5dc18SMarcel Moolenaar * notice, this list of conditions and the following disclaimer in the
1527d5dc18SMarcel Moolenaar * documentation and/or other materials provided with the distribution.
1627d5dc18SMarcel Moolenaar *
1727d5dc18SMarcel Moolenaar * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
1827d5dc18SMarcel Moolenaar * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
1927d5dc18SMarcel Moolenaar * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
2027d5dc18SMarcel Moolenaar * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
2127d5dc18SMarcel Moolenaar * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
2227d5dc18SMarcel Moolenaar * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
2327d5dc18SMarcel Moolenaar * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
2427d5dc18SMarcel Moolenaar * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
2527d5dc18SMarcel Moolenaar * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
2627d5dc18SMarcel Moolenaar * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2727d5dc18SMarcel Moolenaar */
2827d5dc18SMarcel Moolenaar
29381388b9SMatt Macy #include "opt_acpi.h"
30ac4adddfSGanbold Tsagaankhuu #include "opt_platform.h"
31e0fe7c95SAdrian Chadd #include "opt_uart.h"
32ac4adddfSGanbold Tsagaankhuu
3327d5dc18SMarcel Moolenaar #include <sys/param.h>
3427d5dc18SMarcel Moolenaar #include <sys/systm.h>
3527d5dc18SMarcel Moolenaar #include <sys/bus.h>
3627d5dc18SMarcel Moolenaar #include <sys/conf.h>
371c60b24bSColin Percival #include <sys/kernel.h>
381c60b24bSColin Percival #include <sys/sysctl.h>
3927d5dc18SMarcel Moolenaar #include <machine/bus.h>
4027d5dc18SMarcel Moolenaar
41ac4adddfSGanbold Tsagaankhuu #ifdef FDT
42ac4adddfSGanbold Tsagaankhuu #include <dev/fdt/fdt_common.h>
43ac4adddfSGanbold Tsagaankhuu #include <dev/ofw/ofw_bus.h>
44ac4adddfSGanbold Tsagaankhuu #include <dev/ofw/ofw_bus_subr.h>
45ac4adddfSGanbold Tsagaankhuu #endif
46ac4adddfSGanbold Tsagaankhuu
4727d5dc18SMarcel Moolenaar #include <dev/uart/uart.h>
4827d5dc18SMarcel Moolenaar #include <dev/uart/uart_cpu.h>
493bb693afSIan Lepore #ifdef FDT
503bb693afSIan Lepore #include <dev/uart/uart_cpu_fdt.h>
513bb693afSIan Lepore #endif
5227d5dc18SMarcel Moolenaar #include <dev/uart/uart_bus.h>
53167cb33fSIan Lepore #include <dev/uart/uart_dev_ns8250.h>
54fdfbb3f5SIan Lepore #include <dev/uart/uart_ppstypes.h>
55381388b9SMatt Macy #ifdef DEV_ACPI
56381388b9SMatt Macy #include <dev/uart/uart_cpu_acpi.h>
579cf66a04SMarcin Wojtas #include <contrib/dev/acpica/include/acpi.h>
58381388b9SMatt Macy #endif
5976563beaSMarcel Moolenaar
6076563beaSMarcel Moolenaar #include <dev/ic/ns16550.h>
6127d5dc18SMarcel Moolenaar
6227d5dc18SMarcel Moolenaar #include "uart_if.h"
6327d5dc18SMarcel Moolenaar
6427d5dc18SMarcel Moolenaar #define DEFAULT_RCLK 1843200
6527d5dc18SMarcel Moolenaar
66e0fe7c95SAdrian Chadd /*
67e0fe7c95SAdrian Chadd * Set the default baudrate tolerance to 3.0%.
68e0fe7c95SAdrian Chadd *
69e0fe7c95SAdrian Chadd * Some embedded boards have odd reference clocks (eg 25MHz)
70e0fe7c95SAdrian Chadd * and we need to handle higher variances in the target baud rate.
71e0fe7c95SAdrian Chadd */
72e0fe7c95SAdrian Chadd #ifndef UART_DEV_TOLERANCE_PCT
73e0fe7c95SAdrian Chadd #define UART_DEV_TOLERANCE_PCT 30
74e0fe7c95SAdrian Chadd #endif /* UART_DEV_TOLERANCE_PCT */
75e0fe7c95SAdrian Chadd
76ac4adddfSGanbold Tsagaankhuu static int broken_txfifo = 0;
77af3b2549SHans Petter Selasky SYSCTL_INT(_hw, OID_AUTO, broken_txfifo, CTLFLAG_RWTUN,
78ac4adddfSGanbold Tsagaankhuu &broken_txfifo, 0, "UART FIFO has QEMU emulation bug");
79ac4adddfSGanbold Tsagaankhuu
8027d5dc18SMarcel Moolenaar /*
81a113f9ddSWarner Losh * To use early printf on x86, add the following to your kernel config:
82a113f9ddSWarner Losh *
83a113f9ddSWarner Losh * options UART_NS8250_EARLY_PORT=0x3f8
8420289092SAndrew Turner * options EARLY_PRINTF=ns8250
85a113f9ddSWarner Losh */
8620289092SAndrew Turner #if CHECK_EARLY_PRINTF(ns8250)
8720289092SAndrew Turner #if !(defined(__amd64__) || defined(__i386__))
8820289092SAndrew Turner #error ns8250 early putc is x86 specific as it uses inb/outb
8920289092SAndrew Turner #endif
90a113f9ddSWarner Losh static void
uart_ns8250_early_putc(int c)91a113f9ddSWarner Losh uart_ns8250_early_putc(int c)
92a113f9ddSWarner Losh {
93a113f9ddSWarner Losh u_int stat = UART_NS8250_EARLY_PORT + REG_LSR;
94a113f9ddSWarner Losh u_int tx = UART_NS8250_EARLY_PORT + REG_DATA;
95a113f9ddSWarner Losh int limit = 10000; /* 10ms is plenty of time */
96a113f9ddSWarner Losh
97a113f9ddSWarner Losh while ((inb(stat) & LSR_THRE) == 0 && --limit > 0)
98a113f9ddSWarner Losh continue;
99a113f9ddSWarner Losh outb(tx, c);
100a113f9ddSWarner Losh }
101a113f9ddSWarner Losh early_putc_t *early_putc = uart_ns8250_early_putc;
102a113f9ddSWarner Losh #endif /* EARLY_PRINTF */
103a113f9ddSWarner Losh
104a113f9ddSWarner Losh /*
10527d5dc18SMarcel Moolenaar * Clear pending interrupts. THRE is cleared by reading IIR. Data
10627d5dc18SMarcel Moolenaar * that may have been received gets lost here.
10727d5dc18SMarcel Moolenaar */
10827d5dc18SMarcel Moolenaar static void
ns8250_clrint(struct uart_bas * bas)10927d5dc18SMarcel Moolenaar ns8250_clrint(struct uart_bas *bas)
11027d5dc18SMarcel Moolenaar {
111d7ae5af5SMarcel Moolenaar uint8_t iir, lsr;
11227d5dc18SMarcel Moolenaar
11327d5dc18SMarcel Moolenaar iir = uart_getreg(bas, REG_IIR);
11427d5dc18SMarcel Moolenaar while ((iir & IIR_NOPEND) == 0) {
11527d5dc18SMarcel Moolenaar iir &= IIR_IMASK;
116d7ae5af5SMarcel Moolenaar if (iir == IIR_RLS) {
117d7ae5af5SMarcel Moolenaar lsr = uart_getreg(bas, REG_LSR);
118d7ae5af5SMarcel Moolenaar if (lsr & (LSR_BI|LSR_FE|LSR_PE))
119d7ae5af5SMarcel Moolenaar (void)uart_getreg(bas, REG_DATA);
120d7ae5af5SMarcel Moolenaar } else if (iir == IIR_RXRDY || iir == IIR_RXTOUT)
12127d5dc18SMarcel Moolenaar (void)uart_getreg(bas, REG_DATA);
12227d5dc18SMarcel Moolenaar else if (iir == IIR_MLSC)
12327d5dc18SMarcel Moolenaar (void)uart_getreg(bas, REG_MSR);
12427d5dc18SMarcel Moolenaar uart_barrier(bas);
12527d5dc18SMarcel Moolenaar iir = uart_getreg(bas, REG_IIR);
12627d5dc18SMarcel Moolenaar }
12727d5dc18SMarcel Moolenaar }
12827d5dc18SMarcel Moolenaar
12927d5dc18SMarcel Moolenaar static int
ns8250_delay(struct uart_bas * bas)13027d5dc18SMarcel Moolenaar ns8250_delay(struct uart_bas *bas)
13127d5dc18SMarcel Moolenaar {
13227d5dc18SMarcel Moolenaar int divisor;
13327d5dc18SMarcel Moolenaar u_char lcr;
13427d5dc18SMarcel Moolenaar
13527d5dc18SMarcel Moolenaar lcr = uart_getreg(bas, REG_LCR);
13627d5dc18SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
13727d5dc18SMarcel Moolenaar uart_barrier(bas);
13858957d87SBenno Rice divisor = uart_getreg(bas, REG_DLL) | (uart_getreg(bas, REG_DLH) << 8);
13927d5dc18SMarcel Moolenaar uart_barrier(bas);
14027d5dc18SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr);
14127d5dc18SMarcel Moolenaar uart_barrier(bas);
14227d5dc18SMarcel Moolenaar
14327d5dc18SMarcel Moolenaar /* 1/10th the time to transmit 1 character (estimate). */
144ebecffe9SMarcel Moolenaar if (divisor <= 134)
14527d5dc18SMarcel Moolenaar return (16000000 * divisor / bas->rclk);
146ebecffe9SMarcel Moolenaar return (16000 * divisor / (bas->rclk / 1000));
14727d5dc18SMarcel Moolenaar }
14827d5dc18SMarcel Moolenaar
14927d5dc18SMarcel Moolenaar static int
ns8250_divisor(int rclk,int baudrate)15027d5dc18SMarcel Moolenaar ns8250_divisor(int rclk, int baudrate)
15127d5dc18SMarcel Moolenaar {
15227d5dc18SMarcel Moolenaar int actual_baud, divisor;
15327d5dc18SMarcel Moolenaar int error;
15427d5dc18SMarcel Moolenaar
15527d5dc18SMarcel Moolenaar if (baudrate == 0)
15627d5dc18SMarcel Moolenaar return (0);
15727d5dc18SMarcel Moolenaar
15827d5dc18SMarcel Moolenaar divisor = (rclk / (baudrate << 3) + 1) >> 1;
15927d5dc18SMarcel Moolenaar if (divisor == 0 || divisor >= 65536)
16027d5dc18SMarcel Moolenaar return (0);
16127d5dc18SMarcel Moolenaar actual_baud = rclk / (divisor << 4);
16227d5dc18SMarcel Moolenaar
16327d5dc18SMarcel Moolenaar /* 10 times error in percent: */
164b47c1edaSJohn Baldwin error = ((actual_baud - baudrate) * 2000 / baudrate + 1) / 2;
16527d5dc18SMarcel Moolenaar
166e0fe7c95SAdrian Chadd /* enforce maximum error tolerance: */
167e0fe7c95SAdrian Chadd if (error < -UART_DEV_TOLERANCE_PCT || error > UART_DEV_TOLERANCE_PCT)
16827d5dc18SMarcel Moolenaar return (0);
16927d5dc18SMarcel Moolenaar
17027d5dc18SMarcel Moolenaar return (divisor);
17127d5dc18SMarcel Moolenaar }
17227d5dc18SMarcel Moolenaar
17327d5dc18SMarcel Moolenaar static int
ns8250_drain(struct uart_bas * bas,int what)17427d5dc18SMarcel Moolenaar ns8250_drain(struct uart_bas *bas, int what)
17527d5dc18SMarcel Moolenaar {
17627d5dc18SMarcel Moolenaar int delay, limit;
17727d5dc18SMarcel Moolenaar
17827d5dc18SMarcel Moolenaar delay = ns8250_delay(bas);
17927d5dc18SMarcel Moolenaar
18027d5dc18SMarcel Moolenaar if (what & UART_DRAIN_TRANSMITTER) {
18127d5dc18SMarcel Moolenaar /*
18227d5dc18SMarcel Moolenaar * Pick an arbitrary high limit to avoid getting stuck in
18327d5dc18SMarcel Moolenaar * an infinite loop when the hardware is broken. Make the
18427d5dc18SMarcel Moolenaar * limit high enough to handle large FIFOs.
18527d5dc18SMarcel Moolenaar */
18627d5dc18SMarcel Moolenaar limit = 10*1024;
18727d5dc18SMarcel Moolenaar while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit)
18827d5dc18SMarcel Moolenaar DELAY(delay);
18927d5dc18SMarcel Moolenaar if (limit == 0) {
19027d5dc18SMarcel Moolenaar /* printf("ns8250: transmitter appears stuck... "); */
19127d5dc18SMarcel Moolenaar return (EIO);
19227d5dc18SMarcel Moolenaar }
19327d5dc18SMarcel Moolenaar }
19427d5dc18SMarcel Moolenaar
19527d5dc18SMarcel Moolenaar if (what & UART_DRAIN_RECEIVER) {
19627d5dc18SMarcel Moolenaar /*
19727d5dc18SMarcel Moolenaar * Pick an arbitrary high limit to avoid getting stuck in
19827d5dc18SMarcel Moolenaar * an infinite loop when the hardware is broken. Make the
19927d5dc18SMarcel Moolenaar * limit high enough to handle large FIFOs and integrated
20027d5dc18SMarcel Moolenaar * UARTs. The HP rx2600 for example has 3 UARTs on the
20127d5dc18SMarcel Moolenaar * management board that tend to get a lot of data send
20239d6144dSColin Percival * to it when the UART is first activated. Assume that we
20339d6144dSColin Percival * have finished draining if LSR_RXRDY is not asserted both
20439d6144dSColin Percival * prior to and after a DELAY; but as long as LSR_RXRDY is
20539d6144dSColin Percival * asserted, read (and discard) characters as quickly as
20639d6144dSColin Percival * possible.
20727d5dc18SMarcel Moolenaar */
20827d5dc18SMarcel Moolenaar limit=10*4096;
20939d6144dSColin Percival while (limit && (uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) {
21039d6144dSColin Percival do {
21127d5dc18SMarcel Moolenaar (void)uart_getreg(bas, REG_DATA);
21227d5dc18SMarcel Moolenaar uart_barrier(bas);
21339d6144dSColin Percival } while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit);
21439d6144dSColin Percival uart_barrier(bas);
21527d5dc18SMarcel Moolenaar DELAY(delay << 2);
21627d5dc18SMarcel Moolenaar }
21727d5dc18SMarcel Moolenaar if (limit == 0) {
21827d5dc18SMarcel Moolenaar /* printf("ns8250: receiver appears broken... "); */
21927d5dc18SMarcel Moolenaar return (EIO);
22027d5dc18SMarcel Moolenaar }
22127d5dc18SMarcel Moolenaar }
22227d5dc18SMarcel Moolenaar
22327d5dc18SMarcel Moolenaar return (0);
22427d5dc18SMarcel Moolenaar }
22527d5dc18SMarcel Moolenaar
22627d5dc18SMarcel Moolenaar /*
22727d5dc18SMarcel Moolenaar * We can only flush UARTs with FIFOs. UARTs without FIFOs should be
22827d5dc18SMarcel Moolenaar * drained. WARNING: this function clobbers the FIFO setting!
22927d5dc18SMarcel Moolenaar */
23027d5dc18SMarcel Moolenaar static void
ns8250_flush(struct uart_bas * bas,int what)23127d5dc18SMarcel Moolenaar ns8250_flush(struct uart_bas *bas, int what)
23227d5dc18SMarcel Moolenaar {
23327d5dc18SMarcel Moolenaar uint8_t fcr;
234c4b68e7eSColin Percival uint8_t lsr;
235c4b68e7eSColin Percival int drain = 0;
23627d5dc18SMarcel Moolenaar
23727d5dc18SMarcel Moolenaar fcr = FCR_ENABLE;
23827d5dc18SMarcel Moolenaar if (what & UART_FLUSH_TRANSMITTER)
23927d5dc18SMarcel Moolenaar fcr |= FCR_XMT_RST;
24027d5dc18SMarcel Moolenaar if (what & UART_FLUSH_RECEIVER)
24127d5dc18SMarcel Moolenaar fcr |= FCR_RCV_RST;
24227d5dc18SMarcel Moolenaar uart_setreg(bas, REG_FCR, fcr);
24327d5dc18SMarcel Moolenaar uart_barrier(bas);
244c4b68e7eSColin Percival
245c4b68e7eSColin Percival /*
246c4b68e7eSColin Percival * Detect and work around emulated UARTs which don't implement the
247c4b68e7eSColin Percival * FCR register; on these systems we need to drain the FIFO since
248c4b68e7eSColin Percival * the flush we request doesn't happen. One such system is the
249c4b68e7eSColin Percival * Firecracker VMM, aka. the rust-vmm/vm-superio emulation code:
250c4b68e7eSColin Percival * https://github.com/rust-vmm/vm-superio/issues/83
251c4b68e7eSColin Percival */
252c4b68e7eSColin Percival lsr = uart_getreg(bas, REG_LSR);
2535ad8c32cSColin Percival if (((lsr & LSR_TEMT) == 0) && (what & UART_FLUSH_TRANSMITTER))
254c4b68e7eSColin Percival drain |= UART_DRAIN_TRANSMITTER;
255c4b68e7eSColin Percival if ((lsr & LSR_RXRDY) && (what & UART_FLUSH_RECEIVER))
256c4b68e7eSColin Percival drain |= UART_DRAIN_RECEIVER;
257c4b68e7eSColin Percival if (drain != 0) {
258c4b68e7eSColin Percival printf("ns8250: UART FCR is broken\n");
259c4b68e7eSColin Percival ns8250_drain(bas, drain);
260c4b68e7eSColin Percival }
26127d5dc18SMarcel Moolenaar }
26227d5dc18SMarcel Moolenaar
26327d5dc18SMarcel Moolenaar static int
ns8250_param(struct uart_bas * bas,int baudrate,int databits,int stopbits,int parity)26427d5dc18SMarcel Moolenaar ns8250_param(struct uart_bas *bas, int baudrate, int databits, int stopbits,
26527d5dc18SMarcel Moolenaar int parity)
26627d5dc18SMarcel Moolenaar {
26727d5dc18SMarcel Moolenaar int divisor;
26827d5dc18SMarcel Moolenaar uint8_t lcr;
26927d5dc18SMarcel Moolenaar
2708ea7fa16SWei Hu /* Don't change settings when running on Hyper-V */
2718ea7fa16SWei Hu if (vm_guest == VM_GUEST_HV)
2728ea7fa16SWei Hu return (0);
2738ea7fa16SWei Hu
27427d5dc18SMarcel Moolenaar lcr = 0;
27527d5dc18SMarcel Moolenaar if (databits >= 8)
27627d5dc18SMarcel Moolenaar lcr |= LCR_8BITS;
27727d5dc18SMarcel Moolenaar else if (databits == 7)
27827d5dc18SMarcel Moolenaar lcr |= LCR_7BITS;
27927d5dc18SMarcel Moolenaar else if (databits == 6)
28027d5dc18SMarcel Moolenaar lcr |= LCR_6BITS;
28127d5dc18SMarcel Moolenaar else
28227d5dc18SMarcel Moolenaar lcr |= LCR_5BITS;
28327d5dc18SMarcel Moolenaar if (stopbits > 1)
28427d5dc18SMarcel Moolenaar lcr |= LCR_STOPB;
28527d5dc18SMarcel Moolenaar lcr |= parity << 3;
28627d5dc18SMarcel Moolenaar
28727d5dc18SMarcel Moolenaar /* Set baudrate. */
28827d5dc18SMarcel Moolenaar if (baudrate > 0) {
28927d5dc18SMarcel Moolenaar divisor = ns8250_divisor(bas->rclk, baudrate);
29027d5dc18SMarcel Moolenaar if (divisor == 0)
29127d5dc18SMarcel Moolenaar return (EINVAL);
29263f8efd3SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
29363f8efd3SMarcel Moolenaar uart_barrier(bas);
29458957d87SBenno Rice uart_setreg(bas, REG_DLL, divisor & 0xff);
29558957d87SBenno Rice uart_setreg(bas, REG_DLH, (divisor >> 8) & 0xff);
29627d5dc18SMarcel Moolenaar uart_barrier(bas);
29727d5dc18SMarcel Moolenaar }
29827d5dc18SMarcel Moolenaar
29927d5dc18SMarcel Moolenaar /* Set LCR and clear DLAB. */
30027d5dc18SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr);
30127d5dc18SMarcel Moolenaar uart_barrier(bas);
30227d5dc18SMarcel Moolenaar return (0);
30327d5dc18SMarcel Moolenaar }
30427d5dc18SMarcel Moolenaar
30527d5dc18SMarcel Moolenaar /*
30627d5dc18SMarcel Moolenaar * Low-level UART interface.
30727d5dc18SMarcel Moolenaar */
30827d5dc18SMarcel Moolenaar static int ns8250_probe(struct uart_bas *bas);
30927d5dc18SMarcel Moolenaar static void ns8250_init(struct uart_bas *bas, int, int, int, int);
31027d5dc18SMarcel Moolenaar static void ns8250_term(struct uart_bas *bas);
31127d5dc18SMarcel Moolenaar static void ns8250_putc(struct uart_bas *bas, int);
31297202af2SMarius Strobl static int ns8250_rxready(struct uart_bas *bas);
313634e63c9SMarcel Moolenaar static int ns8250_getc(struct uart_bas *bas, struct mtx *);
31427d5dc18SMarcel Moolenaar
315167cb33fSIan Lepore struct uart_ops uart_ns8250_ops = {
31627d5dc18SMarcel Moolenaar .probe = ns8250_probe,
31727d5dc18SMarcel Moolenaar .init = ns8250_init,
31827d5dc18SMarcel Moolenaar .term = ns8250_term,
31927d5dc18SMarcel Moolenaar .putc = ns8250_putc,
32097202af2SMarius Strobl .rxready = ns8250_rxready,
32127d5dc18SMarcel Moolenaar .getc = ns8250_getc,
32227d5dc18SMarcel Moolenaar };
32327d5dc18SMarcel Moolenaar
32427d5dc18SMarcel Moolenaar static int
ns8250_probe(struct uart_bas * bas)32527d5dc18SMarcel Moolenaar ns8250_probe(struct uart_bas *bas)
32627d5dc18SMarcel Moolenaar {
3278bceca4fSBenno Rice u_char val;
32827d5dc18SMarcel Moolenaar
32927d5dc18SMarcel Moolenaar /* Check known 0 bits that don't depend on DLAB. */
33027d5dc18SMarcel Moolenaar val = uart_getreg(bas, REG_IIR);
33127d5dc18SMarcel Moolenaar if (val & 0x30)
33227d5dc18SMarcel Moolenaar return (ENXIO);
3335bdddc29SMarcel Moolenaar /*
3345bdddc29SMarcel Moolenaar * Bit 6 of the MCR (= 0x40) appears to be 1 for the Sun1699
3355bdddc29SMarcel Moolenaar * chip, but otherwise doesn't seem to have a function. In
3365bdddc29SMarcel Moolenaar * other words, uart(4) works regardless. Ignore that bit so
3375bdddc29SMarcel Moolenaar * the probe succeeds.
3385bdddc29SMarcel Moolenaar */
33927d5dc18SMarcel Moolenaar val = uart_getreg(bas, REG_MCR);
3405bdddc29SMarcel Moolenaar if (val & 0xa0)
34127d5dc18SMarcel Moolenaar return (ENXIO);
34227d5dc18SMarcel Moolenaar
34327d5dc18SMarcel Moolenaar return (0);
34427d5dc18SMarcel Moolenaar }
34527d5dc18SMarcel Moolenaar
34627d5dc18SMarcel Moolenaar static void
ns8250_init(struct uart_bas * bas,int baudrate,int databits,int stopbits,int parity)34727d5dc18SMarcel Moolenaar ns8250_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
34827d5dc18SMarcel Moolenaar int parity)
34927d5dc18SMarcel Moolenaar {
350f25b0d6dSOskar Holmlund u_char ier;
35127d5dc18SMarcel Moolenaar
35227d5dc18SMarcel Moolenaar if (bas->rclk == 0)
35327d5dc18SMarcel Moolenaar bas->rclk = DEFAULT_RCLK;
35427d5dc18SMarcel Moolenaar ns8250_param(bas, baudrate, databits, stopbits, parity);
35527d5dc18SMarcel Moolenaar
35627d5dc18SMarcel Moolenaar /* Disable all interrupt sources. */
3570aefb0a6SBenno Rice /*
3580aefb0a6SBenno Rice * We use 0xe0 instead of 0xf0 as the mask because the XScale PXA
3590aefb0a6SBenno Rice * UARTs split the receive time-out interrupt bit out separately as
3600aefb0a6SBenno Rice * 0x10. This gets handled by ier_mask and ier_rxbits below.
3610aefb0a6SBenno Rice */
3620aefb0a6SBenno Rice ier = uart_getreg(bas, REG_IER) & 0xe0;
36358957d87SBenno Rice uart_setreg(bas, REG_IER, ier);
36427d5dc18SMarcel Moolenaar uart_barrier(bas);
36527d5dc18SMarcel Moolenaar
36627d5dc18SMarcel Moolenaar /* Disable the FIFO (if present). */
367f25b0d6dSOskar Holmlund uart_setreg(bas, REG_FCR, 0);
36827d5dc18SMarcel Moolenaar uart_barrier(bas);
36927d5dc18SMarcel Moolenaar
37027d5dc18SMarcel Moolenaar /* Set RTS & DTR. */
37127d5dc18SMarcel Moolenaar uart_setreg(bas, REG_MCR, MCR_IE | MCR_RTS | MCR_DTR);
37227d5dc18SMarcel Moolenaar uart_barrier(bas);
37327d5dc18SMarcel Moolenaar
37427d5dc18SMarcel Moolenaar ns8250_clrint(bas);
37527d5dc18SMarcel Moolenaar }
37627d5dc18SMarcel Moolenaar
37727d5dc18SMarcel Moolenaar static void
ns8250_term(struct uart_bas * bas)37827d5dc18SMarcel Moolenaar ns8250_term(struct uart_bas *bas)
37927d5dc18SMarcel Moolenaar {
38027d5dc18SMarcel Moolenaar
38127d5dc18SMarcel Moolenaar /* Clear RTS & DTR. */
38227d5dc18SMarcel Moolenaar uart_setreg(bas, REG_MCR, MCR_IE);
38327d5dc18SMarcel Moolenaar uart_barrier(bas);
38427d5dc18SMarcel Moolenaar }
38527d5dc18SMarcel Moolenaar
38627d5dc18SMarcel Moolenaar static void
ns8250_putc(struct uart_bas * bas,int c)38727d5dc18SMarcel Moolenaar ns8250_putc(struct uart_bas *bas, int c)
38827d5dc18SMarcel Moolenaar {
38935777a2aSMarcel Moolenaar int limit;
39027d5dc18SMarcel Moolenaar
3918ea7fa16SWei Hu if (vm_guest != VM_GUEST_HV) {
39235777a2aSMarcel Moolenaar limit = 250000;
39327d5dc18SMarcel Moolenaar while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0 && --limit)
39435777a2aSMarcel Moolenaar DELAY(4);
3958ea7fa16SWei Hu }
39627d5dc18SMarcel Moolenaar uart_setreg(bas, REG_DATA, c);
3974e55f723SMarcel Moolenaar uart_barrier(bas);
39827d5dc18SMarcel Moolenaar }
39927d5dc18SMarcel Moolenaar
40027d5dc18SMarcel Moolenaar static int
ns8250_rxready(struct uart_bas * bas)40197202af2SMarius Strobl ns8250_rxready(struct uart_bas *bas)
40227d5dc18SMarcel Moolenaar {
40327d5dc18SMarcel Moolenaar
40497202af2SMarius Strobl return ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) != 0 ? 1 : 0);
40527d5dc18SMarcel Moolenaar }
40627d5dc18SMarcel Moolenaar
40727d5dc18SMarcel Moolenaar static int
ns8250_getc(struct uart_bas * bas,struct mtx * hwmtx)408634e63c9SMarcel Moolenaar ns8250_getc(struct uart_bas *bas, struct mtx *hwmtx)
40927d5dc18SMarcel Moolenaar {
41035777a2aSMarcel Moolenaar int c;
411634e63c9SMarcel Moolenaar
412634e63c9SMarcel Moolenaar uart_lock(hwmtx);
41327d5dc18SMarcel Moolenaar
414634e63c9SMarcel Moolenaar while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0) {
415634e63c9SMarcel Moolenaar uart_unlock(hwmtx);
41635777a2aSMarcel Moolenaar DELAY(4);
417634e63c9SMarcel Moolenaar uart_lock(hwmtx);
418634e63c9SMarcel Moolenaar }
419634e63c9SMarcel Moolenaar
420634e63c9SMarcel Moolenaar c = uart_getreg(bas, REG_DATA);
421634e63c9SMarcel Moolenaar
422634e63c9SMarcel Moolenaar uart_unlock(hwmtx);
423634e63c9SMarcel Moolenaar
424634e63c9SMarcel Moolenaar return (c);
42527d5dc18SMarcel Moolenaar }
42627d5dc18SMarcel Moolenaar
42727d5dc18SMarcel Moolenaar static kobj_method_t ns8250_methods[] = {
42827d5dc18SMarcel Moolenaar KOBJMETHOD(uart_attach, ns8250_bus_attach),
42927d5dc18SMarcel Moolenaar KOBJMETHOD(uart_detach, ns8250_bus_detach),
43027d5dc18SMarcel Moolenaar KOBJMETHOD(uart_flush, ns8250_bus_flush),
43127d5dc18SMarcel Moolenaar KOBJMETHOD(uart_getsig, ns8250_bus_getsig),
43227d5dc18SMarcel Moolenaar KOBJMETHOD(uart_ioctl, ns8250_bus_ioctl),
43327d5dc18SMarcel Moolenaar KOBJMETHOD(uart_ipend, ns8250_bus_ipend),
43427d5dc18SMarcel Moolenaar KOBJMETHOD(uart_param, ns8250_bus_param),
43527d5dc18SMarcel Moolenaar KOBJMETHOD(uart_probe, ns8250_bus_probe),
43627d5dc18SMarcel Moolenaar KOBJMETHOD(uart_receive, ns8250_bus_receive),
43727d5dc18SMarcel Moolenaar KOBJMETHOD(uart_setsig, ns8250_bus_setsig),
43827d5dc18SMarcel Moolenaar KOBJMETHOD(uart_transmit, ns8250_bus_transmit),
439353e4c5aSMarius Strobl KOBJMETHOD(uart_txbusy, ns8250_bus_txbusy),
440d76a1ef4SWarner Losh KOBJMETHOD(uart_grab, ns8250_bus_grab),
441d76a1ef4SWarner Losh KOBJMETHOD(uart_ungrab, ns8250_bus_ungrab),
442353e4c5aSMarius Strobl KOBJMETHOD_END
44327d5dc18SMarcel Moolenaar };
44427d5dc18SMarcel Moolenaar
44527d5dc18SMarcel Moolenaar struct uart_class uart_ns8250_class = {
446f8100ce2SMarcel Moolenaar "ns8250",
44727d5dc18SMarcel Moolenaar ns8250_methods,
44827d5dc18SMarcel Moolenaar sizeof(struct ns8250_softc),
449f8100ce2SMarcel Moolenaar .uc_ops = &uart_ns8250_ops,
45027d5dc18SMarcel Moolenaar .uc_range = 8,
451405ada37SAndrew Turner .uc_rclk = DEFAULT_RCLK,
452405ada37SAndrew Turner .uc_rshift = 0
45327d5dc18SMarcel Moolenaar };
45446a968ecSBjoern A. Zeeb UART_CLASS(uart_ns8250_class);
45527d5dc18SMarcel Moolenaar
456381388b9SMatt Macy /*
457381388b9SMatt Macy * XXX -- refactor out ACPI and FDT ifdefs
458381388b9SMatt Macy */
459381388b9SMatt Macy #ifdef DEV_ACPI
460381388b9SMatt Macy static struct acpi_uart_compat_data acpi_compat_data[] = {
461381388b9SMatt Macy {"AMD0020", &uart_ns8250_class, 0, 2, 0, 48000000, UART_F_BUSY_DETECT, "AMD / Synopsys Designware UART"},
462381388b9SMatt Macy {"AMDI0020", &uart_ns8250_class, 0, 2, 0, 48000000, UART_F_BUSY_DETECT, "AMD / Synopsys Designware UART"},
4639cf66a04SMarcin Wojtas {"MRVL0001", &uart_ns8250_class, ACPI_DBG2_16550_SUBSET, 2, 0, 200000000, UART_F_BUSY_DETECT, "Marvell / Synopsys Designware UART"},
464a852cb95SRebecca Cran {"SCX0006", &uart_ns8250_class, 0, 2, 0, 62500000, UART_F_BUSY_DETECT, "SynQuacer / Synopsys Designware UART"},
465a852cb95SRebecca Cran {"HISI0031", &uart_ns8250_class, 0, 2, 0, 200000000, UART_F_BUSY_DETECT, "HiSilicon / Synopsys Designware UART"},
4667cb73f65SMateusz Kozyra {"NXP0018", &uart_ns8250_class, 0, 0, 0, 350000000, UART_F_BUSY_DETECT, "NXP / Synopsys Designware UART"},
467381388b9SMatt Macy {"PNP0500", &uart_ns8250_class, 0, 0, 0, 0, 0, "Standard PC COM port"},
468381388b9SMatt Macy {"PNP0501", &uart_ns8250_class, 0, 0, 0, 0, 0, "16550A-compatible COM port"},
469381388b9SMatt Macy {"PNP0502", &uart_ns8250_class, 0, 0, 0, 0, 0, "Multiport serial device (non-intelligent 16550)"},
470381388b9SMatt Macy {"PNP0510", &uart_ns8250_class, 0, 0, 0, 0, 0, "Generic IRDA-compatible device"},
471381388b9SMatt Macy {"PNP0511", &uart_ns8250_class, 0, 0, 0, 0, 0, "Generic IRDA-compatible device"},
472381388b9SMatt Macy {"WACF004", &uart_ns8250_class, 0, 0, 0, 0, 0, "Wacom Tablet PC Screen"},
473381388b9SMatt Macy {"WACF00E", &uart_ns8250_class, 0, 0, 0, 0, 0, "Wacom Tablet PC Screen 00e"},
474381388b9SMatt Macy {"FUJ02E5", &uart_ns8250_class, 0, 0, 0, 0, 0, "Wacom Tablet at FuS Lifebook T"},
475381388b9SMatt Macy {NULL, NULL, 0, 0 , 0, 0, 0, NULL},
476381388b9SMatt Macy };
477381388b9SMatt Macy UART_ACPI_CLASS_AND_DEVICE(acpi_compat_data);
478381388b9SMatt Macy #endif
479381388b9SMatt Macy
4803bb693afSIan Lepore #ifdef FDT
4813bb693afSIan Lepore static struct ofw_compat_data compat_data[] = {
4823bb693afSIan Lepore {"ns16550", (uintptr_t)&uart_ns8250_class},
4833b654e08SWojciech Macek {"ns16550a", (uintptr_t)&uart_ns8250_class},
4843bb693afSIan Lepore {NULL, (uintptr_t)NULL},
4853bb693afSIan Lepore };
4863bb693afSIan Lepore UART_FDT_CLASS_AND_DEVICE(compat_data);
4873bb693afSIan Lepore #endif
4883bb693afSIan Lepore
489fdfbb3f5SIan Lepore /* Use token-pasting to form SER_ and MSR_ named constants. */
490fdfbb3f5SIan Lepore #define SER(sig) SER_##sig
491fdfbb3f5SIan Lepore #define SERD(sig) SER_D##sig
492fdfbb3f5SIan Lepore #define MSR(sig) MSR_##sig
493fdfbb3f5SIan Lepore #define MSRD(sig) MSR_D##sig
494fdfbb3f5SIan Lepore
495fdfbb3f5SIan Lepore /*
496fdfbb3f5SIan Lepore * Detect signal changes using software delta detection. The previous state of
497fdfbb3f5SIan Lepore * the signals is in 'var' the new hardware state is in 'msr', and 'sig' is the
498fdfbb3f5SIan Lepore * short name (DCD, CTS, etc) of the signal bit being processed; 'var' gets the
499fdfbb3f5SIan Lepore * new state of both the signal and the delta bits.
500fdfbb3f5SIan Lepore */
501fdfbb3f5SIan Lepore #define SIGCHGSW(var, msr, sig) \
502fdfbb3f5SIan Lepore if ((msr) & MSR(sig)) { \
503fdfbb3f5SIan Lepore if ((var & SER(sig)) == 0) \
504fdfbb3f5SIan Lepore var |= SERD(sig) | SER(sig); \
50527d5dc18SMarcel Moolenaar } else { \
506fdfbb3f5SIan Lepore if ((var & SER(sig)) != 0) \
507fdfbb3f5SIan Lepore var = SERD(sig) | (var & ~SER(sig)); \
508fdfbb3f5SIan Lepore }
509fdfbb3f5SIan Lepore
510fdfbb3f5SIan Lepore /*
511fdfbb3f5SIan Lepore * Detect signal changes using the hardware msr delta bits. This is currently
512fdfbb3f5SIan Lepore * used only when PPS timing information is being captured using the "narrow
513fdfbb3f5SIan Lepore * pulse" option. With a narrow PPS pulse the signal may not still be asserted
514fdfbb3f5SIan Lepore * by time the interrupt handler is invoked. The hardware will latch the fact
515fdfbb3f5SIan Lepore * that it changed in the delta bits.
516fdfbb3f5SIan Lepore */
517fdfbb3f5SIan Lepore #define SIGCHGHW(var, msr, sig) \
518fdfbb3f5SIan Lepore if ((msr) & MSRD(sig)) { \
519fdfbb3f5SIan Lepore if (((msr) & MSR(sig)) != 0) \
520fdfbb3f5SIan Lepore var |= SERD(sig) | SER(sig); \
521fdfbb3f5SIan Lepore else \
522fdfbb3f5SIan Lepore var = SERD(sig) | (var & ~SER(sig)); \
52327d5dc18SMarcel Moolenaar }
52427d5dc18SMarcel Moolenaar
525167cb33fSIan Lepore int
ns8250_bus_attach(struct uart_softc * sc)52627d5dc18SMarcel Moolenaar ns8250_bus_attach(struct uart_softc *sc)
52727d5dc18SMarcel Moolenaar {
52827d5dc18SMarcel Moolenaar struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
52927d5dc18SMarcel Moolenaar struct uart_bas *bas;
530823c77d7SSam Leffler unsigned int ivar;
531ac4adddfSGanbold Tsagaankhuu #ifdef FDT
532ac4adddfSGanbold Tsagaankhuu phandle_t node;
533ac4adddfSGanbold Tsagaankhuu pcell_t cell;
534ac4adddfSGanbold Tsagaankhuu #endif
535ac4adddfSGanbold Tsagaankhuu
536ac4adddfSGanbold Tsagaankhuu #ifdef FDT
537b738dafdSJared McNeill /* Check whether uart has a broken txfifo. */
538ac4adddfSGanbold Tsagaankhuu node = ofw_bus_get_node(sc->sc_dev);
539b1621f22SLuiz Otavio O Souza if ((OF_getencprop(node, "broken-txfifo", &cell, sizeof(cell))) > 0)
540b1621f22SLuiz Otavio O Souza broken_txfifo = cell ? 1 : 0;
541ac4adddfSGanbold Tsagaankhuu #endif
54227d5dc18SMarcel Moolenaar
54327d5dc18SMarcel Moolenaar bas = &sc->sc_bas;
54427d5dc18SMarcel Moolenaar
545f30f0f2bSMatt Macy ns8250->busy_detect = bas->busy_detect;
54627d5dc18SMarcel Moolenaar ns8250->mcr = uart_getreg(bas, REG_MCR);
547823c77d7SSam Leffler ns8250->fcr = FCR_ENABLE;
548823c77d7SSam Leffler if (!resource_int_value("uart", device_get_unit(sc->sc_dev), "flags",
549823c77d7SSam Leffler &ivar)) {
550823c77d7SSam Leffler if (UART_FLAGS_FCR_RX_LOW(ivar))
551823c77d7SSam Leffler ns8250->fcr |= FCR_RX_LOW;
552823c77d7SSam Leffler else if (UART_FLAGS_FCR_RX_MEDL(ivar))
553823c77d7SSam Leffler ns8250->fcr |= FCR_RX_MEDL;
554823c77d7SSam Leffler else if (UART_FLAGS_FCR_RX_HIGH(ivar))
555823c77d7SSam Leffler ns8250->fcr |= FCR_RX_HIGH;
556823c77d7SSam Leffler else
557823c77d7SSam Leffler ns8250->fcr |= FCR_RX_MEDH;
558823c77d7SSam Leffler } else
559823c77d7SSam Leffler ns8250->fcr |= FCR_RX_MEDH;
5600aefb0a6SBenno Rice
5610aefb0a6SBenno Rice /* Get IER mask */
5620aefb0a6SBenno Rice ivar = 0xf0;
5630aefb0a6SBenno Rice resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_mask",
5640aefb0a6SBenno Rice &ivar);
5650aefb0a6SBenno Rice ns8250->ier_mask = (uint8_t)(ivar & 0xff);
5660aefb0a6SBenno Rice
5670aefb0a6SBenno Rice /* Get IER RX interrupt bits */
5680aefb0a6SBenno Rice ivar = IER_EMSC | IER_ERLS | IER_ERXRDY;
5690aefb0a6SBenno Rice resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_rxbits",
5700aefb0a6SBenno Rice &ivar);
5710aefb0a6SBenno Rice ns8250->ier_rxbits = (uint8_t)(ivar & 0xff);
5720aefb0a6SBenno Rice
57327d5dc18SMarcel Moolenaar uart_setreg(bas, REG_FCR, ns8250->fcr);
57427d5dc18SMarcel Moolenaar uart_barrier(bas);
57527d5dc18SMarcel Moolenaar ns8250_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER);
57627d5dc18SMarcel Moolenaar
57727d5dc18SMarcel Moolenaar if (ns8250->mcr & MCR_DTR)
57828710806SPoul-Henning Kamp sc->sc_hwsig |= SER_DTR;
57927d5dc18SMarcel Moolenaar if (ns8250->mcr & MCR_RTS)
58028710806SPoul-Henning Kamp sc->sc_hwsig |= SER_RTS;
58127d5dc18SMarcel Moolenaar ns8250_bus_getsig(sc);
58227d5dc18SMarcel Moolenaar
58327d5dc18SMarcel Moolenaar ns8250_clrint(bas);
5840aefb0a6SBenno Rice ns8250->ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask;
5850aefb0a6SBenno Rice ns8250->ier |= ns8250->ier_rxbits;
58627d5dc18SMarcel Moolenaar uart_setreg(bas, REG_IER, ns8250->ier);
58727d5dc18SMarcel Moolenaar uart_barrier(bas);
5880aefb0a6SBenno Rice
5894fc49975SMarcel Moolenaar /*
5904fc49975SMarcel Moolenaar * Timing of the H/W access was changed with r253161 of uart_core.c
5914fc49975SMarcel Moolenaar * It has been observed that an ITE IT8513E would signal a break
5924fc49975SMarcel Moolenaar * condition with pretty much every character it received, unless
5934fc49975SMarcel Moolenaar * it had enough time to settle between ns8250_bus_attach() and
5944fc49975SMarcel Moolenaar * ns8250_bus_ipend() -- which it accidentally had before r253161.
5954fc49975SMarcel Moolenaar * It's not understood why the UART chip behaves this way and it
5964fc49975SMarcel Moolenaar * could very well be that the DELAY make the H/W work in the same
5974fc49975SMarcel Moolenaar * accidental manner as before. More analysis is warranted, but
5984fc49975SMarcel Moolenaar * at least now we fixed a known regression.
5994fc49975SMarcel Moolenaar */
60040a827b6SMarcel Moolenaar DELAY(200);
60127d5dc18SMarcel Moolenaar return (0);
60227d5dc18SMarcel Moolenaar }
60327d5dc18SMarcel Moolenaar
604167cb33fSIan Lepore int
ns8250_bus_detach(struct uart_softc * sc)60527d5dc18SMarcel Moolenaar ns8250_bus_detach(struct uart_softc *sc)
60627d5dc18SMarcel Moolenaar {
6070aefb0a6SBenno Rice struct ns8250_softc *ns8250;
60827d5dc18SMarcel Moolenaar struct uart_bas *bas;
60958957d87SBenno Rice u_char ier;
61027d5dc18SMarcel Moolenaar
6110aefb0a6SBenno Rice ns8250 = (struct ns8250_softc *)sc;
61227d5dc18SMarcel Moolenaar bas = &sc->sc_bas;
6130aefb0a6SBenno Rice ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask;
61458957d87SBenno Rice uart_setreg(bas, REG_IER, ier);
61527d5dc18SMarcel Moolenaar uart_barrier(bas);
61627d5dc18SMarcel Moolenaar ns8250_clrint(bas);
61727d5dc18SMarcel Moolenaar return (0);
61827d5dc18SMarcel Moolenaar }
61927d5dc18SMarcel Moolenaar
620167cb33fSIan Lepore int
ns8250_bus_flush(struct uart_softc * sc,int what)62127d5dc18SMarcel Moolenaar ns8250_bus_flush(struct uart_softc *sc, int what)
62227d5dc18SMarcel Moolenaar {
62327d5dc18SMarcel Moolenaar struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
62427d5dc18SMarcel Moolenaar struct uart_bas *bas;
62506287620SMarcel Moolenaar int error;
62627d5dc18SMarcel Moolenaar
62727d5dc18SMarcel Moolenaar bas = &sc->sc_bas;
6288af03381SMarcel Moolenaar uart_lock(sc->sc_hwmtx);
6298d1289feSMarcel Moolenaar if (sc->sc_rxfifosz > 1) {
63027d5dc18SMarcel Moolenaar ns8250_flush(bas, what);
63127d5dc18SMarcel Moolenaar uart_setreg(bas, REG_FCR, ns8250->fcr);
63227d5dc18SMarcel Moolenaar uart_barrier(bas);
63306287620SMarcel Moolenaar error = 0;
63406287620SMarcel Moolenaar } else
63506287620SMarcel Moolenaar error = ns8250_drain(bas, what);
6368af03381SMarcel Moolenaar uart_unlock(sc->sc_hwmtx);
63706287620SMarcel Moolenaar return (error);
63827d5dc18SMarcel Moolenaar }
63927d5dc18SMarcel Moolenaar
640167cb33fSIan Lepore int
ns8250_bus_getsig(struct uart_softc * sc)64127d5dc18SMarcel Moolenaar ns8250_bus_getsig(struct uart_softc *sc)
64227d5dc18SMarcel Moolenaar {
643fdfbb3f5SIan Lepore uint32_t old, sig;
64427d5dc18SMarcel Moolenaar uint8_t msr;
64527d5dc18SMarcel Moolenaar
646fdfbb3f5SIan Lepore /*
647fdfbb3f5SIan Lepore * The delta bits are reputed to be broken on some hardware, so use
648fdfbb3f5SIan Lepore * software delta detection by default. Use the hardware delta bits
649fdfbb3f5SIan Lepore * when capturing PPS pulses which are too narrow for software detection
650fdfbb3f5SIan Lepore * to see the edges. Hardware delta for RI doesn't work like the
651fdfbb3f5SIan Lepore * others, so always use software for it. Other threads may be changing
652453130d9SPedro F. Giffuni * other (non-MSR) bits in sc_hwsig, so loop until it can successfully
653fdfbb3f5SIan Lepore * update without other changes happening. Note that the SIGCHGxx()
654fdfbb3f5SIan Lepore * macros carefully preserve the delta bits when we have to loop several
655fdfbb3f5SIan Lepore * times and a signal transitions between iterations.
656fdfbb3f5SIan Lepore */
65727d5dc18SMarcel Moolenaar do {
65827d5dc18SMarcel Moolenaar old = sc->sc_hwsig;
65927d5dc18SMarcel Moolenaar sig = old;
6608af03381SMarcel Moolenaar uart_lock(sc->sc_hwmtx);
66127d5dc18SMarcel Moolenaar msr = uart_getreg(&sc->sc_bas, REG_MSR);
6628af03381SMarcel Moolenaar uart_unlock(sc->sc_hwmtx);
663fdfbb3f5SIan Lepore if (sc->sc_pps_mode & UART_PPS_NARROW_PULSE) {
664fdfbb3f5SIan Lepore SIGCHGHW(sig, msr, DSR);
665fdfbb3f5SIan Lepore SIGCHGHW(sig, msr, CTS);
666fdfbb3f5SIan Lepore SIGCHGHW(sig, msr, DCD);
667fdfbb3f5SIan Lepore } else {
668fdfbb3f5SIan Lepore SIGCHGSW(sig, msr, DSR);
669fdfbb3f5SIan Lepore SIGCHGSW(sig, msr, CTS);
670fdfbb3f5SIan Lepore SIGCHGSW(sig, msr, DCD);
671fdfbb3f5SIan Lepore }
672fdfbb3f5SIan Lepore SIGCHGSW(sig, msr, RI);
673fdfbb3f5SIan Lepore } while (!atomic_cmpset_32(&sc->sc_hwsig, old, sig & ~SER_MASK_DELTA));
67427d5dc18SMarcel Moolenaar return (sig);
67527d5dc18SMarcel Moolenaar }
67627d5dc18SMarcel Moolenaar
677167cb33fSIan Lepore int
ns8250_bus_ioctl(struct uart_softc * sc,int request,intptr_t data)67827d5dc18SMarcel Moolenaar ns8250_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
67927d5dc18SMarcel Moolenaar {
68027d5dc18SMarcel Moolenaar struct uart_bas *bas;
681bfa307a3SMarcel Moolenaar int baudrate, divisor, error;
68284c7b427SMarcel Moolenaar uint8_t efr, lcr;
68327d5dc18SMarcel Moolenaar
68427d5dc18SMarcel Moolenaar bas = &sc->sc_bas;
68506287620SMarcel Moolenaar error = 0;
6868af03381SMarcel Moolenaar uart_lock(sc->sc_hwmtx);
68727d5dc18SMarcel Moolenaar switch (request) {
68827d5dc18SMarcel Moolenaar case UART_IOCTL_BREAK:
68927d5dc18SMarcel Moolenaar lcr = uart_getreg(bas, REG_LCR);
69027d5dc18SMarcel Moolenaar if (data)
69127d5dc18SMarcel Moolenaar lcr |= LCR_SBREAK;
69227d5dc18SMarcel Moolenaar else
69327d5dc18SMarcel Moolenaar lcr &= ~LCR_SBREAK;
69427d5dc18SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr);
69527d5dc18SMarcel Moolenaar uart_barrier(bas);
69627d5dc18SMarcel Moolenaar break;
69784c7b427SMarcel Moolenaar case UART_IOCTL_IFLOW:
69884c7b427SMarcel Moolenaar lcr = uart_getreg(bas, REG_LCR);
69984c7b427SMarcel Moolenaar uart_barrier(bas);
70084c7b427SMarcel Moolenaar uart_setreg(bas, REG_LCR, 0xbf);
70184c7b427SMarcel Moolenaar uart_barrier(bas);
70284c7b427SMarcel Moolenaar efr = uart_getreg(bas, REG_EFR);
70384c7b427SMarcel Moolenaar if (data)
70484c7b427SMarcel Moolenaar efr |= EFR_RTS;
70584c7b427SMarcel Moolenaar else
70684c7b427SMarcel Moolenaar efr &= ~EFR_RTS;
70784c7b427SMarcel Moolenaar uart_setreg(bas, REG_EFR, efr);
70884c7b427SMarcel Moolenaar uart_barrier(bas);
70984c7b427SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr);
71084c7b427SMarcel Moolenaar uart_barrier(bas);
71184c7b427SMarcel Moolenaar break;
71284c7b427SMarcel Moolenaar case UART_IOCTL_OFLOW:
71384c7b427SMarcel Moolenaar lcr = uart_getreg(bas, REG_LCR);
71484c7b427SMarcel Moolenaar uart_barrier(bas);
71584c7b427SMarcel Moolenaar uart_setreg(bas, REG_LCR, 0xbf);
71684c7b427SMarcel Moolenaar uart_barrier(bas);
71784c7b427SMarcel Moolenaar efr = uart_getreg(bas, REG_EFR);
71884c7b427SMarcel Moolenaar if (data)
71984c7b427SMarcel Moolenaar efr |= EFR_CTS;
72084c7b427SMarcel Moolenaar else
72184c7b427SMarcel Moolenaar efr &= ~EFR_CTS;
72284c7b427SMarcel Moolenaar uart_setreg(bas, REG_EFR, efr);
72384c7b427SMarcel Moolenaar uart_barrier(bas);
72484c7b427SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr);
72584c7b427SMarcel Moolenaar uart_barrier(bas);
72684c7b427SMarcel Moolenaar break;
727d8518925SMarcel Moolenaar case UART_IOCTL_BAUD:
728d8518925SMarcel Moolenaar lcr = uart_getreg(bas, REG_LCR);
729d8518925SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
730d8518925SMarcel Moolenaar uart_barrier(bas);
73158957d87SBenno Rice divisor = uart_getreg(bas, REG_DLL) |
73258957d87SBenno Rice (uart_getreg(bas, REG_DLH) << 8);
733d8518925SMarcel Moolenaar uart_barrier(bas);
734d8518925SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr);
735d8518925SMarcel Moolenaar uart_barrier(bas);
736bfa307a3SMarcel Moolenaar baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0;
737bfa307a3SMarcel Moolenaar if (baudrate > 0)
738bfa307a3SMarcel Moolenaar *(int*)data = baudrate;
739bfa307a3SMarcel Moolenaar else
740bfa307a3SMarcel Moolenaar error = ENXIO;
741d8518925SMarcel Moolenaar break;
74227d5dc18SMarcel Moolenaar default:
74306287620SMarcel Moolenaar error = EINVAL;
74406287620SMarcel Moolenaar break;
74527d5dc18SMarcel Moolenaar }
7468af03381SMarcel Moolenaar uart_unlock(sc->sc_hwmtx);
74706287620SMarcel Moolenaar return (error);
74827d5dc18SMarcel Moolenaar }
74927d5dc18SMarcel Moolenaar
750167cb33fSIan Lepore int
ns8250_bus_ipend(struct uart_softc * sc)75127d5dc18SMarcel Moolenaar ns8250_bus_ipend(struct uart_softc *sc)
75227d5dc18SMarcel Moolenaar {
75327d5dc18SMarcel Moolenaar struct uart_bas *bas;
75411e55f91SOlivier Houchard struct ns8250_softc *ns8250;
75527d5dc18SMarcel Moolenaar int ipend;
75627d5dc18SMarcel Moolenaar uint8_t iir, lsr;
75727d5dc18SMarcel Moolenaar
75811e55f91SOlivier Houchard ns8250 = (struct ns8250_softc *)sc;
75927d5dc18SMarcel Moolenaar bas = &sc->sc_bas;
7608af03381SMarcel Moolenaar uart_lock(sc->sc_hwmtx);
76127d5dc18SMarcel Moolenaar iir = uart_getreg(bas, REG_IIR);
762ac4adddfSGanbold Tsagaankhuu
763ac4adddfSGanbold Tsagaankhuu if (ns8250->busy_detect && (iir & IIR_BUSY) == IIR_BUSY) {
764ac4adddfSGanbold Tsagaankhuu (void)uart_getreg(bas, DW_REG_USR);
765ac4adddfSGanbold Tsagaankhuu uart_unlock(sc->sc_hwmtx);
766ac4adddfSGanbold Tsagaankhuu return (0);
767ac4adddfSGanbold Tsagaankhuu }
76806287620SMarcel Moolenaar if (iir & IIR_NOPEND) {
7698af03381SMarcel Moolenaar uart_unlock(sc->sc_hwmtx);
77027d5dc18SMarcel Moolenaar return (0);
77106287620SMarcel Moolenaar }
77227d5dc18SMarcel Moolenaar ipend = 0;
77327d5dc18SMarcel Moolenaar if (iir & IIR_RXRDY) {
77427d5dc18SMarcel Moolenaar lsr = uart_getreg(bas, REG_LSR);
77527d5dc18SMarcel Moolenaar if (lsr & LSR_OE)
7762d511805SMarcel Moolenaar ipend |= SER_INT_OVERRUN;
77727d5dc18SMarcel Moolenaar if (lsr & LSR_BI)
7782d511805SMarcel Moolenaar ipend |= SER_INT_BREAK;
77927d5dc18SMarcel Moolenaar if (lsr & LSR_RXRDY)
7802d511805SMarcel Moolenaar ipend |= SER_INT_RXREADY;
78127d5dc18SMarcel Moolenaar } else {
78211e55f91SOlivier Houchard if (iir & IIR_TXRDY) {
7832d511805SMarcel Moolenaar ipend |= SER_INT_TXIDLE;
7847e7f7beeSMitchell Horne ns8250->ier &= ~IER_ETXRDY;
78511e55f91SOlivier Houchard uart_setreg(bas, REG_IER, ns8250->ier);
7863c7b9077SMichal Meloun uart_barrier(bas);
78711e55f91SOlivier Houchard } else
7882d511805SMarcel Moolenaar ipend |= SER_INT_SIGCHG;
78927d5dc18SMarcel Moolenaar }
790d7ae5af5SMarcel Moolenaar if (ipend == 0)
791d7ae5af5SMarcel Moolenaar ns8250_clrint(bas);
792d7ae5af5SMarcel Moolenaar uart_unlock(sc->sc_hwmtx);
793f6ffc3c2SMarius Strobl return (ipend);
79427d5dc18SMarcel Moolenaar }
79527d5dc18SMarcel Moolenaar
796167cb33fSIan Lepore int
ns8250_bus_param(struct uart_softc * sc,int baudrate,int databits,int stopbits,int parity)79727d5dc18SMarcel Moolenaar ns8250_bus_param(struct uart_softc *sc, int baudrate, int databits,
79827d5dc18SMarcel Moolenaar int stopbits, int parity)
79927d5dc18SMarcel Moolenaar {
80049e368acSZbigniew Bodek struct ns8250_softc *ns8250;
80127d5dc18SMarcel Moolenaar struct uart_bas *bas;
80249e368acSZbigniew Bodek int error, limit;
80327d5dc18SMarcel Moolenaar
80449e368acSZbigniew Bodek ns8250 = (struct ns8250_softc*)sc;
80527d5dc18SMarcel Moolenaar bas = &sc->sc_bas;
8068af03381SMarcel Moolenaar uart_lock(sc->sc_hwmtx);
80749e368acSZbigniew Bodek /*
80849e368acSZbigniew Bodek * When using DW UART with BUSY detection it is necessary to wait
80949e368acSZbigniew Bodek * until all serial transfers are finished before manipulating the
81049e368acSZbigniew Bodek * line control. LCR will not be affected when UART is busy.
81149e368acSZbigniew Bodek */
81249e368acSZbigniew Bodek if (ns8250->busy_detect != 0) {
81349e368acSZbigniew Bodek /*
81449e368acSZbigniew Bodek * Pick an arbitrary high limit to avoid getting stuck in
81549e368acSZbigniew Bodek * an infinite loop in case when the hardware is broken.
81649e368acSZbigniew Bodek */
81749e368acSZbigniew Bodek limit = 10 * 1024;
81849e368acSZbigniew Bodek while (((uart_getreg(bas, DW_REG_USR) & USR_BUSY) != 0) &&
81949e368acSZbigniew Bodek --limit)
82049e368acSZbigniew Bodek DELAY(4);
82149e368acSZbigniew Bodek
82249e368acSZbigniew Bodek if (limit <= 0) {
82349e368acSZbigniew Bodek /* UART appears to be stuck */
82449e368acSZbigniew Bodek uart_unlock(sc->sc_hwmtx);
82549e368acSZbigniew Bodek return (EIO);
82649e368acSZbigniew Bodek }
82749e368acSZbigniew Bodek }
82849e368acSZbigniew Bodek
82906287620SMarcel Moolenaar error = ns8250_param(bas, baudrate, databits, stopbits, parity);
8308af03381SMarcel Moolenaar uart_unlock(sc->sc_hwmtx);
83106287620SMarcel Moolenaar return (error);
83227d5dc18SMarcel Moolenaar }
83327d5dc18SMarcel Moolenaar
834167cb33fSIan Lepore int
ns8250_bus_probe(struct uart_softc * sc)83527d5dc18SMarcel Moolenaar ns8250_bus_probe(struct uart_softc *sc)
83627d5dc18SMarcel Moolenaar {
83727d5dc18SMarcel Moolenaar struct uart_bas *bas;
83827d5dc18SMarcel Moolenaar int count, delay, error, limit;
83958957d87SBenno Rice uint8_t lsr, mcr, ier;
84027d5dc18SMarcel Moolenaar
84127d5dc18SMarcel Moolenaar bas = &sc->sc_bas;
84227d5dc18SMarcel Moolenaar
84327d5dc18SMarcel Moolenaar error = ns8250_probe(bas);
84427d5dc18SMarcel Moolenaar if (error)
84527d5dc18SMarcel Moolenaar return (error);
84627d5dc18SMarcel Moolenaar
84727d5dc18SMarcel Moolenaar mcr = MCR_IE;
84827d5dc18SMarcel Moolenaar if (sc->sc_sysdev == NULL) {
84927d5dc18SMarcel Moolenaar /* By using ns8250_init() we also set DTR and RTS. */
850d902fb71SMarcel Moolenaar ns8250_init(bas, 115200, 8, 1, UART_PARITY_NONE);
85127d5dc18SMarcel Moolenaar } else
85227d5dc18SMarcel Moolenaar mcr |= MCR_DTR | MCR_RTS;
85327d5dc18SMarcel Moolenaar
85427d5dc18SMarcel Moolenaar error = ns8250_drain(bas, UART_DRAIN_TRANSMITTER);
85527d5dc18SMarcel Moolenaar if (error)
85627d5dc18SMarcel Moolenaar return (error);
85727d5dc18SMarcel Moolenaar
85827d5dc18SMarcel Moolenaar /*
85927d5dc18SMarcel Moolenaar * Set loopback mode. This avoids having garbage on the wire and
86027d5dc18SMarcel Moolenaar * also allows us send and receive data. We set DTR and RTS to
86127d5dc18SMarcel Moolenaar * avoid the possibility that automatic flow-control prevents
86289eef2deSThomas Moestl * any data from being sent.
86327d5dc18SMarcel Moolenaar */
86489eef2deSThomas Moestl uart_setreg(bas, REG_MCR, MCR_LOOPBACK | MCR_IE | MCR_DTR | MCR_RTS);
86527d5dc18SMarcel Moolenaar uart_barrier(bas);
86627d5dc18SMarcel Moolenaar
86727d5dc18SMarcel Moolenaar /*
86827d5dc18SMarcel Moolenaar * Enable FIFOs. And check that the UART has them. If not, we're
86989eef2deSThomas Moestl * done. Since this is the first time we enable the FIFOs, we reset
87089eef2deSThomas Moestl * them.
87127d5dc18SMarcel Moolenaar */
872f25b0d6dSOskar Holmlund uart_setreg(bas, REG_FCR, FCR_ENABLE);
87327d5dc18SMarcel Moolenaar uart_barrier(bas);
8748d1289feSMarcel Moolenaar if (!(uart_getreg(bas, REG_IIR) & IIR_FIFO_MASK)) {
87527d5dc18SMarcel Moolenaar /*
87627d5dc18SMarcel Moolenaar * NS16450 or INS8250. We don't bother to differentiate
87727d5dc18SMarcel Moolenaar * between them. They're too old to be interesting.
87827d5dc18SMarcel Moolenaar */
87927d5dc18SMarcel Moolenaar uart_setreg(bas, REG_MCR, mcr);
88027d5dc18SMarcel Moolenaar uart_barrier(bas);
8818d1289feSMarcel Moolenaar sc->sc_rxfifosz = sc->sc_txfifosz = 1;
88227d5dc18SMarcel Moolenaar device_set_desc(sc->sc_dev, "8250 or 16450 or compatible");
88327d5dc18SMarcel Moolenaar return (0);
88427d5dc18SMarcel Moolenaar }
88527d5dc18SMarcel Moolenaar
886f25b0d6dSOskar Holmlund uart_setreg(bas, REG_FCR, FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST);
88727d5dc18SMarcel Moolenaar uart_barrier(bas);
88827d5dc18SMarcel Moolenaar
88927d5dc18SMarcel Moolenaar count = 0;
89027d5dc18SMarcel Moolenaar delay = ns8250_delay(bas);
89127d5dc18SMarcel Moolenaar
89227d5dc18SMarcel Moolenaar /* We have FIFOs. Drain the transmitter and receiver. */
89327d5dc18SMarcel Moolenaar error = ns8250_drain(bas, UART_DRAIN_RECEIVER|UART_DRAIN_TRANSMITTER);
89427d5dc18SMarcel Moolenaar if (error) {
89527d5dc18SMarcel Moolenaar uart_setreg(bas, REG_MCR, mcr);
896f25b0d6dSOskar Holmlund uart_setreg(bas, REG_FCR, 0);
89727d5dc18SMarcel Moolenaar uart_barrier(bas);
89827d5dc18SMarcel Moolenaar goto describe;
89927d5dc18SMarcel Moolenaar }
90027d5dc18SMarcel Moolenaar
90127d5dc18SMarcel Moolenaar /*
90227d5dc18SMarcel Moolenaar * We should have a sufficiently clean "pipe" to determine the
90327d5dc18SMarcel Moolenaar * size of the FIFOs. We send as much characters as is reasonable
9046bccea7cSRebecca Cran * and wait for the overflow bit in the LSR register to be
90589eef2deSThomas Moestl * asserted, counting the characters as we send them. Based on
90689eef2deSThomas Moestl * that count we know the FIFO size.
90727d5dc18SMarcel Moolenaar */
90889eef2deSThomas Moestl do {
90927d5dc18SMarcel Moolenaar uart_setreg(bas, REG_DATA, 0);
91027d5dc18SMarcel Moolenaar uart_barrier(bas);
91127d5dc18SMarcel Moolenaar count++;
91227d5dc18SMarcel Moolenaar
91327d5dc18SMarcel Moolenaar limit = 30;
91489eef2deSThomas Moestl lsr = 0;
91589eef2deSThomas Moestl /*
91689eef2deSThomas Moestl * LSR bits are cleared upon read, so we must accumulate
91789eef2deSThomas Moestl * them to be able to test LSR_OE below.
91889eef2deSThomas Moestl */
91989eef2deSThomas Moestl while (((lsr |= uart_getreg(bas, REG_LSR)) & LSR_TEMT) == 0 &&
92089eef2deSThomas Moestl --limit)
92127d5dc18SMarcel Moolenaar DELAY(delay);
92227d5dc18SMarcel Moolenaar if (limit == 0) {
9234a9a4165SMark Johnston /* See the comment in ns8250_init(). */
9244a9a4165SMark Johnston ier = uart_getreg(bas, REG_IER) & 0xe0;
92558957d87SBenno Rice uart_setreg(bas, REG_IER, ier);
92627d5dc18SMarcel Moolenaar uart_setreg(bas, REG_MCR, mcr);
927f25b0d6dSOskar Holmlund uart_setreg(bas, REG_FCR, 0);
92827d5dc18SMarcel Moolenaar uart_barrier(bas);
92927d5dc18SMarcel Moolenaar count = 0;
93027d5dc18SMarcel Moolenaar goto describe;
93127d5dc18SMarcel Moolenaar }
9326e71b3c3SEd Maste } while ((lsr & LSR_OE) == 0 && count < 260);
93389eef2deSThomas Moestl count--;
93427d5dc18SMarcel Moolenaar
93527d5dc18SMarcel Moolenaar uart_setreg(bas, REG_MCR, mcr);
93627d5dc18SMarcel Moolenaar
93727d5dc18SMarcel Moolenaar /* Reset FIFOs. */
93827d5dc18SMarcel Moolenaar ns8250_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER);
93927d5dc18SMarcel Moolenaar
94027d5dc18SMarcel Moolenaar describe:
94189eef2deSThomas Moestl if (count >= 14 && count <= 16) {
94227d5dc18SMarcel Moolenaar sc->sc_rxfifosz = 16;
94327d5dc18SMarcel Moolenaar device_set_desc(sc->sc_dev, "16550 or compatible");
94489eef2deSThomas Moestl } else if (count >= 28 && count <= 32) {
94527d5dc18SMarcel Moolenaar sc->sc_rxfifosz = 32;
94627d5dc18SMarcel Moolenaar device_set_desc(sc->sc_dev, "16650 or compatible");
94789eef2deSThomas Moestl } else if (count >= 56 && count <= 64) {
94827d5dc18SMarcel Moolenaar sc->sc_rxfifosz = 64;
94927d5dc18SMarcel Moolenaar device_set_desc(sc->sc_dev, "16750 or compatible");
95089eef2deSThomas Moestl } else if (count >= 112 && count <= 128) {
95127d5dc18SMarcel Moolenaar sc->sc_rxfifosz = 128;
95227d5dc18SMarcel Moolenaar device_set_desc(sc->sc_dev, "16950 or compatible");
9536e71b3c3SEd Maste } else if (count >= 224 && count <= 256) {
9546e71b3c3SEd Maste sc->sc_rxfifosz = 256;
9556e71b3c3SEd Maste device_set_desc(sc->sc_dev, "16x50 with 256 byte FIFO");
95627d5dc18SMarcel Moolenaar } else {
957c21e0da2SMarcel Moolenaar sc->sc_rxfifosz = 16;
95827d5dc18SMarcel Moolenaar device_set_desc(sc->sc_dev,
95927d5dc18SMarcel Moolenaar "Non-standard ns8250 class UART with FIFOs");
96027d5dc18SMarcel Moolenaar }
96127d5dc18SMarcel Moolenaar
96227d5dc18SMarcel Moolenaar /*
96327d5dc18SMarcel Moolenaar * Force the Tx FIFO size to 16 bytes for now. We don't program the
96427d5dc18SMarcel Moolenaar * Tx trigger. Also, we assume that all data has been sent when the
96527d5dc18SMarcel Moolenaar * interrupt happens.
96627d5dc18SMarcel Moolenaar */
96727d5dc18SMarcel Moolenaar sc->sc_txfifosz = 16;
96827d5dc18SMarcel Moolenaar
969dc70e792SMarcel Moolenaar #if 0
970dc70e792SMarcel Moolenaar /*
971dc70e792SMarcel Moolenaar * XXX there are some issues related to hardware flow control and
972453130d9SPedro F. Giffuni * it's likely that uart(4) is the cause. This basically needs more
973dc70e792SMarcel Moolenaar * investigation, but we avoid using for hardware flow control
974dc70e792SMarcel Moolenaar * until then.
975dc70e792SMarcel Moolenaar */
97684c7b427SMarcel Moolenaar /* 16650s or higher have automatic flow control. */
97784c7b427SMarcel Moolenaar if (sc->sc_rxfifosz > 16) {
97884c7b427SMarcel Moolenaar sc->sc_hwiflow = 1;
97984c7b427SMarcel Moolenaar sc->sc_hwoflow = 1;
98084c7b427SMarcel Moolenaar }
981dc70e792SMarcel Moolenaar #endif
98284c7b427SMarcel Moolenaar
98327d5dc18SMarcel Moolenaar return (0);
98427d5dc18SMarcel Moolenaar }
98527d5dc18SMarcel Moolenaar
986167cb33fSIan Lepore int
ns8250_bus_receive(struct uart_softc * sc)98727d5dc18SMarcel Moolenaar ns8250_bus_receive(struct uart_softc *sc)
98827d5dc18SMarcel Moolenaar {
98927d5dc18SMarcel Moolenaar struct uart_bas *bas;
99027d5dc18SMarcel Moolenaar int xc;
99127d5dc18SMarcel Moolenaar uint8_t lsr;
99227d5dc18SMarcel Moolenaar
99327d5dc18SMarcel Moolenaar bas = &sc->sc_bas;
9948af03381SMarcel Moolenaar uart_lock(sc->sc_hwmtx);
99527d5dc18SMarcel Moolenaar lsr = uart_getreg(bas, REG_LSR);
99644ed791bSMarcel Moolenaar while (lsr & LSR_RXRDY) {
99744ed791bSMarcel Moolenaar if (uart_rx_full(sc)) {
99844ed791bSMarcel Moolenaar sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
99927d5dc18SMarcel Moolenaar break;
100044ed791bSMarcel Moolenaar }
100127d5dc18SMarcel Moolenaar xc = uart_getreg(bas, REG_DATA);
100227d5dc18SMarcel Moolenaar if (lsr & LSR_FE)
100327d5dc18SMarcel Moolenaar xc |= UART_STAT_FRAMERR;
100427d5dc18SMarcel Moolenaar if (lsr & LSR_PE)
100527d5dc18SMarcel Moolenaar xc |= UART_STAT_PARERR;
100627d5dc18SMarcel Moolenaar uart_rx_put(sc, xc);
100744ed791bSMarcel Moolenaar lsr = uart_getreg(bas, REG_LSR);
100844ed791bSMarcel Moolenaar }
100944ed791bSMarcel Moolenaar /* Discard everything left in the Rx FIFO. */
101044ed791bSMarcel Moolenaar while (lsr & LSR_RXRDY) {
101144ed791bSMarcel Moolenaar (void)uart_getreg(bas, REG_DATA);
101244ed791bSMarcel Moolenaar uart_barrier(bas);
101344ed791bSMarcel Moolenaar lsr = uart_getreg(bas, REG_LSR);
101427d5dc18SMarcel Moolenaar }
10158af03381SMarcel Moolenaar uart_unlock(sc->sc_hwmtx);
101627d5dc18SMarcel Moolenaar return (0);
101727d5dc18SMarcel Moolenaar }
101827d5dc18SMarcel Moolenaar
1019167cb33fSIan Lepore int
ns8250_bus_setsig(struct uart_softc * sc,int sig)102027d5dc18SMarcel Moolenaar ns8250_bus_setsig(struct uart_softc *sc, int sig)
102127d5dc18SMarcel Moolenaar {
102227d5dc18SMarcel Moolenaar struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
102327d5dc18SMarcel Moolenaar struct uart_bas *bas;
102427d5dc18SMarcel Moolenaar uint32_t new, old;
102527d5dc18SMarcel Moolenaar
102627d5dc18SMarcel Moolenaar bas = &sc->sc_bas;
102727d5dc18SMarcel Moolenaar do {
102827d5dc18SMarcel Moolenaar old = sc->sc_hwsig;
102927d5dc18SMarcel Moolenaar new = old;
103028710806SPoul-Henning Kamp if (sig & SER_DDTR) {
1031fdfbb3f5SIan Lepore new = (new & ~SER_DTR) | (sig & (SER_DTR | SER_DDTR));
103227d5dc18SMarcel Moolenaar }
103328710806SPoul-Henning Kamp if (sig & SER_DRTS) {
1034fdfbb3f5SIan Lepore new = (new & ~SER_RTS) | (sig & (SER_RTS | SER_DRTS));
103527d5dc18SMarcel Moolenaar }
103627d5dc18SMarcel Moolenaar } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
10378af03381SMarcel Moolenaar uart_lock(sc->sc_hwmtx);
103827d5dc18SMarcel Moolenaar ns8250->mcr &= ~(MCR_DTR|MCR_RTS);
103928710806SPoul-Henning Kamp if (new & SER_DTR)
104027d5dc18SMarcel Moolenaar ns8250->mcr |= MCR_DTR;
104128710806SPoul-Henning Kamp if (new & SER_RTS)
104227d5dc18SMarcel Moolenaar ns8250->mcr |= MCR_RTS;
104327d5dc18SMarcel Moolenaar uart_setreg(bas, REG_MCR, ns8250->mcr);
104427d5dc18SMarcel Moolenaar uart_barrier(bas);
10458af03381SMarcel Moolenaar uart_unlock(sc->sc_hwmtx);
104627d5dc18SMarcel Moolenaar return (0);
104727d5dc18SMarcel Moolenaar }
104827d5dc18SMarcel Moolenaar
1049167cb33fSIan Lepore int
ns8250_bus_transmit(struct uart_softc * sc)105027d5dc18SMarcel Moolenaar ns8250_bus_transmit(struct uart_softc *sc)
105127d5dc18SMarcel Moolenaar {
105227d5dc18SMarcel Moolenaar struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
105327d5dc18SMarcel Moolenaar struct uart_bas *bas;
105427d5dc18SMarcel Moolenaar int i;
105527d5dc18SMarcel Moolenaar
105627d5dc18SMarcel Moolenaar bas = &sc->sc_bas;
10578af03381SMarcel Moolenaar uart_lock(sc->sc_hwmtx);
105827d5dc18SMarcel Moolenaar while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0)
10594e352a45SAlexander Motin DELAY(4);
106027d5dc18SMarcel Moolenaar for (i = 0; i < sc->sc_txdatasz; i++) {
106127d5dc18SMarcel Moolenaar uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]);
106227d5dc18SMarcel Moolenaar uart_barrier(bas);
106327d5dc18SMarcel Moolenaar }
10647e7f7beeSMitchell Horne if (!broken_txfifo)
10657e7f7beeSMitchell Horne ns8250->ier |= IER_ETXRDY;
10667e7f7beeSMitchell Horne uart_setreg(bas, REG_IER, ns8250->ier);
10673c7b9077SMichal Meloun uart_barrier(bas);
10681c60b24bSColin Percival if (broken_txfifo)
10691c60b24bSColin Percival ns8250_drain(bas, UART_DRAIN_TRANSMITTER);
10701c60b24bSColin Percival else
107127d5dc18SMarcel Moolenaar sc->sc_txbusy = 1;
10728af03381SMarcel Moolenaar uart_unlock(sc->sc_hwmtx);
10731c60b24bSColin Percival if (broken_txfifo)
10741c60b24bSColin Percival uart_sched_softih(sc, SER_INT_TXIDLE);
107527d5dc18SMarcel Moolenaar return (0);
107627d5dc18SMarcel Moolenaar }
1077d76a1ef4SWarner Losh
1078353e4c5aSMarius Strobl bool
ns8250_bus_txbusy(struct uart_softc * sc)1079353e4c5aSMarius Strobl ns8250_bus_txbusy(struct uart_softc *sc)
1080353e4c5aSMarius Strobl {
1081353e4c5aSMarius Strobl struct uart_bas *bas = &sc->sc_bas;
1082353e4c5aSMarius Strobl
1083353e4c5aSMarius Strobl if ((uart_getreg(bas, REG_LSR) & (LSR_TEMT | LSR_THRE)) !=
1084353e4c5aSMarius Strobl (LSR_TEMT | LSR_THRE))
1085353e4c5aSMarius Strobl return (true);
1086353e4c5aSMarius Strobl return (false);
1087353e4c5aSMarius Strobl }
1088353e4c5aSMarius Strobl
1089d76a1ef4SWarner Losh void
ns8250_bus_grab(struct uart_softc * sc)1090d76a1ef4SWarner Losh ns8250_bus_grab(struct uart_softc *sc)
1091d76a1ef4SWarner Losh {
1092d76a1ef4SWarner Losh struct uart_bas *bas = &sc->sc_bas;
1093caf6d6b4SOlivier Houchard struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
10948bc9a079SOlivier Houchard u_char ier;
1095d76a1ef4SWarner Losh
1096d76a1ef4SWarner Losh /*
1097d76a1ef4SWarner Losh * turn off all interrupts to enter polling mode. Leave the
1098d76a1ef4SWarner Losh * saved mask alone. We'll restore whatever it was in ungrab.
1099453130d9SPedro F. Giffuni * All pending interrupt signals are reset when IER is set to 0.
1100d76a1ef4SWarner Losh */
1101d76a1ef4SWarner Losh uart_lock(sc->sc_hwmtx);
11028bc9a079SOlivier Houchard ier = uart_getreg(bas, REG_IER);
11038bc9a079SOlivier Houchard uart_setreg(bas, REG_IER, ier & ns8250->ier_mask);
1104d76a1ef4SWarner Losh uart_barrier(bas);
1105d76a1ef4SWarner Losh uart_unlock(sc->sc_hwmtx);
1106d76a1ef4SWarner Losh }
1107d76a1ef4SWarner Losh
1108d76a1ef4SWarner Losh void
ns8250_bus_ungrab(struct uart_softc * sc)1109d76a1ef4SWarner Losh ns8250_bus_ungrab(struct uart_softc *sc)
1110d76a1ef4SWarner Losh {
1111d76a1ef4SWarner Losh struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
1112d76a1ef4SWarner Losh struct uart_bas *bas = &sc->sc_bas;
1113d76a1ef4SWarner Losh
1114d76a1ef4SWarner Losh /*
1115d76a1ef4SWarner Losh * Restore previous interrupt mask
1116d76a1ef4SWarner Losh */
1117d76a1ef4SWarner Losh uart_lock(sc->sc_hwmtx);
1118d76a1ef4SWarner Losh uart_setreg(bas, REG_IER, ns8250->ier);
1119d76a1ef4SWarner Losh uart_barrier(bas);
1120d76a1ef4SWarner Losh uart_unlock(sc->sc_hwmtx);
1121d76a1ef4SWarner Losh }
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