1098ca2bdSWarner Losh /*- 227d5dc18SMarcel Moolenaar * Copyright (c) 2003 Marcel Moolenaar 327d5dc18SMarcel Moolenaar * All rights reserved. 427d5dc18SMarcel Moolenaar * 527d5dc18SMarcel Moolenaar * Redistribution and use in source and binary forms, with or without 627d5dc18SMarcel Moolenaar * modification, are permitted provided that the following conditions 727d5dc18SMarcel Moolenaar * are met: 827d5dc18SMarcel Moolenaar * 927d5dc18SMarcel Moolenaar * 1. Redistributions of source code must retain the above copyright 1027d5dc18SMarcel Moolenaar * notice, this list of conditions and the following disclaimer. 1127d5dc18SMarcel Moolenaar * 2. Redistributions in binary form must reproduce the above copyright 1227d5dc18SMarcel Moolenaar * notice, this list of conditions and the following disclaimer in the 1327d5dc18SMarcel Moolenaar * documentation and/or other materials provided with the distribution. 1427d5dc18SMarcel Moolenaar * 1527d5dc18SMarcel Moolenaar * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 1627d5dc18SMarcel Moolenaar * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 1727d5dc18SMarcel Moolenaar * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 1827d5dc18SMarcel Moolenaar * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 1927d5dc18SMarcel Moolenaar * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 2027d5dc18SMarcel Moolenaar * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2127d5dc18SMarcel Moolenaar * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2227d5dc18SMarcel Moolenaar * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2327d5dc18SMarcel Moolenaar * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 2427d5dc18SMarcel Moolenaar * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2527d5dc18SMarcel Moolenaar */ 2627d5dc18SMarcel Moolenaar 2727d5dc18SMarcel Moolenaar #include <sys/cdefs.h> 2827d5dc18SMarcel Moolenaar __FBSDID("$FreeBSD$"); 2927d5dc18SMarcel Moolenaar 3027d5dc18SMarcel Moolenaar #include <sys/param.h> 3127d5dc18SMarcel Moolenaar #include <sys/systm.h> 3227d5dc18SMarcel Moolenaar #include <sys/bus.h> 3327d5dc18SMarcel Moolenaar #include <sys/conf.h> 3427d5dc18SMarcel Moolenaar #include <machine/bus.h> 3527d5dc18SMarcel Moolenaar 3627d5dc18SMarcel Moolenaar #include <dev/uart/uart.h> 3727d5dc18SMarcel Moolenaar #include <dev/uart/uart_cpu.h> 3827d5dc18SMarcel Moolenaar #include <dev/uart/uart_bus.h> 3976563beaSMarcel Moolenaar 4076563beaSMarcel Moolenaar #include <dev/ic/ns16550.h> 4127d5dc18SMarcel Moolenaar 4227d5dc18SMarcel Moolenaar #include "uart_if.h" 4327d5dc18SMarcel Moolenaar 4427d5dc18SMarcel Moolenaar #define DEFAULT_RCLK 1843200 4527d5dc18SMarcel Moolenaar 4627d5dc18SMarcel Moolenaar /* 4727d5dc18SMarcel Moolenaar * Clear pending interrupts. THRE is cleared by reading IIR. Data 4827d5dc18SMarcel Moolenaar * that may have been received gets lost here. 4927d5dc18SMarcel Moolenaar */ 5027d5dc18SMarcel Moolenaar static void 5127d5dc18SMarcel Moolenaar ns8250_clrint(struct uart_bas *bas) 5227d5dc18SMarcel Moolenaar { 5327d5dc18SMarcel Moolenaar uint8_t iir; 5427d5dc18SMarcel Moolenaar 5527d5dc18SMarcel Moolenaar iir = uart_getreg(bas, REG_IIR); 5627d5dc18SMarcel Moolenaar while ((iir & IIR_NOPEND) == 0) { 5727d5dc18SMarcel Moolenaar iir &= IIR_IMASK; 5827d5dc18SMarcel Moolenaar if (iir == IIR_RLS) 5927d5dc18SMarcel Moolenaar (void)uart_getreg(bas, REG_LSR); 6027d5dc18SMarcel Moolenaar else if (iir == IIR_RXRDY || iir == IIR_RXTOUT) 6127d5dc18SMarcel Moolenaar (void)uart_getreg(bas, REG_DATA); 6227d5dc18SMarcel Moolenaar else if (iir == IIR_MLSC) 6327d5dc18SMarcel Moolenaar (void)uart_getreg(bas, REG_MSR); 6427d5dc18SMarcel Moolenaar uart_barrier(bas); 6527d5dc18SMarcel Moolenaar iir = uart_getreg(bas, REG_IIR); 6627d5dc18SMarcel Moolenaar } 6727d5dc18SMarcel Moolenaar } 6827d5dc18SMarcel Moolenaar 6927d5dc18SMarcel Moolenaar static int 7027d5dc18SMarcel Moolenaar ns8250_delay(struct uart_bas *bas) 7127d5dc18SMarcel Moolenaar { 7227d5dc18SMarcel Moolenaar int divisor; 7327d5dc18SMarcel Moolenaar u_char lcr; 7427d5dc18SMarcel Moolenaar 7527d5dc18SMarcel Moolenaar lcr = uart_getreg(bas, REG_LCR); 7627d5dc18SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 7727d5dc18SMarcel Moolenaar uart_barrier(bas); 7858957d87SBenno Rice divisor = uart_getreg(bas, REG_DLL) | (uart_getreg(bas, REG_DLH) << 8); 7927d5dc18SMarcel Moolenaar uart_barrier(bas); 8027d5dc18SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr); 8127d5dc18SMarcel Moolenaar uart_barrier(bas); 8227d5dc18SMarcel Moolenaar 8327d5dc18SMarcel Moolenaar /* 1/10th the time to transmit 1 character (estimate). */ 84ebecffe9SMarcel Moolenaar if (divisor <= 134) 8527d5dc18SMarcel Moolenaar return (16000000 * divisor / bas->rclk); 86ebecffe9SMarcel Moolenaar return (16000 * divisor / (bas->rclk / 1000)); 8727d5dc18SMarcel Moolenaar } 8827d5dc18SMarcel Moolenaar 8927d5dc18SMarcel Moolenaar static int 9027d5dc18SMarcel Moolenaar ns8250_divisor(int rclk, int baudrate) 9127d5dc18SMarcel Moolenaar { 9227d5dc18SMarcel Moolenaar int actual_baud, divisor; 9327d5dc18SMarcel Moolenaar int error; 9427d5dc18SMarcel Moolenaar 9527d5dc18SMarcel Moolenaar if (baudrate == 0) 9627d5dc18SMarcel Moolenaar return (0); 9727d5dc18SMarcel Moolenaar 9827d5dc18SMarcel Moolenaar divisor = (rclk / (baudrate << 3) + 1) >> 1; 9927d5dc18SMarcel Moolenaar if (divisor == 0 || divisor >= 65536) 10027d5dc18SMarcel Moolenaar return (0); 10127d5dc18SMarcel Moolenaar actual_baud = rclk / (divisor << 4); 10227d5dc18SMarcel Moolenaar 10327d5dc18SMarcel Moolenaar /* 10 times error in percent: */ 10427d5dc18SMarcel Moolenaar error = ((actual_baud - baudrate) * 2000 / baudrate + 1) >> 1; 10527d5dc18SMarcel Moolenaar 10627d5dc18SMarcel Moolenaar /* 3.0% maximum error tolerance: */ 10727d5dc18SMarcel Moolenaar if (error < -30 || error > 30) 10827d5dc18SMarcel Moolenaar return (0); 10927d5dc18SMarcel Moolenaar 11027d5dc18SMarcel Moolenaar return (divisor); 11127d5dc18SMarcel Moolenaar } 11227d5dc18SMarcel Moolenaar 11327d5dc18SMarcel Moolenaar static int 11427d5dc18SMarcel Moolenaar ns8250_drain(struct uart_bas *bas, int what) 11527d5dc18SMarcel Moolenaar { 11627d5dc18SMarcel Moolenaar int delay, limit; 11727d5dc18SMarcel Moolenaar 11827d5dc18SMarcel Moolenaar delay = ns8250_delay(bas); 11927d5dc18SMarcel Moolenaar 12027d5dc18SMarcel Moolenaar if (what & UART_DRAIN_TRANSMITTER) { 12127d5dc18SMarcel Moolenaar /* 12227d5dc18SMarcel Moolenaar * Pick an arbitrary high limit to avoid getting stuck in 12327d5dc18SMarcel Moolenaar * an infinite loop when the hardware is broken. Make the 12427d5dc18SMarcel Moolenaar * limit high enough to handle large FIFOs. 12527d5dc18SMarcel Moolenaar */ 12627d5dc18SMarcel Moolenaar limit = 10*1024; 12727d5dc18SMarcel Moolenaar while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) 12827d5dc18SMarcel Moolenaar DELAY(delay); 12927d5dc18SMarcel Moolenaar if (limit == 0) { 13027d5dc18SMarcel Moolenaar /* printf("ns8250: transmitter appears stuck... "); */ 13127d5dc18SMarcel Moolenaar return (EIO); 13227d5dc18SMarcel Moolenaar } 13327d5dc18SMarcel Moolenaar } 13427d5dc18SMarcel Moolenaar 13527d5dc18SMarcel Moolenaar if (what & UART_DRAIN_RECEIVER) { 13627d5dc18SMarcel Moolenaar /* 13727d5dc18SMarcel Moolenaar * Pick an arbitrary high limit to avoid getting stuck in 13827d5dc18SMarcel Moolenaar * an infinite loop when the hardware is broken. Make the 13927d5dc18SMarcel Moolenaar * limit high enough to handle large FIFOs and integrated 14027d5dc18SMarcel Moolenaar * UARTs. The HP rx2600 for example has 3 UARTs on the 14127d5dc18SMarcel Moolenaar * management board that tend to get a lot of data send 14227d5dc18SMarcel Moolenaar * to it when the UART is first activated. 14327d5dc18SMarcel Moolenaar */ 14427d5dc18SMarcel Moolenaar limit=10*4096; 14527d5dc18SMarcel Moolenaar while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) { 14627d5dc18SMarcel Moolenaar (void)uart_getreg(bas, REG_DATA); 14727d5dc18SMarcel Moolenaar uart_barrier(bas); 14827d5dc18SMarcel Moolenaar DELAY(delay << 2); 14927d5dc18SMarcel Moolenaar } 15027d5dc18SMarcel Moolenaar if (limit == 0) { 15127d5dc18SMarcel Moolenaar /* printf("ns8250: receiver appears broken... "); */ 15227d5dc18SMarcel Moolenaar return (EIO); 15327d5dc18SMarcel Moolenaar } 15427d5dc18SMarcel Moolenaar } 15527d5dc18SMarcel Moolenaar 15627d5dc18SMarcel Moolenaar return (0); 15727d5dc18SMarcel Moolenaar } 15827d5dc18SMarcel Moolenaar 15927d5dc18SMarcel Moolenaar /* 16027d5dc18SMarcel Moolenaar * We can only flush UARTs with FIFOs. UARTs without FIFOs should be 16127d5dc18SMarcel Moolenaar * drained. WARNING: this function clobbers the FIFO setting! 16227d5dc18SMarcel Moolenaar */ 16327d5dc18SMarcel Moolenaar static void 16427d5dc18SMarcel Moolenaar ns8250_flush(struct uart_bas *bas, int what) 16527d5dc18SMarcel Moolenaar { 16627d5dc18SMarcel Moolenaar uint8_t fcr; 16727d5dc18SMarcel Moolenaar 16827d5dc18SMarcel Moolenaar fcr = FCR_ENABLE; 16927d5dc18SMarcel Moolenaar if (what & UART_FLUSH_TRANSMITTER) 17027d5dc18SMarcel Moolenaar fcr |= FCR_XMT_RST; 17127d5dc18SMarcel Moolenaar if (what & UART_FLUSH_RECEIVER) 17227d5dc18SMarcel Moolenaar fcr |= FCR_RCV_RST; 17327d5dc18SMarcel Moolenaar uart_setreg(bas, REG_FCR, fcr); 17427d5dc18SMarcel Moolenaar uart_barrier(bas); 17527d5dc18SMarcel Moolenaar } 17627d5dc18SMarcel Moolenaar 17727d5dc18SMarcel Moolenaar static int 17827d5dc18SMarcel Moolenaar ns8250_param(struct uart_bas *bas, int baudrate, int databits, int stopbits, 17927d5dc18SMarcel Moolenaar int parity) 18027d5dc18SMarcel Moolenaar { 18127d5dc18SMarcel Moolenaar int divisor; 18227d5dc18SMarcel Moolenaar uint8_t lcr; 18327d5dc18SMarcel Moolenaar 18427d5dc18SMarcel Moolenaar lcr = 0; 18527d5dc18SMarcel Moolenaar if (databits >= 8) 18627d5dc18SMarcel Moolenaar lcr |= LCR_8BITS; 18727d5dc18SMarcel Moolenaar else if (databits == 7) 18827d5dc18SMarcel Moolenaar lcr |= LCR_7BITS; 18927d5dc18SMarcel Moolenaar else if (databits == 6) 19027d5dc18SMarcel Moolenaar lcr |= LCR_6BITS; 19127d5dc18SMarcel Moolenaar else 19227d5dc18SMarcel Moolenaar lcr |= LCR_5BITS; 19327d5dc18SMarcel Moolenaar if (stopbits > 1) 19427d5dc18SMarcel Moolenaar lcr |= LCR_STOPB; 19527d5dc18SMarcel Moolenaar lcr |= parity << 3; 19627d5dc18SMarcel Moolenaar 19727d5dc18SMarcel Moolenaar /* Set baudrate. */ 19827d5dc18SMarcel Moolenaar if (baudrate > 0) { 19927d5dc18SMarcel Moolenaar divisor = ns8250_divisor(bas->rclk, baudrate); 20027d5dc18SMarcel Moolenaar if (divisor == 0) 20127d5dc18SMarcel Moolenaar return (EINVAL); 20263f8efd3SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 20363f8efd3SMarcel Moolenaar uart_barrier(bas); 20458957d87SBenno Rice uart_setreg(bas, REG_DLL, divisor & 0xff); 20558957d87SBenno Rice uart_setreg(bas, REG_DLH, (divisor >> 8) & 0xff); 20627d5dc18SMarcel Moolenaar uart_barrier(bas); 20727d5dc18SMarcel Moolenaar } 20827d5dc18SMarcel Moolenaar 20927d5dc18SMarcel Moolenaar /* Set LCR and clear DLAB. */ 21027d5dc18SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr); 21127d5dc18SMarcel Moolenaar uart_barrier(bas); 21227d5dc18SMarcel Moolenaar return (0); 21327d5dc18SMarcel Moolenaar } 21427d5dc18SMarcel Moolenaar 21527d5dc18SMarcel Moolenaar /* 21627d5dc18SMarcel Moolenaar * Low-level UART interface. 21727d5dc18SMarcel Moolenaar */ 21827d5dc18SMarcel Moolenaar static int ns8250_probe(struct uart_bas *bas); 21927d5dc18SMarcel Moolenaar static void ns8250_init(struct uart_bas *bas, int, int, int, int); 22027d5dc18SMarcel Moolenaar static void ns8250_term(struct uart_bas *bas); 22127d5dc18SMarcel Moolenaar static void ns8250_putc(struct uart_bas *bas, int); 22297202af2SMarius Strobl static int ns8250_rxready(struct uart_bas *bas); 223634e63c9SMarcel Moolenaar static int ns8250_getc(struct uart_bas *bas, struct mtx *); 22427d5dc18SMarcel Moolenaar 225f8100ce2SMarcel Moolenaar static struct uart_ops uart_ns8250_ops = { 22627d5dc18SMarcel Moolenaar .probe = ns8250_probe, 22727d5dc18SMarcel Moolenaar .init = ns8250_init, 22827d5dc18SMarcel Moolenaar .term = ns8250_term, 22927d5dc18SMarcel Moolenaar .putc = ns8250_putc, 23097202af2SMarius Strobl .rxready = ns8250_rxready, 23127d5dc18SMarcel Moolenaar .getc = ns8250_getc, 23227d5dc18SMarcel Moolenaar }; 23327d5dc18SMarcel Moolenaar 23427d5dc18SMarcel Moolenaar static int 23527d5dc18SMarcel Moolenaar ns8250_probe(struct uart_bas *bas) 23627d5dc18SMarcel Moolenaar { 2378bceca4fSBenno Rice u_char val; 23827d5dc18SMarcel Moolenaar 23927d5dc18SMarcel Moolenaar /* Check known 0 bits that don't depend on DLAB. */ 24027d5dc18SMarcel Moolenaar val = uart_getreg(bas, REG_IIR); 24127d5dc18SMarcel Moolenaar if (val & 0x30) 24227d5dc18SMarcel Moolenaar return (ENXIO); 24327d5dc18SMarcel Moolenaar val = uart_getreg(bas, REG_MCR); 24427d5dc18SMarcel Moolenaar if (val & 0xe0) 24527d5dc18SMarcel Moolenaar return (ENXIO); 24627d5dc18SMarcel Moolenaar 24727d5dc18SMarcel Moolenaar return (0); 24827d5dc18SMarcel Moolenaar } 24927d5dc18SMarcel Moolenaar 25027d5dc18SMarcel Moolenaar static void 25127d5dc18SMarcel Moolenaar ns8250_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, 25227d5dc18SMarcel Moolenaar int parity) 25327d5dc18SMarcel Moolenaar { 25458957d87SBenno Rice u_char ier; 25527d5dc18SMarcel Moolenaar 25627d5dc18SMarcel Moolenaar if (bas->rclk == 0) 25727d5dc18SMarcel Moolenaar bas->rclk = DEFAULT_RCLK; 25827d5dc18SMarcel Moolenaar ns8250_param(bas, baudrate, databits, stopbits, parity); 25927d5dc18SMarcel Moolenaar 26027d5dc18SMarcel Moolenaar /* Disable all interrupt sources. */ 2610aefb0a6SBenno Rice /* 2620aefb0a6SBenno Rice * We use 0xe0 instead of 0xf0 as the mask because the XScale PXA 2630aefb0a6SBenno Rice * UARTs split the receive time-out interrupt bit out separately as 2640aefb0a6SBenno Rice * 0x10. This gets handled by ier_mask and ier_rxbits below. 2650aefb0a6SBenno Rice */ 2660aefb0a6SBenno Rice ier = uart_getreg(bas, REG_IER) & 0xe0; 26758957d87SBenno Rice uart_setreg(bas, REG_IER, ier); 26827d5dc18SMarcel Moolenaar uart_barrier(bas); 26927d5dc18SMarcel Moolenaar 27027d5dc18SMarcel Moolenaar /* Disable the FIFO (if present). */ 27127d5dc18SMarcel Moolenaar uart_setreg(bas, REG_FCR, 0); 27227d5dc18SMarcel Moolenaar uart_barrier(bas); 27327d5dc18SMarcel Moolenaar 27427d5dc18SMarcel Moolenaar /* Set RTS & DTR. */ 27527d5dc18SMarcel Moolenaar uart_setreg(bas, REG_MCR, MCR_IE | MCR_RTS | MCR_DTR); 27627d5dc18SMarcel Moolenaar uart_barrier(bas); 27727d5dc18SMarcel Moolenaar 27827d5dc18SMarcel Moolenaar ns8250_clrint(bas); 27927d5dc18SMarcel Moolenaar } 28027d5dc18SMarcel Moolenaar 28127d5dc18SMarcel Moolenaar static void 28227d5dc18SMarcel Moolenaar ns8250_term(struct uart_bas *bas) 28327d5dc18SMarcel Moolenaar { 28427d5dc18SMarcel Moolenaar 28527d5dc18SMarcel Moolenaar /* Clear RTS & DTR. */ 28627d5dc18SMarcel Moolenaar uart_setreg(bas, REG_MCR, MCR_IE); 28727d5dc18SMarcel Moolenaar uart_barrier(bas); 28827d5dc18SMarcel Moolenaar } 28927d5dc18SMarcel Moolenaar 29027d5dc18SMarcel Moolenaar static void 29127d5dc18SMarcel Moolenaar ns8250_putc(struct uart_bas *bas, int c) 29227d5dc18SMarcel Moolenaar { 29335777a2aSMarcel Moolenaar int limit; 29427d5dc18SMarcel Moolenaar 29535777a2aSMarcel Moolenaar limit = 250000; 29627d5dc18SMarcel Moolenaar while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0 && --limit) 29735777a2aSMarcel Moolenaar DELAY(4); 29827d5dc18SMarcel Moolenaar uart_setreg(bas, REG_DATA, c); 2994e55f723SMarcel Moolenaar uart_barrier(bas); 30035777a2aSMarcel Moolenaar limit = 250000; 30127d5dc18SMarcel Moolenaar while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) 30235777a2aSMarcel Moolenaar DELAY(4); 30327d5dc18SMarcel Moolenaar } 30427d5dc18SMarcel Moolenaar 30527d5dc18SMarcel Moolenaar static int 30697202af2SMarius Strobl ns8250_rxready(struct uart_bas *bas) 30727d5dc18SMarcel Moolenaar { 30827d5dc18SMarcel Moolenaar 30997202af2SMarius Strobl return ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) != 0 ? 1 : 0); 31027d5dc18SMarcel Moolenaar } 31127d5dc18SMarcel Moolenaar 31227d5dc18SMarcel Moolenaar static int 313634e63c9SMarcel Moolenaar ns8250_getc(struct uart_bas *bas, struct mtx *hwmtx) 31427d5dc18SMarcel Moolenaar { 31535777a2aSMarcel Moolenaar int c; 316634e63c9SMarcel Moolenaar 317634e63c9SMarcel Moolenaar uart_lock(hwmtx); 31827d5dc18SMarcel Moolenaar 319634e63c9SMarcel Moolenaar while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0) { 320634e63c9SMarcel Moolenaar uart_unlock(hwmtx); 32135777a2aSMarcel Moolenaar DELAY(4); 322634e63c9SMarcel Moolenaar uart_lock(hwmtx); 323634e63c9SMarcel Moolenaar } 324634e63c9SMarcel Moolenaar 325634e63c9SMarcel Moolenaar c = uart_getreg(bas, REG_DATA); 326634e63c9SMarcel Moolenaar 327634e63c9SMarcel Moolenaar uart_unlock(hwmtx); 328634e63c9SMarcel Moolenaar 329634e63c9SMarcel Moolenaar return (c); 33027d5dc18SMarcel Moolenaar } 33127d5dc18SMarcel Moolenaar 33227d5dc18SMarcel Moolenaar /* 33327d5dc18SMarcel Moolenaar * High-level UART interface. 33427d5dc18SMarcel Moolenaar */ 33527d5dc18SMarcel Moolenaar struct ns8250_softc { 33627d5dc18SMarcel Moolenaar struct uart_softc base; 33727d5dc18SMarcel Moolenaar uint8_t fcr; 33827d5dc18SMarcel Moolenaar uint8_t ier; 33927d5dc18SMarcel Moolenaar uint8_t mcr; 3400aefb0a6SBenno Rice 3410aefb0a6SBenno Rice uint8_t ier_mask; 3420aefb0a6SBenno Rice uint8_t ier_rxbits; 34327d5dc18SMarcel Moolenaar }; 34427d5dc18SMarcel Moolenaar 34527d5dc18SMarcel Moolenaar static int ns8250_bus_attach(struct uart_softc *); 34627d5dc18SMarcel Moolenaar static int ns8250_bus_detach(struct uart_softc *); 34727d5dc18SMarcel Moolenaar static int ns8250_bus_flush(struct uart_softc *, int); 34827d5dc18SMarcel Moolenaar static int ns8250_bus_getsig(struct uart_softc *); 34927d5dc18SMarcel Moolenaar static int ns8250_bus_ioctl(struct uart_softc *, int, intptr_t); 35027d5dc18SMarcel Moolenaar static int ns8250_bus_ipend(struct uart_softc *); 35127d5dc18SMarcel Moolenaar static int ns8250_bus_param(struct uart_softc *, int, int, int, int); 35227d5dc18SMarcel Moolenaar static int ns8250_bus_probe(struct uart_softc *); 35327d5dc18SMarcel Moolenaar static int ns8250_bus_receive(struct uart_softc *); 35427d5dc18SMarcel Moolenaar static int ns8250_bus_setsig(struct uart_softc *, int); 35527d5dc18SMarcel Moolenaar static int ns8250_bus_transmit(struct uart_softc *); 35627d5dc18SMarcel Moolenaar 35727d5dc18SMarcel Moolenaar static kobj_method_t ns8250_methods[] = { 35827d5dc18SMarcel Moolenaar KOBJMETHOD(uart_attach, ns8250_bus_attach), 35927d5dc18SMarcel Moolenaar KOBJMETHOD(uart_detach, ns8250_bus_detach), 36027d5dc18SMarcel Moolenaar KOBJMETHOD(uart_flush, ns8250_bus_flush), 36127d5dc18SMarcel Moolenaar KOBJMETHOD(uart_getsig, ns8250_bus_getsig), 36227d5dc18SMarcel Moolenaar KOBJMETHOD(uart_ioctl, ns8250_bus_ioctl), 36327d5dc18SMarcel Moolenaar KOBJMETHOD(uart_ipend, ns8250_bus_ipend), 36427d5dc18SMarcel Moolenaar KOBJMETHOD(uart_param, ns8250_bus_param), 36527d5dc18SMarcel Moolenaar KOBJMETHOD(uart_probe, ns8250_bus_probe), 36627d5dc18SMarcel Moolenaar KOBJMETHOD(uart_receive, ns8250_bus_receive), 36727d5dc18SMarcel Moolenaar KOBJMETHOD(uart_setsig, ns8250_bus_setsig), 36827d5dc18SMarcel Moolenaar KOBJMETHOD(uart_transmit, ns8250_bus_transmit), 36927d5dc18SMarcel Moolenaar { 0, 0 } 37027d5dc18SMarcel Moolenaar }; 37127d5dc18SMarcel Moolenaar 37227d5dc18SMarcel Moolenaar struct uart_class uart_ns8250_class = { 373f8100ce2SMarcel Moolenaar "ns8250", 37427d5dc18SMarcel Moolenaar ns8250_methods, 37527d5dc18SMarcel Moolenaar sizeof(struct ns8250_softc), 376f8100ce2SMarcel Moolenaar .uc_ops = &uart_ns8250_ops, 37727d5dc18SMarcel Moolenaar .uc_range = 8, 37827d5dc18SMarcel Moolenaar .uc_rclk = DEFAULT_RCLK 37927d5dc18SMarcel Moolenaar }; 38027d5dc18SMarcel Moolenaar 38127d5dc18SMarcel Moolenaar #define SIGCHG(c, i, s, d) \ 38227d5dc18SMarcel Moolenaar if (c) { \ 38327d5dc18SMarcel Moolenaar i |= (i & s) ? s : s | d; \ 38427d5dc18SMarcel Moolenaar } else { \ 38527d5dc18SMarcel Moolenaar i = (i & s) ? (i & ~s) | d : i; \ 38627d5dc18SMarcel Moolenaar } 38727d5dc18SMarcel Moolenaar 38827d5dc18SMarcel Moolenaar static int 38927d5dc18SMarcel Moolenaar ns8250_bus_attach(struct uart_softc *sc) 39027d5dc18SMarcel Moolenaar { 39127d5dc18SMarcel Moolenaar struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 39227d5dc18SMarcel Moolenaar struct uart_bas *bas; 393823c77d7SSam Leffler unsigned int ivar; 39427d5dc18SMarcel Moolenaar 39527d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 39627d5dc18SMarcel Moolenaar 39727d5dc18SMarcel Moolenaar ns8250->mcr = uart_getreg(bas, REG_MCR); 398823c77d7SSam Leffler ns8250->fcr = FCR_ENABLE; 399823c77d7SSam Leffler if (!resource_int_value("uart", device_get_unit(sc->sc_dev), "flags", 400823c77d7SSam Leffler &ivar)) { 401823c77d7SSam Leffler if (UART_FLAGS_FCR_RX_LOW(ivar)) 402823c77d7SSam Leffler ns8250->fcr |= FCR_RX_LOW; 403823c77d7SSam Leffler else if (UART_FLAGS_FCR_RX_MEDL(ivar)) 404823c77d7SSam Leffler ns8250->fcr |= FCR_RX_MEDL; 405823c77d7SSam Leffler else if (UART_FLAGS_FCR_RX_HIGH(ivar)) 406823c77d7SSam Leffler ns8250->fcr |= FCR_RX_HIGH; 407823c77d7SSam Leffler else 408823c77d7SSam Leffler ns8250->fcr |= FCR_RX_MEDH; 409823c77d7SSam Leffler } else 410823c77d7SSam Leffler ns8250->fcr |= FCR_RX_MEDH; 4110aefb0a6SBenno Rice 4120aefb0a6SBenno Rice /* Get IER mask */ 4130aefb0a6SBenno Rice ivar = 0xf0; 4140aefb0a6SBenno Rice resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_mask", 4150aefb0a6SBenno Rice &ivar); 4160aefb0a6SBenno Rice ns8250->ier_mask = (uint8_t)(ivar & 0xff); 4170aefb0a6SBenno Rice 4180aefb0a6SBenno Rice /* Get IER RX interrupt bits */ 4190aefb0a6SBenno Rice ivar = IER_EMSC | IER_ERLS | IER_ERXRDY; 4200aefb0a6SBenno Rice resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_rxbits", 4210aefb0a6SBenno Rice &ivar); 4220aefb0a6SBenno Rice ns8250->ier_rxbits = (uint8_t)(ivar & 0xff); 4230aefb0a6SBenno Rice 42427d5dc18SMarcel Moolenaar uart_setreg(bas, REG_FCR, ns8250->fcr); 42527d5dc18SMarcel Moolenaar uart_barrier(bas); 42627d5dc18SMarcel Moolenaar ns8250_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 42727d5dc18SMarcel Moolenaar 42827d5dc18SMarcel Moolenaar if (ns8250->mcr & MCR_DTR) 42928710806SPoul-Henning Kamp sc->sc_hwsig |= SER_DTR; 43027d5dc18SMarcel Moolenaar if (ns8250->mcr & MCR_RTS) 43128710806SPoul-Henning Kamp sc->sc_hwsig |= SER_RTS; 43227d5dc18SMarcel Moolenaar ns8250_bus_getsig(sc); 43327d5dc18SMarcel Moolenaar 43427d5dc18SMarcel Moolenaar ns8250_clrint(bas); 4350aefb0a6SBenno Rice ns8250->ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 4360aefb0a6SBenno Rice ns8250->ier |= ns8250->ier_rxbits; 43727d5dc18SMarcel Moolenaar uart_setreg(bas, REG_IER, ns8250->ier); 43827d5dc18SMarcel Moolenaar uart_barrier(bas); 4390aefb0a6SBenno Rice 44027d5dc18SMarcel Moolenaar return (0); 44127d5dc18SMarcel Moolenaar } 44227d5dc18SMarcel Moolenaar 44327d5dc18SMarcel Moolenaar static int 44427d5dc18SMarcel Moolenaar ns8250_bus_detach(struct uart_softc *sc) 44527d5dc18SMarcel Moolenaar { 4460aefb0a6SBenno Rice struct ns8250_softc *ns8250; 44727d5dc18SMarcel Moolenaar struct uart_bas *bas; 44858957d87SBenno Rice u_char ier; 44927d5dc18SMarcel Moolenaar 4500aefb0a6SBenno Rice ns8250 = (struct ns8250_softc *)sc; 45127d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 4520aefb0a6SBenno Rice ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 45358957d87SBenno Rice uart_setreg(bas, REG_IER, ier); 45427d5dc18SMarcel Moolenaar uart_barrier(bas); 45527d5dc18SMarcel Moolenaar ns8250_clrint(bas); 45627d5dc18SMarcel Moolenaar return (0); 45727d5dc18SMarcel Moolenaar } 45827d5dc18SMarcel Moolenaar 45927d5dc18SMarcel Moolenaar static int 46027d5dc18SMarcel Moolenaar ns8250_bus_flush(struct uart_softc *sc, int what) 46127d5dc18SMarcel Moolenaar { 46227d5dc18SMarcel Moolenaar struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 46327d5dc18SMarcel Moolenaar struct uart_bas *bas; 46406287620SMarcel Moolenaar int error; 46527d5dc18SMarcel Moolenaar 46627d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 4678af03381SMarcel Moolenaar uart_lock(sc->sc_hwmtx); 4688d1289feSMarcel Moolenaar if (sc->sc_rxfifosz > 1) { 46927d5dc18SMarcel Moolenaar ns8250_flush(bas, what); 47027d5dc18SMarcel Moolenaar uart_setreg(bas, REG_FCR, ns8250->fcr); 47127d5dc18SMarcel Moolenaar uart_barrier(bas); 47206287620SMarcel Moolenaar error = 0; 47306287620SMarcel Moolenaar } else 47406287620SMarcel Moolenaar error = ns8250_drain(bas, what); 4758af03381SMarcel Moolenaar uart_unlock(sc->sc_hwmtx); 47606287620SMarcel Moolenaar return (error); 47727d5dc18SMarcel Moolenaar } 47827d5dc18SMarcel Moolenaar 47927d5dc18SMarcel Moolenaar static int 48027d5dc18SMarcel Moolenaar ns8250_bus_getsig(struct uart_softc *sc) 48127d5dc18SMarcel Moolenaar { 48227d5dc18SMarcel Moolenaar uint32_t new, old, sig; 48327d5dc18SMarcel Moolenaar uint8_t msr; 48427d5dc18SMarcel Moolenaar 48527d5dc18SMarcel Moolenaar do { 48627d5dc18SMarcel Moolenaar old = sc->sc_hwsig; 48727d5dc18SMarcel Moolenaar sig = old; 4888af03381SMarcel Moolenaar uart_lock(sc->sc_hwmtx); 48927d5dc18SMarcel Moolenaar msr = uart_getreg(&sc->sc_bas, REG_MSR); 4908af03381SMarcel Moolenaar uart_unlock(sc->sc_hwmtx); 49128710806SPoul-Henning Kamp SIGCHG(msr & MSR_DSR, sig, SER_DSR, SER_DDSR); 49228710806SPoul-Henning Kamp SIGCHG(msr & MSR_CTS, sig, SER_CTS, SER_DCTS); 49328710806SPoul-Henning Kamp SIGCHG(msr & MSR_DCD, sig, SER_DCD, SER_DDCD); 49428710806SPoul-Henning Kamp SIGCHG(msr & MSR_RI, sig, SER_RI, SER_DRI); 495ea549414SMarcel Moolenaar new = sig & ~SER_MASK_DELTA; 49627d5dc18SMarcel Moolenaar } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 49727d5dc18SMarcel Moolenaar return (sig); 49827d5dc18SMarcel Moolenaar } 49927d5dc18SMarcel Moolenaar 50027d5dc18SMarcel Moolenaar static int 50127d5dc18SMarcel Moolenaar ns8250_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) 50227d5dc18SMarcel Moolenaar { 50327d5dc18SMarcel Moolenaar struct uart_bas *bas; 504bfa307a3SMarcel Moolenaar int baudrate, divisor, error; 50584c7b427SMarcel Moolenaar uint8_t efr, lcr; 50627d5dc18SMarcel Moolenaar 50727d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 50806287620SMarcel Moolenaar error = 0; 5098af03381SMarcel Moolenaar uart_lock(sc->sc_hwmtx); 51027d5dc18SMarcel Moolenaar switch (request) { 51127d5dc18SMarcel Moolenaar case UART_IOCTL_BREAK: 51227d5dc18SMarcel Moolenaar lcr = uart_getreg(bas, REG_LCR); 51327d5dc18SMarcel Moolenaar if (data) 51427d5dc18SMarcel Moolenaar lcr |= LCR_SBREAK; 51527d5dc18SMarcel Moolenaar else 51627d5dc18SMarcel Moolenaar lcr &= ~LCR_SBREAK; 51727d5dc18SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr); 51827d5dc18SMarcel Moolenaar uart_barrier(bas); 51927d5dc18SMarcel Moolenaar break; 52084c7b427SMarcel Moolenaar case UART_IOCTL_IFLOW: 52184c7b427SMarcel Moolenaar lcr = uart_getreg(bas, REG_LCR); 52284c7b427SMarcel Moolenaar uart_barrier(bas); 52384c7b427SMarcel Moolenaar uart_setreg(bas, REG_LCR, 0xbf); 52484c7b427SMarcel Moolenaar uart_barrier(bas); 52584c7b427SMarcel Moolenaar efr = uart_getreg(bas, REG_EFR); 52684c7b427SMarcel Moolenaar if (data) 52784c7b427SMarcel Moolenaar efr |= EFR_RTS; 52884c7b427SMarcel Moolenaar else 52984c7b427SMarcel Moolenaar efr &= ~EFR_RTS; 53084c7b427SMarcel Moolenaar uart_setreg(bas, REG_EFR, efr); 53184c7b427SMarcel Moolenaar uart_barrier(bas); 53284c7b427SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr); 53384c7b427SMarcel Moolenaar uart_barrier(bas); 53484c7b427SMarcel Moolenaar break; 53584c7b427SMarcel Moolenaar case UART_IOCTL_OFLOW: 53684c7b427SMarcel Moolenaar lcr = uart_getreg(bas, REG_LCR); 53784c7b427SMarcel Moolenaar uart_barrier(bas); 53884c7b427SMarcel Moolenaar uart_setreg(bas, REG_LCR, 0xbf); 53984c7b427SMarcel Moolenaar uart_barrier(bas); 54084c7b427SMarcel Moolenaar efr = uart_getreg(bas, REG_EFR); 54184c7b427SMarcel Moolenaar if (data) 54284c7b427SMarcel Moolenaar efr |= EFR_CTS; 54384c7b427SMarcel Moolenaar else 54484c7b427SMarcel Moolenaar efr &= ~EFR_CTS; 54584c7b427SMarcel Moolenaar uart_setreg(bas, REG_EFR, efr); 54684c7b427SMarcel Moolenaar uart_barrier(bas); 54784c7b427SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr); 54884c7b427SMarcel Moolenaar uart_barrier(bas); 54984c7b427SMarcel Moolenaar break; 550d8518925SMarcel Moolenaar case UART_IOCTL_BAUD: 551d8518925SMarcel Moolenaar lcr = uart_getreg(bas, REG_LCR); 552d8518925SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 553d8518925SMarcel Moolenaar uart_barrier(bas); 55458957d87SBenno Rice divisor = uart_getreg(bas, REG_DLL) | 55558957d87SBenno Rice (uart_getreg(bas, REG_DLH) << 8); 556d8518925SMarcel Moolenaar uart_barrier(bas); 557d8518925SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr); 558d8518925SMarcel Moolenaar uart_barrier(bas); 559bfa307a3SMarcel Moolenaar baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0; 560bfa307a3SMarcel Moolenaar if (baudrate > 0) 561bfa307a3SMarcel Moolenaar *(int*)data = baudrate; 562bfa307a3SMarcel Moolenaar else 563bfa307a3SMarcel Moolenaar error = ENXIO; 564d8518925SMarcel Moolenaar break; 56527d5dc18SMarcel Moolenaar default: 56606287620SMarcel Moolenaar error = EINVAL; 56706287620SMarcel Moolenaar break; 56827d5dc18SMarcel Moolenaar } 5698af03381SMarcel Moolenaar uart_unlock(sc->sc_hwmtx); 57006287620SMarcel Moolenaar return (error); 57127d5dc18SMarcel Moolenaar } 57227d5dc18SMarcel Moolenaar 57327d5dc18SMarcel Moolenaar static int 57427d5dc18SMarcel Moolenaar ns8250_bus_ipend(struct uart_softc *sc) 57527d5dc18SMarcel Moolenaar { 57627d5dc18SMarcel Moolenaar struct uart_bas *bas; 57727d5dc18SMarcel Moolenaar int ipend; 57827d5dc18SMarcel Moolenaar uint8_t iir, lsr; 57927d5dc18SMarcel Moolenaar 58027d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 5818af03381SMarcel Moolenaar uart_lock(sc->sc_hwmtx); 58227d5dc18SMarcel Moolenaar iir = uart_getreg(bas, REG_IIR); 58306287620SMarcel Moolenaar if (iir & IIR_NOPEND) { 5848af03381SMarcel Moolenaar uart_unlock(sc->sc_hwmtx); 58527d5dc18SMarcel Moolenaar return (0); 58606287620SMarcel Moolenaar } 58727d5dc18SMarcel Moolenaar ipend = 0; 58827d5dc18SMarcel Moolenaar if (iir & IIR_RXRDY) { 58927d5dc18SMarcel Moolenaar lsr = uart_getreg(bas, REG_LSR); 5908af03381SMarcel Moolenaar uart_unlock(sc->sc_hwmtx); 59127d5dc18SMarcel Moolenaar if (lsr & LSR_OE) 5922d511805SMarcel Moolenaar ipend |= SER_INT_OVERRUN; 59327d5dc18SMarcel Moolenaar if (lsr & LSR_BI) 5942d511805SMarcel Moolenaar ipend |= SER_INT_BREAK; 59527d5dc18SMarcel Moolenaar if (lsr & LSR_RXRDY) 5962d511805SMarcel Moolenaar ipend |= SER_INT_RXREADY; 59727d5dc18SMarcel Moolenaar } else { 5988af03381SMarcel Moolenaar uart_unlock(sc->sc_hwmtx); 59927d5dc18SMarcel Moolenaar if (iir & IIR_TXRDY) 6002d511805SMarcel Moolenaar ipend |= SER_INT_TXIDLE; 60127d5dc18SMarcel Moolenaar else 6022d511805SMarcel Moolenaar ipend |= SER_INT_SIGCHG; 60327d5dc18SMarcel Moolenaar } 60427d5dc18SMarcel Moolenaar return ((sc->sc_leaving) ? 0 : ipend); 60527d5dc18SMarcel Moolenaar } 60627d5dc18SMarcel Moolenaar 60727d5dc18SMarcel Moolenaar static int 60827d5dc18SMarcel Moolenaar ns8250_bus_param(struct uart_softc *sc, int baudrate, int databits, 60927d5dc18SMarcel Moolenaar int stopbits, int parity) 61027d5dc18SMarcel Moolenaar { 61127d5dc18SMarcel Moolenaar struct uart_bas *bas; 61206287620SMarcel Moolenaar int error; 61327d5dc18SMarcel Moolenaar 61427d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 6158af03381SMarcel Moolenaar uart_lock(sc->sc_hwmtx); 61606287620SMarcel Moolenaar error = ns8250_param(bas, baudrate, databits, stopbits, parity); 6178af03381SMarcel Moolenaar uart_unlock(sc->sc_hwmtx); 61806287620SMarcel Moolenaar return (error); 61927d5dc18SMarcel Moolenaar } 62027d5dc18SMarcel Moolenaar 62127d5dc18SMarcel Moolenaar static int 62227d5dc18SMarcel Moolenaar ns8250_bus_probe(struct uart_softc *sc) 62327d5dc18SMarcel Moolenaar { 6240aefb0a6SBenno Rice struct ns8250_softc *ns8250; 62527d5dc18SMarcel Moolenaar struct uart_bas *bas; 62627d5dc18SMarcel Moolenaar int count, delay, error, limit; 62758957d87SBenno Rice uint8_t lsr, mcr, ier; 62827d5dc18SMarcel Moolenaar 6290aefb0a6SBenno Rice ns8250 = (struct ns8250_softc *)sc; 63027d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 63127d5dc18SMarcel Moolenaar 63227d5dc18SMarcel Moolenaar error = ns8250_probe(bas); 63327d5dc18SMarcel Moolenaar if (error) 63427d5dc18SMarcel Moolenaar return (error); 63527d5dc18SMarcel Moolenaar 63627d5dc18SMarcel Moolenaar mcr = MCR_IE; 63727d5dc18SMarcel Moolenaar if (sc->sc_sysdev == NULL) { 63827d5dc18SMarcel Moolenaar /* By using ns8250_init() we also set DTR and RTS. */ 639d902fb71SMarcel Moolenaar ns8250_init(bas, 115200, 8, 1, UART_PARITY_NONE); 64027d5dc18SMarcel Moolenaar } else 64127d5dc18SMarcel Moolenaar mcr |= MCR_DTR | MCR_RTS; 64227d5dc18SMarcel Moolenaar 64327d5dc18SMarcel Moolenaar error = ns8250_drain(bas, UART_DRAIN_TRANSMITTER); 64427d5dc18SMarcel Moolenaar if (error) 64527d5dc18SMarcel Moolenaar return (error); 64627d5dc18SMarcel Moolenaar 64727d5dc18SMarcel Moolenaar /* 64827d5dc18SMarcel Moolenaar * Set loopback mode. This avoids having garbage on the wire and 64927d5dc18SMarcel Moolenaar * also allows us send and receive data. We set DTR and RTS to 65027d5dc18SMarcel Moolenaar * avoid the possibility that automatic flow-control prevents 65189eef2deSThomas Moestl * any data from being sent. 65227d5dc18SMarcel Moolenaar */ 65389eef2deSThomas Moestl uart_setreg(bas, REG_MCR, MCR_LOOPBACK | MCR_IE | MCR_DTR | MCR_RTS); 65427d5dc18SMarcel Moolenaar uart_barrier(bas); 65527d5dc18SMarcel Moolenaar 65627d5dc18SMarcel Moolenaar /* 65727d5dc18SMarcel Moolenaar * Enable FIFOs. And check that the UART has them. If not, we're 65889eef2deSThomas Moestl * done. Since this is the first time we enable the FIFOs, we reset 65989eef2deSThomas Moestl * them. 66027d5dc18SMarcel Moolenaar */ 66127d5dc18SMarcel Moolenaar uart_setreg(bas, REG_FCR, FCR_ENABLE); 66227d5dc18SMarcel Moolenaar uart_barrier(bas); 6638d1289feSMarcel Moolenaar if (!(uart_getreg(bas, REG_IIR) & IIR_FIFO_MASK)) { 66427d5dc18SMarcel Moolenaar /* 66527d5dc18SMarcel Moolenaar * NS16450 or INS8250. We don't bother to differentiate 66627d5dc18SMarcel Moolenaar * between them. They're too old to be interesting. 66727d5dc18SMarcel Moolenaar */ 66827d5dc18SMarcel Moolenaar uart_setreg(bas, REG_MCR, mcr); 66927d5dc18SMarcel Moolenaar uart_barrier(bas); 6708d1289feSMarcel Moolenaar sc->sc_rxfifosz = sc->sc_txfifosz = 1; 67127d5dc18SMarcel Moolenaar device_set_desc(sc->sc_dev, "8250 or 16450 or compatible"); 67227d5dc18SMarcel Moolenaar return (0); 67327d5dc18SMarcel Moolenaar } 67427d5dc18SMarcel Moolenaar 67589eef2deSThomas Moestl uart_setreg(bas, REG_FCR, FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST); 67627d5dc18SMarcel Moolenaar uart_barrier(bas); 67727d5dc18SMarcel Moolenaar 67827d5dc18SMarcel Moolenaar count = 0; 67927d5dc18SMarcel Moolenaar delay = ns8250_delay(bas); 68027d5dc18SMarcel Moolenaar 68127d5dc18SMarcel Moolenaar /* We have FIFOs. Drain the transmitter and receiver. */ 68227d5dc18SMarcel Moolenaar error = ns8250_drain(bas, UART_DRAIN_RECEIVER|UART_DRAIN_TRANSMITTER); 68327d5dc18SMarcel Moolenaar if (error) { 68427d5dc18SMarcel Moolenaar uart_setreg(bas, REG_MCR, mcr); 68527d5dc18SMarcel Moolenaar uart_setreg(bas, REG_FCR, 0); 68627d5dc18SMarcel Moolenaar uart_barrier(bas); 68727d5dc18SMarcel Moolenaar goto describe; 68827d5dc18SMarcel Moolenaar } 68927d5dc18SMarcel Moolenaar 69027d5dc18SMarcel Moolenaar /* 69127d5dc18SMarcel Moolenaar * We should have a sufficiently clean "pipe" to determine the 69227d5dc18SMarcel Moolenaar * size of the FIFOs. We send as much characters as is reasonable 69389eef2deSThomas Moestl * and wait for the the overflow bit in the LSR register to be 69489eef2deSThomas Moestl * asserted, counting the characters as we send them. Based on 69589eef2deSThomas Moestl * that count we know the FIFO size. 69627d5dc18SMarcel Moolenaar */ 69789eef2deSThomas Moestl do { 69827d5dc18SMarcel Moolenaar uart_setreg(bas, REG_DATA, 0); 69927d5dc18SMarcel Moolenaar uart_barrier(bas); 70027d5dc18SMarcel Moolenaar count++; 70127d5dc18SMarcel Moolenaar 70227d5dc18SMarcel Moolenaar limit = 30; 70389eef2deSThomas Moestl lsr = 0; 70489eef2deSThomas Moestl /* 70589eef2deSThomas Moestl * LSR bits are cleared upon read, so we must accumulate 70689eef2deSThomas Moestl * them to be able to test LSR_OE below. 70789eef2deSThomas Moestl */ 70889eef2deSThomas Moestl while (((lsr |= uart_getreg(bas, REG_LSR)) & LSR_TEMT) == 0 && 70989eef2deSThomas Moestl --limit) 71027d5dc18SMarcel Moolenaar DELAY(delay); 71127d5dc18SMarcel Moolenaar if (limit == 0) { 7120aefb0a6SBenno Rice ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 71358957d87SBenno Rice uart_setreg(bas, REG_IER, ier); 71427d5dc18SMarcel Moolenaar uart_setreg(bas, REG_MCR, mcr); 71527d5dc18SMarcel Moolenaar uart_setreg(bas, REG_FCR, 0); 71627d5dc18SMarcel Moolenaar uart_barrier(bas); 71727d5dc18SMarcel Moolenaar count = 0; 71827d5dc18SMarcel Moolenaar goto describe; 71927d5dc18SMarcel Moolenaar } 720d882cf92SMarcel Moolenaar } while ((lsr & LSR_OE) == 0 && count < 130); 72189eef2deSThomas Moestl count--; 72227d5dc18SMarcel Moolenaar 72327d5dc18SMarcel Moolenaar uart_setreg(bas, REG_MCR, mcr); 72427d5dc18SMarcel Moolenaar 72527d5dc18SMarcel Moolenaar /* Reset FIFOs. */ 72627d5dc18SMarcel Moolenaar ns8250_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 72727d5dc18SMarcel Moolenaar 72827d5dc18SMarcel Moolenaar describe: 72989eef2deSThomas Moestl if (count >= 14 && count <= 16) { 73027d5dc18SMarcel Moolenaar sc->sc_rxfifosz = 16; 73127d5dc18SMarcel Moolenaar device_set_desc(sc->sc_dev, "16550 or compatible"); 73289eef2deSThomas Moestl } else if (count >= 28 && count <= 32) { 73327d5dc18SMarcel Moolenaar sc->sc_rxfifosz = 32; 73427d5dc18SMarcel Moolenaar device_set_desc(sc->sc_dev, "16650 or compatible"); 73589eef2deSThomas Moestl } else if (count >= 56 && count <= 64) { 73627d5dc18SMarcel Moolenaar sc->sc_rxfifosz = 64; 73727d5dc18SMarcel Moolenaar device_set_desc(sc->sc_dev, "16750 or compatible"); 73889eef2deSThomas Moestl } else if (count >= 112 && count <= 128) { 73927d5dc18SMarcel Moolenaar sc->sc_rxfifosz = 128; 74027d5dc18SMarcel Moolenaar device_set_desc(sc->sc_dev, "16950 or compatible"); 74127d5dc18SMarcel Moolenaar } else { 742c21e0da2SMarcel Moolenaar sc->sc_rxfifosz = 16; 74327d5dc18SMarcel Moolenaar device_set_desc(sc->sc_dev, 74427d5dc18SMarcel Moolenaar "Non-standard ns8250 class UART with FIFOs"); 74527d5dc18SMarcel Moolenaar } 74627d5dc18SMarcel Moolenaar 74727d5dc18SMarcel Moolenaar /* 74827d5dc18SMarcel Moolenaar * Force the Tx FIFO size to 16 bytes for now. We don't program the 74927d5dc18SMarcel Moolenaar * Tx trigger. Also, we assume that all data has been sent when the 75027d5dc18SMarcel Moolenaar * interrupt happens. 75127d5dc18SMarcel Moolenaar */ 75227d5dc18SMarcel Moolenaar sc->sc_txfifosz = 16; 75327d5dc18SMarcel Moolenaar 754dc70e792SMarcel Moolenaar #if 0 755dc70e792SMarcel Moolenaar /* 756dc70e792SMarcel Moolenaar * XXX there are some issues related to hardware flow control and 757dc70e792SMarcel Moolenaar * it's likely that uart(4) is the cause. This basicly needs more 758dc70e792SMarcel Moolenaar * investigation, but we avoid using for hardware flow control 759dc70e792SMarcel Moolenaar * until then. 760dc70e792SMarcel Moolenaar */ 76184c7b427SMarcel Moolenaar /* 16650s or higher have automatic flow control. */ 76284c7b427SMarcel Moolenaar if (sc->sc_rxfifosz > 16) { 76384c7b427SMarcel Moolenaar sc->sc_hwiflow = 1; 76484c7b427SMarcel Moolenaar sc->sc_hwoflow = 1; 76584c7b427SMarcel Moolenaar } 766dc70e792SMarcel Moolenaar #endif 76784c7b427SMarcel Moolenaar 76827d5dc18SMarcel Moolenaar return (0); 76927d5dc18SMarcel Moolenaar } 77027d5dc18SMarcel Moolenaar 77127d5dc18SMarcel Moolenaar static int 77227d5dc18SMarcel Moolenaar ns8250_bus_receive(struct uart_softc *sc) 77327d5dc18SMarcel Moolenaar { 77427d5dc18SMarcel Moolenaar struct uart_bas *bas; 77527d5dc18SMarcel Moolenaar int xc; 77627d5dc18SMarcel Moolenaar uint8_t lsr; 77727d5dc18SMarcel Moolenaar 77827d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 7798af03381SMarcel Moolenaar uart_lock(sc->sc_hwmtx); 78027d5dc18SMarcel Moolenaar lsr = uart_getreg(bas, REG_LSR); 78144ed791bSMarcel Moolenaar while (lsr & LSR_RXRDY) { 78244ed791bSMarcel Moolenaar if (uart_rx_full(sc)) { 78344ed791bSMarcel Moolenaar sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; 78427d5dc18SMarcel Moolenaar break; 78544ed791bSMarcel Moolenaar } 78627d5dc18SMarcel Moolenaar xc = uart_getreg(bas, REG_DATA); 78727d5dc18SMarcel Moolenaar if (lsr & LSR_FE) 78827d5dc18SMarcel Moolenaar xc |= UART_STAT_FRAMERR; 78927d5dc18SMarcel Moolenaar if (lsr & LSR_PE) 79027d5dc18SMarcel Moolenaar xc |= UART_STAT_PARERR; 79127d5dc18SMarcel Moolenaar uart_rx_put(sc, xc); 79244ed791bSMarcel Moolenaar lsr = uart_getreg(bas, REG_LSR); 79344ed791bSMarcel Moolenaar } 79444ed791bSMarcel Moolenaar /* Discard everything left in the Rx FIFO. */ 79544ed791bSMarcel Moolenaar while (lsr & LSR_RXRDY) { 79644ed791bSMarcel Moolenaar (void)uart_getreg(bas, REG_DATA); 79744ed791bSMarcel Moolenaar uart_barrier(bas); 79844ed791bSMarcel Moolenaar lsr = uart_getreg(bas, REG_LSR); 79927d5dc18SMarcel Moolenaar } 8008af03381SMarcel Moolenaar uart_unlock(sc->sc_hwmtx); 80127d5dc18SMarcel Moolenaar return (0); 80227d5dc18SMarcel Moolenaar } 80327d5dc18SMarcel Moolenaar 80427d5dc18SMarcel Moolenaar static int 80527d5dc18SMarcel Moolenaar ns8250_bus_setsig(struct uart_softc *sc, int sig) 80627d5dc18SMarcel Moolenaar { 80727d5dc18SMarcel Moolenaar struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 80827d5dc18SMarcel Moolenaar struct uart_bas *bas; 80927d5dc18SMarcel Moolenaar uint32_t new, old; 81027d5dc18SMarcel Moolenaar 81127d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 81227d5dc18SMarcel Moolenaar do { 81327d5dc18SMarcel Moolenaar old = sc->sc_hwsig; 81427d5dc18SMarcel Moolenaar new = old; 81528710806SPoul-Henning Kamp if (sig & SER_DDTR) { 81628710806SPoul-Henning Kamp SIGCHG(sig & SER_DTR, new, SER_DTR, 81728710806SPoul-Henning Kamp SER_DDTR); 81827d5dc18SMarcel Moolenaar } 81928710806SPoul-Henning Kamp if (sig & SER_DRTS) { 82028710806SPoul-Henning Kamp SIGCHG(sig & SER_RTS, new, SER_RTS, 82128710806SPoul-Henning Kamp SER_DRTS); 82227d5dc18SMarcel Moolenaar } 82327d5dc18SMarcel Moolenaar } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 8248af03381SMarcel Moolenaar uart_lock(sc->sc_hwmtx); 82527d5dc18SMarcel Moolenaar ns8250->mcr &= ~(MCR_DTR|MCR_RTS); 82628710806SPoul-Henning Kamp if (new & SER_DTR) 82727d5dc18SMarcel Moolenaar ns8250->mcr |= MCR_DTR; 82828710806SPoul-Henning Kamp if (new & SER_RTS) 82927d5dc18SMarcel Moolenaar ns8250->mcr |= MCR_RTS; 83027d5dc18SMarcel Moolenaar uart_setreg(bas, REG_MCR, ns8250->mcr); 83127d5dc18SMarcel Moolenaar uart_barrier(bas); 8328af03381SMarcel Moolenaar uart_unlock(sc->sc_hwmtx); 83327d5dc18SMarcel Moolenaar return (0); 83427d5dc18SMarcel Moolenaar } 83527d5dc18SMarcel Moolenaar 83627d5dc18SMarcel Moolenaar static int 83727d5dc18SMarcel Moolenaar ns8250_bus_transmit(struct uart_softc *sc) 83827d5dc18SMarcel Moolenaar { 83927d5dc18SMarcel Moolenaar struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 84027d5dc18SMarcel Moolenaar struct uart_bas *bas; 84127d5dc18SMarcel Moolenaar int i; 84227d5dc18SMarcel Moolenaar 84327d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 8448af03381SMarcel Moolenaar uart_lock(sc->sc_hwmtx); 84527d5dc18SMarcel Moolenaar while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0) 84627d5dc18SMarcel Moolenaar ; 84727d5dc18SMarcel Moolenaar uart_setreg(bas, REG_IER, ns8250->ier | IER_ETXRDY); 84827d5dc18SMarcel Moolenaar uart_barrier(bas); 84927d5dc18SMarcel Moolenaar for (i = 0; i < sc->sc_txdatasz; i++) { 85027d5dc18SMarcel Moolenaar uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]); 85127d5dc18SMarcel Moolenaar uart_barrier(bas); 85227d5dc18SMarcel Moolenaar } 85327d5dc18SMarcel Moolenaar sc->sc_txbusy = 1; 8548af03381SMarcel Moolenaar uart_unlock(sc->sc_hwmtx); 85527d5dc18SMarcel Moolenaar return (0); 85627d5dc18SMarcel Moolenaar } 857