1098ca2bdSWarner Losh /*- 227d5dc18SMarcel Moolenaar * Copyright (c) 2003 Marcel Moolenaar 327d5dc18SMarcel Moolenaar * All rights reserved. 427d5dc18SMarcel Moolenaar * 527d5dc18SMarcel Moolenaar * Redistribution and use in source and binary forms, with or without 627d5dc18SMarcel Moolenaar * modification, are permitted provided that the following conditions 727d5dc18SMarcel Moolenaar * are met: 827d5dc18SMarcel Moolenaar * 927d5dc18SMarcel Moolenaar * 1. Redistributions of source code must retain the above copyright 1027d5dc18SMarcel Moolenaar * notice, this list of conditions and the following disclaimer. 1127d5dc18SMarcel Moolenaar * 2. Redistributions in binary form must reproduce the above copyright 1227d5dc18SMarcel Moolenaar * notice, this list of conditions and the following disclaimer in the 1327d5dc18SMarcel Moolenaar * documentation and/or other materials provided with the distribution. 1427d5dc18SMarcel Moolenaar * 1527d5dc18SMarcel Moolenaar * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 1627d5dc18SMarcel Moolenaar * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 1727d5dc18SMarcel Moolenaar * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 1827d5dc18SMarcel Moolenaar * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 1927d5dc18SMarcel Moolenaar * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 2027d5dc18SMarcel Moolenaar * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2127d5dc18SMarcel Moolenaar * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2227d5dc18SMarcel Moolenaar * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2327d5dc18SMarcel Moolenaar * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 2427d5dc18SMarcel Moolenaar * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2527d5dc18SMarcel Moolenaar */ 2627d5dc18SMarcel Moolenaar 27ac4adddfSGanbold Tsagaankhuu #include "opt_platform.h" 28ac4adddfSGanbold Tsagaankhuu 2927d5dc18SMarcel Moolenaar #include <sys/cdefs.h> 3027d5dc18SMarcel Moolenaar __FBSDID("$FreeBSD$"); 3127d5dc18SMarcel Moolenaar 3227d5dc18SMarcel Moolenaar #include <sys/param.h> 3327d5dc18SMarcel Moolenaar #include <sys/systm.h> 3427d5dc18SMarcel Moolenaar #include <sys/bus.h> 3527d5dc18SMarcel Moolenaar #include <sys/conf.h> 361c60b24bSColin Percival #include <sys/kernel.h> 371c60b24bSColin Percival #include <sys/sysctl.h> 3827d5dc18SMarcel Moolenaar #include <machine/bus.h> 3927d5dc18SMarcel Moolenaar 40ac4adddfSGanbold Tsagaankhuu #ifdef FDT 41ac4adddfSGanbold Tsagaankhuu #include <dev/fdt/fdt_common.h> 42ac4adddfSGanbold Tsagaankhuu #include <dev/ofw/ofw_bus.h> 43ac4adddfSGanbold Tsagaankhuu #include <dev/ofw/ofw_bus_subr.h> 44ac4adddfSGanbold Tsagaankhuu #endif 45ac4adddfSGanbold Tsagaankhuu 4627d5dc18SMarcel Moolenaar #include <dev/uart/uart.h> 4727d5dc18SMarcel Moolenaar #include <dev/uart/uart_cpu.h> 4827d5dc18SMarcel Moolenaar #include <dev/uart/uart_bus.h> 49167cb33fSIan Lepore #include <dev/uart/uart_dev_ns8250.h> 5076563beaSMarcel Moolenaar 5176563beaSMarcel Moolenaar #include <dev/ic/ns16550.h> 5227d5dc18SMarcel Moolenaar 5327d5dc18SMarcel Moolenaar #include "uart_if.h" 5427d5dc18SMarcel Moolenaar 5527d5dc18SMarcel Moolenaar #define DEFAULT_RCLK 1843200 5627d5dc18SMarcel Moolenaar 57ac4adddfSGanbold Tsagaankhuu static int broken_txfifo = 0; 58ac4adddfSGanbold Tsagaankhuu SYSCTL_INT(_hw, OID_AUTO, broken_txfifo, CTLFLAG_RW | CTLFLAG_TUN, 59ac4adddfSGanbold Tsagaankhuu &broken_txfifo, 0, "UART FIFO has QEMU emulation bug"); 60ac4adddfSGanbold Tsagaankhuu TUNABLE_INT("hw.broken_txfifo", &broken_txfifo); 61ac4adddfSGanbold Tsagaankhuu 6227d5dc18SMarcel Moolenaar /* 6327d5dc18SMarcel Moolenaar * Clear pending interrupts. THRE is cleared by reading IIR. Data 6427d5dc18SMarcel Moolenaar * that may have been received gets lost here. 6527d5dc18SMarcel Moolenaar */ 6627d5dc18SMarcel Moolenaar static void 6727d5dc18SMarcel Moolenaar ns8250_clrint(struct uart_bas *bas) 6827d5dc18SMarcel Moolenaar { 69d7ae5af5SMarcel Moolenaar uint8_t iir, lsr; 7027d5dc18SMarcel Moolenaar 7127d5dc18SMarcel Moolenaar iir = uart_getreg(bas, REG_IIR); 7227d5dc18SMarcel Moolenaar while ((iir & IIR_NOPEND) == 0) { 7327d5dc18SMarcel Moolenaar iir &= IIR_IMASK; 74d7ae5af5SMarcel Moolenaar if (iir == IIR_RLS) { 75d7ae5af5SMarcel Moolenaar lsr = uart_getreg(bas, REG_LSR); 76d7ae5af5SMarcel Moolenaar if (lsr & (LSR_BI|LSR_FE|LSR_PE)) 77d7ae5af5SMarcel Moolenaar (void)uart_getreg(bas, REG_DATA); 78d7ae5af5SMarcel Moolenaar } else if (iir == IIR_RXRDY || iir == IIR_RXTOUT) 7927d5dc18SMarcel Moolenaar (void)uart_getreg(bas, REG_DATA); 8027d5dc18SMarcel Moolenaar else if (iir == IIR_MLSC) 8127d5dc18SMarcel Moolenaar (void)uart_getreg(bas, REG_MSR); 8227d5dc18SMarcel Moolenaar uart_barrier(bas); 8327d5dc18SMarcel Moolenaar iir = uart_getreg(bas, REG_IIR); 8427d5dc18SMarcel Moolenaar } 8527d5dc18SMarcel Moolenaar } 8627d5dc18SMarcel Moolenaar 8727d5dc18SMarcel Moolenaar static int 8827d5dc18SMarcel Moolenaar ns8250_delay(struct uart_bas *bas) 8927d5dc18SMarcel Moolenaar { 9027d5dc18SMarcel Moolenaar int divisor; 9127d5dc18SMarcel Moolenaar u_char lcr; 9227d5dc18SMarcel Moolenaar 9327d5dc18SMarcel Moolenaar lcr = uart_getreg(bas, REG_LCR); 9427d5dc18SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 9527d5dc18SMarcel Moolenaar uart_barrier(bas); 9658957d87SBenno Rice divisor = uart_getreg(bas, REG_DLL) | (uart_getreg(bas, REG_DLH) << 8); 9727d5dc18SMarcel Moolenaar uart_barrier(bas); 9827d5dc18SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr); 9927d5dc18SMarcel Moolenaar uart_barrier(bas); 10027d5dc18SMarcel Moolenaar 10127d5dc18SMarcel Moolenaar /* 1/10th the time to transmit 1 character (estimate). */ 102ebecffe9SMarcel Moolenaar if (divisor <= 134) 10327d5dc18SMarcel Moolenaar return (16000000 * divisor / bas->rclk); 104ebecffe9SMarcel Moolenaar return (16000 * divisor / (bas->rclk / 1000)); 10527d5dc18SMarcel Moolenaar } 10627d5dc18SMarcel Moolenaar 10727d5dc18SMarcel Moolenaar static int 10827d5dc18SMarcel Moolenaar ns8250_divisor(int rclk, int baudrate) 10927d5dc18SMarcel Moolenaar { 11027d5dc18SMarcel Moolenaar int actual_baud, divisor; 11127d5dc18SMarcel Moolenaar int error; 11227d5dc18SMarcel Moolenaar 11327d5dc18SMarcel Moolenaar if (baudrate == 0) 11427d5dc18SMarcel Moolenaar return (0); 11527d5dc18SMarcel Moolenaar 11627d5dc18SMarcel Moolenaar divisor = (rclk / (baudrate << 3) + 1) >> 1; 11727d5dc18SMarcel Moolenaar if (divisor == 0 || divisor >= 65536) 11827d5dc18SMarcel Moolenaar return (0); 11927d5dc18SMarcel Moolenaar actual_baud = rclk / (divisor << 4); 12027d5dc18SMarcel Moolenaar 12127d5dc18SMarcel Moolenaar /* 10 times error in percent: */ 12227d5dc18SMarcel Moolenaar error = ((actual_baud - baudrate) * 2000 / baudrate + 1) >> 1; 12327d5dc18SMarcel Moolenaar 12427d5dc18SMarcel Moolenaar /* 3.0% maximum error tolerance: */ 12527d5dc18SMarcel Moolenaar if (error < -30 || error > 30) 12627d5dc18SMarcel Moolenaar return (0); 12727d5dc18SMarcel Moolenaar 12827d5dc18SMarcel Moolenaar return (divisor); 12927d5dc18SMarcel Moolenaar } 13027d5dc18SMarcel Moolenaar 13127d5dc18SMarcel Moolenaar static int 13227d5dc18SMarcel Moolenaar ns8250_drain(struct uart_bas *bas, int what) 13327d5dc18SMarcel Moolenaar { 13427d5dc18SMarcel Moolenaar int delay, limit; 13527d5dc18SMarcel Moolenaar 13627d5dc18SMarcel Moolenaar delay = ns8250_delay(bas); 13727d5dc18SMarcel Moolenaar 13827d5dc18SMarcel Moolenaar if (what & UART_DRAIN_TRANSMITTER) { 13927d5dc18SMarcel Moolenaar /* 14027d5dc18SMarcel Moolenaar * Pick an arbitrary high limit to avoid getting stuck in 14127d5dc18SMarcel Moolenaar * an infinite loop when the hardware is broken. Make the 14227d5dc18SMarcel Moolenaar * limit high enough to handle large FIFOs. 14327d5dc18SMarcel Moolenaar */ 14427d5dc18SMarcel Moolenaar limit = 10*1024; 14527d5dc18SMarcel Moolenaar while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) 14627d5dc18SMarcel Moolenaar DELAY(delay); 14727d5dc18SMarcel Moolenaar if (limit == 0) { 14827d5dc18SMarcel Moolenaar /* printf("ns8250: transmitter appears stuck... "); */ 14927d5dc18SMarcel Moolenaar return (EIO); 15027d5dc18SMarcel Moolenaar } 15127d5dc18SMarcel Moolenaar } 15227d5dc18SMarcel Moolenaar 15327d5dc18SMarcel Moolenaar if (what & UART_DRAIN_RECEIVER) { 15427d5dc18SMarcel Moolenaar /* 15527d5dc18SMarcel Moolenaar * Pick an arbitrary high limit to avoid getting stuck in 15627d5dc18SMarcel Moolenaar * an infinite loop when the hardware is broken. Make the 15727d5dc18SMarcel Moolenaar * limit high enough to handle large FIFOs and integrated 15827d5dc18SMarcel Moolenaar * UARTs. The HP rx2600 for example has 3 UARTs on the 15927d5dc18SMarcel Moolenaar * management board that tend to get a lot of data send 16027d5dc18SMarcel Moolenaar * to it when the UART is first activated. 16127d5dc18SMarcel Moolenaar */ 16227d5dc18SMarcel Moolenaar limit=10*4096; 16327d5dc18SMarcel Moolenaar while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) { 16427d5dc18SMarcel Moolenaar (void)uart_getreg(bas, REG_DATA); 16527d5dc18SMarcel Moolenaar uart_barrier(bas); 16627d5dc18SMarcel Moolenaar DELAY(delay << 2); 16727d5dc18SMarcel Moolenaar } 16827d5dc18SMarcel Moolenaar if (limit == 0) { 16927d5dc18SMarcel Moolenaar /* printf("ns8250: receiver appears broken... "); */ 17027d5dc18SMarcel Moolenaar return (EIO); 17127d5dc18SMarcel Moolenaar } 17227d5dc18SMarcel Moolenaar } 17327d5dc18SMarcel Moolenaar 17427d5dc18SMarcel Moolenaar return (0); 17527d5dc18SMarcel Moolenaar } 17627d5dc18SMarcel Moolenaar 17727d5dc18SMarcel Moolenaar /* 17827d5dc18SMarcel Moolenaar * We can only flush UARTs with FIFOs. UARTs without FIFOs should be 17927d5dc18SMarcel Moolenaar * drained. WARNING: this function clobbers the FIFO setting! 18027d5dc18SMarcel Moolenaar */ 18127d5dc18SMarcel Moolenaar static void 18227d5dc18SMarcel Moolenaar ns8250_flush(struct uart_bas *bas, int what) 18327d5dc18SMarcel Moolenaar { 18427d5dc18SMarcel Moolenaar uint8_t fcr; 18527d5dc18SMarcel Moolenaar 18627d5dc18SMarcel Moolenaar fcr = FCR_ENABLE; 18727d5dc18SMarcel Moolenaar if (what & UART_FLUSH_TRANSMITTER) 18827d5dc18SMarcel Moolenaar fcr |= FCR_XMT_RST; 18927d5dc18SMarcel Moolenaar if (what & UART_FLUSH_RECEIVER) 19027d5dc18SMarcel Moolenaar fcr |= FCR_RCV_RST; 19127d5dc18SMarcel Moolenaar uart_setreg(bas, REG_FCR, fcr); 19227d5dc18SMarcel Moolenaar uart_barrier(bas); 19327d5dc18SMarcel Moolenaar } 19427d5dc18SMarcel Moolenaar 19527d5dc18SMarcel Moolenaar static int 19627d5dc18SMarcel Moolenaar ns8250_param(struct uart_bas *bas, int baudrate, int databits, int stopbits, 19727d5dc18SMarcel Moolenaar int parity) 19827d5dc18SMarcel Moolenaar { 19927d5dc18SMarcel Moolenaar int divisor; 20027d5dc18SMarcel Moolenaar uint8_t lcr; 20127d5dc18SMarcel Moolenaar 20227d5dc18SMarcel Moolenaar lcr = 0; 20327d5dc18SMarcel Moolenaar if (databits >= 8) 20427d5dc18SMarcel Moolenaar lcr |= LCR_8BITS; 20527d5dc18SMarcel Moolenaar else if (databits == 7) 20627d5dc18SMarcel Moolenaar lcr |= LCR_7BITS; 20727d5dc18SMarcel Moolenaar else if (databits == 6) 20827d5dc18SMarcel Moolenaar lcr |= LCR_6BITS; 20927d5dc18SMarcel Moolenaar else 21027d5dc18SMarcel Moolenaar lcr |= LCR_5BITS; 21127d5dc18SMarcel Moolenaar if (stopbits > 1) 21227d5dc18SMarcel Moolenaar lcr |= LCR_STOPB; 21327d5dc18SMarcel Moolenaar lcr |= parity << 3; 21427d5dc18SMarcel Moolenaar 21527d5dc18SMarcel Moolenaar /* Set baudrate. */ 21627d5dc18SMarcel Moolenaar if (baudrate > 0) { 21727d5dc18SMarcel Moolenaar divisor = ns8250_divisor(bas->rclk, baudrate); 21827d5dc18SMarcel Moolenaar if (divisor == 0) 21927d5dc18SMarcel Moolenaar return (EINVAL); 22063f8efd3SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 22163f8efd3SMarcel Moolenaar uart_barrier(bas); 22258957d87SBenno Rice uart_setreg(bas, REG_DLL, divisor & 0xff); 22358957d87SBenno Rice uart_setreg(bas, REG_DLH, (divisor >> 8) & 0xff); 22427d5dc18SMarcel Moolenaar uart_barrier(bas); 22527d5dc18SMarcel Moolenaar } 22627d5dc18SMarcel Moolenaar 22727d5dc18SMarcel Moolenaar /* Set LCR and clear DLAB. */ 22827d5dc18SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr); 22927d5dc18SMarcel Moolenaar uart_barrier(bas); 23027d5dc18SMarcel Moolenaar return (0); 23127d5dc18SMarcel Moolenaar } 23227d5dc18SMarcel Moolenaar 23327d5dc18SMarcel Moolenaar /* 23427d5dc18SMarcel Moolenaar * Low-level UART interface. 23527d5dc18SMarcel Moolenaar */ 23627d5dc18SMarcel Moolenaar static int ns8250_probe(struct uart_bas *bas); 23727d5dc18SMarcel Moolenaar static void ns8250_init(struct uart_bas *bas, int, int, int, int); 23827d5dc18SMarcel Moolenaar static void ns8250_term(struct uart_bas *bas); 23927d5dc18SMarcel Moolenaar static void ns8250_putc(struct uart_bas *bas, int); 24097202af2SMarius Strobl static int ns8250_rxready(struct uart_bas *bas); 241634e63c9SMarcel Moolenaar static int ns8250_getc(struct uart_bas *bas, struct mtx *); 24227d5dc18SMarcel Moolenaar 243167cb33fSIan Lepore struct uart_ops uart_ns8250_ops = { 24427d5dc18SMarcel Moolenaar .probe = ns8250_probe, 24527d5dc18SMarcel Moolenaar .init = ns8250_init, 24627d5dc18SMarcel Moolenaar .term = ns8250_term, 24727d5dc18SMarcel Moolenaar .putc = ns8250_putc, 24897202af2SMarius Strobl .rxready = ns8250_rxready, 24927d5dc18SMarcel Moolenaar .getc = ns8250_getc, 25027d5dc18SMarcel Moolenaar }; 25127d5dc18SMarcel Moolenaar 25227d5dc18SMarcel Moolenaar static int 25327d5dc18SMarcel Moolenaar ns8250_probe(struct uart_bas *bas) 25427d5dc18SMarcel Moolenaar { 2558bceca4fSBenno Rice u_char val; 25627d5dc18SMarcel Moolenaar 25727d5dc18SMarcel Moolenaar /* Check known 0 bits that don't depend on DLAB. */ 25827d5dc18SMarcel Moolenaar val = uart_getreg(bas, REG_IIR); 25927d5dc18SMarcel Moolenaar if (val & 0x30) 26027d5dc18SMarcel Moolenaar return (ENXIO); 2615bdddc29SMarcel Moolenaar /* 2625bdddc29SMarcel Moolenaar * Bit 6 of the MCR (= 0x40) appears to be 1 for the Sun1699 2635bdddc29SMarcel Moolenaar * chip, but otherwise doesn't seem to have a function. In 2645bdddc29SMarcel Moolenaar * other words, uart(4) works regardless. Ignore that bit so 2655bdddc29SMarcel Moolenaar * the probe succeeds. 2665bdddc29SMarcel Moolenaar */ 26727d5dc18SMarcel Moolenaar val = uart_getreg(bas, REG_MCR); 2685bdddc29SMarcel Moolenaar if (val & 0xa0) 26927d5dc18SMarcel Moolenaar return (ENXIO); 27027d5dc18SMarcel Moolenaar 27127d5dc18SMarcel Moolenaar return (0); 27227d5dc18SMarcel Moolenaar } 27327d5dc18SMarcel Moolenaar 27427d5dc18SMarcel Moolenaar static void 27527d5dc18SMarcel Moolenaar ns8250_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, 27627d5dc18SMarcel Moolenaar int parity) 27727d5dc18SMarcel Moolenaar { 27858957d87SBenno Rice u_char ier; 27927d5dc18SMarcel Moolenaar 28027d5dc18SMarcel Moolenaar if (bas->rclk == 0) 28127d5dc18SMarcel Moolenaar bas->rclk = DEFAULT_RCLK; 28227d5dc18SMarcel Moolenaar ns8250_param(bas, baudrate, databits, stopbits, parity); 28327d5dc18SMarcel Moolenaar 28427d5dc18SMarcel Moolenaar /* Disable all interrupt sources. */ 2850aefb0a6SBenno Rice /* 2860aefb0a6SBenno Rice * We use 0xe0 instead of 0xf0 as the mask because the XScale PXA 2870aefb0a6SBenno Rice * UARTs split the receive time-out interrupt bit out separately as 2880aefb0a6SBenno Rice * 0x10. This gets handled by ier_mask and ier_rxbits below. 2890aefb0a6SBenno Rice */ 2900aefb0a6SBenno Rice ier = uart_getreg(bas, REG_IER) & 0xe0; 29158957d87SBenno Rice uart_setreg(bas, REG_IER, ier); 29227d5dc18SMarcel Moolenaar uart_barrier(bas); 29327d5dc18SMarcel Moolenaar 29427d5dc18SMarcel Moolenaar /* Disable the FIFO (if present). */ 29527d5dc18SMarcel Moolenaar uart_setreg(bas, REG_FCR, 0); 29627d5dc18SMarcel Moolenaar uart_barrier(bas); 29727d5dc18SMarcel Moolenaar 29827d5dc18SMarcel Moolenaar /* Set RTS & DTR. */ 29927d5dc18SMarcel Moolenaar uart_setreg(bas, REG_MCR, MCR_IE | MCR_RTS | MCR_DTR); 30027d5dc18SMarcel Moolenaar uart_barrier(bas); 30127d5dc18SMarcel Moolenaar 30227d5dc18SMarcel Moolenaar ns8250_clrint(bas); 30327d5dc18SMarcel Moolenaar } 30427d5dc18SMarcel Moolenaar 30527d5dc18SMarcel Moolenaar static void 30627d5dc18SMarcel Moolenaar ns8250_term(struct uart_bas *bas) 30727d5dc18SMarcel Moolenaar { 30827d5dc18SMarcel Moolenaar 30927d5dc18SMarcel Moolenaar /* Clear RTS & DTR. */ 31027d5dc18SMarcel Moolenaar uart_setreg(bas, REG_MCR, MCR_IE); 31127d5dc18SMarcel Moolenaar uart_barrier(bas); 31227d5dc18SMarcel Moolenaar } 31327d5dc18SMarcel Moolenaar 31427d5dc18SMarcel Moolenaar static void 31527d5dc18SMarcel Moolenaar ns8250_putc(struct uart_bas *bas, int c) 31627d5dc18SMarcel Moolenaar { 31735777a2aSMarcel Moolenaar int limit; 31827d5dc18SMarcel Moolenaar 31935777a2aSMarcel Moolenaar limit = 250000; 32027d5dc18SMarcel Moolenaar while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0 && --limit) 32135777a2aSMarcel Moolenaar DELAY(4); 32227d5dc18SMarcel Moolenaar uart_setreg(bas, REG_DATA, c); 3234e55f723SMarcel Moolenaar uart_barrier(bas); 32435777a2aSMarcel Moolenaar limit = 250000; 32527d5dc18SMarcel Moolenaar while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) 32635777a2aSMarcel Moolenaar DELAY(4); 32727d5dc18SMarcel Moolenaar } 32827d5dc18SMarcel Moolenaar 32927d5dc18SMarcel Moolenaar static int 33097202af2SMarius Strobl ns8250_rxready(struct uart_bas *bas) 33127d5dc18SMarcel Moolenaar { 33227d5dc18SMarcel Moolenaar 33397202af2SMarius Strobl return ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) != 0 ? 1 : 0); 33427d5dc18SMarcel Moolenaar } 33527d5dc18SMarcel Moolenaar 33627d5dc18SMarcel Moolenaar static int 337634e63c9SMarcel Moolenaar ns8250_getc(struct uart_bas *bas, struct mtx *hwmtx) 33827d5dc18SMarcel Moolenaar { 33935777a2aSMarcel Moolenaar int c; 340634e63c9SMarcel Moolenaar 341634e63c9SMarcel Moolenaar uart_lock(hwmtx); 34227d5dc18SMarcel Moolenaar 343634e63c9SMarcel Moolenaar while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0) { 344634e63c9SMarcel Moolenaar uart_unlock(hwmtx); 34535777a2aSMarcel Moolenaar DELAY(4); 346634e63c9SMarcel Moolenaar uart_lock(hwmtx); 347634e63c9SMarcel Moolenaar } 348634e63c9SMarcel Moolenaar 349634e63c9SMarcel Moolenaar c = uart_getreg(bas, REG_DATA); 350634e63c9SMarcel Moolenaar 351634e63c9SMarcel Moolenaar uart_unlock(hwmtx); 352634e63c9SMarcel Moolenaar 353634e63c9SMarcel Moolenaar return (c); 35427d5dc18SMarcel Moolenaar } 35527d5dc18SMarcel Moolenaar 35627d5dc18SMarcel Moolenaar static kobj_method_t ns8250_methods[] = { 35727d5dc18SMarcel Moolenaar KOBJMETHOD(uart_attach, ns8250_bus_attach), 35827d5dc18SMarcel Moolenaar KOBJMETHOD(uart_detach, ns8250_bus_detach), 35927d5dc18SMarcel Moolenaar KOBJMETHOD(uart_flush, ns8250_bus_flush), 36027d5dc18SMarcel Moolenaar KOBJMETHOD(uart_getsig, ns8250_bus_getsig), 36127d5dc18SMarcel Moolenaar KOBJMETHOD(uart_ioctl, ns8250_bus_ioctl), 36227d5dc18SMarcel Moolenaar KOBJMETHOD(uart_ipend, ns8250_bus_ipend), 36327d5dc18SMarcel Moolenaar KOBJMETHOD(uart_param, ns8250_bus_param), 36427d5dc18SMarcel Moolenaar KOBJMETHOD(uart_probe, ns8250_bus_probe), 36527d5dc18SMarcel Moolenaar KOBJMETHOD(uart_receive, ns8250_bus_receive), 36627d5dc18SMarcel Moolenaar KOBJMETHOD(uart_setsig, ns8250_bus_setsig), 36727d5dc18SMarcel Moolenaar KOBJMETHOD(uart_transmit, ns8250_bus_transmit), 36827d5dc18SMarcel Moolenaar { 0, 0 } 36927d5dc18SMarcel Moolenaar }; 37027d5dc18SMarcel Moolenaar 37127d5dc18SMarcel Moolenaar struct uart_class uart_ns8250_class = { 372f8100ce2SMarcel Moolenaar "ns8250", 37327d5dc18SMarcel Moolenaar ns8250_methods, 37427d5dc18SMarcel Moolenaar sizeof(struct ns8250_softc), 375f8100ce2SMarcel Moolenaar .uc_ops = &uart_ns8250_ops, 37627d5dc18SMarcel Moolenaar .uc_range = 8, 37727d5dc18SMarcel Moolenaar .uc_rclk = DEFAULT_RCLK 37827d5dc18SMarcel Moolenaar }; 37927d5dc18SMarcel Moolenaar 38027d5dc18SMarcel Moolenaar #define SIGCHG(c, i, s, d) \ 38127d5dc18SMarcel Moolenaar if (c) { \ 38227d5dc18SMarcel Moolenaar i |= (i & s) ? s : s | d; \ 38327d5dc18SMarcel Moolenaar } else { \ 38427d5dc18SMarcel Moolenaar i = (i & s) ? (i & ~s) | d : i; \ 38527d5dc18SMarcel Moolenaar } 38627d5dc18SMarcel Moolenaar 387167cb33fSIan Lepore int 38827d5dc18SMarcel Moolenaar ns8250_bus_attach(struct uart_softc *sc) 38927d5dc18SMarcel Moolenaar { 39027d5dc18SMarcel Moolenaar struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 39127d5dc18SMarcel Moolenaar struct uart_bas *bas; 392823c77d7SSam Leffler unsigned int ivar; 393ac4adddfSGanbold Tsagaankhuu #ifdef FDT 394ac4adddfSGanbold Tsagaankhuu phandle_t node; 395ac4adddfSGanbold Tsagaankhuu pcell_t cell; 396ac4adddfSGanbold Tsagaankhuu #endif 397ac4adddfSGanbold Tsagaankhuu 398ac4adddfSGanbold Tsagaankhuu ns8250->busy_detect = 0; 399ac4adddfSGanbold Tsagaankhuu 400ac4adddfSGanbold Tsagaankhuu #ifdef FDT 401ac4adddfSGanbold Tsagaankhuu /* 402ac4adddfSGanbold Tsagaankhuu * Check whether uart requires to read USR reg when IIR_BUSY and 403ac4adddfSGanbold Tsagaankhuu * has broken txfifo. 404ac4adddfSGanbold Tsagaankhuu */ 405ac4adddfSGanbold Tsagaankhuu node = ofw_bus_get_node(sc->sc_dev); 406ac4adddfSGanbold Tsagaankhuu if ((OF_getprop(node, "busy-detect", &cell, sizeof(cell))) > 0) 407ac4adddfSGanbold Tsagaankhuu ns8250->busy_detect = 1; 408ac4adddfSGanbold Tsagaankhuu if ((OF_getprop(node, "broken-txfifo", &cell, sizeof(cell))) > 0) 409ac4adddfSGanbold Tsagaankhuu broken_txfifo = 1; 410ac4adddfSGanbold Tsagaankhuu #endif 41127d5dc18SMarcel Moolenaar 41227d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 41327d5dc18SMarcel Moolenaar 41427d5dc18SMarcel Moolenaar ns8250->mcr = uart_getreg(bas, REG_MCR); 415823c77d7SSam Leffler ns8250->fcr = FCR_ENABLE; 416823c77d7SSam Leffler if (!resource_int_value("uart", device_get_unit(sc->sc_dev), "flags", 417823c77d7SSam Leffler &ivar)) { 418823c77d7SSam Leffler if (UART_FLAGS_FCR_RX_LOW(ivar)) 419823c77d7SSam Leffler ns8250->fcr |= FCR_RX_LOW; 420823c77d7SSam Leffler else if (UART_FLAGS_FCR_RX_MEDL(ivar)) 421823c77d7SSam Leffler ns8250->fcr |= FCR_RX_MEDL; 422823c77d7SSam Leffler else if (UART_FLAGS_FCR_RX_HIGH(ivar)) 423823c77d7SSam Leffler ns8250->fcr |= FCR_RX_HIGH; 424823c77d7SSam Leffler else 425823c77d7SSam Leffler ns8250->fcr |= FCR_RX_MEDH; 426823c77d7SSam Leffler } else 427823c77d7SSam Leffler ns8250->fcr |= FCR_RX_MEDH; 4280aefb0a6SBenno Rice 4290aefb0a6SBenno Rice /* Get IER mask */ 4300aefb0a6SBenno Rice ivar = 0xf0; 4310aefb0a6SBenno Rice resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_mask", 4320aefb0a6SBenno Rice &ivar); 4330aefb0a6SBenno Rice ns8250->ier_mask = (uint8_t)(ivar & 0xff); 4340aefb0a6SBenno Rice 4350aefb0a6SBenno Rice /* Get IER RX interrupt bits */ 4360aefb0a6SBenno Rice ivar = IER_EMSC | IER_ERLS | IER_ERXRDY; 4370aefb0a6SBenno Rice resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_rxbits", 4380aefb0a6SBenno Rice &ivar); 4390aefb0a6SBenno Rice ns8250->ier_rxbits = (uint8_t)(ivar & 0xff); 4400aefb0a6SBenno Rice 44127d5dc18SMarcel Moolenaar uart_setreg(bas, REG_FCR, ns8250->fcr); 44227d5dc18SMarcel Moolenaar uart_barrier(bas); 44327d5dc18SMarcel Moolenaar ns8250_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 44427d5dc18SMarcel Moolenaar 44527d5dc18SMarcel Moolenaar if (ns8250->mcr & MCR_DTR) 44628710806SPoul-Henning Kamp sc->sc_hwsig |= SER_DTR; 44727d5dc18SMarcel Moolenaar if (ns8250->mcr & MCR_RTS) 44828710806SPoul-Henning Kamp sc->sc_hwsig |= SER_RTS; 44927d5dc18SMarcel Moolenaar ns8250_bus_getsig(sc); 45027d5dc18SMarcel Moolenaar 45127d5dc18SMarcel Moolenaar ns8250_clrint(bas); 4520aefb0a6SBenno Rice ns8250->ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 4530aefb0a6SBenno Rice ns8250->ier |= ns8250->ier_rxbits; 45427d5dc18SMarcel Moolenaar uart_setreg(bas, REG_IER, ns8250->ier); 45527d5dc18SMarcel Moolenaar uart_barrier(bas); 4560aefb0a6SBenno Rice 45727d5dc18SMarcel Moolenaar return (0); 45827d5dc18SMarcel Moolenaar } 45927d5dc18SMarcel Moolenaar 460167cb33fSIan Lepore int 46127d5dc18SMarcel Moolenaar ns8250_bus_detach(struct uart_softc *sc) 46227d5dc18SMarcel Moolenaar { 4630aefb0a6SBenno Rice struct ns8250_softc *ns8250; 46427d5dc18SMarcel Moolenaar struct uart_bas *bas; 46558957d87SBenno Rice u_char ier; 46627d5dc18SMarcel Moolenaar 4670aefb0a6SBenno Rice ns8250 = (struct ns8250_softc *)sc; 46827d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 4690aefb0a6SBenno Rice ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 47058957d87SBenno Rice uart_setreg(bas, REG_IER, ier); 47127d5dc18SMarcel Moolenaar uart_barrier(bas); 47227d5dc18SMarcel Moolenaar ns8250_clrint(bas); 47327d5dc18SMarcel Moolenaar return (0); 47427d5dc18SMarcel Moolenaar } 47527d5dc18SMarcel Moolenaar 476167cb33fSIan Lepore int 47727d5dc18SMarcel Moolenaar ns8250_bus_flush(struct uart_softc *sc, int what) 47827d5dc18SMarcel Moolenaar { 47927d5dc18SMarcel Moolenaar struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 48027d5dc18SMarcel Moolenaar struct uart_bas *bas; 48106287620SMarcel Moolenaar int error; 48227d5dc18SMarcel Moolenaar 48327d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 4848af03381SMarcel Moolenaar uart_lock(sc->sc_hwmtx); 4858d1289feSMarcel Moolenaar if (sc->sc_rxfifosz > 1) { 48627d5dc18SMarcel Moolenaar ns8250_flush(bas, what); 48727d5dc18SMarcel Moolenaar uart_setreg(bas, REG_FCR, ns8250->fcr); 48827d5dc18SMarcel Moolenaar uart_barrier(bas); 48906287620SMarcel Moolenaar error = 0; 49006287620SMarcel Moolenaar } else 49106287620SMarcel Moolenaar error = ns8250_drain(bas, what); 4928af03381SMarcel Moolenaar uart_unlock(sc->sc_hwmtx); 49306287620SMarcel Moolenaar return (error); 49427d5dc18SMarcel Moolenaar } 49527d5dc18SMarcel Moolenaar 496167cb33fSIan Lepore int 49727d5dc18SMarcel Moolenaar ns8250_bus_getsig(struct uart_softc *sc) 49827d5dc18SMarcel Moolenaar { 49927d5dc18SMarcel Moolenaar uint32_t new, old, sig; 50027d5dc18SMarcel Moolenaar uint8_t msr; 50127d5dc18SMarcel Moolenaar 50227d5dc18SMarcel Moolenaar do { 50327d5dc18SMarcel Moolenaar old = sc->sc_hwsig; 50427d5dc18SMarcel Moolenaar sig = old; 5058af03381SMarcel Moolenaar uart_lock(sc->sc_hwmtx); 50627d5dc18SMarcel Moolenaar msr = uart_getreg(&sc->sc_bas, REG_MSR); 5078af03381SMarcel Moolenaar uart_unlock(sc->sc_hwmtx); 50828710806SPoul-Henning Kamp SIGCHG(msr & MSR_DSR, sig, SER_DSR, SER_DDSR); 50928710806SPoul-Henning Kamp SIGCHG(msr & MSR_CTS, sig, SER_CTS, SER_DCTS); 51028710806SPoul-Henning Kamp SIGCHG(msr & MSR_DCD, sig, SER_DCD, SER_DDCD); 51128710806SPoul-Henning Kamp SIGCHG(msr & MSR_RI, sig, SER_RI, SER_DRI); 512ea549414SMarcel Moolenaar new = sig & ~SER_MASK_DELTA; 51327d5dc18SMarcel Moolenaar } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 51427d5dc18SMarcel Moolenaar return (sig); 51527d5dc18SMarcel Moolenaar } 51627d5dc18SMarcel Moolenaar 517167cb33fSIan Lepore int 51827d5dc18SMarcel Moolenaar ns8250_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) 51927d5dc18SMarcel Moolenaar { 52027d5dc18SMarcel Moolenaar struct uart_bas *bas; 521bfa307a3SMarcel Moolenaar int baudrate, divisor, error; 52284c7b427SMarcel Moolenaar uint8_t efr, lcr; 52327d5dc18SMarcel Moolenaar 52427d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 52506287620SMarcel Moolenaar error = 0; 5268af03381SMarcel Moolenaar uart_lock(sc->sc_hwmtx); 52727d5dc18SMarcel Moolenaar switch (request) { 52827d5dc18SMarcel Moolenaar case UART_IOCTL_BREAK: 52927d5dc18SMarcel Moolenaar lcr = uart_getreg(bas, REG_LCR); 53027d5dc18SMarcel Moolenaar if (data) 53127d5dc18SMarcel Moolenaar lcr |= LCR_SBREAK; 53227d5dc18SMarcel Moolenaar else 53327d5dc18SMarcel Moolenaar lcr &= ~LCR_SBREAK; 53427d5dc18SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr); 53527d5dc18SMarcel Moolenaar uart_barrier(bas); 53627d5dc18SMarcel Moolenaar break; 53784c7b427SMarcel Moolenaar case UART_IOCTL_IFLOW: 53884c7b427SMarcel Moolenaar lcr = uart_getreg(bas, REG_LCR); 53984c7b427SMarcel Moolenaar uart_barrier(bas); 54084c7b427SMarcel Moolenaar uart_setreg(bas, REG_LCR, 0xbf); 54184c7b427SMarcel Moolenaar uart_barrier(bas); 54284c7b427SMarcel Moolenaar efr = uart_getreg(bas, REG_EFR); 54384c7b427SMarcel Moolenaar if (data) 54484c7b427SMarcel Moolenaar efr |= EFR_RTS; 54584c7b427SMarcel Moolenaar else 54684c7b427SMarcel Moolenaar efr &= ~EFR_RTS; 54784c7b427SMarcel Moolenaar uart_setreg(bas, REG_EFR, efr); 54884c7b427SMarcel Moolenaar uart_barrier(bas); 54984c7b427SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr); 55084c7b427SMarcel Moolenaar uart_barrier(bas); 55184c7b427SMarcel Moolenaar break; 55284c7b427SMarcel Moolenaar case UART_IOCTL_OFLOW: 55384c7b427SMarcel Moolenaar lcr = uart_getreg(bas, REG_LCR); 55484c7b427SMarcel Moolenaar uart_barrier(bas); 55584c7b427SMarcel Moolenaar uart_setreg(bas, REG_LCR, 0xbf); 55684c7b427SMarcel Moolenaar uart_barrier(bas); 55784c7b427SMarcel Moolenaar efr = uart_getreg(bas, REG_EFR); 55884c7b427SMarcel Moolenaar if (data) 55984c7b427SMarcel Moolenaar efr |= EFR_CTS; 56084c7b427SMarcel Moolenaar else 56184c7b427SMarcel Moolenaar efr &= ~EFR_CTS; 56284c7b427SMarcel Moolenaar uart_setreg(bas, REG_EFR, efr); 56384c7b427SMarcel Moolenaar uart_barrier(bas); 56484c7b427SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr); 56584c7b427SMarcel Moolenaar uart_barrier(bas); 56684c7b427SMarcel Moolenaar break; 567d8518925SMarcel Moolenaar case UART_IOCTL_BAUD: 568d8518925SMarcel Moolenaar lcr = uart_getreg(bas, REG_LCR); 569d8518925SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 570d8518925SMarcel Moolenaar uart_barrier(bas); 57158957d87SBenno Rice divisor = uart_getreg(bas, REG_DLL) | 57258957d87SBenno Rice (uart_getreg(bas, REG_DLH) << 8); 573d8518925SMarcel Moolenaar uart_barrier(bas); 574d8518925SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr); 575d8518925SMarcel Moolenaar uart_barrier(bas); 576bfa307a3SMarcel Moolenaar baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0; 577bfa307a3SMarcel Moolenaar if (baudrate > 0) 578bfa307a3SMarcel Moolenaar *(int*)data = baudrate; 579bfa307a3SMarcel Moolenaar else 580bfa307a3SMarcel Moolenaar error = ENXIO; 581d8518925SMarcel Moolenaar break; 58227d5dc18SMarcel Moolenaar default: 58306287620SMarcel Moolenaar error = EINVAL; 58406287620SMarcel Moolenaar break; 58527d5dc18SMarcel Moolenaar } 5868af03381SMarcel Moolenaar uart_unlock(sc->sc_hwmtx); 58706287620SMarcel Moolenaar return (error); 58827d5dc18SMarcel Moolenaar } 58927d5dc18SMarcel Moolenaar 590167cb33fSIan Lepore int 59127d5dc18SMarcel Moolenaar ns8250_bus_ipend(struct uart_softc *sc) 59227d5dc18SMarcel Moolenaar { 59327d5dc18SMarcel Moolenaar struct uart_bas *bas; 59411e55f91SOlivier Houchard struct ns8250_softc *ns8250; 59527d5dc18SMarcel Moolenaar int ipend; 59627d5dc18SMarcel Moolenaar uint8_t iir, lsr; 59727d5dc18SMarcel Moolenaar 59811e55f91SOlivier Houchard ns8250 = (struct ns8250_softc *)sc; 59927d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 6008af03381SMarcel Moolenaar uart_lock(sc->sc_hwmtx); 60127d5dc18SMarcel Moolenaar iir = uart_getreg(bas, REG_IIR); 602ac4adddfSGanbold Tsagaankhuu 603ac4adddfSGanbold Tsagaankhuu if (ns8250->busy_detect && (iir & IIR_BUSY) == IIR_BUSY) { 604ac4adddfSGanbold Tsagaankhuu (void)uart_getreg(bas, DW_REG_USR); 605ac4adddfSGanbold Tsagaankhuu uart_unlock(sc->sc_hwmtx); 606ac4adddfSGanbold Tsagaankhuu return (0); 607ac4adddfSGanbold Tsagaankhuu } 60806287620SMarcel Moolenaar if (iir & IIR_NOPEND) { 6098af03381SMarcel Moolenaar uart_unlock(sc->sc_hwmtx); 61027d5dc18SMarcel Moolenaar return (0); 61106287620SMarcel Moolenaar } 61227d5dc18SMarcel Moolenaar ipend = 0; 61327d5dc18SMarcel Moolenaar if (iir & IIR_RXRDY) { 61427d5dc18SMarcel Moolenaar lsr = uart_getreg(bas, REG_LSR); 61527d5dc18SMarcel Moolenaar if (lsr & LSR_OE) 6162d511805SMarcel Moolenaar ipend |= SER_INT_OVERRUN; 61727d5dc18SMarcel Moolenaar if (lsr & LSR_BI) 6182d511805SMarcel Moolenaar ipend |= SER_INT_BREAK; 61927d5dc18SMarcel Moolenaar if (lsr & LSR_RXRDY) 6202d511805SMarcel Moolenaar ipend |= SER_INT_RXREADY; 62127d5dc18SMarcel Moolenaar } else { 62211e55f91SOlivier Houchard if (iir & IIR_TXRDY) { 6232d511805SMarcel Moolenaar ipend |= SER_INT_TXIDLE; 62411e55f91SOlivier Houchard uart_setreg(bas, REG_IER, ns8250->ier); 62511e55f91SOlivier Houchard } else 6262d511805SMarcel Moolenaar ipend |= SER_INT_SIGCHG; 62727d5dc18SMarcel Moolenaar } 628d7ae5af5SMarcel Moolenaar if (ipend == 0) 629d7ae5af5SMarcel Moolenaar ns8250_clrint(bas); 630d7ae5af5SMarcel Moolenaar uart_unlock(sc->sc_hwmtx); 631f6ffc3c2SMarius Strobl return (ipend); 63227d5dc18SMarcel Moolenaar } 63327d5dc18SMarcel Moolenaar 634167cb33fSIan Lepore int 63527d5dc18SMarcel Moolenaar ns8250_bus_param(struct uart_softc *sc, int baudrate, int databits, 63627d5dc18SMarcel Moolenaar int stopbits, int parity) 63727d5dc18SMarcel Moolenaar { 63827d5dc18SMarcel Moolenaar struct uart_bas *bas; 63906287620SMarcel Moolenaar int error; 64027d5dc18SMarcel Moolenaar 64127d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 6428af03381SMarcel Moolenaar uart_lock(sc->sc_hwmtx); 64306287620SMarcel Moolenaar error = ns8250_param(bas, baudrate, databits, stopbits, parity); 6448af03381SMarcel Moolenaar uart_unlock(sc->sc_hwmtx); 64506287620SMarcel Moolenaar return (error); 64627d5dc18SMarcel Moolenaar } 64727d5dc18SMarcel Moolenaar 648167cb33fSIan Lepore int 64927d5dc18SMarcel Moolenaar ns8250_bus_probe(struct uart_softc *sc) 65027d5dc18SMarcel Moolenaar { 6510aefb0a6SBenno Rice struct ns8250_softc *ns8250; 65227d5dc18SMarcel Moolenaar struct uart_bas *bas; 65327d5dc18SMarcel Moolenaar int count, delay, error, limit; 65458957d87SBenno Rice uint8_t lsr, mcr, ier; 65527d5dc18SMarcel Moolenaar 6560aefb0a6SBenno Rice ns8250 = (struct ns8250_softc *)sc; 65727d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 65827d5dc18SMarcel Moolenaar 65927d5dc18SMarcel Moolenaar error = ns8250_probe(bas); 66027d5dc18SMarcel Moolenaar if (error) 66127d5dc18SMarcel Moolenaar return (error); 66227d5dc18SMarcel Moolenaar 66327d5dc18SMarcel Moolenaar mcr = MCR_IE; 66427d5dc18SMarcel Moolenaar if (sc->sc_sysdev == NULL) { 66527d5dc18SMarcel Moolenaar /* By using ns8250_init() we also set DTR and RTS. */ 666d902fb71SMarcel Moolenaar ns8250_init(bas, 115200, 8, 1, UART_PARITY_NONE); 66727d5dc18SMarcel Moolenaar } else 66827d5dc18SMarcel Moolenaar mcr |= MCR_DTR | MCR_RTS; 66927d5dc18SMarcel Moolenaar 67027d5dc18SMarcel Moolenaar error = ns8250_drain(bas, UART_DRAIN_TRANSMITTER); 67127d5dc18SMarcel Moolenaar if (error) 67227d5dc18SMarcel Moolenaar return (error); 67327d5dc18SMarcel Moolenaar 67427d5dc18SMarcel Moolenaar /* 67527d5dc18SMarcel Moolenaar * Set loopback mode. This avoids having garbage on the wire and 67627d5dc18SMarcel Moolenaar * also allows us send and receive data. We set DTR and RTS to 67727d5dc18SMarcel Moolenaar * avoid the possibility that automatic flow-control prevents 67889eef2deSThomas Moestl * any data from being sent. 67927d5dc18SMarcel Moolenaar */ 68089eef2deSThomas Moestl uart_setreg(bas, REG_MCR, MCR_LOOPBACK | MCR_IE | MCR_DTR | MCR_RTS); 68127d5dc18SMarcel Moolenaar uart_barrier(bas); 68227d5dc18SMarcel Moolenaar 68327d5dc18SMarcel Moolenaar /* 68427d5dc18SMarcel Moolenaar * Enable FIFOs. And check that the UART has them. If not, we're 68589eef2deSThomas Moestl * done. Since this is the first time we enable the FIFOs, we reset 68689eef2deSThomas Moestl * them. 68727d5dc18SMarcel Moolenaar */ 68827d5dc18SMarcel Moolenaar uart_setreg(bas, REG_FCR, FCR_ENABLE); 68927d5dc18SMarcel Moolenaar uart_barrier(bas); 6908d1289feSMarcel Moolenaar if (!(uart_getreg(bas, REG_IIR) & IIR_FIFO_MASK)) { 69127d5dc18SMarcel Moolenaar /* 69227d5dc18SMarcel Moolenaar * NS16450 or INS8250. We don't bother to differentiate 69327d5dc18SMarcel Moolenaar * between them. They're too old to be interesting. 69427d5dc18SMarcel Moolenaar */ 69527d5dc18SMarcel Moolenaar uart_setreg(bas, REG_MCR, mcr); 69627d5dc18SMarcel Moolenaar uart_barrier(bas); 6978d1289feSMarcel Moolenaar sc->sc_rxfifosz = sc->sc_txfifosz = 1; 69827d5dc18SMarcel Moolenaar device_set_desc(sc->sc_dev, "8250 or 16450 or compatible"); 69927d5dc18SMarcel Moolenaar return (0); 70027d5dc18SMarcel Moolenaar } 70127d5dc18SMarcel Moolenaar 70289eef2deSThomas Moestl uart_setreg(bas, REG_FCR, FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST); 70327d5dc18SMarcel Moolenaar uart_barrier(bas); 70427d5dc18SMarcel Moolenaar 70527d5dc18SMarcel Moolenaar count = 0; 70627d5dc18SMarcel Moolenaar delay = ns8250_delay(bas); 70727d5dc18SMarcel Moolenaar 70827d5dc18SMarcel Moolenaar /* We have FIFOs. Drain the transmitter and receiver. */ 70927d5dc18SMarcel Moolenaar error = ns8250_drain(bas, UART_DRAIN_RECEIVER|UART_DRAIN_TRANSMITTER); 71027d5dc18SMarcel Moolenaar if (error) { 71127d5dc18SMarcel Moolenaar uart_setreg(bas, REG_MCR, mcr); 71227d5dc18SMarcel Moolenaar uart_setreg(bas, REG_FCR, 0); 71327d5dc18SMarcel Moolenaar uart_barrier(bas); 71427d5dc18SMarcel Moolenaar goto describe; 71527d5dc18SMarcel Moolenaar } 71627d5dc18SMarcel Moolenaar 71727d5dc18SMarcel Moolenaar /* 71827d5dc18SMarcel Moolenaar * We should have a sufficiently clean "pipe" to determine the 71927d5dc18SMarcel Moolenaar * size of the FIFOs. We send as much characters as is reasonable 7206bccea7cSRebecca Cran * and wait for the overflow bit in the LSR register to be 72189eef2deSThomas Moestl * asserted, counting the characters as we send them. Based on 72289eef2deSThomas Moestl * that count we know the FIFO size. 72327d5dc18SMarcel Moolenaar */ 72489eef2deSThomas Moestl do { 72527d5dc18SMarcel Moolenaar uart_setreg(bas, REG_DATA, 0); 72627d5dc18SMarcel Moolenaar uart_barrier(bas); 72727d5dc18SMarcel Moolenaar count++; 72827d5dc18SMarcel Moolenaar 72927d5dc18SMarcel Moolenaar limit = 30; 73089eef2deSThomas Moestl lsr = 0; 73189eef2deSThomas Moestl /* 73289eef2deSThomas Moestl * LSR bits are cleared upon read, so we must accumulate 73389eef2deSThomas Moestl * them to be able to test LSR_OE below. 73489eef2deSThomas Moestl */ 73589eef2deSThomas Moestl while (((lsr |= uart_getreg(bas, REG_LSR)) & LSR_TEMT) == 0 && 73689eef2deSThomas Moestl --limit) 73727d5dc18SMarcel Moolenaar DELAY(delay); 73827d5dc18SMarcel Moolenaar if (limit == 0) { 7390aefb0a6SBenno Rice ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 74058957d87SBenno Rice uart_setreg(bas, REG_IER, ier); 74127d5dc18SMarcel Moolenaar uart_setreg(bas, REG_MCR, mcr); 74227d5dc18SMarcel Moolenaar uart_setreg(bas, REG_FCR, 0); 74327d5dc18SMarcel Moolenaar uart_barrier(bas); 74427d5dc18SMarcel Moolenaar count = 0; 74527d5dc18SMarcel Moolenaar goto describe; 74627d5dc18SMarcel Moolenaar } 747d882cf92SMarcel Moolenaar } while ((lsr & LSR_OE) == 0 && count < 130); 74889eef2deSThomas Moestl count--; 74927d5dc18SMarcel Moolenaar 75027d5dc18SMarcel Moolenaar uart_setreg(bas, REG_MCR, mcr); 75127d5dc18SMarcel Moolenaar 75227d5dc18SMarcel Moolenaar /* Reset FIFOs. */ 75327d5dc18SMarcel Moolenaar ns8250_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 75427d5dc18SMarcel Moolenaar 75527d5dc18SMarcel Moolenaar describe: 75689eef2deSThomas Moestl if (count >= 14 && count <= 16) { 75727d5dc18SMarcel Moolenaar sc->sc_rxfifosz = 16; 75827d5dc18SMarcel Moolenaar device_set_desc(sc->sc_dev, "16550 or compatible"); 75989eef2deSThomas Moestl } else if (count >= 28 && count <= 32) { 76027d5dc18SMarcel Moolenaar sc->sc_rxfifosz = 32; 76127d5dc18SMarcel Moolenaar device_set_desc(sc->sc_dev, "16650 or compatible"); 76289eef2deSThomas Moestl } else if (count >= 56 && count <= 64) { 76327d5dc18SMarcel Moolenaar sc->sc_rxfifosz = 64; 76427d5dc18SMarcel Moolenaar device_set_desc(sc->sc_dev, "16750 or compatible"); 76589eef2deSThomas Moestl } else if (count >= 112 && count <= 128) { 76627d5dc18SMarcel Moolenaar sc->sc_rxfifosz = 128; 76727d5dc18SMarcel Moolenaar device_set_desc(sc->sc_dev, "16950 or compatible"); 76827d5dc18SMarcel Moolenaar } else { 769c21e0da2SMarcel Moolenaar sc->sc_rxfifosz = 16; 77027d5dc18SMarcel Moolenaar device_set_desc(sc->sc_dev, 77127d5dc18SMarcel Moolenaar "Non-standard ns8250 class UART with FIFOs"); 77227d5dc18SMarcel Moolenaar } 77327d5dc18SMarcel Moolenaar 77427d5dc18SMarcel Moolenaar /* 77527d5dc18SMarcel Moolenaar * Force the Tx FIFO size to 16 bytes for now. We don't program the 77627d5dc18SMarcel Moolenaar * Tx trigger. Also, we assume that all data has been sent when the 77727d5dc18SMarcel Moolenaar * interrupt happens. 77827d5dc18SMarcel Moolenaar */ 77927d5dc18SMarcel Moolenaar sc->sc_txfifosz = 16; 78027d5dc18SMarcel Moolenaar 781dc70e792SMarcel Moolenaar #if 0 782dc70e792SMarcel Moolenaar /* 783dc70e792SMarcel Moolenaar * XXX there are some issues related to hardware flow control and 784dc70e792SMarcel Moolenaar * it's likely that uart(4) is the cause. This basicly needs more 785dc70e792SMarcel Moolenaar * investigation, but we avoid using for hardware flow control 786dc70e792SMarcel Moolenaar * until then. 787dc70e792SMarcel Moolenaar */ 78884c7b427SMarcel Moolenaar /* 16650s or higher have automatic flow control. */ 78984c7b427SMarcel Moolenaar if (sc->sc_rxfifosz > 16) { 79084c7b427SMarcel Moolenaar sc->sc_hwiflow = 1; 79184c7b427SMarcel Moolenaar sc->sc_hwoflow = 1; 79284c7b427SMarcel Moolenaar } 793dc70e792SMarcel Moolenaar #endif 79484c7b427SMarcel Moolenaar 79527d5dc18SMarcel Moolenaar return (0); 79627d5dc18SMarcel Moolenaar } 79727d5dc18SMarcel Moolenaar 798167cb33fSIan Lepore int 79927d5dc18SMarcel Moolenaar ns8250_bus_receive(struct uart_softc *sc) 80027d5dc18SMarcel Moolenaar { 80127d5dc18SMarcel Moolenaar struct uart_bas *bas; 80227d5dc18SMarcel Moolenaar int xc; 80327d5dc18SMarcel Moolenaar uint8_t lsr; 80427d5dc18SMarcel Moolenaar 80527d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 8068af03381SMarcel Moolenaar uart_lock(sc->sc_hwmtx); 80727d5dc18SMarcel Moolenaar lsr = uart_getreg(bas, REG_LSR); 80844ed791bSMarcel Moolenaar while (lsr & LSR_RXRDY) { 80944ed791bSMarcel Moolenaar if (uart_rx_full(sc)) { 81044ed791bSMarcel Moolenaar sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; 81127d5dc18SMarcel Moolenaar break; 81244ed791bSMarcel Moolenaar } 81327d5dc18SMarcel Moolenaar xc = uart_getreg(bas, REG_DATA); 81427d5dc18SMarcel Moolenaar if (lsr & LSR_FE) 81527d5dc18SMarcel Moolenaar xc |= UART_STAT_FRAMERR; 81627d5dc18SMarcel Moolenaar if (lsr & LSR_PE) 81727d5dc18SMarcel Moolenaar xc |= UART_STAT_PARERR; 81827d5dc18SMarcel Moolenaar uart_rx_put(sc, xc); 81944ed791bSMarcel Moolenaar lsr = uart_getreg(bas, REG_LSR); 82044ed791bSMarcel Moolenaar } 82144ed791bSMarcel Moolenaar /* Discard everything left in the Rx FIFO. */ 82244ed791bSMarcel Moolenaar while (lsr & LSR_RXRDY) { 82344ed791bSMarcel Moolenaar (void)uart_getreg(bas, REG_DATA); 82444ed791bSMarcel Moolenaar uart_barrier(bas); 82544ed791bSMarcel Moolenaar lsr = uart_getreg(bas, REG_LSR); 82627d5dc18SMarcel Moolenaar } 8278af03381SMarcel Moolenaar uart_unlock(sc->sc_hwmtx); 82827d5dc18SMarcel Moolenaar return (0); 82927d5dc18SMarcel Moolenaar } 83027d5dc18SMarcel Moolenaar 831167cb33fSIan Lepore int 83227d5dc18SMarcel Moolenaar ns8250_bus_setsig(struct uart_softc *sc, int sig) 83327d5dc18SMarcel Moolenaar { 83427d5dc18SMarcel Moolenaar struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 83527d5dc18SMarcel Moolenaar struct uart_bas *bas; 83627d5dc18SMarcel Moolenaar uint32_t new, old; 83727d5dc18SMarcel Moolenaar 83827d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 83927d5dc18SMarcel Moolenaar do { 84027d5dc18SMarcel Moolenaar old = sc->sc_hwsig; 84127d5dc18SMarcel Moolenaar new = old; 84228710806SPoul-Henning Kamp if (sig & SER_DDTR) { 84328710806SPoul-Henning Kamp SIGCHG(sig & SER_DTR, new, SER_DTR, 84428710806SPoul-Henning Kamp SER_DDTR); 84527d5dc18SMarcel Moolenaar } 84628710806SPoul-Henning Kamp if (sig & SER_DRTS) { 84728710806SPoul-Henning Kamp SIGCHG(sig & SER_RTS, new, SER_RTS, 84828710806SPoul-Henning Kamp SER_DRTS); 84927d5dc18SMarcel Moolenaar } 85027d5dc18SMarcel Moolenaar } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 8518af03381SMarcel Moolenaar uart_lock(sc->sc_hwmtx); 85227d5dc18SMarcel Moolenaar ns8250->mcr &= ~(MCR_DTR|MCR_RTS); 85328710806SPoul-Henning Kamp if (new & SER_DTR) 85427d5dc18SMarcel Moolenaar ns8250->mcr |= MCR_DTR; 85528710806SPoul-Henning Kamp if (new & SER_RTS) 85627d5dc18SMarcel Moolenaar ns8250->mcr |= MCR_RTS; 85727d5dc18SMarcel Moolenaar uart_setreg(bas, REG_MCR, ns8250->mcr); 85827d5dc18SMarcel Moolenaar uart_barrier(bas); 8598af03381SMarcel Moolenaar uart_unlock(sc->sc_hwmtx); 86027d5dc18SMarcel Moolenaar return (0); 86127d5dc18SMarcel Moolenaar } 86227d5dc18SMarcel Moolenaar 863167cb33fSIan Lepore int 86427d5dc18SMarcel Moolenaar ns8250_bus_transmit(struct uart_softc *sc) 86527d5dc18SMarcel Moolenaar { 86627d5dc18SMarcel Moolenaar struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 86727d5dc18SMarcel Moolenaar struct uart_bas *bas; 86827d5dc18SMarcel Moolenaar int i; 86927d5dc18SMarcel Moolenaar 87027d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 8718af03381SMarcel Moolenaar uart_lock(sc->sc_hwmtx); 87227d5dc18SMarcel Moolenaar while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0) 87327d5dc18SMarcel Moolenaar ; 87427d5dc18SMarcel Moolenaar uart_setreg(bas, REG_IER, ns8250->ier | IER_ETXRDY); 87527d5dc18SMarcel Moolenaar uart_barrier(bas); 87627d5dc18SMarcel Moolenaar for (i = 0; i < sc->sc_txdatasz; i++) { 87727d5dc18SMarcel Moolenaar uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]); 87827d5dc18SMarcel Moolenaar uart_barrier(bas); 87927d5dc18SMarcel Moolenaar } 8801c60b24bSColin Percival if (broken_txfifo) 8811c60b24bSColin Percival ns8250_drain(bas, UART_DRAIN_TRANSMITTER); 8821c60b24bSColin Percival else 88327d5dc18SMarcel Moolenaar sc->sc_txbusy = 1; 8848af03381SMarcel Moolenaar uart_unlock(sc->sc_hwmtx); 8851c60b24bSColin Percival if (broken_txfifo) 8861c60b24bSColin Percival uart_sched_softih(sc, SER_INT_TXIDLE); 88727d5dc18SMarcel Moolenaar return (0); 88827d5dc18SMarcel Moolenaar } 889