1098ca2bdSWarner Losh /*- 24d846d26SWarner Losh * SPDX-License-Identifier: BSD-2-Clause 3718cf2ccSPedro F. Giffuni * 427d5dc18SMarcel Moolenaar * Copyright (c) 2003 Marcel Moolenaar 527d5dc18SMarcel Moolenaar * All rights reserved. 627d5dc18SMarcel Moolenaar * 727d5dc18SMarcel Moolenaar * Redistribution and use in source and binary forms, with or without 827d5dc18SMarcel Moolenaar * modification, are permitted provided that the following conditions 927d5dc18SMarcel Moolenaar * are met: 1027d5dc18SMarcel Moolenaar * 1127d5dc18SMarcel Moolenaar * 1. Redistributions of source code must retain the above copyright 1227d5dc18SMarcel Moolenaar * notice, this list of conditions and the following disclaimer. 1327d5dc18SMarcel Moolenaar * 2. Redistributions in binary form must reproduce the above copyright 1427d5dc18SMarcel Moolenaar * notice, this list of conditions and the following disclaimer in the 1527d5dc18SMarcel Moolenaar * documentation and/or other materials provided with the distribution. 1627d5dc18SMarcel Moolenaar * 1727d5dc18SMarcel Moolenaar * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 1827d5dc18SMarcel Moolenaar * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 1927d5dc18SMarcel Moolenaar * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 2027d5dc18SMarcel Moolenaar * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 2127d5dc18SMarcel Moolenaar * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 2227d5dc18SMarcel Moolenaar * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2327d5dc18SMarcel Moolenaar * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2427d5dc18SMarcel Moolenaar * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2527d5dc18SMarcel Moolenaar * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 2627d5dc18SMarcel Moolenaar * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2727d5dc18SMarcel Moolenaar */ 2827d5dc18SMarcel Moolenaar 29381388b9SMatt Macy #include "opt_acpi.h" 30ac4adddfSGanbold Tsagaankhuu #include "opt_platform.h" 31e0fe7c95SAdrian Chadd #include "opt_uart.h" 32ac4adddfSGanbold Tsagaankhuu 3327d5dc18SMarcel Moolenaar #include <sys/param.h> 3427d5dc18SMarcel Moolenaar #include <sys/systm.h> 3527d5dc18SMarcel Moolenaar #include <sys/bus.h> 3627d5dc18SMarcel Moolenaar #include <sys/conf.h> 371c60b24bSColin Percival #include <sys/kernel.h> 381c60b24bSColin Percival #include <sys/sysctl.h> 3927d5dc18SMarcel Moolenaar #include <machine/bus.h> 4027d5dc18SMarcel Moolenaar 41ac4adddfSGanbold Tsagaankhuu #ifdef FDT 42ac4adddfSGanbold Tsagaankhuu #include <dev/fdt/fdt_common.h> 43ac4adddfSGanbold Tsagaankhuu #include <dev/ofw/ofw_bus.h> 44ac4adddfSGanbold Tsagaankhuu #include <dev/ofw/ofw_bus_subr.h> 45ac4adddfSGanbold Tsagaankhuu #endif 46ac4adddfSGanbold Tsagaankhuu 4727d5dc18SMarcel Moolenaar #include <dev/uart/uart.h> 4827d5dc18SMarcel Moolenaar #include <dev/uart/uart_cpu.h> 493bb693afSIan Lepore #ifdef FDT 503bb693afSIan Lepore #include <dev/uart/uart_cpu_fdt.h> 513bb693afSIan Lepore #endif 5227d5dc18SMarcel Moolenaar #include <dev/uart/uart_bus.h> 53167cb33fSIan Lepore #include <dev/uart/uart_dev_ns8250.h> 54fdfbb3f5SIan Lepore #include <dev/uart/uart_ppstypes.h> 55381388b9SMatt Macy #ifdef DEV_ACPI 56381388b9SMatt Macy #include <dev/uart/uart_cpu_acpi.h> 579cf66a04SMarcin Wojtas #include <contrib/dev/acpica/include/acpi.h> 58381388b9SMatt Macy #endif 5976563beaSMarcel Moolenaar 6076563beaSMarcel Moolenaar #include <dev/ic/ns16550.h> 6127d5dc18SMarcel Moolenaar 6227d5dc18SMarcel Moolenaar #include "uart_if.h" 6327d5dc18SMarcel Moolenaar 6427d5dc18SMarcel Moolenaar #define DEFAULT_RCLK 1843200 6527d5dc18SMarcel Moolenaar 66e0fe7c95SAdrian Chadd /* 67e0fe7c95SAdrian Chadd * Set the default baudrate tolerance to 3.0%. 68e0fe7c95SAdrian Chadd * 69e0fe7c95SAdrian Chadd * Some embedded boards have odd reference clocks (eg 25MHz) 70e0fe7c95SAdrian Chadd * and we need to handle higher variances in the target baud rate. 71e0fe7c95SAdrian Chadd */ 72e0fe7c95SAdrian Chadd #ifndef UART_DEV_TOLERANCE_PCT 73e0fe7c95SAdrian Chadd #define UART_DEV_TOLERANCE_PCT 30 74e0fe7c95SAdrian Chadd #endif /* UART_DEV_TOLERANCE_PCT */ 75e0fe7c95SAdrian Chadd 76ac4adddfSGanbold Tsagaankhuu static int broken_txfifo = 0; 77af3b2549SHans Petter Selasky SYSCTL_INT(_hw, OID_AUTO, broken_txfifo, CTLFLAG_RWTUN, 78ac4adddfSGanbold Tsagaankhuu &broken_txfifo, 0, "UART FIFO has QEMU emulation bug"); 79ac4adddfSGanbold Tsagaankhuu 8027d5dc18SMarcel Moolenaar /* 81a113f9ddSWarner Losh * To use early printf on x86, add the following to your kernel config: 82a113f9ddSWarner Losh * 83a113f9ddSWarner Losh * options UART_NS8250_EARLY_PORT=0x3f8 84a113f9ddSWarner Losh * options EARLY_PRINTF 85a113f9ddSWarner Losh */ 86a113f9ddSWarner Losh #if defined(EARLY_PRINTF) && (defined(__amd64__) || defined(__i386__)) 87a113f9ddSWarner Losh static void 88a113f9ddSWarner Losh uart_ns8250_early_putc(int c) 89a113f9ddSWarner Losh { 90a113f9ddSWarner Losh u_int stat = UART_NS8250_EARLY_PORT + REG_LSR; 91a113f9ddSWarner Losh u_int tx = UART_NS8250_EARLY_PORT + REG_DATA; 92a113f9ddSWarner Losh int limit = 10000; /* 10ms is plenty of time */ 93a113f9ddSWarner Losh 94a113f9ddSWarner Losh while ((inb(stat) & LSR_THRE) == 0 && --limit > 0) 95a113f9ddSWarner Losh continue; 96a113f9ddSWarner Losh outb(tx, c); 97a113f9ddSWarner Losh } 98a113f9ddSWarner Losh early_putc_t *early_putc = uart_ns8250_early_putc; 99a113f9ddSWarner Losh #endif /* EARLY_PRINTF */ 100a113f9ddSWarner Losh 101a113f9ddSWarner Losh /* 10227d5dc18SMarcel Moolenaar * Clear pending interrupts. THRE is cleared by reading IIR. Data 10327d5dc18SMarcel Moolenaar * that may have been received gets lost here. 10427d5dc18SMarcel Moolenaar */ 10527d5dc18SMarcel Moolenaar static void 10627d5dc18SMarcel Moolenaar ns8250_clrint(struct uart_bas *bas) 10727d5dc18SMarcel Moolenaar { 108d7ae5af5SMarcel Moolenaar uint8_t iir, lsr; 10927d5dc18SMarcel Moolenaar 11027d5dc18SMarcel Moolenaar iir = uart_getreg(bas, REG_IIR); 11127d5dc18SMarcel Moolenaar while ((iir & IIR_NOPEND) == 0) { 11227d5dc18SMarcel Moolenaar iir &= IIR_IMASK; 113d7ae5af5SMarcel Moolenaar if (iir == IIR_RLS) { 114d7ae5af5SMarcel Moolenaar lsr = uart_getreg(bas, REG_LSR); 115d7ae5af5SMarcel Moolenaar if (lsr & (LSR_BI|LSR_FE|LSR_PE)) 116d7ae5af5SMarcel Moolenaar (void)uart_getreg(bas, REG_DATA); 117d7ae5af5SMarcel Moolenaar } else if (iir == IIR_RXRDY || iir == IIR_RXTOUT) 11827d5dc18SMarcel Moolenaar (void)uart_getreg(bas, REG_DATA); 11927d5dc18SMarcel Moolenaar else if (iir == IIR_MLSC) 12027d5dc18SMarcel Moolenaar (void)uart_getreg(bas, REG_MSR); 12127d5dc18SMarcel Moolenaar uart_barrier(bas); 12227d5dc18SMarcel Moolenaar iir = uart_getreg(bas, REG_IIR); 12327d5dc18SMarcel Moolenaar } 12427d5dc18SMarcel Moolenaar } 12527d5dc18SMarcel Moolenaar 12627d5dc18SMarcel Moolenaar static int 12727d5dc18SMarcel Moolenaar ns8250_delay(struct uart_bas *bas) 12827d5dc18SMarcel Moolenaar { 12927d5dc18SMarcel Moolenaar int divisor; 13027d5dc18SMarcel Moolenaar u_char lcr; 13127d5dc18SMarcel Moolenaar 13227d5dc18SMarcel Moolenaar lcr = uart_getreg(bas, REG_LCR); 13327d5dc18SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 13427d5dc18SMarcel Moolenaar uart_barrier(bas); 13558957d87SBenno Rice divisor = uart_getreg(bas, REG_DLL) | (uart_getreg(bas, REG_DLH) << 8); 13627d5dc18SMarcel Moolenaar uart_barrier(bas); 13727d5dc18SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr); 13827d5dc18SMarcel Moolenaar uart_barrier(bas); 13927d5dc18SMarcel Moolenaar 14027d5dc18SMarcel Moolenaar /* 1/10th the time to transmit 1 character (estimate). */ 141ebecffe9SMarcel Moolenaar if (divisor <= 134) 14227d5dc18SMarcel Moolenaar return (16000000 * divisor / bas->rclk); 143ebecffe9SMarcel Moolenaar return (16000 * divisor / (bas->rclk / 1000)); 14427d5dc18SMarcel Moolenaar } 14527d5dc18SMarcel Moolenaar 14627d5dc18SMarcel Moolenaar static int 14727d5dc18SMarcel Moolenaar ns8250_divisor(int rclk, int baudrate) 14827d5dc18SMarcel Moolenaar { 14927d5dc18SMarcel Moolenaar int actual_baud, divisor; 15027d5dc18SMarcel Moolenaar int error; 15127d5dc18SMarcel Moolenaar 15227d5dc18SMarcel Moolenaar if (baudrate == 0) 15327d5dc18SMarcel Moolenaar return (0); 15427d5dc18SMarcel Moolenaar 15527d5dc18SMarcel Moolenaar divisor = (rclk / (baudrate << 3) + 1) >> 1; 15627d5dc18SMarcel Moolenaar if (divisor == 0 || divisor >= 65536) 15727d5dc18SMarcel Moolenaar return (0); 15827d5dc18SMarcel Moolenaar actual_baud = rclk / (divisor << 4); 15927d5dc18SMarcel Moolenaar 16027d5dc18SMarcel Moolenaar /* 10 times error in percent: */ 161b47c1edaSJohn Baldwin error = ((actual_baud - baudrate) * 2000 / baudrate + 1) / 2; 16227d5dc18SMarcel Moolenaar 163e0fe7c95SAdrian Chadd /* enforce maximum error tolerance: */ 164e0fe7c95SAdrian Chadd if (error < -UART_DEV_TOLERANCE_PCT || error > UART_DEV_TOLERANCE_PCT) 16527d5dc18SMarcel Moolenaar return (0); 16627d5dc18SMarcel Moolenaar 16727d5dc18SMarcel Moolenaar return (divisor); 16827d5dc18SMarcel Moolenaar } 16927d5dc18SMarcel Moolenaar 17027d5dc18SMarcel Moolenaar static int 17127d5dc18SMarcel Moolenaar ns8250_drain(struct uart_bas *bas, int what) 17227d5dc18SMarcel Moolenaar { 17327d5dc18SMarcel Moolenaar int delay, limit; 17427d5dc18SMarcel Moolenaar 17527d5dc18SMarcel Moolenaar delay = ns8250_delay(bas); 17627d5dc18SMarcel Moolenaar 17727d5dc18SMarcel Moolenaar if (what & UART_DRAIN_TRANSMITTER) { 17827d5dc18SMarcel Moolenaar /* 17927d5dc18SMarcel Moolenaar * Pick an arbitrary high limit to avoid getting stuck in 18027d5dc18SMarcel Moolenaar * an infinite loop when the hardware is broken. Make the 18127d5dc18SMarcel Moolenaar * limit high enough to handle large FIFOs. 18227d5dc18SMarcel Moolenaar */ 18327d5dc18SMarcel Moolenaar limit = 10*1024; 18427d5dc18SMarcel Moolenaar while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) 18527d5dc18SMarcel Moolenaar DELAY(delay); 18627d5dc18SMarcel Moolenaar if (limit == 0) { 18727d5dc18SMarcel Moolenaar /* printf("ns8250: transmitter appears stuck... "); */ 18827d5dc18SMarcel Moolenaar return (EIO); 18927d5dc18SMarcel Moolenaar } 19027d5dc18SMarcel Moolenaar } 19127d5dc18SMarcel Moolenaar 19227d5dc18SMarcel Moolenaar if (what & UART_DRAIN_RECEIVER) { 19327d5dc18SMarcel Moolenaar /* 19427d5dc18SMarcel Moolenaar * Pick an arbitrary high limit to avoid getting stuck in 19527d5dc18SMarcel Moolenaar * an infinite loop when the hardware is broken. Make the 19627d5dc18SMarcel Moolenaar * limit high enough to handle large FIFOs and integrated 19727d5dc18SMarcel Moolenaar * UARTs. The HP rx2600 for example has 3 UARTs on the 19827d5dc18SMarcel Moolenaar * management board that tend to get a lot of data send 19939d6144dSColin Percival * to it when the UART is first activated. Assume that we 20039d6144dSColin Percival * have finished draining if LSR_RXRDY is not asserted both 20139d6144dSColin Percival * prior to and after a DELAY; but as long as LSR_RXRDY is 20239d6144dSColin Percival * asserted, read (and discard) characters as quickly as 20339d6144dSColin Percival * possible. 20427d5dc18SMarcel Moolenaar */ 20527d5dc18SMarcel Moolenaar limit=10*4096; 20639d6144dSColin Percival while (limit && (uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) { 20739d6144dSColin Percival do { 20827d5dc18SMarcel Moolenaar (void)uart_getreg(bas, REG_DATA); 20927d5dc18SMarcel Moolenaar uart_barrier(bas); 21039d6144dSColin Percival } while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit); 21139d6144dSColin Percival uart_barrier(bas); 21227d5dc18SMarcel Moolenaar DELAY(delay << 2); 21327d5dc18SMarcel Moolenaar } 21427d5dc18SMarcel Moolenaar if (limit == 0) { 21527d5dc18SMarcel Moolenaar /* printf("ns8250: receiver appears broken... "); */ 21627d5dc18SMarcel Moolenaar return (EIO); 21727d5dc18SMarcel Moolenaar } 21827d5dc18SMarcel Moolenaar } 21927d5dc18SMarcel Moolenaar 22027d5dc18SMarcel Moolenaar return (0); 22127d5dc18SMarcel Moolenaar } 22227d5dc18SMarcel Moolenaar 22327d5dc18SMarcel Moolenaar /* 22427d5dc18SMarcel Moolenaar * We can only flush UARTs with FIFOs. UARTs without FIFOs should be 22527d5dc18SMarcel Moolenaar * drained. WARNING: this function clobbers the FIFO setting! 22627d5dc18SMarcel Moolenaar */ 22727d5dc18SMarcel Moolenaar static void 22827d5dc18SMarcel Moolenaar ns8250_flush(struct uart_bas *bas, int what) 22927d5dc18SMarcel Moolenaar { 23027d5dc18SMarcel Moolenaar uint8_t fcr; 231c4b68e7eSColin Percival uint8_t lsr; 232c4b68e7eSColin Percival int drain = 0; 23327d5dc18SMarcel Moolenaar 23427d5dc18SMarcel Moolenaar fcr = FCR_ENABLE; 23527d5dc18SMarcel Moolenaar if (what & UART_FLUSH_TRANSMITTER) 23627d5dc18SMarcel Moolenaar fcr |= FCR_XMT_RST; 23727d5dc18SMarcel Moolenaar if (what & UART_FLUSH_RECEIVER) 23827d5dc18SMarcel Moolenaar fcr |= FCR_RCV_RST; 23927d5dc18SMarcel Moolenaar uart_setreg(bas, REG_FCR, fcr); 24027d5dc18SMarcel Moolenaar uart_barrier(bas); 241c4b68e7eSColin Percival 242c4b68e7eSColin Percival /* 243c4b68e7eSColin Percival * Detect and work around emulated UARTs which don't implement the 244c4b68e7eSColin Percival * FCR register; on these systems we need to drain the FIFO since 245c4b68e7eSColin Percival * the flush we request doesn't happen. One such system is the 246c4b68e7eSColin Percival * Firecracker VMM, aka. the rust-vmm/vm-superio emulation code: 247c4b68e7eSColin Percival * https://github.com/rust-vmm/vm-superio/issues/83 248c4b68e7eSColin Percival */ 249c4b68e7eSColin Percival lsr = uart_getreg(bas, REG_LSR); 2505ad8c32cSColin Percival if (((lsr & LSR_TEMT) == 0) && (what & UART_FLUSH_TRANSMITTER)) 251c4b68e7eSColin Percival drain |= UART_DRAIN_TRANSMITTER; 252c4b68e7eSColin Percival if ((lsr & LSR_RXRDY) && (what & UART_FLUSH_RECEIVER)) 253c4b68e7eSColin Percival drain |= UART_DRAIN_RECEIVER; 254c4b68e7eSColin Percival if (drain != 0) { 255c4b68e7eSColin Percival printf("ns8250: UART FCR is broken\n"); 256c4b68e7eSColin Percival ns8250_drain(bas, drain); 257c4b68e7eSColin Percival } 25827d5dc18SMarcel Moolenaar } 25927d5dc18SMarcel Moolenaar 26027d5dc18SMarcel Moolenaar static int 26127d5dc18SMarcel Moolenaar ns8250_param(struct uart_bas *bas, int baudrate, int databits, int stopbits, 26227d5dc18SMarcel Moolenaar int parity) 26327d5dc18SMarcel Moolenaar { 26427d5dc18SMarcel Moolenaar int divisor; 26527d5dc18SMarcel Moolenaar uint8_t lcr; 26627d5dc18SMarcel Moolenaar 2678ea7fa16SWei Hu /* Don't change settings when running on Hyper-V */ 2688ea7fa16SWei Hu if (vm_guest == VM_GUEST_HV) 2698ea7fa16SWei Hu return (0); 2708ea7fa16SWei Hu 27127d5dc18SMarcel Moolenaar lcr = 0; 27227d5dc18SMarcel Moolenaar if (databits >= 8) 27327d5dc18SMarcel Moolenaar lcr |= LCR_8BITS; 27427d5dc18SMarcel Moolenaar else if (databits == 7) 27527d5dc18SMarcel Moolenaar lcr |= LCR_7BITS; 27627d5dc18SMarcel Moolenaar else if (databits == 6) 27727d5dc18SMarcel Moolenaar lcr |= LCR_6BITS; 27827d5dc18SMarcel Moolenaar else 27927d5dc18SMarcel Moolenaar lcr |= LCR_5BITS; 28027d5dc18SMarcel Moolenaar if (stopbits > 1) 28127d5dc18SMarcel Moolenaar lcr |= LCR_STOPB; 28227d5dc18SMarcel Moolenaar lcr |= parity << 3; 28327d5dc18SMarcel Moolenaar 28427d5dc18SMarcel Moolenaar /* Set baudrate. */ 28527d5dc18SMarcel Moolenaar if (baudrate > 0) { 28627d5dc18SMarcel Moolenaar divisor = ns8250_divisor(bas->rclk, baudrate); 28727d5dc18SMarcel Moolenaar if (divisor == 0) 28827d5dc18SMarcel Moolenaar return (EINVAL); 28963f8efd3SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 29063f8efd3SMarcel Moolenaar uart_barrier(bas); 29158957d87SBenno Rice uart_setreg(bas, REG_DLL, divisor & 0xff); 29258957d87SBenno Rice uart_setreg(bas, REG_DLH, (divisor >> 8) & 0xff); 29327d5dc18SMarcel Moolenaar uart_barrier(bas); 29427d5dc18SMarcel Moolenaar } 29527d5dc18SMarcel Moolenaar 29627d5dc18SMarcel Moolenaar /* Set LCR and clear DLAB. */ 29727d5dc18SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr); 29827d5dc18SMarcel Moolenaar uart_barrier(bas); 29927d5dc18SMarcel Moolenaar return (0); 30027d5dc18SMarcel Moolenaar } 30127d5dc18SMarcel Moolenaar 30227d5dc18SMarcel Moolenaar /* 30327d5dc18SMarcel Moolenaar * Low-level UART interface. 30427d5dc18SMarcel Moolenaar */ 30527d5dc18SMarcel Moolenaar static int ns8250_probe(struct uart_bas *bas); 30627d5dc18SMarcel Moolenaar static void ns8250_init(struct uart_bas *bas, int, int, int, int); 30727d5dc18SMarcel Moolenaar static void ns8250_term(struct uart_bas *bas); 30827d5dc18SMarcel Moolenaar static void ns8250_putc(struct uart_bas *bas, int); 30997202af2SMarius Strobl static int ns8250_rxready(struct uart_bas *bas); 310634e63c9SMarcel Moolenaar static int ns8250_getc(struct uart_bas *bas, struct mtx *); 31127d5dc18SMarcel Moolenaar 312167cb33fSIan Lepore struct uart_ops uart_ns8250_ops = { 31327d5dc18SMarcel Moolenaar .probe = ns8250_probe, 31427d5dc18SMarcel Moolenaar .init = ns8250_init, 31527d5dc18SMarcel Moolenaar .term = ns8250_term, 31627d5dc18SMarcel Moolenaar .putc = ns8250_putc, 31797202af2SMarius Strobl .rxready = ns8250_rxready, 31827d5dc18SMarcel Moolenaar .getc = ns8250_getc, 31927d5dc18SMarcel Moolenaar }; 32027d5dc18SMarcel Moolenaar 32127d5dc18SMarcel Moolenaar static int 32227d5dc18SMarcel Moolenaar ns8250_probe(struct uart_bas *bas) 32327d5dc18SMarcel Moolenaar { 3248bceca4fSBenno Rice u_char val; 32527d5dc18SMarcel Moolenaar 32627d5dc18SMarcel Moolenaar /* Check known 0 bits that don't depend on DLAB. */ 32727d5dc18SMarcel Moolenaar val = uart_getreg(bas, REG_IIR); 32827d5dc18SMarcel Moolenaar if (val & 0x30) 32927d5dc18SMarcel Moolenaar return (ENXIO); 3305bdddc29SMarcel Moolenaar /* 3315bdddc29SMarcel Moolenaar * Bit 6 of the MCR (= 0x40) appears to be 1 for the Sun1699 3325bdddc29SMarcel Moolenaar * chip, but otherwise doesn't seem to have a function. In 3335bdddc29SMarcel Moolenaar * other words, uart(4) works regardless. Ignore that bit so 3345bdddc29SMarcel Moolenaar * the probe succeeds. 3355bdddc29SMarcel Moolenaar */ 33627d5dc18SMarcel Moolenaar val = uart_getreg(bas, REG_MCR); 3375bdddc29SMarcel Moolenaar if (val & 0xa0) 33827d5dc18SMarcel Moolenaar return (ENXIO); 33927d5dc18SMarcel Moolenaar 34027d5dc18SMarcel Moolenaar return (0); 34127d5dc18SMarcel Moolenaar } 34227d5dc18SMarcel Moolenaar 34327d5dc18SMarcel Moolenaar static void 34427d5dc18SMarcel Moolenaar ns8250_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, 34527d5dc18SMarcel Moolenaar int parity) 34627d5dc18SMarcel Moolenaar { 347f25b0d6dSOskar Holmlund u_char ier; 34827d5dc18SMarcel Moolenaar 34927d5dc18SMarcel Moolenaar if (bas->rclk == 0) 35027d5dc18SMarcel Moolenaar bas->rclk = DEFAULT_RCLK; 35127d5dc18SMarcel Moolenaar ns8250_param(bas, baudrate, databits, stopbits, parity); 35227d5dc18SMarcel Moolenaar 35327d5dc18SMarcel Moolenaar /* Disable all interrupt sources. */ 3540aefb0a6SBenno Rice /* 3550aefb0a6SBenno Rice * We use 0xe0 instead of 0xf0 as the mask because the XScale PXA 3560aefb0a6SBenno Rice * UARTs split the receive time-out interrupt bit out separately as 3570aefb0a6SBenno Rice * 0x10. This gets handled by ier_mask and ier_rxbits below. 3580aefb0a6SBenno Rice */ 3590aefb0a6SBenno Rice ier = uart_getreg(bas, REG_IER) & 0xe0; 36058957d87SBenno Rice uart_setreg(bas, REG_IER, ier); 36127d5dc18SMarcel Moolenaar uart_barrier(bas); 36227d5dc18SMarcel Moolenaar 36327d5dc18SMarcel Moolenaar /* Disable the FIFO (if present). */ 364f25b0d6dSOskar Holmlund uart_setreg(bas, REG_FCR, 0); 36527d5dc18SMarcel Moolenaar uart_barrier(bas); 36627d5dc18SMarcel Moolenaar 36727d5dc18SMarcel Moolenaar /* Set RTS & DTR. */ 36827d5dc18SMarcel Moolenaar uart_setreg(bas, REG_MCR, MCR_IE | MCR_RTS | MCR_DTR); 36927d5dc18SMarcel Moolenaar uart_barrier(bas); 37027d5dc18SMarcel Moolenaar 37127d5dc18SMarcel Moolenaar ns8250_clrint(bas); 37227d5dc18SMarcel Moolenaar } 37327d5dc18SMarcel Moolenaar 37427d5dc18SMarcel Moolenaar static void 37527d5dc18SMarcel Moolenaar ns8250_term(struct uart_bas *bas) 37627d5dc18SMarcel Moolenaar { 37727d5dc18SMarcel Moolenaar 37827d5dc18SMarcel Moolenaar /* Clear RTS & DTR. */ 37927d5dc18SMarcel Moolenaar uart_setreg(bas, REG_MCR, MCR_IE); 38027d5dc18SMarcel Moolenaar uart_barrier(bas); 38127d5dc18SMarcel Moolenaar } 38227d5dc18SMarcel Moolenaar 38327d5dc18SMarcel Moolenaar static void 38427d5dc18SMarcel Moolenaar ns8250_putc(struct uart_bas *bas, int c) 38527d5dc18SMarcel Moolenaar { 38635777a2aSMarcel Moolenaar int limit; 38727d5dc18SMarcel Moolenaar 3888ea7fa16SWei Hu if (vm_guest != VM_GUEST_HV) { 38935777a2aSMarcel Moolenaar limit = 250000; 39027d5dc18SMarcel Moolenaar while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0 && --limit) 39135777a2aSMarcel Moolenaar DELAY(4); 3928ea7fa16SWei Hu } 39327d5dc18SMarcel Moolenaar uart_setreg(bas, REG_DATA, c); 3944e55f723SMarcel Moolenaar uart_barrier(bas); 39527d5dc18SMarcel Moolenaar } 39627d5dc18SMarcel Moolenaar 39727d5dc18SMarcel Moolenaar static int 39897202af2SMarius Strobl ns8250_rxready(struct uart_bas *bas) 39927d5dc18SMarcel Moolenaar { 40027d5dc18SMarcel Moolenaar 40197202af2SMarius Strobl return ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) != 0 ? 1 : 0); 40227d5dc18SMarcel Moolenaar } 40327d5dc18SMarcel Moolenaar 40427d5dc18SMarcel Moolenaar static int 405634e63c9SMarcel Moolenaar ns8250_getc(struct uart_bas *bas, struct mtx *hwmtx) 40627d5dc18SMarcel Moolenaar { 40735777a2aSMarcel Moolenaar int c; 408634e63c9SMarcel Moolenaar 409634e63c9SMarcel Moolenaar uart_lock(hwmtx); 41027d5dc18SMarcel Moolenaar 411634e63c9SMarcel Moolenaar while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0) { 412634e63c9SMarcel Moolenaar uart_unlock(hwmtx); 41335777a2aSMarcel Moolenaar DELAY(4); 414634e63c9SMarcel Moolenaar uart_lock(hwmtx); 415634e63c9SMarcel Moolenaar } 416634e63c9SMarcel Moolenaar 417634e63c9SMarcel Moolenaar c = uart_getreg(bas, REG_DATA); 418634e63c9SMarcel Moolenaar 419634e63c9SMarcel Moolenaar uart_unlock(hwmtx); 420634e63c9SMarcel Moolenaar 421634e63c9SMarcel Moolenaar return (c); 42227d5dc18SMarcel Moolenaar } 42327d5dc18SMarcel Moolenaar 42427d5dc18SMarcel Moolenaar static kobj_method_t ns8250_methods[] = { 42527d5dc18SMarcel Moolenaar KOBJMETHOD(uart_attach, ns8250_bus_attach), 42627d5dc18SMarcel Moolenaar KOBJMETHOD(uart_detach, ns8250_bus_detach), 42727d5dc18SMarcel Moolenaar KOBJMETHOD(uart_flush, ns8250_bus_flush), 42827d5dc18SMarcel Moolenaar KOBJMETHOD(uart_getsig, ns8250_bus_getsig), 42927d5dc18SMarcel Moolenaar KOBJMETHOD(uart_ioctl, ns8250_bus_ioctl), 43027d5dc18SMarcel Moolenaar KOBJMETHOD(uart_ipend, ns8250_bus_ipend), 43127d5dc18SMarcel Moolenaar KOBJMETHOD(uart_param, ns8250_bus_param), 43227d5dc18SMarcel Moolenaar KOBJMETHOD(uart_probe, ns8250_bus_probe), 43327d5dc18SMarcel Moolenaar KOBJMETHOD(uart_receive, ns8250_bus_receive), 43427d5dc18SMarcel Moolenaar KOBJMETHOD(uart_setsig, ns8250_bus_setsig), 43527d5dc18SMarcel Moolenaar KOBJMETHOD(uart_transmit, ns8250_bus_transmit), 436353e4c5aSMarius Strobl KOBJMETHOD(uart_txbusy, ns8250_bus_txbusy), 437d76a1ef4SWarner Losh KOBJMETHOD(uart_grab, ns8250_bus_grab), 438d76a1ef4SWarner Losh KOBJMETHOD(uart_ungrab, ns8250_bus_ungrab), 439353e4c5aSMarius Strobl KOBJMETHOD_END 44027d5dc18SMarcel Moolenaar }; 44127d5dc18SMarcel Moolenaar 44227d5dc18SMarcel Moolenaar struct uart_class uart_ns8250_class = { 443f8100ce2SMarcel Moolenaar "ns8250", 44427d5dc18SMarcel Moolenaar ns8250_methods, 44527d5dc18SMarcel Moolenaar sizeof(struct ns8250_softc), 446f8100ce2SMarcel Moolenaar .uc_ops = &uart_ns8250_ops, 44727d5dc18SMarcel Moolenaar .uc_range = 8, 448405ada37SAndrew Turner .uc_rclk = DEFAULT_RCLK, 449405ada37SAndrew Turner .uc_rshift = 0 45027d5dc18SMarcel Moolenaar }; 45127d5dc18SMarcel Moolenaar 452381388b9SMatt Macy /* 453381388b9SMatt Macy * XXX -- refactor out ACPI and FDT ifdefs 454381388b9SMatt Macy */ 455381388b9SMatt Macy #ifdef DEV_ACPI 456381388b9SMatt Macy static struct acpi_uart_compat_data acpi_compat_data[] = { 457381388b9SMatt Macy {"AMD0020", &uart_ns8250_class, 0, 2, 0, 48000000, UART_F_BUSY_DETECT, "AMD / Synopsys Designware UART"}, 458381388b9SMatt Macy {"AMDI0020", &uart_ns8250_class, 0, 2, 0, 48000000, UART_F_BUSY_DETECT, "AMD / Synopsys Designware UART"}, 4599cf66a04SMarcin Wojtas {"MRVL0001", &uart_ns8250_class, ACPI_DBG2_16550_SUBSET, 2, 0, 200000000, UART_F_BUSY_DETECT, "Marvell / Synopsys Designware UART"}, 460a852cb95SRebecca Cran {"SCX0006", &uart_ns8250_class, 0, 2, 0, 62500000, UART_F_BUSY_DETECT, "SynQuacer / Synopsys Designware UART"}, 461a852cb95SRebecca Cran {"HISI0031", &uart_ns8250_class, 0, 2, 0, 200000000, UART_F_BUSY_DETECT, "HiSilicon / Synopsys Designware UART"}, 4627cb73f65SMateusz Kozyra {"NXP0018", &uart_ns8250_class, 0, 0, 0, 350000000, UART_F_BUSY_DETECT, "NXP / Synopsys Designware UART"}, 463381388b9SMatt Macy {"PNP0500", &uart_ns8250_class, 0, 0, 0, 0, 0, "Standard PC COM port"}, 464381388b9SMatt Macy {"PNP0501", &uart_ns8250_class, 0, 0, 0, 0, 0, "16550A-compatible COM port"}, 465381388b9SMatt Macy {"PNP0502", &uart_ns8250_class, 0, 0, 0, 0, 0, "Multiport serial device (non-intelligent 16550)"}, 466381388b9SMatt Macy {"PNP0510", &uart_ns8250_class, 0, 0, 0, 0, 0, "Generic IRDA-compatible device"}, 467381388b9SMatt Macy {"PNP0511", &uart_ns8250_class, 0, 0, 0, 0, 0, "Generic IRDA-compatible device"}, 468381388b9SMatt Macy {"WACF004", &uart_ns8250_class, 0, 0, 0, 0, 0, "Wacom Tablet PC Screen"}, 469381388b9SMatt Macy {"WACF00E", &uart_ns8250_class, 0, 0, 0, 0, 0, "Wacom Tablet PC Screen 00e"}, 470381388b9SMatt Macy {"FUJ02E5", &uart_ns8250_class, 0, 0, 0, 0, 0, "Wacom Tablet at FuS Lifebook T"}, 471381388b9SMatt Macy {NULL, NULL, 0, 0 , 0, 0, 0, NULL}, 472381388b9SMatt Macy }; 473381388b9SMatt Macy UART_ACPI_CLASS_AND_DEVICE(acpi_compat_data); 474381388b9SMatt Macy #endif 475381388b9SMatt Macy 4763bb693afSIan Lepore #ifdef FDT 4773bb693afSIan Lepore static struct ofw_compat_data compat_data[] = { 4783bb693afSIan Lepore {"ns16550", (uintptr_t)&uart_ns8250_class}, 4793b654e08SWojciech Macek {"ns16550a", (uintptr_t)&uart_ns8250_class}, 4803bb693afSIan Lepore {NULL, (uintptr_t)NULL}, 4813bb693afSIan Lepore }; 4823bb693afSIan Lepore UART_FDT_CLASS_AND_DEVICE(compat_data); 4833bb693afSIan Lepore #endif 4843bb693afSIan Lepore 485fdfbb3f5SIan Lepore /* Use token-pasting to form SER_ and MSR_ named constants. */ 486fdfbb3f5SIan Lepore #define SER(sig) SER_##sig 487fdfbb3f5SIan Lepore #define SERD(sig) SER_D##sig 488fdfbb3f5SIan Lepore #define MSR(sig) MSR_##sig 489fdfbb3f5SIan Lepore #define MSRD(sig) MSR_D##sig 490fdfbb3f5SIan Lepore 491fdfbb3f5SIan Lepore /* 492fdfbb3f5SIan Lepore * Detect signal changes using software delta detection. The previous state of 493fdfbb3f5SIan Lepore * the signals is in 'var' the new hardware state is in 'msr', and 'sig' is the 494fdfbb3f5SIan Lepore * short name (DCD, CTS, etc) of the signal bit being processed; 'var' gets the 495fdfbb3f5SIan Lepore * new state of both the signal and the delta bits. 496fdfbb3f5SIan Lepore */ 497fdfbb3f5SIan Lepore #define SIGCHGSW(var, msr, sig) \ 498fdfbb3f5SIan Lepore if ((msr) & MSR(sig)) { \ 499fdfbb3f5SIan Lepore if ((var & SER(sig)) == 0) \ 500fdfbb3f5SIan Lepore var |= SERD(sig) | SER(sig); \ 50127d5dc18SMarcel Moolenaar } else { \ 502fdfbb3f5SIan Lepore if ((var & SER(sig)) != 0) \ 503fdfbb3f5SIan Lepore var = SERD(sig) | (var & ~SER(sig)); \ 504fdfbb3f5SIan Lepore } 505fdfbb3f5SIan Lepore 506fdfbb3f5SIan Lepore /* 507fdfbb3f5SIan Lepore * Detect signal changes using the hardware msr delta bits. This is currently 508fdfbb3f5SIan Lepore * used only when PPS timing information is being captured using the "narrow 509fdfbb3f5SIan Lepore * pulse" option. With a narrow PPS pulse the signal may not still be asserted 510fdfbb3f5SIan Lepore * by time the interrupt handler is invoked. The hardware will latch the fact 511fdfbb3f5SIan Lepore * that it changed in the delta bits. 512fdfbb3f5SIan Lepore */ 513fdfbb3f5SIan Lepore #define SIGCHGHW(var, msr, sig) \ 514fdfbb3f5SIan Lepore if ((msr) & MSRD(sig)) { \ 515fdfbb3f5SIan Lepore if (((msr) & MSR(sig)) != 0) \ 516fdfbb3f5SIan Lepore var |= SERD(sig) | SER(sig); \ 517fdfbb3f5SIan Lepore else \ 518fdfbb3f5SIan Lepore var = SERD(sig) | (var & ~SER(sig)); \ 51927d5dc18SMarcel Moolenaar } 52027d5dc18SMarcel Moolenaar 521167cb33fSIan Lepore int 52227d5dc18SMarcel Moolenaar ns8250_bus_attach(struct uart_softc *sc) 52327d5dc18SMarcel Moolenaar { 52427d5dc18SMarcel Moolenaar struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 52527d5dc18SMarcel Moolenaar struct uart_bas *bas; 526823c77d7SSam Leffler unsigned int ivar; 527ac4adddfSGanbold Tsagaankhuu #ifdef FDT 528ac4adddfSGanbold Tsagaankhuu phandle_t node; 529ac4adddfSGanbold Tsagaankhuu pcell_t cell; 530ac4adddfSGanbold Tsagaankhuu #endif 531ac4adddfSGanbold Tsagaankhuu 532ac4adddfSGanbold Tsagaankhuu #ifdef FDT 533b738dafdSJared McNeill /* Check whether uart has a broken txfifo. */ 534ac4adddfSGanbold Tsagaankhuu node = ofw_bus_get_node(sc->sc_dev); 535b1621f22SLuiz Otavio O Souza if ((OF_getencprop(node, "broken-txfifo", &cell, sizeof(cell))) > 0) 536b1621f22SLuiz Otavio O Souza broken_txfifo = cell ? 1 : 0; 537ac4adddfSGanbold Tsagaankhuu #endif 53827d5dc18SMarcel Moolenaar 53927d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 54027d5dc18SMarcel Moolenaar 541f30f0f2bSMatt Macy ns8250->busy_detect = bas->busy_detect; 54227d5dc18SMarcel Moolenaar ns8250->mcr = uart_getreg(bas, REG_MCR); 543823c77d7SSam Leffler ns8250->fcr = FCR_ENABLE; 544823c77d7SSam Leffler if (!resource_int_value("uart", device_get_unit(sc->sc_dev), "flags", 545823c77d7SSam Leffler &ivar)) { 546823c77d7SSam Leffler if (UART_FLAGS_FCR_RX_LOW(ivar)) 547823c77d7SSam Leffler ns8250->fcr |= FCR_RX_LOW; 548823c77d7SSam Leffler else if (UART_FLAGS_FCR_RX_MEDL(ivar)) 549823c77d7SSam Leffler ns8250->fcr |= FCR_RX_MEDL; 550823c77d7SSam Leffler else if (UART_FLAGS_FCR_RX_HIGH(ivar)) 551823c77d7SSam Leffler ns8250->fcr |= FCR_RX_HIGH; 552823c77d7SSam Leffler else 553823c77d7SSam Leffler ns8250->fcr |= FCR_RX_MEDH; 554823c77d7SSam Leffler } else 555823c77d7SSam Leffler ns8250->fcr |= FCR_RX_MEDH; 5560aefb0a6SBenno Rice 5570aefb0a6SBenno Rice /* Get IER mask */ 5580aefb0a6SBenno Rice ivar = 0xf0; 5590aefb0a6SBenno Rice resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_mask", 5600aefb0a6SBenno Rice &ivar); 5610aefb0a6SBenno Rice ns8250->ier_mask = (uint8_t)(ivar & 0xff); 5620aefb0a6SBenno Rice 5630aefb0a6SBenno Rice /* Get IER RX interrupt bits */ 5640aefb0a6SBenno Rice ivar = IER_EMSC | IER_ERLS | IER_ERXRDY; 5650aefb0a6SBenno Rice resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_rxbits", 5660aefb0a6SBenno Rice &ivar); 5670aefb0a6SBenno Rice ns8250->ier_rxbits = (uint8_t)(ivar & 0xff); 5680aefb0a6SBenno Rice 56927d5dc18SMarcel Moolenaar uart_setreg(bas, REG_FCR, ns8250->fcr); 57027d5dc18SMarcel Moolenaar uart_barrier(bas); 57127d5dc18SMarcel Moolenaar ns8250_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 57227d5dc18SMarcel Moolenaar 57327d5dc18SMarcel Moolenaar if (ns8250->mcr & MCR_DTR) 57428710806SPoul-Henning Kamp sc->sc_hwsig |= SER_DTR; 57527d5dc18SMarcel Moolenaar if (ns8250->mcr & MCR_RTS) 57628710806SPoul-Henning Kamp sc->sc_hwsig |= SER_RTS; 57727d5dc18SMarcel Moolenaar ns8250_bus_getsig(sc); 57827d5dc18SMarcel Moolenaar 57927d5dc18SMarcel Moolenaar ns8250_clrint(bas); 5800aefb0a6SBenno Rice ns8250->ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 5810aefb0a6SBenno Rice ns8250->ier |= ns8250->ier_rxbits; 58227d5dc18SMarcel Moolenaar uart_setreg(bas, REG_IER, ns8250->ier); 58327d5dc18SMarcel Moolenaar uart_barrier(bas); 5840aefb0a6SBenno Rice 5854fc49975SMarcel Moolenaar /* 5864fc49975SMarcel Moolenaar * Timing of the H/W access was changed with r253161 of uart_core.c 5874fc49975SMarcel Moolenaar * It has been observed that an ITE IT8513E would signal a break 5884fc49975SMarcel Moolenaar * condition with pretty much every character it received, unless 5894fc49975SMarcel Moolenaar * it had enough time to settle between ns8250_bus_attach() and 5904fc49975SMarcel Moolenaar * ns8250_bus_ipend() -- which it accidentally had before r253161. 5914fc49975SMarcel Moolenaar * It's not understood why the UART chip behaves this way and it 5924fc49975SMarcel Moolenaar * could very well be that the DELAY make the H/W work in the same 5934fc49975SMarcel Moolenaar * accidental manner as before. More analysis is warranted, but 5944fc49975SMarcel Moolenaar * at least now we fixed a known regression. 5954fc49975SMarcel Moolenaar */ 59640a827b6SMarcel Moolenaar DELAY(200); 59727d5dc18SMarcel Moolenaar return (0); 59827d5dc18SMarcel Moolenaar } 59927d5dc18SMarcel Moolenaar 600167cb33fSIan Lepore int 60127d5dc18SMarcel Moolenaar ns8250_bus_detach(struct uart_softc *sc) 60227d5dc18SMarcel Moolenaar { 6030aefb0a6SBenno Rice struct ns8250_softc *ns8250; 60427d5dc18SMarcel Moolenaar struct uart_bas *bas; 60558957d87SBenno Rice u_char ier; 60627d5dc18SMarcel Moolenaar 6070aefb0a6SBenno Rice ns8250 = (struct ns8250_softc *)sc; 60827d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 6090aefb0a6SBenno Rice ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 61058957d87SBenno Rice uart_setreg(bas, REG_IER, ier); 61127d5dc18SMarcel Moolenaar uart_barrier(bas); 61227d5dc18SMarcel Moolenaar ns8250_clrint(bas); 61327d5dc18SMarcel Moolenaar return (0); 61427d5dc18SMarcel Moolenaar } 61527d5dc18SMarcel Moolenaar 616167cb33fSIan Lepore int 61727d5dc18SMarcel Moolenaar ns8250_bus_flush(struct uart_softc *sc, int what) 61827d5dc18SMarcel Moolenaar { 61927d5dc18SMarcel Moolenaar struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 62027d5dc18SMarcel Moolenaar struct uart_bas *bas; 62106287620SMarcel Moolenaar int error; 62227d5dc18SMarcel Moolenaar 62327d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 6248af03381SMarcel Moolenaar uart_lock(sc->sc_hwmtx); 6258d1289feSMarcel Moolenaar if (sc->sc_rxfifosz > 1) { 62627d5dc18SMarcel Moolenaar ns8250_flush(bas, what); 62727d5dc18SMarcel Moolenaar uart_setreg(bas, REG_FCR, ns8250->fcr); 62827d5dc18SMarcel Moolenaar uart_barrier(bas); 62906287620SMarcel Moolenaar error = 0; 63006287620SMarcel Moolenaar } else 63106287620SMarcel Moolenaar error = ns8250_drain(bas, what); 6328af03381SMarcel Moolenaar uart_unlock(sc->sc_hwmtx); 63306287620SMarcel Moolenaar return (error); 63427d5dc18SMarcel Moolenaar } 63527d5dc18SMarcel Moolenaar 636167cb33fSIan Lepore int 63727d5dc18SMarcel Moolenaar ns8250_bus_getsig(struct uart_softc *sc) 63827d5dc18SMarcel Moolenaar { 639fdfbb3f5SIan Lepore uint32_t old, sig; 64027d5dc18SMarcel Moolenaar uint8_t msr; 64127d5dc18SMarcel Moolenaar 642fdfbb3f5SIan Lepore /* 643fdfbb3f5SIan Lepore * The delta bits are reputed to be broken on some hardware, so use 644fdfbb3f5SIan Lepore * software delta detection by default. Use the hardware delta bits 645fdfbb3f5SIan Lepore * when capturing PPS pulses which are too narrow for software detection 646fdfbb3f5SIan Lepore * to see the edges. Hardware delta for RI doesn't work like the 647fdfbb3f5SIan Lepore * others, so always use software for it. Other threads may be changing 648453130d9SPedro F. Giffuni * other (non-MSR) bits in sc_hwsig, so loop until it can successfully 649fdfbb3f5SIan Lepore * update without other changes happening. Note that the SIGCHGxx() 650fdfbb3f5SIan Lepore * macros carefully preserve the delta bits when we have to loop several 651fdfbb3f5SIan Lepore * times and a signal transitions between iterations. 652fdfbb3f5SIan Lepore */ 65327d5dc18SMarcel Moolenaar do { 65427d5dc18SMarcel Moolenaar old = sc->sc_hwsig; 65527d5dc18SMarcel Moolenaar sig = old; 6568af03381SMarcel Moolenaar uart_lock(sc->sc_hwmtx); 65727d5dc18SMarcel Moolenaar msr = uart_getreg(&sc->sc_bas, REG_MSR); 6588af03381SMarcel Moolenaar uart_unlock(sc->sc_hwmtx); 659fdfbb3f5SIan Lepore if (sc->sc_pps_mode & UART_PPS_NARROW_PULSE) { 660fdfbb3f5SIan Lepore SIGCHGHW(sig, msr, DSR); 661fdfbb3f5SIan Lepore SIGCHGHW(sig, msr, CTS); 662fdfbb3f5SIan Lepore SIGCHGHW(sig, msr, DCD); 663fdfbb3f5SIan Lepore } else { 664fdfbb3f5SIan Lepore SIGCHGSW(sig, msr, DSR); 665fdfbb3f5SIan Lepore SIGCHGSW(sig, msr, CTS); 666fdfbb3f5SIan Lepore SIGCHGSW(sig, msr, DCD); 667fdfbb3f5SIan Lepore } 668fdfbb3f5SIan Lepore SIGCHGSW(sig, msr, RI); 669fdfbb3f5SIan Lepore } while (!atomic_cmpset_32(&sc->sc_hwsig, old, sig & ~SER_MASK_DELTA)); 67027d5dc18SMarcel Moolenaar return (sig); 67127d5dc18SMarcel Moolenaar } 67227d5dc18SMarcel Moolenaar 673167cb33fSIan Lepore int 67427d5dc18SMarcel Moolenaar ns8250_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) 67527d5dc18SMarcel Moolenaar { 67627d5dc18SMarcel Moolenaar struct uart_bas *bas; 677bfa307a3SMarcel Moolenaar int baudrate, divisor, error; 67884c7b427SMarcel Moolenaar uint8_t efr, lcr; 67927d5dc18SMarcel Moolenaar 68027d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 68106287620SMarcel Moolenaar error = 0; 6828af03381SMarcel Moolenaar uart_lock(sc->sc_hwmtx); 68327d5dc18SMarcel Moolenaar switch (request) { 68427d5dc18SMarcel Moolenaar case UART_IOCTL_BREAK: 68527d5dc18SMarcel Moolenaar lcr = uart_getreg(bas, REG_LCR); 68627d5dc18SMarcel Moolenaar if (data) 68727d5dc18SMarcel Moolenaar lcr |= LCR_SBREAK; 68827d5dc18SMarcel Moolenaar else 68927d5dc18SMarcel Moolenaar lcr &= ~LCR_SBREAK; 69027d5dc18SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr); 69127d5dc18SMarcel Moolenaar uart_barrier(bas); 69227d5dc18SMarcel Moolenaar break; 69384c7b427SMarcel Moolenaar case UART_IOCTL_IFLOW: 69484c7b427SMarcel Moolenaar lcr = uart_getreg(bas, REG_LCR); 69584c7b427SMarcel Moolenaar uart_barrier(bas); 69684c7b427SMarcel Moolenaar uart_setreg(bas, REG_LCR, 0xbf); 69784c7b427SMarcel Moolenaar uart_barrier(bas); 69884c7b427SMarcel Moolenaar efr = uart_getreg(bas, REG_EFR); 69984c7b427SMarcel Moolenaar if (data) 70084c7b427SMarcel Moolenaar efr |= EFR_RTS; 70184c7b427SMarcel Moolenaar else 70284c7b427SMarcel Moolenaar efr &= ~EFR_RTS; 70384c7b427SMarcel Moolenaar uart_setreg(bas, REG_EFR, efr); 70484c7b427SMarcel Moolenaar uart_barrier(bas); 70584c7b427SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr); 70684c7b427SMarcel Moolenaar uart_barrier(bas); 70784c7b427SMarcel Moolenaar break; 70884c7b427SMarcel Moolenaar case UART_IOCTL_OFLOW: 70984c7b427SMarcel Moolenaar lcr = uart_getreg(bas, REG_LCR); 71084c7b427SMarcel Moolenaar uart_barrier(bas); 71184c7b427SMarcel Moolenaar uart_setreg(bas, REG_LCR, 0xbf); 71284c7b427SMarcel Moolenaar uart_barrier(bas); 71384c7b427SMarcel Moolenaar efr = uart_getreg(bas, REG_EFR); 71484c7b427SMarcel Moolenaar if (data) 71584c7b427SMarcel Moolenaar efr |= EFR_CTS; 71684c7b427SMarcel Moolenaar else 71784c7b427SMarcel Moolenaar efr &= ~EFR_CTS; 71884c7b427SMarcel Moolenaar uart_setreg(bas, REG_EFR, efr); 71984c7b427SMarcel Moolenaar uart_barrier(bas); 72084c7b427SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr); 72184c7b427SMarcel Moolenaar uart_barrier(bas); 72284c7b427SMarcel Moolenaar break; 723d8518925SMarcel Moolenaar case UART_IOCTL_BAUD: 724d8518925SMarcel Moolenaar lcr = uart_getreg(bas, REG_LCR); 725d8518925SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 726d8518925SMarcel Moolenaar uart_barrier(bas); 72758957d87SBenno Rice divisor = uart_getreg(bas, REG_DLL) | 72858957d87SBenno Rice (uart_getreg(bas, REG_DLH) << 8); 729d8518925SMarcel Moolenaar uart_barrier(bas); 730d8518925SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr); 731d8518925SMarcel Moolenaar uart_barrier(bas); 732bfa307a3SMarcel Moolenaar baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0; 733bfa307a3SMarcel Moolenaar if (baudrate > 0) 734bfa307a3SMarcel Moolenaar *(int*)data = baudrate; 735bfa307a3SMarcel Moolenaar else 736bfa307a3SMarcel Moolenaar error = ENXIO; 737d8518925SMarcel Moolenaar break; 73827d5dc18SMarcel Moolenaar default: 73906287620SMarcel Moolenaar error = EINVAL; 74006287620SMarcel Moolenaar break; 74127d5dc18SMarcel Moolenaar } 7428af03381SMarcel Moolenaar uart_unlock(sc->sc_hwmtx); 74306287620SMarcel Moolenaar return (error); 74427d5dc18SMarcel Moolenaar } 74527d5dc18SMarcel Moolenaar 746167cb33fSIan Lepore int 74727d5dc18SMarcel Moolenaar ns8250_bus_ipend(struct uart_softc *sc) 74827d5dc18SMarcel Moolenaar { 74927d5dc18SMarcel Moolenaar struct uart_bas *bas; 75011e55f91SOlivier Houchard struct ns8250_softc *ns8250; 75127d5dc18SMarcel Moolenaar int ipend; 75227d5dc18SMarcel Moolenaar uint8_t iir, lsr; 75327d5dc18SMarcel Moolenaar 75411e55f91SOlivier Houchard ns8250 = (struct ns8250_softc *)sc; 75527d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 7568af03381SMarcel Moolenaar uart_lock(sc->sc_hwmtx); 75727d5dc18SMarcel Moolenaar iir = uart_getreg(bas, REG_IIR); 758ac4adddfSGanbold Tsagaankhuu 759ac4adddfSGanbold Tsagaankhuu if (ns8250->busy_detect && (iir & IIR_BUSY) == IIR_BUSY) { 760ac4adddfSGanbold Tsagaankhuu (void)uart_getreg(bas, DW_REG_USR); 761ac4adddfSGanbold Tsagaankhuu uart_unlock(sc->sc_hwmtx); 762ac4adddfSGanbold Tsagaankhuu return (0); 763ac4adddfSGanbold Tsagaankhuu } 76406287620SMarcel Moolenaar if (iir & IIR_NOPEND) { 7658af03381SMarcel Moolenaar uart_unlock(sc->sc_hwmtx); 76627d5dc18SMarcel Moolenaar return (0); 76706287620SMarcel Moolenaar } 76827d5dc18SMarcel Moolenaar ipend = 0; 76927d5dc18SMarcel Moolenaar if (iir & IIR_RXRDY) { 77027d5dc18SMarcel Moolenaar lsr = uart_getreg(bas, REG_LSR); 77127d5dc18SMarcel Moolenaar if (lsr & LSR_OE) 7722d511805SMarcel Moolenaar ipend |= SER_INT_OVERRUN; 77327d5dc18SMarcel Moolenaar if (lsr & LSR_BI) 7742d511805SMarcel Moolenaar ipend |= SER_INT_BREAK; 77527d5dc18SMarcel Moolenaar if (lsr & LSR_RXRDY) 7762d511805SMarcel Moolenaar ipend |= SER_INT_RXREADY; 77727d5dc18SMarcel Moolenaar } else { 77811e55f91SOlivier Houchard if (iir & IIR_TXRDY) { 7792d511805SMarcel Moolenaar ipend |= SER_INT_TXIDLE; 7807e7f7beeSMitchell Horne ns8250->ier &= ~IER_ETXRDY; 78111e55f91SOlivier Houchard uart_setreg(bas, REG_IER, ns8250->ier); 7823c7b9077SMichal Meloun uart_barrier(bas); 78311e55f91SOlivier Houchard } else 7842d511805SMarcel Moolenaar ipend |= SER_INT_SIGCHG; 78527d5dc18SMarcel Moolenaar } 786d7ae5af5SMarcel Moolenaar if (ipend == 0) 787d7ae5af5SMarcel Moolenaar ns8250_clrint(bas); 788d7ae5af5SMarcel Moolenaar uart_unlock(sc->sc_hwmtx); 789f6ffc3c2SMarius Strobl return (ipend); 79027d5dc18SMarcel Moolenaar } 79127d5dc18SMarcel Moolenaar 792167cb33fSIan Lepore int 79327d5dc18SMarcel Moolenaar ns8250_bus_param(struct uart_softc *sc, int baudrate, int databits, 79427d5dc18SMarcel Moolenaar int stopbits, int parity) 79527d5dc18SMarcel Moolenaar { 79649e368acSZbigniew Bodek struct ns8250_softc *ns8250; 79727d5dc18SMarcel Moolenaar struct uart_bas *bas; 79849e368acSZbigniew Bodek int error, limit; 79927d5dc18SMarcel Moolenaar 80049e368acSZbigniew Bodek ns8250 = (struct ns8250_softc*)sc; 80127d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 8028af03381SMarcel Moolenaar uart_lock(sc->sc_hwmtx); 80349e368acSZbigniew Bodek /* 80449e368acSZbigniew Bodek * When using DW UART with BUSY detection it is necessary to wait 80549e368acSZbigniew Bodek * until all serial transfers are finished before manipulating the 80649e368acSZbigniew Bodek * line control. LCR will not be affected when UART is busy. 80749e368acSZbigniew Bodek */ 80849e368acSZbigniew Bodek if (ns8250->busy_detect != 0) { 80949e368acSZbigniew Bodek /* 81049e368acSZbigniew Bodek * Pick an arbitrary high limit to avoid getting stuck in 81149e368acSZbigniew Bodek * an infinite loop in case when the hardware is broken. 81249e368acSZbigniew Bodek */ 81349e368acSZbigniew Bodek limit = 10 * 1024; 81449e368acSZbigniew Bodek while (((uart_getreg(bas, DW_REG_USR) & USR_BUSY) != 0) && 81549e368acSZbigniew Bodek --limit) 81649e368acSZbigniew Bodek DELAY(4); 81749e368acSZbigniew Bodek 81849e368acSZbigniew Bodek if (limit <= 0) { 81949e368acSZbigniew Bodek /* UART appears to be stuck */ 82049e368acSZbigniew Bodek uart_unlock(sc->sc_hwmtx); 82149e368acSZbigniew Bodek return (EIO); 82249e368acSZbigniew Bodek } 82349e368acSZbigniew Bodek } 82449e368acSZbigniew Bodek 82506287620SMarcel Moolenaar error = ns8250_param(bas, baudrate, databits, stopbits, parity); 8268af03381SMarcel Moolenaar uart_unlock(sc->sc_hwmtx); 82706287620SMarcel Moolenaar return (error); 82827d5dc18SMarcel Moolenaar } 82927d5dc18SMarcel Moolenaar 830167cb33fSIan Lepore int 83127d5dc18SMarcel Moolenaar ns8250_bus_probe(struct uart_softc *sc) 83227d5dc18SMarcel Moolenaar { 83327d5dc18SMarcel Moolenaar struct uart_bas *bas; 83427d5dc18SMarcel Moolenaar int count, delay, error, limit; 83558957d87SBenno Rice uint8_t lsr, mcr, ier; 83627d5dc18SMarcel Moolenaar 83727d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 83827d5dc18SMarcel Moolenaar 83927d5dc18SMarcel Moolenaar error = ns8250_probe(bas); 84027d5dc18SMarcel Moolenaar if (error) 84127d5dc18SMarcel Moolenaar return (error); 84227d5dc18SMarcel Moolenaar 84327d5dc18SMarcel Moolenaar mcr = MCR_IE; 84427d5dc18SMarcel Moolenaar if (sc->sc_sysdev == NULL) { 84527d5dc18SMarcel Moolenaar /* By using ns8250_init() we also set DTR and RTS. */ 846d902fb71SMarcel Moolenaar ns8250_init(bas, 115200, 8, 1, UART_PARITY_NONE); 84727d5dc18SMarcel Moolenaar } else 84827d5dc18SMarcel Moolenaar mcr |= MCR_DTR | MCR_RTS; 84927d5dc18SMarcel Moolenaar 85027d5dc18SMarcel Moolenaar error = ns8250_drain(bas, UART_DRAIN_TRANSMITTER); 85127d5dc18SMarcel Moolenaar if (error) 85227d5dc18SMarcel Moolenaar return (error); 85327d5dc18SMarcel Moolenaar 85427d5dc18SMarcel Moolenaar /* 85527d5dc18SMarcel Moolenaar * Set loopback mode. This avoids having garbage on the wire and 85627d5dc18SMarcel Moolenaar * also allows us send and receive data. We set DTR and RTS to 85727d5dc18SMarcel Moolenaar * avoid the possibility that automatic flow-control prevents 85889eef2deSThomas Moestl * any data from being sent. 85927d5dc18SMarcel Moolenaar */ 86089eef2deSThomas Moestl uart_setreg(bas, REG_MCR, MCR_LOOPBACK | MCR_IE | MCR_DTR | MCR_RTS); 86127d5dc18SMarcel Moolenaar uart_barrier(bas); 86227d5dc18SMarcel Moolenaar 86327d5dc18SMarcel Moolenaar /* 86427d5dc18SMarcel Moolenaar * Enable FIFOs. And check that the UART has them. If not, we're 86589eef2deSThomas Moestl * done. Since this is the first time we enable the FIFOs, we reset 86689eef2deSThomas Moestl * them. 86727d5dc18SMarcel Moolenaar */ 868f25b0d6dSOskar Holmlund uart_setreg(bas, REG_FCR, FCR_ENABLE); 86927d5dc18SMarcel Moolenaar uart_barrier(bas); 8708d1289feSMarcel Moolenaar if (!(uart_getreg(bas, REG_IIR) & IIR_FIFO_MASK)) { 87127d5dc18SMarcel Moolenaar /* 87227d5dc18SMarcel Moolenaar * NS16450 or INS8250. We don't bother to differentiate 87327d5dc18SMarcel Moolenaar * between them. They're too old to be interesting. 87427d5dc18SMarcel Moolenaar */ 87527d5dc18SMarcel Moolenaar uart_setreg(bas, REG_MCR, mcr); 87627d5dc18SMarcel Moolenaar uart_barrier(bas); 8778d1289feSMarcel Moolenaar sc->sc_rxfifosz = sc->sc_txfifosz = 1; 87827d5dc18SMarcel Moolenaar device_set_desc(sc->sc_dev, "8250 or 16450 or compatible"); 87927d5dc18SMarcel Moolenaar return (0); 88027d5dc18SMarcel Moolenaar } 88127d5dc18SMarcel Moolenaar 882f25b0d6dSOskar Holmlund uart_setreg(bas, REG_FCR, FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST); 88327d5dc18SMarcel Moolenaar uart_barrier(bas); 88427d5dc18SMarcel Moolenaar 88527d5dc18SMarcel Moolenaar count = 0; 88627d5dc18SMarcel Moolenaar delay = ns8250_delay(bas); 88727d5dc18SMarcel Moolenaar 88827d5dc18SMarcel Moolenaar /* We have FIFOs. Drain the transmitter and receiver. */ 88927d5dc18SMarcel Moolenaar error = ns8250_drain(bas, UART_DRAIN_RECEIVER|UART_DRAIN_TRANSMITTER); 89027d5dc18SMarcel Moolenaar if (error) { 89127d5dc18SMarcel Moolenaar uart_setreg(bas, REG_MCR, mcr); 892f25b0d6dSOskar Holmlund uart_setreg(bas, REG_FCR, 0); 89327d5dc18SMarcel Moolenaar uart_barrier(bas); 89427d5dc18SMarcel Moolenaar goto describe; 89527d5dc18SMarcel Moolenaar } 89627d5dc18SMarcel Moolenaar 89727d5dc18SMarcel Moolenaar /* 89827d5dc18SMarcel Moolenaar * We should have a sufficiently clean "pipe" to determine the 89927d5dc18SMarcel Moolenaar * size of the FIFOs. We send as much characters as is reasonable 9006bccea7cSRebecca Cran * and wait for the overflow bit in the LSR register to be 90189eef2deSThomas Moestl * asserted, counting the characters as we send them. Based on 90289eef2deSThomas Moestl * that count we know the FIFO size. 90327d5dc18SMarcel Moolenaar */ 90489eef2deSThomas Moestl do { 90527d5dc18SMarcel Moolenaar uart_setreg(bas, REG_DATA, 0); 90627d5dc18SMarcel Moolenaar uart_barrier(bas); 90727d5dc18SMarcel Moolenaar count++; 90827d5dc18SMarcel Moolenaar 90927d5dc18SMarcel Moolenaar limit = 30; 91089eef2deSThomas Moestl lsr = 0; 91189eef2deSThomas Moestl /* 91289eef2deSThomas Moestl * LSR bits are cleared upon read, so we must accumulate 91389eef2deSThomas Moestl * them to be able to test LSR_OE below. 91489eef2deSThomas Moestl */ 91589eef2deSThomas Moestl while (((lsr |= uart_getreg(bas, REG_LSR)) & LSR_TEMT) == 0 && 91689eef2deSThomas Moestl --limit) 91727d5dc18SMarcel Moolenaar DELAY(delay); 91827d5dc18SMarcel Moolenaar if (limit == 0) { 9194a9a4165SMark Johnston /* See the comment in ns8250_init(). */ 9204a9a4165SMark Johnston ier = uart_getreg(bas, REG_IER) & 0xe0; 92158957d87SBenno Rice uart_setreg(bas, REG_IER, ier); 92227d5dc18SMarcel Moolenaar uart_setreg(bas, REG_MCR, mcr); 923f25b0d6dSOskar Holmlund uart_setreg(bas, REG_FCR, 0); 92427d5dc18SMarcel Moolenaar uart_barrier(bas); 92527d5dc18SMarcel Moolenaar count = 0; 92627d5dc18SMarcel Moolenaar goto describe; 92727d5dc18SMarcel Moolenaar } 9286e71b3c3SEd Maste } while ((lsr & LSR_OE) == 0 && count < 260); 92989eef2deSThomas Moestl count--; 93027d5dc18SMarcel Moolenaar 93127d5dc18SMarcel Moolenaar uart_setreg(bas, REG_MCR, mcr); 93227d5dc18SMarcel Moolenaar 93327d5dc18SMarcel Moolenaar /* Reset FIFOs. */ 93427d5dc18SMarcel Moolenaar ns8250_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 93527d5dc18SMarcel Moolenaar 93627d5dc18SMarcel Moolenaar describe: 93789eef2deSThomas Moestl if (count >= 14 && count <= 16) { 93827d5dc18SMarcel Moolenaar sc->sc_rxfifosz = 16; 93927d5dc18SMarcel Moolenaar device_set_desc(sc->sc_dev, "16550 or compatible"); 94089eef2deSThomas Moestl } else if (count >= 28 && count <= 32) { 94127d5dc18SMarcel Moolenaar sc->sc_rxfifosz = 32; 94227d5dc18SMarcel Moolenaar device_set_desc(sc->sc_dev, "16650 or compatible"); 94389eef2deSThomas Moestl } else if (count >= 56 && count <= 64) { 94427d5dc18SMarcel Moolenaar sc->sc_rxfifosz = 64; 94527d5dc18SMarcel Moolenaar device_set_desc(sc->sc_dev, "16750 or compatible"); 94689eef2deSThomas Moestl } else if (count >= 112 && count <= 128) { 94727d5dc18SMarcel Moolenaar sc->sc_rxfifosz = 128; 94827d5dc18SMarcel Moolenaar device_set_desc(sc->sc_dev, "16950 or compatible"); 9496e71b3c3SEd Maste } else if (count >= 224 && count <= 256) { 9506e71b3c3SEd Maste sc->sc_rxfifosz = 256; 9516e71b3c3SEd Maste device_set_desc(sc->sc_dev, "16x50 with 256 byte FIFO"); 95227d5dc18SMarcel Moolenaar } else { 953c21e0da2SMarcel Moolenaar sc->sc_rxfifosz = 16; 95427d5dc18SMarcel Moolenaar device_set_desc(sc->sc_dev, 95527d5dc18SMarcel Moolenaar "Non-standard ns8250 class UART with FIFOs"); 95627d5dc18SMarcel Moolenaar } 95727d5dc18SMarcel Moolenaar 95827d5dc18SMarcel Moolenaar /* 95927d5dc18SMarcel Moolenaar * Force the Tx FIFO size to 16 bytes for now. We don't program the 96027d5dc18SMarcel Moolenaar * Tx trigger. Also, we assume that all data has been sent when the 96127d5dc18SMarcel Moolenaar * interrupt happens. 96227d5dc18SMarcel Moolenaar */ 96327d5dc18SMarcel Moolenaar sc->sc_txfifosz = 16; 96427d5dc18SMarcel Moolenaar 965dc70e792SMarcel Moolenaar #if 0 966dc70e792SMarcel Moolenaar /* 967dc70e792SMarcel Moolenaar * XXX there are some issues related to hardware flow control and 968453130d9SPedro F. Giffuni * it's likely that uart(4) is the cause. This basically needs more 969dc70e792SMarcel Moolenaar * investigation, but we avoid using for hardware flow control 970dc70e792SMarcel Moolenaar * until then. 971dc70e792SMarcel Moolenaar */ 97284c7b427SMarcel Moolenaar /* 16650s or higher have automatic flow control. */ 97384c7b427SMarcel Moolenaar if (sc->sc_rxfifosz > 16) { 97484c7b427SMarcel Moolenaar sc->sc_hwiflow = 1; 97584c7b427SMarcel Moolenaar sc->sc_hwoflow = 1; 97684c7b427SMarcel Moolenaar } 977dc70e792SMarcel Moolenaar #endif 97884c7b427SMarcel Moolenaar 97927d5dc18SMarcel Moolenaar return (0); 98027d5dc18SMarcel Moolenaar } 98127d5dc18SMarcel Moolenaar 982167cb33fSIan Lepore int 98327d5dc18SMarcel Moolenaar ns8250_bus_receive(struct uart_softc *sc) 98427d5dc18SMarcel Moolenaar { 98527d5dc18SMarcel Moolenaar struct uart_bas *bas; 98627d5dc18SMarcel Moolenaar int xc; 98727d5dc18SMarcel Moolenaar uint8_t lsr; 98827d5dc18SMarcel Moolenaar 98927d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 9908af03381SMarcel Moolenaar uart_lock(sc->sc_hwmtx); 99127d5dc18SMarcel Moolenaar lsr = uart_getreg(bas, REG_LSR); 99244ed791bSMarcel Moolenaar while (lsr & LSR_RXRDY) { 99344ed791bSMarcel Moolenaar if (uart_rx_full(sc)) { 99444ed791bSMarcel Moolenaar sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; 99527d5dc18SMarcel Moolenaar break; 99644ed791bSMarcel Moolenaar } 99727d5dc18SMarcel Moolenaar xc = uart_getreg(bas, REG_DATA); 99827d5dc18SMarcel Moolenaar if (lsr & LSR_FE) 99927d5dc18SMarcel Moolenaar xc |= UART_STAT_FRAMERR; 100027d5dc18SMarcel Moolenaar if (lsr & LSR_PE) 100127d5dc18SMarcel Moolenaar xc |= UART_STAT_PARERR; 100227d5dc18SMarcel Moolenaar uart_rx_put(sc, xc); 100344ed791bSMarcel Moolenaar lsr = uart_getreg(bas, REG_LSR); 100444ed791bSMarcel Moolenaar } 100544ed791bSMarcel Moolenaar /* Discard everything left in the Rx FIFO. */ 100644ed791bSMarcel Moolenaar while (lsr & LSR_RXRDY) { 100744ed791bSMarcel Moolenaar (void)uart_getreg(bas, REG_DATA); 100844ed791bSMarcel Moolenaar uart_barrier(bas); 100944ed791bSMarcel Moolenaar lsr = uart_getreg(bas, REG_LSR); 101027d5dc18SMarcel Moolenaar } 10118af03381SMarcel Moolenaar uart_unlock(sc->sc_hwmtx); 101227d5dc18SMarcel Moolenaar return (0); 101327d5dc18SMarcel Moolenaar } 101427d5dc18SMarcel Moolenaar 1015167cb33fSIan Lepore int 101627d5dc18SMarcel Moolenaar ns8250_bus_setsig(struct uart_softc *sc, int sig) 101727d5dc18SMarcel Moolenaar { 101827d5dc18SMarcel Moolenaar struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 101927d5dc18SMarcel Moolenaar struct uart_bas *bas; 102027d5dc18SMarcel Moolenaar uint32_t new, old; 102127d5dc18SMarcel Moolenaar 102227d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 102327d5dc18SMarcel Moolenaar do { 102427d5dc18SMarcel Moolenaar old = sc->sc_hwsig; 102527d5dc18SMarcel Moolenaar new = old; 102628710806SPoul-Henning Kamp if (sig & SER_DDTR) { 1027fdfbb3f5SIan Lepore new = (new & ~SER_DTR) | (sig & (SER_DTR | SER_DDTR)); 102827d5dc18SMarcel Moolenaar } 102928710806SPoul-Henning Kamp if (sig & SER_DRTS) { 1030fdfbb3f5SIan Lepore new = (new & ~SER_RTS) | (sig & (SER_RTS | SER_DRTS)); 103127d5dc18SMarcel Moolenaar } 103227d5dc18SMarcel Moolenaar } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 10338af03381SMarcel Moolenaar uart_lock(sc->sc_hwmtx); 103427d5dc18SMarcel Moolenaar ns8250->mcr &= ~(MCR_DTR|MCR_RTS); 103528710806SPoul-Henning Kamp if (new & SER_DTR) 103627d5dc18SMarcel Moolenaar ns8250->mcr |= MCR_DTR; 103728710806SPoul-Henning Kamp if (new & SER_RTS) 103827d5dc18SMarcel Moolenaar ns8250->mcr |= MCR_RTS; 103927d5dc18SMarcel Moolenaar uart_setreg(bas, REG_MCR, ns8250->mcr); 104027d5dc18SMarcel Moolenaar uart_barrier(bas); 10418af03381SMarcel Moolenaar uart_unlock(sc->sc_hwmtx); 104227d5dc18SMarcel Moolenaar return (0); 104327d5dc18SMarcel Moolenaar } 104427d5dc18SMarcel Moolenaar 1045167cb33fSIan Lepore int 104627d5dc18SMarcel Moolenaar ns8250_bus_transmit(struct uart_softc *sc) 104727d5dc18SMarcel Moolenaar { 104827d5dc18SMarcel Moolenaar struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 104927d5dc18SMarcel Moolenaar struct uart_bas *bas; 105027d5dc18SMarcel Moolenaar int i; 105127d5dc18SMarcel Moolenaar 105227d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 10538af03381SMarcel Moolenaar uart_lock(sc->sc_hwmtx); 105427d5dc18SMarcel Moolenaar while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0) 10554e352a45SAlexander Motin DELAY(4); 105627d5dc18SMarcel Moolenaar for (i = 0; i < sc->sc_txdatasz; i++) { 105727d5dc18SMarcel Moolenaar uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]); 105827d5dc18SMarcel Moolenaar uart_barrier(bas); 105927d5dc18SMarcel Moolenaar } 10607e7f7beeSMitchell Horne if (!broken_txfifo) 10617e7f7beeSMitchell Horne ns8250->ier |= IER_ETXRDY; 10627e7f7beeSMitchell Horne uart_setreg(bas, REG_IER, ns8250->ier); 10633c7b9077SMichal Meloun uart_barrier(bas); 10641c60b24bSColin Percival if (broken_txfifo) 10651c60b24bSColin Percival ns8250_drain(bas, UART_DRAIN_TRANSMITTER); 10661c60b24bSColin Percival else 106727d5dc18SMarcel Moolenaar sc->sc_txbusy = 1; 10688af03381SMarcel Moolenaar uart_unlock(sc->sc_hwmtx); 10691c60b24bSColin Percival if (broken_txfifo) 10701c60b24bSColin Percival uart_sched_softih(sc, SER_INT_TXIDLE); 107127d5dc18SMarcel Moolenaar return (0); 107227d5dc18SMarcel Moolenaar } 1073d76a1ef4SWarner Losh 1074353e4c5aSMarius Strobl bool 1075353e4c5aSMarius Strobl ns8250_bus_txbusy(struct uart_softc *sc) 1076353e4c5aSMarius Strobl { 1077353e4c5aSMarius Strobl struct uart_bas *bas = &sc->sc_bas; 1078353e4c5aSMarius Strobl 1079353e4c5aSMarius Strobl if ((uart_getreg(bas, REG_LSR) & (LSR_TEMT | LSR_THRE)) != 1080353e4c5aSMarius Strobl (LSR_TEMT | LSR_THRE)) 1081353e4c5aSMarius Strobl return (true); 1082353e4c5aSMarius Strobl return (false); 1083353e4c5aSMarius Strobl } 1084353e4c5aSMarius Strobl 1085d76a1ef4SWarner Losh void 1086d76a1ef4SWarner Losh ns8250_bus_grab(struct uart_softc *sc) 1087d76a1ef4SWarner Losh { 1088d76a1ef4SWarner Losh struct uart_bas *bas = &sc->sc_bas; 1089caf6d6b4SOlivier Houchard struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 10908bc9a079SOlivier Houchard u_char ier; 1091d76a1ef4SWarner Losh 1092d76a1ef4SWarner Losh /* 1093d76a1ef4SWarner Losh * turn off all interrupts to enter polling mode. Leave the 1094d76a1ef4SWarner Losh * saved mask alone. We'll restore whatever it was in ungrab. 1095453130d9SPedro F. Giffuni * All pending interrupt signals are reset when IER is set to 0. 1096d76a1ef4SWarner Losh */ 1097d76a1ef4SWarner Losh uart_lock(sc->sc_hwmtx); 10988bc9a079SOlivier Houchard ier = uart_getreg(bas, REG_IER); 10998bc9a079SOlivier Houchard uart_setreg(bas, REG_IER, ier & ns8250->ier_mask); 1100d76a1ef4SWarner Losh uart_barrier(bas); 1101d76a1ef4SWarner Losh uart_unlock(sc->sc_hwmtx); 1102d76a1ef4SWarner Losh } 1103d76a1ef4SWarner Losh 1104d76a1ef4SWarner Losh void 1105d76a1ef4SWarner Losh ns8250_bus_ungrab(struct uart_softc *sc) 1106d76a1ef4SWarner Losh { 1107d76a1ef4SWarner Losh struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 1108d76a1ef4SWarner Losh struct uart_bas *bas = &sc->sc_bas; 1109d76a1ef4SWarner Losh 1110d76a1ef4SWarner Losh /* 1111d76a1ef4SWarner Losh * Restore previous interrupt mask 1112d76a1ef4SWarner Losh */ 1113d76a1ef4SWarner Losh uart_lock(sc->sc_hwmtx); 1114d76a1ef4SWarner Losh uart_setreg(bas, REG_IER, ns8250->ier); 1115d76a1ef4SWarner Losh uart_barrier(bas); 1116d76a1ef4SWarner Losh uart_unlock(sc->sc_hwmtx); 1117d76a1ef4SWarner Losh } 1118