1098ca2bdSWarner Losh /*- 2718cf2ccSPedro F. Giffuni * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3718cf2ccSPedro F. Giffuni * 427d5dc18SMarcel Moolenaar * Copyright (c) 2003 Marcel Moolenaar 527d5dc18SMarcel Moolenaar * All rights reserved. 627d5dc18SMarcel Moolenaar * 727d5dc18SMarcel Moolenaar * Redistribution and use in source and binary forms, with or without 827d5dc18SMarcel Moolenaar * modification, are permitted provided that the following conditions 927d5dc18SMarcel Moolenaar * are met: 1027d5dc18SMarcel Moolenaar * 1127d5dc18SMarcel Moolenaar * 1. Redistributions of source code must retain the above copyright 1227d5dc18SMarcel Moolenaar * notice, this list of conditions and the following disclaimer. 1327d5dc18SMarcel Moolenaar * 2. Redistributions in binary form must reproduce the above copyright 1427d5dc18SMarcel Moolenaar * notice, this list of conditions and the following disclaimer in the 1527d5dc18SMarcel Moolenaar * documentation and/or other materials provided with the distribution. 1627d5dc18SMarcel Moolenaar * 1727d5dc18SMarcel Moolenaar * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 1827d5dc18SMarcel Moolenaar * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 1927d5dc18SMarcel Moolenaar * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 2027d5dc18SMarcel Moolenaar * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 2127d5dc18SMarcel Moolenaar * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 2227d5dc18SMarcel Moolenaar * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2327d5dc18SMarcel Moolenaar * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2427d5dc18SMarcel Moolenaar * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2527d5dc18SMarcel Moolenaar * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 2627d5dc18SMarcel Moolenaar * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2727d5dc18SMarcel Moolenaar */ 2827d5dc18SMarcel Moolenaar 29381388b9SMatt Macy #include "opt_acpi.h" 30ac4adddfSGanbold Tsagaankhuu #include "opt_platform.h" 31e0fe7c95SAdrian Chadd #include "opt_uart.h" 32ac4adddfSGanbold Tsagaankhuu 3327d5dc18SMarcel Moolenaar #include <sys/cdefs.h> 3427d5dc18SMarcel Moolenaar __FBSDID("$FreeBSD$"); 3527d5dc18SMarcel Moolenaar 3627d5dc18SMarcel Moolenaar #include <sys/param.h> 3727d5dc18SMarcel Moolenaar #include <sys/systm.h> 3827d5dc18SMarcel Moolenaar #include <sys/bus.h> 3927d5dc18SMarcel Moolenaar #include <sys/conf.h> 401c60b24bSColin Percival #include <sys/kernel.h> 411c60b24bSColin Percival #include <sys/sysctl.h> 4227d5dc18SMarcel Moolenaar #include <machine/bus.h> 4327d5dc18SMarcel Moolenaar 44ac4adddfSGanbold Tsagaankhuu #ifdef FDT 45ac4adddfSGanbold Tsagaankhuu #include <dev/fdt/fdt_common.h> 46ac4adddfSGanbold Tsagaankhuu #include <dev/ofw/ofw_bus.h> 47ac4adddfSGanbold Tsagaankhuu #include <dev/ofw/ofw_bus_subr.h> 48ac4adddfSGanbold Tsagaankhuu #endif 49ac4adddfSGanbold Tsagaankhuu 5027d5dc18SMarcel Moolenaar #include <dev/uart/uart.h> 5127d5dc18SMarcel Moolenaar #include <dev/uart/uart_cpu.h> 523bb693afSIan Lepore #ifdef FDT 533bb693afSIan Lepore #include <dev/uart/uart_cpu_fdt.h> 543bb693afSIan Lepore #endif 5527d5dc18SMarcel Moolenaar #include <dev/uart/uart_bus.h> 56167cb33fSIan Lepore #include <dev/uart/uart_dev_ns8250.h> 57fdfbb3f5SIan Lepore #include <dev/uart/uart_ppstypes.h> 58381388b9SMatt Macy #ifdef DEV_ACPI 59381388b9SMatt Macy #include <dev/uart/uart_cpu_acpi.h> 60381388b9SMatt Macy #endif 6176563beaSMarcel Moolenaar 6276563beaSMarcel Moolenaar #include <dev/ic/ns16550.h> 6327d5dc18SMarcel Moolenaar 6427d5dc18SMarcel Moolenaar #include "uart_if.h" 6527d5dc18SMarcel Moolenaar 6627d5dc18SMarcel Moolenaar #define DEFAULT_RCLK 1843200 6727d5dc18SMarcel Moolenaar 68e0fe7c95SAdrian Chadd /* 69e0fe7c95SAdrian Chadd * Set the default baudrate tolerance to 3.0%. 70e0fe7c95SAdrian Chadd * 71e0fe7c95SAdrian Chadd * Some embedded boards have odd reference clocks (eg 25MHz) 72e0fe7c95SAdrian Chadd * and we need to handle higher variances in the target baud rate. 73e0fe7c95SAdrian Chadd */ 74e0fe7c95SAdrian Chadd #ifndef UART_DEV_TOLERANCE_PCT 75e0fe7c95SAdrian Chadd #define UART_DEV_TOLERANCE_PCT 30 76e0fe7c95SAdrian Chadd #endif /* UART_DEV_TOLERANCE_PCT */ 77e0fe7c95SAdrian Chadd 78ac4adddfSGanbold Tsagaankhuu static int broken_txfifo = 0; 79af3b2549SHans Petter Selasky SYSCTL_INT(_hw, OID_AUTO, broken_txfifo, CTLFLAG_RWTUN, 80ac4adddfSGanbold Tsagaankhuu &broken_txfifo, 0, "UART FIFO has QEMU emulation bug"); 81ac4adddfSGanbold Tsagaankhuu 8227d5dc18SMarcel Moolenaar /* 8327d5dc18SMarcel Moolenaar * Clear pending interrupts. THRE is cleared by reading IIR. Data 8427d5dc18SMarcel Moolenaar * that may have been received gets lost here. 8527d5dc18SMarcel Moolenaar */ 8627d5dc18SMarcel Moolenaar static void 8727d5dc18SMarcel Moolenaar ns8250_clrint(struct uart_bas *bas) 8827d5dc18SMarcel Moolenaar { 89d7ae5af5SMarcel Moolenaar uint8_t iir, lsr; 9027d5dc18SMarcel Moolenaar 9127d5dc18SMarcel Moolenaar iir = uart_getreg(bas, REG_IIR); 9227d5dc18SMarcel Moolenaar while ((iir & IIR_NOPEND) == 0) { 9327d5dc18SMarcel Moolenaar iir &= IIR_IMASK; 94d7ae5af5SMarcel Moolenaar if (iir == IIR_RLS) { 95d7ae5af5SMarcel Moolenaar lsr = uart_getreg(bas, REG_LSR); 96d7ae5af5SMarcel Moolenaar if (lsr & (LSR_BI|LSR_FE|LSR_PE)) 97d7ae5af5SMarcel Moolenaar (void)uart_getreg(bas, REG_DATA); 98d7ae5af5SMarcel Moolenaar } else if (iir == IIR_RXRDY || iir == IIR_RXTOUT) 9927d5dc18SMarcel Moolenaar (void)uart_getreg(bas, REG_DATA); 10027d5dc18SMarcel Moolenaar else if (iir == IIR_MLSC) 10127d5dc18SMarcel Moolenaar (void)uart_getreg(bas, REG_MSR); 10227d5dc18SMarcel Moolenaar uart_barrier(bas); 10327d5dc18SMarcel Moolenaar iir = uart_getreg(bas, REG_IIR); 10427d5dc18SMarcel Moolenaar } 10527d5dc18SMarcel Moolenaar } 10627d5dc18SMarcel Moolenaar 10727d5dc18SMarcel Moolenaar static int 10827d5dc18SMarcel Moolenaar ns8250_delay(struct uart_bas *bas) 10927d5dc18SMarcel Moolenaar { 11027d5dc18SMarcel Moolenaar int divisor; 11127d5dc18SMarcel Moolenaar u_char lcr; 11227d5dc18SMarcel Moolenaar 11327d5dc18SMarcel Moolenaar lcr = uart_getreg(bas, REG_LCR); 11427d5dc18SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 11527d5dc18SMarcel Moolenaar uart_barrier(bas); 11658957d87SBenno Rice divisor = uart_getreg(bas, REG_DLL) | (uart_getreg(bas, REG_DLH) << 8); 11727d5dc18SMarcel Moolenaar uart_barrier(bas); 11827d5dc18SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr); 11927d5dc18SMarcel Moolenaar uart_barrier(bas); 12027d5dc18SMarcel Moolenaar 12127d5dc18SMarcel Moolenaar /* 1/10th the time to transmit 1 character (estimate). */ 122ebecffe9SMarcel Moolenaar if (divisor <= 134) 12327d5dc18SMarcel Moolenaar return (16000000 * divisor / bas->rclk); 124ebecffe9SMarcel Moolenaar return (16000 * divisor / (bas->rclk / 1000)); 12527d5dc18SMarcel Moolenaar } 12627d5dc18SMarcel Moolenaar 12727d5dc18SMarcel Moolenaar static int 12827d5dc18SMarcel Moolenaar ns8250_divisor(int rclk, int baudrate) 12927d5dc18SMarcel Moolenaar { 13027d5dc18SMarcel Moolenaar int actual_baud, divisor; 13127d5dc18SMarcel Moolenaar int error; 13227d5dc18SMarcel Moolenaar 13327d5dc18SMarcel Moolenaar if (baudrate == 0) 13427d5dc18SMarcel Moolenaar return (0); 13527d5dc18SMarcel Moolenaar 13627d5dc18SMarcel Moolenaar divisor = (rclk / (baudrate << 3) + 1) >> 1; 13727d5dc18SMarcel Moolenaar if (divisor == 0 || divisor >= 65536) 13827d5dc18SMarcel Moolenaar return (0); 13927d5dc18SMarcel Moolenaar actual_baud = rclk / (divisor << 4); 14027d5dc18SMarcel Moolenaar 14127d5dc18SMarcel Moolenaar /* 10 times error in percent: */ 14227d5dc18SMarcel Moolenaar error = ((actual_baud - baudrate) * 2000 / baudrate + 1) >> 1; 14327d5dc18SMarcel Moolenaar 144e0fe7c95SAdrian Chadd /* enforce maximum error tolerance: */ 145e0fe7c95SAdrian Chadd if (error < -UART_DEV_TOLERANCE_PCT || error > UART_DEV_TOLERANCE_PCT) 14627d5dc18SMarcel Moolenaar return (0); 14727d5dc18SMarcel Moolenaar 14827d5dc18SMarcel Moolenaar return (divisor); 14927d5dc18SMarcel Moolenaar } 15027d5dc18SMarcel Moolenaar 15127d5dc18SMarcel Moolenaar static int 15227d5dc18SMarcel Moolenaar ns8250_drain(struct uart_bas *bas, int what) 15327d5dc18SMarcel Moolenaar { 15427d5dc18SMarcel Moolenaar int delay, limit; 15527d5dc18SMarcel Moolenaar 15627d5dc18SMarcel Moolenaar delay = ns8250_delay(bas); 15727d5dc18SMarcel Moolenaar 15827d5dc18SMarcel Moolenaar if (what & UART_DRAIN_TRANSMITTER) { 15927d5dc18SMarcel Moolenaar /* 16027d5dc18SMarcel Moolenaar * Pick an arbitrary high limit to avoid getting stuck in 16127d5dc18SMarcel Moolenaar * an infinite loop when the hardware is broken. Make the 16227d5dc18SMarcel Moolenaar * limit high enough to handle large FIFOs. 16327d5dc18SMarcel Moolenaar */ 16427d5dc18SMarcel Moolenaar limit = 10*1024; 16527d5dc18SMarcel Moolenaar while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) 16627d5dc18SMarcel Moolenaar DELAY(delay); 16727d5dc18SMarcel Moolenaar if (limit == 0) { 16827d5dc18SMarcel Moolenaar /* printf("ns8250: transmitter appears stuck... "); */ 16927d5dc18SMarcel Moolenaar return (EIO); 17027d5dc18SMarcel Moolenaar } 17127d5dc18SMarcel Moolenaar } 17227d5dc18SMarcel Moolenaar 17327d5dc18SMarcel Moolenaar if (what & UART_DRAIN_RECEIVER) { 17427d5dc18SMarcel Moolenaar /* 17527d5dc18SMarcel Moolenaar * Pick an arbitrary high limit to avoid getting stuck in 17627d5dc18SMarcel Moolenaar * an infinite loop when the hardware is broken. Make the 17727d5dc18SMarcel Moolenaar * limit high enough to handle large FIFOs and integrated 17827d5dc18SMarcel Moolenaar * UARTs. The HP rx2600 for example has 3 UARTs on the 17927d5dc18SMarcel Moolenaar * management board that tend to get a lot of data send 18027d5dc18SMarcel Moolenaar * to it when the UART is first activated. 18127d5dc18SMarcel Moolenaar */ 18227d5dc18SMarcel Moolenaar limit=10*4096; 18327d5dc18SMarcel Moolenaar while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) { 18427d5dc18SMarcel Moolenaar (void)uart_getreg(bas, REG_DATA); 18527d5dc18SMarcel Moolenaar uart_barrier(bas); 18627d5dc18SMarcel Moolenaar DELAY(delay << 2); 18727d5dc18SMarcel Moolenaar } 18827d5dc18SMarcel Moolenaar if (limit == 0) { 18927d5dc18SMarcel Moolenaar /* printf("ns8250: receiver appears broken... "); */ 19027d5dc18SMarcel Moolenaar return (EIO); 19127d5dc18SMarcel Moolenaar } 19227d5dc18SMarcel Moolenaar } 19327d5dc18SMarcel Moolenaar 19427d5dc18SMarcel Moolenaar return (0); 19527d5dc18SMarcel Moolenaar } 19627d5dc18SMarcel Moolenaar 19727d5dc18SMarcel Moolenaar /* 19827d5dc18SMarcel Moolenaar * We can only flush UARTs with FIFOs. UARTs without FIFOs should be 19927d5dc18SMarcel Moolenaar * drained. WARNING: this function clobbers the FIFO setting! 20027d5dc18SMarcel Moolenaar */ 20127d5dc18SMarcel Moolenaar static void 20227d5dc18SMarcel Moolenaar ns8250_flush(struct uart_bas *bas, int what) 20327d5dc18SMarcel Moolenaar { 20427d5dc18SMarcel Moolenaar uint8_t fcr; 20527d5dc18SMarcel Moolenaar 20627d5dc18SMarcel Moolenaar fcr = FCR_ENABLE; 207b192bae6SRuslan Bukin #ifdef CPU_XBURST 208b192bae6SRuslan Bukin fcr |= FCR_UART_ON; 209b192bae6SRuslan Bukin #endif 21027d5dc18SMarcel Moolenaar if (what & UART_FLUSH_TRANSMITTER) 21127d5dc18SMarcel Moolenaar fcr |= FCR_XMT_RST; 21227d5dc18SMarcel Moolenaar if (what & UART_FLUSH_RECEIVER) 21327d5dc18SMarcel Moolenaar fcr |= FCR_RCV_RST; 21427d5dc18SMarcel Moolenaar uart_setreg(bas, REG_FCR, fcr); 21527d5dc18SMarcel Moolenaar uart_barrier(bas); 21627d5dc18SMarcel Moolenaar } 21727d5dc18SMarcel Moolenaar 21827d5dc18SMarcel Moolenaar static int 21927d5dc18SMarcel Moolenaar ns8250_param(struct uart_bas *bas, int baudrate, int databits, int stopbits, 22027d5dc18SMarcel Moolenaar int parity) 22127d5dc18SMarcel Moolenaar { 22227d5dc18SMarcel Moolenaar int divisor; 22327d5dc18SMarcel Moolenaar uint8_t lcr; 22427d5dc18SMarcel Moolenaar 22527d5dc18SMarcel Moolenaar lcr = 0; 22627d5dc18SMarcel Moolenaar if (databits >= 8) 22727d5dc18SMarcel Moolenaar lcr |= LCR_8BITS; 22827d5dc18SMarcel Moolenaar else if (databits == 7) 22927d5dc18SMarcel Moolenaar lcr |= LCR_7BITS; 23027d5dc18SMarcel Moolenaar else if (databits == 6) 23127d5dc18SMarcel Moolenaar lcr |= LCR_6BITS; 23227d5dc18SMarcel Moolenaar else 23327d5dc18SMarcel Moolenaar lcr |= LCR_5BITS; 23427d5dc18SMarcel Moolenaar if (stopbits > 1) 23527d5dc18SMarcel Moolenaar lcr |= LCR_STOPB; 23627d5dc18SMarcel Moolenaar lcr |= parity << 3; 23727d5dc18SMarcel Moolenaar 23827d5dc18SMarcel Moolenaar /* Set baudrate. */ 23927d5dc18SMarcel Moolenaar if (baudrate > 0) { 24027d5dc18SMarcel Moolenaar divisor = ns8250_divisor(bas->rclk, baudrate); 24127d5dc18SMarcel Moolenaar if (divisor == 0) 24227d5dc18SMarcel Moolenaar return (EINVAL); 24363f8efd3SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 24463f8efd3SMarcel Moolenaar uart_barrier(bas); 24558957d87SBenno Rice uart_setreg(bas, REG_DLL, divisor & 0xff); 24658957d87SBenno Rice uart_setreg(bas, REG_DLH, (divisor >> 8) & 0xff); 24727d5dc18SMarcel Moolenaar uart_barrier(bas); 24827d5dc18SMarcel Moolenaar } 24927d5dc18SMarcel Moolenaar 25027d5dc18SMarcel Moolenaar /* Set LCR and clear DLAB. */ 25127d5dc18SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr); 25227d5dc18SMarcel Moolenaar uart_barrier(bas); 25327d5dc18SMarcel Moolenaar return (0); 25427d5dc18SMarcel Moolenaar } 25527d5dc18SMarcel Moolenaar 25627d5dc18SMarcel Moolenaar /* 25727d5dc18SMarcel Moolenaar * Low-level UART interface. 25827d5dc18SMarcel Moolenaar */ 25927d5dc18SMarcel Moolenaar static int ns8250_probe(struct uart_bas *bas); 26027d5dc18SMarcel Moolenaar static void ns8250_init(struct uart_bas *bas, int, int, int, int); 26127d5dc18SMarcel Moolenaar static void ns8250_term(struct uart_bas *bas); 26227d5dc18SMarcel Moolenaar static void ns8250_putc(struct uart_bas *bas, int); 26397202af2SMarius Strobl static int ns8250_rxready(struct uart_bas *bas); 264634e63c9SMarcel Moolenaar static int ns8250_getc(struct uart_bas *bas, struct mtx *); 26527d5dc18SMarcel Moolenaar 266167cb33fSIan Lepore struct uart_ops uart_ns8250_ops = { 26727d5dc18SMarcel Moolenaar .probe = ns8250_probe, 26827d5dc18SMarcel Moolenaar .init = ns8250_init, 26927d5dc18SMarcel Moolenaar .term = ns8250_term, 27027d5dc18SMarcel Moolenaar .putc = ns8250_putc, 27197202af2SMarius Strobl .rxready = ns8250_rxready, 27227d5dc18SMarcel Moolenaar .getc = ns8250_getc, 27327d5dc18SMarcel Moolenaar }; 27427d5dc18SMarcel Moolenaar 27527d5dc18SMarcel Moolenaar static int 27627d5dc18SMarcel Moolenaar ns8250_probe(struct uart_bas *bas) 27727d5dc18SMarcel Moolenaar { 2788bceca4fSBenno Rice u_char val; 27927d5dc18SMarcel Moolenaar 280b192bae6SRuslan Bukin #ifdef CPU_XBURST 281b192bae6SRuslan Bukin uart_setreg(bas, REG_FCR, FCR_UART_ON); 282b192bae6SRuslan Bukin #endif 283b192bae6SRuslan Bukin 28427d5dc18SMarcel Moolenaar /* Check known 0 bits that don't depend on DLAB. */ 28527d5dc18SMarcel Moolenaar val = uart_getreg(bas, REG_IIR); 28627d5dc18SMarcel Moolenaar if (val & 0x30) 28727d5dc18SMarcel Moolenaar return (ENXIO); 2885bdddc29SMarcel Moolenaar /* 2895bdddc29SMarcel Moolenaar * Bit 6 of the MCR (= 0x40) appears to be 1 for the Sun1699 2905bdddc29SMarcel Moolenaar * chip, but otherwise doesn't seem to have a function. In 2915bdddc29SMarcel Moolenaar * other words, uart(4) works regardless. Ignore that bit so 2925bdddc29SMarcel Moolenaar * the probe succeeds. 2935bdddc29SMarcel Moolenaar */ 29427d5dc18SMarcel Moolenaar val = uart_getreg(bas, REG_MCR); 2955bdddc29SMarcel Moolenaar if (val & 0xa0) 29627d5dc18SMarcel Moolenaar return (ENXIO); 29727d5dc18SMarcel Moolenaar 29827d5dc18SMarcel Moolenaar return (0); 29927d5dc18SMarcel Moolenaar } 30027d5dc18SMarcel Moolenaar 30127d5dc18SMarcel Moolenaar static void 30227d5dc18SMarcel Moolenaar ns8250_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, 30327d5dc18SMarcel Moolenaar int parity) 30427d5dc18SMarcel Moolenaar { 305b192bae6SRuslan Bukin u_char ier, val; 30627d5dc18SMarcel Moolenaar 30727d5dc18SMarcel Moolenaar if (bas->rclk == 0) 30827d5dc18SMarcel Moolenaar bas->rclk = DEFAULT_RCLK; 30927d5dc18SMarcel Moolenaar ns8250_param(bas, baudrate, databits, stopbits, parity); 31027d5dc18SMarcel Moolenaar 31127d5dc18SMarcel Moolenaar /* Disable all interrupt sources. */ 3120aefb0a6SBenno Rice /* 3130aefb0a6SBenno Rice * We use 0xe0 instead of 0xf0 as the mask because the XScale PXA 3140aefb0a6SBenno Rice * UARTs split the receive time-out interrupt bit out separately as 3150aefb0a6SBenno Rice * 0x10. This gets handled by ier_mask and ier_rxbits below. 3160aefb0a6SBenno Rice */ 3170aefb0a6SBenno Rice ier = uart_getreg(bas, REG_IER) & 0xe0; 31858957d87SBenno Rice uart_setreg(bas, REG_IER, ier); 31927d5dc18SMarcel Moolenaar uart_barrier(bas); 32027d5dc18SMarcel Moolenaar 32127d5dc18SMarcel Moolenaar /* Disable the FIFO (if present). */ 322b192bae6SRuslan Bukin val = 0; 323b192bae6SRuslan Bukin #ifdef CPU_XBURST 3244e352a45SAlexander Motin val |= FCR_UART_ON; 325b192bae6SRuslan Bukin #endif 326b192bae6SRuslan Bukin uart_setreg(bas, REG_FCR, val); 32727d5dc18SMarcel Moolenaar uart_barrier(bas); 32827d5dc18SMarcel Moolenaar 32927d5dc18SMarcel Moolenaar /* Set RTS & DTR. */ 33027d5dc18SMarcel Moolenaar uart_setreg(bas, REG_MCR, MCR_IE | MCR_RTS | MCR_DTR); 33127d5dc18SMarcel Moolenaar uart_barrier(bas); 33227d5dc18SMarcel Moolenaar 33327d5dc18SMarcel Moolenaar ns8250_clrint(bas); 33427d5dc18SMarcel Moolenaar } 33527d5dc18SMarcel Moolenaar 33627d5dc18SMarcel Moolenaar static void 33727d5dc18SMarcel Moolenaar ns8250_term(struct uart_bas *bas) 33827d5dc18SMarcel Moolenaar { 33927d5dc18SMarcel Moolenaar 34027d5dc18SMarcel Moolenaar /* Clear RTS & DTR. */ 34127d5dc18SMarcel Moolenaar uart_setreg(bas, REG_MCR, MCR_IE); 34227d5dc18SMarcel Moolenaar uart_barrier(bas); 34327d5dc18SMarcel Moolenaar } 34427d5dc18SMarcel Moolenaar 34527d5dc18SMarcel Moolenaar static void 34627d5dc18SMarcel Moolenaar ns8250_putc(struct uart_bas *bas, int c) 34727d5dc18SMarcel Moolenaar { 34835777a2aSMarcel Moolenaar int limit; 34927d5dc18SMarcel Moolenaar 35035777a2aSMarcel Moolenaar limit = 250000; 35127d5dc18SMarcel Moolenaar while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0 && --limit) 35235777a2aSMarcel Moolenaar DELAY(4); 35327d5dc18SMarcel Moolenaar uart_setreg(bas, REG_DATA, c); 3544e55f723SMarcel Moolenaar uart_barrier(bas); 35527d5dc18SMarcel Moolenaar } 35627d5dc18SMarcel Moolenaar 35727d5dc18SMarcel Moolenaar static int 35897202af2SMarius Strobl ns8250_rxready(struct uart_bas *bas) 35927d5dc18SMarcel Moolenaar { 36027d5dc18SMarcel Moolenaar 36197202af2SMarius Strobl return ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) != 0 ? 1 : 0); 36227d5dc18SMarcel Moolenaar } 36327d5dc18SMarcel Moolenaar 36427d5dc18SMarcel Moolenaar static int 365634e63c9SMarcel Moolenaar ns8250_getc(struct uart_bas *bas, struct mtx *hwmtx) 36627d5dc18SMarcel Moolenaar { 36735777a2aSMarcel Moolenaar int c; 368634e63c9SMarcel Moolenaar 369634e63c9SMarcel Moolenaar uart_lock(hwmtx); 37027d5dc18SMarcel Moolenaar 371634e63c9SMarcel Moolenaar while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0) { 372634e63c9SMarcel Moolenaar uart_unlock(hwmtx); 37335777a2aSMarcel Moolenaar DELAY(4); 374634e63c9SMarcel Moolenaar uart_lock(hwmtx); 375634e63c9SMarcel Moolenaar } 376634e63c9SMarcel Moolenaar 377634e63c9SMarcel Moolenaar c = uart_getreg(bas, REG_DATA); 378634e63c9SMarcel Moolenaar 379634e63c9SMarcel Moolenaar uart_unlock(hwmtx); 380634e63c9SMarcel Moolenaar 381634e63c9SMarcel Moolenaar return (c); 38227d5dc18SMarcel Moolenaar } 38327d5dc18SMarcel Moolenaar 38427d5dc18SMarcel Moolenaar static kobj_method_t ns8250_methods[] = { 38527d5dc18SMarcel Moolenaar KOBJMETHOD(uart_attach, ns8250_bus_attach), 38627d5dc18SMarcel Moolenaar KOBJMETHOD(uart_detach, ns8250_bus_detach), 38727d5dc18SMarcel Moolenaar KOBJMETHOD(uart_flush, ns8250_bus_flush), 38827d5dc18SMarcel Moolenaar KOBJMETHOD(uart_getsig, ns8250_bus_getsig), 38927d5dc18SMarcel Moolenaar KOBJMETHOD(uart_ioctl, ns8250_bus_ioctl), 39027d5dc18SMarcel Moolenaar KOBJMETHOD(uart_ipend, ns8250_bus_ipend), 39127d5dc18SMarcel Moolenaar KOBJMETHOD(uart_param, ns8250_bus_param), 39227d5dc18SMarcel Moolenaar KOBJMETHOD(uart_probe, ns8250_bus_probe), 39327d5dc18SMarcel Moolenaar KOBJMETHOD(uart_receive, ns8250_bus_receive), 39427d5dc18SMarcel Moolenaar KOBJMETHOD(uart_setsig, ns8250_bus_setsig), 39527d5dc18SMarcel Moolenaar KOBJMETHOD(uart_transmit, ns8250_bus_transmit), 396d76a1ef4SWarner Losh KOBJMETHOD(uart_grab, ns8250_bus_grab), 397d76a1ef4SWarner Losh KOBJMETHOD(uart_ungrab, ns8250_bus_ungrab), 39827d5dc18SMarcel Moolenaar { 0, 0 } 39927d5dc18SMarcel Moolenaar }; 40027d5dc18SMarcel Moolenaar 40127d5dc18SMarcel Moolenaar struct uart_class uart_ns8250_class = { 402f8100ce2SMarcel Moolenaar "ns8250", 40327d5dc18SMarcel Moolenaar ns8250_methods, 40427d5dc18SMarcel Moolenaar sizeof(struct ns8250_softc), 405f8100ce2SMarcel Moolenaar .uc_ops = &uart_ns8250_ops, 40627d5dc18SMarcel Moolenaar .uc_range = 8, 407405ada37SAndrew Turner .uc_rclk = DEFAULT_RCLK, 408405ada37SAndrew Turner .uc_rshift = 0 40927d5dc18SMarcel Moolenaar }; 41027d5dc18SMarcel Moolenaar 411381388b9SMatt Macy /* 412381388b9SMatt Macy * XXX -- refactor out ACPI and FDT ifdefs 413381388b9SMatt Macy */ 414381388b9SMatt Macy #ifdef DEV_ACPI 415381388b9SMatt Macy static struct acpi_uart_compat_data acpi_compat_data[] = { 416381388b9SMatt Macy {"AMD0020", &uart_ns8250_class, 0, 2, 0, 48000000, UART_F_BUSY_DETECT, "AMD / Synopsys Designware UART"}, 417381388b9SMatt Macy {"AMDI0020", &uart_ns8250_class, 0, 2, 0, 48000000, UART_F_BUSY_DETECT, "AMD / Synopsys Designware UART"}, 418381388b9SMatt Macy {"PNP0500", &uart_ns8250_class, 0, 0, 0, 0, 0, "Standard PC COM port"}, 419381388b9SMatt Macy {"PNP0501", &uart_ns8250_class, 0, 0, 0, 0, 0, "16550A-compatible COM port"}, 420381388b9SMatt Macy {"PNP0502", &uart_ns8250_class, 0, 0, 0, 0, 0, "Multiport serial device (non-intelligent 16550)"}, 421381388b9SMatt Macy {"PNP0510", &uart_ns8250_class, 0, 0, 0, 0, 0, "Generic IRDA-compatible device"}, 422381388b9SMatt Macy {"PNP0511", &uart_ns8250_class, 0, 0, 0, 0, 0, "Generic IRDA-compatible device"}, 423381388b9SMatt Macy {"WACF004", &uart_ns8250_class, 0, 0, 0, 0, 0, "Wacom Tablet PC Screen"}, 424381388b9SMatt Macy {"WACF00E", &uart_ns8250_class, 0, 0, 0, 0, 0, "Wacom Tablet PC Screen 00e"}, 425381388b9SMatt Macy {"FUJ02E5", &uart_ns8250_class, 0, 0, 0, 0, 0, "Wacom Tablet at FuS Lifebook T"}, 426381388b9SMatt Macy {NULL, NULL, 0, 0 , 0, 0, 0, NULL}, 427381388b9SMatt Macy }; 428381388b9SMatt Macy UART_ACPI_CLASS_AND_DEVICE(acpi_compat_data); 429381388b9SMatt Macy #endif 430381388b9SMatt Macy 4313bb693afSIan Lepore #ifdef FDT 4323bb693afSIan Lepore static struct ofw_compat_data compat_data[] = { 4333bb693afSIan Lepore {"ns16550", (uintptr_t)&uart_ns8250_class}, 4343b654e08SWojciech Macek {"ns16550a", (uintptr_t)&uart_ns8250_class}, 4353bb693afSIan Lepore {NULL, (uintptr_t)NULL}, 4363bb693afSIan Lepore }; 4373bb693afSIan Lepore UART_FDT_CLASS_AND_DEVICE(compat_data); 4383bb693afSIan Lepore #endif 4393bb693afSIan Lepore 440fdfbb3f5SIan Lepore /* Use token-pasting to form SER_ and MSR_ named constants. */ 441fdfbb3f5SIan Lepore #define SER(sig) SER_##sig 442fdfbb3f5SIan Lepore #define SERD(sig) SER_D##sig 443fdfbb3f5SIan Lepore #define MSR(sig) MSR_##sig 444fdfbb3f5SIan Lepore #define MSRD(sig) MSR_D##sig 445fdfbb3f5SIan Lepore 446fdfbb3f5SIan Lepore /* 447fdfbb3f5SIan Lepore * Detect signal changes using software delta detection. The previous state of 448fdfbb3f5SIan Lepore * the signals is in 'var' the new hardware state is in 'msr', and 'sig' is the 449fdfbb3f5SIan Lepore * short name (DCD, CTS, etc) of the signal bit being processed; 'var' gets the 450fdfbb3f5SIan Lepore * new state of both the signal and the delta bits. 451fdfbb3f5SIan Lepore */ 452fdfbb3f5SIan Lepore #define SIGCHGSW(var, msr, sig) \ 453fdfbb3f5SIan Lepore if ((msr) & MSR(sig)) { \ 454fdfbb3f5SIan Lepore if ((var & SER(sig)) == 0) \ 455fdfbb3f5SIan Lepore var |= SERD(sig) | SER(sig); \ 45627d5dc18SMarcel Moolenaar } else { \ 457fdfbb3f5SIan Lepore if ((var & SER(sig)) != 0) \ 458fdfbb3f5SIan Lepore var = SERD(sig) | (var & ~SER(sig)); \ 459fdfbb3f5SIan Lepore } 460fdfbb3f5SIan Lepore 461fdfbb3f5SIan Lepore /* 462fdfbb3f5SIan Lepore * Detect signal changes using the hardware msr delta bits. This is currently 463fdfbb3f5SIan Lepore * used only when PPS timing information is being captured using the "narrow 464fdfbb3f5SIan Lepore * pulse" option. With a narrow PPS pulse the signal may not still be asserted 465fdfbb3f5SIan Lepore * by time the interrupt handler is invoked. The hardware will latch the fact 466fdfbb3f5SIan Lepore * that it changed in the delta bits. 467fdfbb3f5SIan Lepore */ 468fdfbb3f5SIan Lepore #define SIGCHGHW(var, msr, sig) \ 469fdfbb3f5SIan Lepore if ((msr) & MSRD(sig)) { \ 470fdfbb3f5SIan Lepore if (((msr) & MSR(sig)) != 0) \ 471fdfbb3f5SIan Lepore var |= SERD(sig) | SER(sig); \ 472fdfbb3f5SIan Lepore else \ 473fdfbb3f5SIan Lepore var = SERD(sig) | (var & ~SER(sig)); \ 47427d5dc18SMarcel Moolenaar } 47527d5dc18SMarcel Moolenaar 476167cb33fSIan Lepore int 47727d5dc18SMarcel Moolenaar ns8250_bus_attach(struct uart_softc *sc) 47827d5dc18SMarcel Moolenaar { 47927d5dc18SMarcel Moolenaar struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 48027d5dc18SMarcel Moolenaar struct uart_bas *bas; 481823c77d7SSam Leffler unsigned int ivar; 482ac4adddfSGanbold Tsagaankhuu #ifdef FDT 483ac4adddfSGanbold Tsagaankhuu phandle_t node; 484ac4adddfSGanbold Tsagaankhuu pcell_t cell; 485ac4adddfSGanbold Tsagaankhuu #endif 486ac4adddfSGanbold Tsagaankhuu 487ac4adddfSGanbold Tsagaankhuu #ifdef FDT 488b738dafdSJared McNeill /* Check whether uart has a broken txfifo. */ 489ac4adddfSGanbold Tsagaankhuu node = ofw_bus_get_node(sc->sc_dev); 490b1621f22SLuiz Otavio O Souza if ((OF_getencprop(node, "broken-txfifo", &cell, sizeof(cell))) > 0) 491b1621f22SLuiz Otavio O Souza broken_txfifo = cell ? 1 : 0; 492ac4adddfSGanbold Tsagaankhuu #endif 49327d5dc18SMarcel Moolenaar 49427d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 49527d5dc18SMarcel Moolenaar 496f30f0f2bSMatt Macy ns8250->busy_detect = bas->busy_detect; 49727d5dc18SMarcel Moolenaar ns8250->mcr = uart_getreg(bas, REG_MCR); 498823c77d7SSam Leffler ns8250->fcr = FCR_ENABLE; 499b192bae6SRuslan Bukin #ifdef CPU_XBURST 500b192bae6SRuslan Bukin ns8250->fcr |= FCR_UART_ON; 501b192bae6SRuslan Bukin #endif 502823c77d7SSam Leffler if (!resource_int_value("uart", device_get_unit(sc->sc_dev), "flags", 503823c77d7SSam Leffler &ivar)) { 504823c77d7SSam Leffler if (UART_FLAGS_FCR_RX_LOW(ivar)) 505823c77d7SSam Leffler ns8250->fcr |= FCR_RX_LOW; 506823c77d7SSam Leffler else if (UART_FLAGS_FCR_RX_MEDL(ivar)) 507823c77d7SSam Leffler ns8250->fcr |= FCR_RX_MEDL; 508823c77d7SSam Leffler else if (UART_FLAGS_FCR_RX_HIGH(ivar)) 509823c77d7SSam Leffler ns8250->fcr |= FCR_RX_HIGH; 510823c77d7SSam Leffler else 511823c77d7SSam Leffler ns8250->fcr |= FCR_RX_MEDH; 512823c77d7SSam Leffler } else 513823c77d7SSam Leffler ns8250->fcr |= FCR_RX_MEDH; 5140aefb0a6SBenno Rice 5150aefb0a6SBenno Rice /* Get IER mask */ 5160aefb0a6SBenno Rice ivar = 0xf0; 5170aefb0a6SBenno Rice resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_mask", 5180aefb0a6SBenno Rice &ivar); 5190aefb0a6SBenno Rice ns8250->ier_mask = (uint8_t)(ivar & 0xff); 5200aefb0a6SBenno Rice 5210aefb0a6SBenno Rice /* Get IER RX interrupt bits */ 5220aefb0a6SBenno Rice ivar = IER_EMSC | IER_ERLS | IER_ERXRDY; 5230aefb0a6SBenno Rice resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_rxbits", 5240aefb0a6SBenno Rice &ivar); 5250aefb0a6SBenno Rice ns8250->ier_rxbits = (uint8_t)(ivar & 0xff); 5260aefb0a6SBenno Rice 52727d5dc18SMarcel Moolenaar uart_setreg(bas, REG_FCR, ns8250->fcr); 52827d5dc18SMarcel Moolenaar uart_barrier(bas); 52927d5dc18SMarcel Moolenaar ns8250_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 53027d5dc18SMarcel Moolenaar 53127d5dc18SMarcel Moolenaar if (ns8250->mcr & MCR_DTR) 53228710806SPoul-Henning Kamp sc->sc_hwsig |= SER_DTR; 53327d5dc18SMarcel Moolenaar if (ns8250->mcr & MCR_RTS) 53428710806SPoul-Henning Kamp sc->sc_hwsig |= SER_RTS; 53527d5dc18SMarcel Moolenaar ns8250_bus_getsig(sc); 53627d5dc18SMarcel Moolenaar 53727d5dc18SMarcel Moolenaar ns8250_clrint(bas); 5380aefb0a6SBenno Rice ns8250->ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 5390aefb0a6SBenno Rice ns8250->ier |= ns8250->ier_rxbits; 54027d5dc18SMarcel Moolenaar uart_setreg(bas, REG_IER, ns8250->ier); 54127d5dc18SMarcel Moolenaar uart_barrier(bas); 5420aefb0a6SBenno Rice 5434fc49975SMarcel Moolenaar /* 5444fc49975SMarcel Moolenaar * Timing of the H/W access was changed with r253161 of uart_core.c 5454fc49975SMarcel Moolenaar * It has been observed that an ITE IT8513E would signal a break 5464fc49975SMarcel Moolenaar * condition with pretty much every character it received, unless 5474fc49975SMarcel Moolenaar * it had enough time to settle between ns8250_bus_attach() and 5484fc49975SMarcel Moolenaar * ns8250_bus_ipend() -- which it accidentally had before r253161. 5494fc49975SMarcel Moolenaar * It's not understood why the UART chip behaves this way and it 5504fc49975SMarcel Moolenaar * could very well be that the DELAY make the H/W work in the same 5514fc49975SMarcel Moolenaar * accidental manner as before. More analysis is warranted, but 5524fc49975SMarcel Moolenaar * at least now we fixed a known regression. 5534fc49975SMarcel Moolenaar */ 55440a827b6SMarcel Moolenaar DELAY(200); 55527d5dc18SMarcel Moolenaar return (0); 55627d5dc18SMarcel Moolenaar } 55727d5dc18SMarcel Moolenaar 558167cb33fSIan Lepore int 55927d5dc18SMarcel Moolenaar ns8250_bus_detach(struct uart_softc *sc) 56027d5dc18SMarcel Moolenaar { 5610aefb0a6SBenno Rice struct ns8250_softc *ns8250; 56227d5dc18SMarcel Moolenaar struct uart_bas *bas; 56358957d87SBenno Rice u_char ier; 56427d5dc18SMarcel Moolenaar 5650aefb0a6SBenno Rice ns8250 = (struct ns8250_softc *)sc; 56627d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 5670aefb0a6SBenno Rice ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 56858957d87SBenno Rice uart_setreg(bas, REG_IER, ier); 56927d5dc18SMarcel Moolenaar uart_barrier(bas); 57027d5dc18SMarcel Moolenaar ns8250_clrint(bas); 57127d5dc18SMarcel Moolenaar return (0); 57227d5dc18SMarcel Moolenaar } 57327d5dc18SMarcel Moolenaar 574167cb33fSIan Lepore int 57527d5dc18SMarcel Moolenaar ns8250_bus_flush(struct uart_softc *sc, int what) 57627d5dc18SMarcel Moolenaar { 57727d5dc18SMarcel Moolenaar struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 57827d5dc18SMarcel Moolenaar struct uart_bas *bas; 57906287620SMarcel Moolenaar int error; 58027d5dc18SMarcel Moolenaar 58127d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 5828af03381SMarcel Moolenaar uart_lock(sc->sc_hwmtx); 5838d1289feSMarcel Moolenaar if (sc->sc_rxfifosz > 1) { 58427d5dc18SMarcel Moolenaar ns8250_flush(bas, what); 58527d5dc18SMarcel Moolenaar uart_setreg(bas, REG_FCR, ns8250->fcr); 58627d5dc18SMarcel Moolenaar uart_barrier(bas); 58706287620SMarcel Moolenaar error = 0; 58806287620SMarcel Moolenaar } else 58906287620SMarcel Moolenaar error = ns8250_drain(bas, what); 5908af03381SMarcel Moolenaar uart_unlock(sc->sc_hwmtx); 59106287620SMarcel Moolenaar return (error); 59227d5dc18SMarcel Moolenaar } 59327d5dc18SMarcel Moolenaar 594167cb33fSIan Lepore int 59527d5dc18SMarcel Moolenaar ns8250_bus_getsig(struct uart_softc *sc) 59627d5dc18SMarcel Moolenaar { 597fdfbb3f5SIan Lepore uint32_t old, sig; 59827d5dc18SMarcel Moolenaar uint8_t msr; 59927d5dc18SMarcel Moolenaar 600fdfbb3f5SIan Lepore /* 601fdfbb3f5SIan Lepore * The delta bits are reputed to be broken on some hardware, so use 602fdfbb3f5SIan Lepore * software delta detection by default. Use the hardware delta bits 603fdfbb3f5SIan Lepore * when capturing PPS pulses which are too narrow for software detection 604fdfbb3f5SIan Lepore * to see the edges. Hardware delta for RI doesn't work like the 605fdfbb3f5SIan Lepore * others, so always use software for it. Other threads may be changing 606453130d9SPedro F. Giffuni * other (non-MSR) bits in sc_hwsig, so loop until it can successfully 607fdfbb3f5SIan Lepore * update without other changes happening. Note that the SIGCHGxx() 608fdfbb3f5SIan Lepore * macros carefully preserve the delta bits when we have to loop several 609fdfbb3f5SIan Lepore * times and a signal transitions between iterations. 610fdfbb3f5SIan Lepore */ 61127d5dc18SMarcel Moolenaar do { 61227d5dc18SMarcel Moolenaar old = sc->sc_hwsig; 61327d5dc18SMarcel Moolenaar sig = old; 6148af03381SMarcel Moolenaar uart_lock(sc->sc_hwmtx); 61527d5dc18SMarcel Moolenaar msr = uart_getreg(&sc->sc_bas, REG_MSR); 6168af03381SMarcel Moolenaar uart_unlock(sc->sc_hwmtx); 617fdfbb3f5SIan Lepore if (sc->sc_pps_mode & UART_PPS_NARROW_PULSE) { 618fdfbb3f5SIan Lepore SIGCHGHW(sig, msr, DSR); 619fdfbb3f5SIan Lepore SIGCHGHW(sig, msr, CTS); 620fdfbb3f5SIan Lepore SIGCHGHW(sig, msr, DCD); 621fdfbb3f5SIan Lepore } else { 622fdfbb3f5SIan Lepore SIGCHGSW(sig, msr, DSR); 623fdfbb3f5SIan Lepore SIGCHGSW(sig, msr, CTS); 624fdfbb3f5SIan Lepore SIGCHGSW(sig, msr, DCD); 625fdfbb3f5SIan Lepore } 626fdfbb3f5SIan Lepore SIGCHGSW(sig, msr, RI); 627fdfbb3f5SIan Lepore } while (!atomic_cmpset_32(&sc->sc_hwsig, old, sig & ~SER_MASK_DELTA)); 62827d5dc18SMarcel Moolenaar return (sig); 62927d5dc18SMarcel Moolenaar } 63027d5dc18SMarcel Moolenaar 631167cb33fSIan Lepore int 63227d5dc18SMarcel Moolenaar ns8250_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) 63327d5dc18SMarcel Moolenaar { 63427d5dc18SMarcel Moolenaar struct uart_bas *bas; 635bfa307a3SMarcel Moolenaar int baudrate, divisor, error; 63684c7b427SMarcel Moolenaar uint8_t efr, lcr; 63727d5dc18SMarcel Moolenaar 63827d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 63906287620SMarcel Moolenaar error = 0; 6408af03381SMarcel Moolenaar uart_lock(sc->sc_hwmtx); 64127d5dc18SMarcel Moolenaar switch (request) { 64227d5dc18SMarcel Moolenaar case UART_IOCTL_BREAK: 64327d5dc18SMarcel Moolenaar lcr = uart_getreg(bas, REG_LCR); 64427d5dc18SMarcel Moolenaar if (data) 64527d5dc18SMarcel Moolenaar lcr |= LCR_SBREAK; 64627d5dc18SMarcel Moolenaar else 64727d5dc18SMarcel Moolenaar lcr &= ~LCR_SBREAK; 64827d5dc18SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr); 64927d5dc18SMarcel Moolenaar uart_barrier(bas); 65027d5dc18SMarcel Moolenaar break; 65184c7b427SMarcel Moolenaar case UART_IOCTL_IFLOW: 65284c7b427SMarcel Moolenaar lcr = uart_getreg(bas, REG_LCR); 65384c7b427SMarcel Moolenaar uart_barrier(bas); 65484c7b427SMarcel Moolenaar uart_setreg(bas, REG_LCR, 0xbf); 65584c7b427SMarcel Moolenaar uart_barrier(bas); 65684c7b427SMarcel Moolenaar efr = uart_getreg(bas, REG_EFR); 65784c7b427SMarcel Moolenaar if (data) 65884c7b427SMarcel Moolenaar efr |= EFR_RTS; 65984c7b427SMarcel Moolenaar else 66084c7b427SMarcel Moolenaar efr &= ~EFR_RTS; 66184c7b427SMarcel Moolenaar uart_setreg(bas, REG_EFR, efr); 66284c7b427SMarcel Moolenaar uart_barrier(bas); 66384c7b427SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr); 66484c7b427SMarcel Moolenaar uart_barrier(bas); 66584c7b427SMarcel Moolenaar break; 66684c7b427SMarcel Moolenaar case UART_IOCTL_OFLOW: 66784c7b427SMarcel Moolenaar lcr = uart_getreg(bas, REG_LCR); 66884c7b427SMarcel Moolenaar uart_barrier(bas); 66984c7b427SMarcel Moolenaar uart_setreg(bas, REG_LCR, 0xbf); 67084c7b427SMarcel Moolenaar uart_barrier(bas); 67184c7b427SMarcel Moolenaar efr = uart_getreg(bas, REG_EFR); 67284c7b427SMarcel Moolenaar if (data) 67384c7b427SMarcel Moolenaar efr |= EFR_CTS; 67484c7b427SMarcel Moolenaar else 67584c7b427SMarcel Moolenaar efr &= ~EFR_CTS; 67684c7b427SMarcel Moolenaar uart_setreg(bas, REG_EFR, efr); 67784c7b427SMarcel Moolenaar uart_barrier(bas); 67884c7b427SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr); 67984c7b427SMarcel Moolenaar uart_barrier(bas); 68084c7b427SMarcel Moolenaar break; 681d8518925SMarcel Moolenaar case UART_IOCTL_BAUD: 682d8518925SMarcel Moolenaar lcr = uart_getreg(bas, REG_LCR); 683d8518925SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 684d8518925SMarcel Moolenaar uart_barrier(bas); 68558957d87SBenno Rice divisor = uart_getreg(bas, REG_DLL) | 68658957d87SBenno Rice (uart_getreg(bas, REG_DLH) << 8); 687d8518925SMarcel Moolenaar uart_barrier(bas); 688d8518925SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr); 689d8518925SMarcel Moolenaar uart_barrier(bas); 690bfa307a3SMarcel Moolenaar baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0; 691bfa307a3SMarcel Moolenaar if (baudrate > 0) 692bfa307a3SMarcel Moolenaar *(int*)data = baudrate; 693bfa307a3SMarcel Moolenaar else 694bfa307a3SMarcel Moolenaar error = ENXIO; 695d8518925SMarcel Moolenaar break; 69627d5dc18SMarcel Moolenaar default: 69706287620SMarcel Moolenaar error = EINVAL; 69806287620SMarcel Moolenaar break; 69927d5dc18SMarcel Moolenaar } 7008af03381SMarcel Moolenaar uart_unlock(sc->sc_hwmtx); 70106287620SMarcel Moolenaar return (error); 70227d5dc18SMarcel Moolenaar } 70327d5dc18SMarcel Moolenaar 704167cb33fSIan Lepore int 70527d5dc18SMarcel Moolenaar ns8250_bus_ipend(struct uart_softc *sc) 70627d5dc18SMarcel Moolenaar { 70727d5dc18SMarcel Moolenaar struct uart_bas *bas; 70811e55f91SOlivier Houchard struct ns8250_softc *ns8250; 70927d5dc18SMarcel Moolenaar int ipend; 71027d5dc18SMarcel Moolenaar uint8_t iir, lsr; 71127d5dc18SMarcel Moolenaar 71211e55f91SOlivier Houchard ns8250 = (struct ns8250_softc *)sc; 71327d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 7148af03381SMarcel Moolenaar uart_lock(sc->sc_hwmtx); 71527d5dc18SMarcel Moolenaar iir = uart_getreg(bas, REG_IIR); 716ac4adddfSGanbold Tsagaankhuu 717ac4adddfSGanbold Tsagaankhuu if (ns8250->busy_detect && (iir & IIR_BUSY) == IIR_BUSY) { 718ac4adddfSGanbold Tsagaankhuu (void)uart_getreg(bas, DW_REG_USR); 719ac4adddfSGanbold Tsagaankhuu uart_unlock(sc->sc_hwmtx); 720ac4adddfSGanbold Tsagaankhuu return (0); 721ac4adddfSGanbold Tsagaankhuu } 72206287620SMarcel Moolenaar if (iir & IIR_NOPEND) { 7238af03381SMarcel Moolenaar uart_unlock(sc->sc_hwmtx); 72427d5dc18SMarcel Moolenaar return (0); 72506287620SMarcel Moolenaar } 72627d5dc18SMarcel Moolenaar ipend = 0; 72727d5dc18SMarcel Moolenaar if (iir & IIR_RXRDY) { 72827d5dc18SMarcel Moolenaar lsr = uart_getreg(bas, REG_LSR); 72927d5dc18SMarcel Moolenaar if (lsr & LSR_OE) 7302d511805SMarcel Moolenaar ipend |= SER_INT_OVERRUN; 73127d5dc18SMarcel Moolenaar if (lsr & LSR_BI) 7322d511805SMarcel Moolenaar ipend |= SER_INT_BREAK; 73327d5dc18SMarcel Moolenaar if (lsr & LSR_RXRDY) 7342d511805SMarcel Moolenaar ipend |= SER_INT_RXREADY; 73527d5dc18SMarcel Moolenaar } else { 73611e55f91SOlivier Houchard if (iir & IIR_TXRDY) { 7372d511805SMarcel Moolenaar ipend |= SER_INT_TXIDLE; 73811e55f91SOlivier Houchard uart_setreg(bas, REG_IER, ns8250->ier); 7393c7b9077SMichal Meloun uart_barrier(bas); 74011e55f91SOlivier Houchard } else 7412d511805SMarcel Moolenaar ipend |= SER_INT_SIGCHG; 74227d5dc18SMarcel Moolenaar } 743d7ae5af5SMarcel Moolenaar if (ipend == 0) 744d7ae5af5SMarcel Moolenaar ns8250_clrint(bas); 745d7ae5af5SMarcel Moolenaar uart_unlock(sc->sc_hwmtx); 746f6ffc3c2SMarius Strobl return (ipend); 74727d5dc18SMarcel Moolenaar } 74827d5dc18SMarcel Moolenaar 749167cb33fSIan Lepore int 75027d5dc18SMarcel Moolenaar ns8250_bus_param(struct uart_softc *sc, int baudrate, int databits, 75127d5dc18SMarcel Moolenaar int stopbits, int parity) 75227d5dc18SMarcel Moolenaar { 75349e368acSZbigniew Bodek struct ns8250_softc *ns8250; 75427d5dc18SMarcel Moolenaar struct uart_bas *bas; 75549e368acSZbigniew Bodek int error, limit; 75627d5dc18SMarcel Moolenaar 75749e368acSZbigniew Bodek ns8250 = (struct ns8250_softc*)sc; 75827d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 7598af03381SMarcel Moolenaar uart_lock(sc->sc_hwmtx); 76049e368acSZbigniew Bodek /* 76149e368acSZbigniew Bodek * When using DW UART with BUSY detection it is necessary to wait 76249e368acSZbigniew Bodek * until all serial transfers are finished before manipulating the 76349e368acSZbigniew Bodek * line control. LCR will not be affected when UART is busy. 76449e368acSZbigniew Bodek */ 76549e368acSZbigniew Bodek if (ns8250->busy_detect != 0) { 76649e368acSZbigniew Bodek /* 76749e368acSZbigniew Bodek * Pick an arbitrary high limit to avoid getting stuck in 76849e368acSZbigniew Bodek * an infinite loop in case when the hardware is broken. 76949e368acSZbigniew Bodek */ 77049e368acSZbigniew Bodek limit = 10 * 1024; 77149e368acSZbigniew Bodek while (((uart_getreg(bas, DW_REG_USR) & USR_BUSY) != 0) && 77249e368acSZbigniew Bodek --limit) 77349e368acSZbigniew Bodek DELAY(4); 77449e368acSZbigniew Bodek 77549e368acSZbigniew Bodek if (limit <= 0) { 77649e368acSZbigniew Bodek /* UART appears to be stuck */ 77749e368acSZbigniew Bodek uart_unlock(sc->sc_hwmtx); 77849e368acSZbigniew Bodek return (EIO); 77949e368acSZbigniew Bodek } 78049e368acSZbigniew Bodek } 78149e368acSZbigniew Bodek 78206287620SMarcel Moolenaar error = ns8250_param(bas, baudrate, databits, stopbits, parity); 7838af03381SMarcel Moolenaar uart_unlock(sc->sc_hwmtx); 78406287620SMarcel Moolenaar return (error); 78527d5dc18SMarcel Moolenaar } 78627d5dc18SMarcel Moolenaar 787167cb33fSIan Lepore int 78827d5dc18SMarcel Moolenaar ns8250_bus_probe(struct uart_softc *sc) 78927d5dc18SMarcel Moolenaar { 7900aefb0a6SBenno Rice struct ns8250_softc *ns8250; 79127d5dc18SMarcel Moolenaar struct uart_bas *bas; 79227d5dc18SMarcel Moolenaar int count, delay, error, limit; 79358957d87SBenno Rice uint8_t lsr, mcr, ier; 794b192bae6SRuslan Bukin uint8_t val; 79527d5dc18SMarcel Moolenaar 7960aefb0a6SBenno Rice ns8250 = (struct ns8250_softc *)sc; 79727d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 79827d5dc18SMarcel Moolenaar 79927d5dc18SMarcel Moolenaar error = ns8250_probe(bas); 80027d5dc18SMarcel Moolenaar if (error) 80127d5dc18SMarcel Moolenaar return (error); 80227d5dc18SMarcel Moolenaar 80327d5dc18SMarcel Moolenaar mcr = MCR_IE; 80427d5dc18SMarcel Moolenaar if (sc->sc_sysdev == NULL) { 80527d5dc18SMarcel Moolenaar /* By using ns8250_init() we also set DTR and RTS. */ 806d902fb71SMarcel Moolenaar ns8250_init(bas, 115200, 8, 1, UART_PARITY_NONE); 80727d5dc18SMarcel Moolenaar } else 80827d5dc18SMarcel Moolenaar mcr |= MCR_DTR | MCR_RTS; 80927d5dc18SMarcel Moolenaar 81027d5dc18SMarcel Moolenaar error = ns8250_drain(bas, UART_DRAIN_TRANSMITTER); 81127d5dc18SMarcel Moolenaar if (error) 81227d5dc18SMarcel Moolenaar return (error); 81327d5dc18SMarcel Moolenaar 81427d5dc18SMarcel Moolenaar /* 81527d5dc18SMarcel Moolenaar * Set loopback mode. This avoids having garbage on the wire and 81627d5dc18SMarcel Moolenaar * also allows us send and receive data. We set DTR and RTS to 81727d5dc18SMarcel Moolenaar * avoid the possibility that automatic flow-control prevents 81889eef2deSThomas Moestl * any data from being sent. 81927d5dc18SMarcel Moolenaar */ 82089eef2deSThomas Moestl uart_setreg(bas, REG_MCR, MCR_LOOPBACK | MCR_IE | MCR_DTR | MCR_RTS); 82127d5dc18SMarcel Moolenaar uart_barrier(bas); 82227d5dc18SMarcel Moolenaar 82327d5dc18SMarcel Moolenaar /* 82427d5dc18SMarcel Moolenaar * Enable FIFOs. And check that the UART has them. If not, we're 82589eef2deSThomas Moestl * done. Since this is the first time we enable the FIFOs, we reset 82689eef2deSThomas Moestl * them. 82727d5dc18SMarcel Moolenaar */ 828b192bae6SRuslan Bukin val = FCR_ENABLE; 829b192bae6SRuslan Bukin #ifdef CPU_XBURST 830b192bae6SRuslan Bukin val |= FCR_UART_ON; 831b192bae6SRuslan Bukin #endif 832b192bae6SRuslan Bukin uart_setreg(bas, REG_FCR, val); 83327d5dc18SMarcel Moolenaar uart_barrier(bas); 8348d1289feSMarcel Moolenaar if (!(uart_getreg(bas, REG_IIR) & IIR_FIFO_MASK)) { 83527d5dc18SMarcel Moolenaar /* 83627d5dc18SMarcel Moolenaar * NS16450 or INS8250. We don't bother to differentiate 83727d5dc18SMarcel Moolenaar * between them. They're too old to be interesting. 83827d5dc18SMarcel Moolenaar */ 83927d5dc18SMarcel Moolenaar uart_setreg(bas, REG_MCR, mcr); 84027d5dc18SMarcel Moolenaar uart_barrier(bas); 8418d1289feSMarcel Moolenaar sc->sc_rxfifosz = sc->sc_txfifosz = 1; 84227d5dc18SMarcel Moolenaar device_set_desc(sc->sc_dev, "8250 or 16450 or compatible"); 84327d5dc18SMarcel Moolenaar return (0); 84427d5dc18SMarcel Moolenaar } 84527d5dc18SMarcel Moolenaar 846b192bae6SRuslan Bukin val = FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST; 847b192bae6SRuslan Bukin #ifdef CPU_XBURST 848b192bae6SRuslan Bukin val |= FCR_UART_ON; 849b192bae6SRuslan Bukin #endif 850b192bae6SRuslan Bukin uart_setreg(bas, REG_FCR, val); 85127d5dc18SMarcel Moolenaar uart_barrier(bas); 85227d5dc18SMarcel Moolenaar 85327d5dc18SMarcel Moolenaar count = 0; 85427d5dc18SMarcel Moolenaar delay = ns8250_delay(bas); 85527d5dc18SMarcel Moolenaar 85627d5dc18SMarcel Moolenaar /* We have FIFOs. Drain the transmitter and receiver. */ 85727d5dc18SMarcel Moolenaar error = ns8250_drain(bas, UART_DRAIN_RECEIVER|UART_DRAIN_TRANSMITTER); 85827d5dc18SMarcel Moolenaar if (error) { 85927d5dc18SMarcel Moolenaar uart_setreg(bas, REG_MCR, mcr); 860b192bae6SRuslan Bukin val = 0; 861b192bae6SRuslan Bukin #ifdef CPU_XBURST 862b192bae6SRuslan Bukin val |= FCR_UART_ON; 863b192bae6SRuslan Bukin #endif 864b192bae6SRuslan Bukin uart_setreg(bas, REG_FCR, val); 86527d5dc18SMarcel Moolenaar uart_barrier(bas); 86627d5dc18SMarcel Moolenaar goto describe; 86727d5dc18SMarcel Moolenaar } 86827d5dc18SMarcel Moolenaar 86927d5dc18SMarcel Moolenaar /* 87027d5dc18SMarcel Moolenaar * We should have a sufficiently clean "pipe" to determine the 87127d5dc18SMarcel Moolenaar * size of the FIFOs. We send as much characters as is reasonable 8726bccea7cSRebecca Cran * and wait for the overflow bit in the LSR register to be 87389eef2deSThomas Moestl * asserted, counting the characters as we send them. Based on 87489eef2deSThomas Moestl * that count we know the FIFO size. 87527d5dc18SMarcel Moolenaar */ 87689eef2deSThomas Moestl do { 87727d5dc18SMarcel Moolenaar uart_setreg(bas, REG_DATA, 0); 87827d5dc18SMarcel Moolenaar uart_barrier(bas); 87927d5dc18SMarcel Moolenaar count++; 88027d5dc18SMarcel Moolenaar 88127d5dc18SMarcel Moolenaar limit = 30; 88289eef2deSThomas Moestl lsr = 0; 88389eef2deSThomas Moestl /* 88489eef2deSThomas Moestl * LSR bits are cleared upon read, so we must accumulate 88589eef2deSThomas Moestl * them to be able to test LSR_OE below. 88689eef2deSThomas Moestl */ 88789eef2deSThomas Moestl while (((lsr |= uart_getreg(bas, REG_LSR)) & LSR_TEMT) == 0 && 88889eef2deSThomas Moestl --limit) 88927d5dc18SMarcel Moolenaar DELAY(delay); 89027d5dc18SMarcel Moolenaar if (limit == 0) { 8910aefb0a6SBenno Rice ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 89258957d87SBenno Rice uart_setreg(bas, REG_IER, ier); 89327d5dc18SMarcel Moolenaar uart_setreg(bas, REG_MCR, mcr); 894b192bae6SRuslan Bukin val = 0; 895b192bae6SRuslan Bukin #ifdef CPU_XBURST 896b192bae6SRuslan Bukin val |= FCR_UART_ON; 897b192bae6SRuslan Bukin #endif 898b192bae6SRuslan Bukin uart_setreg(bas, REG_FCR, val); 89927d5dc18SMarcel Moolenaar uart_barrier(bas); 90027d5dc18SMarcel Moolenaar count = 0; 90127d5dc18SMarcel Moolenaar goto describe; 90227d5dc18SMarcel Moolenaar } 9036e71b3c3SEd Maste } while ((lsr & LSR_OE) == 0 && count < 260); 90489eef2deSThomas Moestl count--; 90527d5dc18SMarcel Moolenaar 90627d5dc18SMarcel Moolenaar uart_setreg(bas, REG_MCR, mcr); 90727d5dc18SMarcel Moolenaar 90827d5dc18SMarcel Moolenaar /* Reset FIFOs. */ 90927d5dc18SMarcel Moolenaar ns8250_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 91027d5dc18SMarcel Moolenaar 91127d5dc18SMarcel Moolenaar describe: 91289eef2deSThomas Moestl if (count >= 14 && count <= 16) { 91327d5dc18SMarcel Moolenaar sc->sc_rxfifosz = 16; 91427d5dc18SMarcel Moolenaar device_set_desc(sc->sc_dev, "16550 or compatible"); 91589eef2deSThomas Moestl } else if (count >= 28 && count <= 32) { 91627d5dc18SMarcel Moolenaar sc->sc_rxfifosz = 32; 91727d5dc18SMarcel Moolenaar device_set_desc(sc->sc_dev, "16650 or compatible"); 91889eef2deSThomas Moestl } else if (count >= 56 && count <= 64) { 91927d5dc18SMarcel Moolenaar sc->sc_rxfifosz = 64; 92027d5dc18SMarcel Moolenaar device_set_desc(sc->sc_dev, "16750 or compatible"); 92189eef2deSThomas Moestl } else if (count >= 112 && count <= 128) { 92227d5dc18SMarcel Moolenaar sc->sc_rxfifosz = 128; 92327d5dc18SMarcel Moolenaar device_set_desc(sc->sc_dev, "16950 or compatible"); 9246e71b3c3SEd Maste } else if (count >= 224 && count <= 256) { 9256e71b3c3SEd Maste sc->sc_rxfifosz = 256; 9266e71b3c3SEd Maste device_set_desc(sc->sc_dev, "16x50 with 256 byte FIFO"); 92727d5dc18SMarcel Moolenaar } else { 928c21e0da2SMarcel Moolenaar sc->sc_rxfifosz = 16; 92927d5dc18SMarcel Moolenaar device_set_desc(sc->sc_dev, 93027d5dc18SMarcel Moolenaar "Non-standard ns8250 class UART with FIFOs"); 93127d5dc18SMarcel Moolenaar } 93227d5dc18SMarcel Moolenaar 93327d5dc18SMarcel Moolenaar /* 93427d5dc18SMarcel Moolenaar * Force the Tx FIFO size to 16 bytes for now. We don't program the 93527d5dc18SMarcel Moolenaar * Tx trigger. Also, we assume that all data has been sent when the 93627d5dc18SMarcel Moolenaar * interrupt happens. 93727d5dc18SMarcel Moolenaar */ 93827d5dc18SMarcel Moolenaar sc->sc_txfifosz = 16; 93927d5dc18SMarcel Moolenaar 940dc70e792SMarcel Moolenaar #if 0 941dc70e792SMarcel Moolenaar /* 942dc70e792SMarcel Moolenaar * XXX there are some issues related to hardware flow control and 943453130d9SPedro F. Giffuni * it's likely that uart(4) is the cause. This basically needs more 944dc70e792SMarcel Moolenaar * investigation, but we avoid using for hardware flow control 945dc70e792SMarcel Moolenaar * until then. 946dc70e792SMarcel Moolenaar */ 94784c7b427SMarcel Moolenaar /* 16650s or higher have automatic flow control. */ 94884c7b427SMarcel Moolenaar if (sc->sc_rxfifosz > 16) { 94984c7b427SMarcel Moolenaar sc->sc_hwiflow = 1; 95084c7b427SMarcel Moolenaar sc->sc_hwoflow = 1; 95184c7b427SMarcel Moolenaar } 952dc70e792SMarcel Moolenaar #endif 95384c7b427SMarcel Moolenaar 95427d5dc18SMarcel Moolenaar return (0); 95527d5dc18SMarcel Moolenaar } 95627d5dc18SMarcel Moolenaar 957167cb33fSIan Lepore int 95827d5dc18SMarcel Moolenaar ns8250_bus_receive(struct uart_softc *sc) 95927d5dc18SMarcel Moolenaar { 96027d5dc18SMarcel Moolenaar struct uart_bas *bas; 96127d5dc18SMarcel Moolenaar int xc; 96227d5dc18SMarcel Moolenaar uint8_t lsr; 96327d5dc18SMarcel Moolenaar 96427d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 9658af03381SMarcel Moolenaar uart_lock(sc->sc_hwmtx); 96627d5dc18SMarcel Moolenaar lsr = uart_getreg(bas, REG_LSR); 96744ed791bSMarcel Moolenaar while (lsr & LSR_RXRDY) { 96844ed791bSMarcel Moolenaar if (uart_rx_full(sc)) { 96944ed791bSMarcel Moolenaar sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; 97027d5dc18SMarcel Moolenaar break; 97144ed791bSMarcel Moolenaar } 97227d5dc18SMarcel Moolenaar xc = uart_getreg(bas, REG_DATA); 97327d5dc18SMarcel Moolenaar if (lsr & LSR_FE) 97427d5dc18SMarcel Moolenaar xc |= UART_STAT_FRAMERR; 97527d5dc18SMarcel Moolenaar if (lsr & LSR_PE) 97627d5dc18SMarcel Moolenaar xc |= UART_STAT_PARERR; 97727d5dc18SMarcel Moolenaar uart_rx_put(sc, xc); 97844ed791bSMarcel Moolenaar lsr = uart_getreg(bas, REG_LSR); 97944ed791bSMarcel Moolenaar } 98044ed791bSMarcel Moolenaar /* Discard everything left in the Rx FIFO. */ 98144ed791bSMarcel Moolenaar while (lsr & LSR_RXRDY) { 98244ed791bSMarcel Moolenaar (void)uart_getreg(bas, REG_DATA); 98344ed791bSMarcel Moolenaar uart_barrier(bas); 98444ed791bSMarcel Moolenaar lsr = uart_getreg(bas, REG_LSR); 98527d5dc18SMarcel Moolenaar } 9868af03381SMarcel Moolenaar uart_unlock(sc->sc_hwmtx); 98727d5dc18SMarcel Moolenaar return (0); 98827d5dc18SMarcel Moolenaar } 98927d5dc18SMarcel Moolenaar 990167cb33fSIan Lepore int 99127d5dc18SMarcel Moolenaar ns8250_bus_setsig(struct uart_softc *sc, int sig) 99227d5dc18SMarcel Moolenaar { 99327d5dc18SMarcel Moolenaar struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 99427d5dc18SMarcel Moolenaar struct uart_bas *bas; 99527d5dc18SMarcel Moolenaar uint32_t new, old; 99627d5dc18SMarcel Moolenaar 99727d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 99827d5dc18SMarcel Moolenaar do { 99927d5dc18SMarcel Moolenaar old = sc->sc_hwsig; 100027d5dc18SMarcel Moolenaar new = old; 100128710806SPoul-Henning Kamp if (sig & SER_DDTR) { 1002fdfbb3f5SIan Lepore new = (new & ~SER_DTR) | (sig & (SER_DTR | SER_DDTR)); 100327d5dc18SMarcel Moolenaar } 100428710806SPoul-Henning Kamp if (sig & SER_DRTS) { 1005fdfbb3f5SIan Lepore new = (new & ~SER_RTS) | (sig & (SER_RTS | SER_DRTS)); 100627d5dc18SMarcel Moolenaar } 100727d5dc18SMarcel Moolenaar } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 10088af03381SMarcel Moolenaar uart_lock(sc->sc_hwmtx); 100927d5dc18SMarcel Moolenaar ns8250->mcr &= ~(MCR_DTR|MCR_RTS); 101028710806SPoul-Henning Kamp if (new & SER_DTR) 101127d5dc18SMarcel Moolenaar ns8250->mcr |= MCR_DTR; 101228710806SPoul-Henning Kamp if (new & SER_RTS) 101327d5dc18SMarcel Moolenaar ns8250->mcr |= MCR_RTS; 101427d5dc18SMarcel Moolenaar uart_setreg(bas, REG_MCR, ns8250->mcr); 101527d5dc18SMarcel Moolenaar uart_barrier(bas); 10168af03381SMarcel Moolenaar uart_unlock(sc->sc_hwmtx); 101727d5dc18SMarcel Moolenaar return (0); 101827d5dc18SMarcel Moolenaar } 101927d5dc18SMarcel Moolenaar 1020167cb33fSIan Lepore int 102127d5dc18SMarcel Moolenaar ns8250_bus_transmit(struct uart_softc *sc) 102227d5dc18SMarcel Moolenaar { 102327d5dc18SMarcel Moolenaar struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 102427d5dc18SMarcel Moolenaar struct uart_bas *bas; 102527d5dc18SMarcel Moolenaar int i; 102627d5dc18SMarcel Moolenaar 102727d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 10288af03381SMarcel Moolenaar uart_lock(sc->sc_hwmtx); 10294e352a45SAlexander Motin if (sc->sc_txdatasz > 1) { 10304e352a45SAlexander Motin if ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0) 10314e352a45SAlexander Motin ns8250_drain(bas, UART_DRAIN_TRANSMITTER); 10324e352a45SAlexander Motin } else { 103327d5dc18SMarcel Moolenaar while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0) 10344e352a45SAlexander Motin DELAY(4); 10354e352a45SAlexander Motin } 103627d5dc18SMarcel Moolenaar for (i = 0; i < sc->sc_txdatasz; i++) { 103727d5dc18SMarcel Moolenaar uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]); 103827d5dc18SMarcel Moolenaar uart_barrier(bas); 103927d5dc18SMarcel Moolenaar } 10403c7b9077SMichal Meloun uart_setreg(bas, REG_IER, ns8250->ier | IER_ETXRDY); 10413c7b9077SMichal Meloun uart_barrier(bas); 10421c60b24bSColin Percival if (broken_txfifo) 10431c60b24bSColin Percival ns8250_drain(bas, UART_DRAIN_TRANSMITTER); 10441c60b24bSColin Percival else 104527d5dc18SMarcel Moolenaar sc->sc_txbusy = 1; 10468af03381SMarcel Moolenaar uart_unlock(sc->sc_hwmtx); 10471c60b24bSColin Percival if (broken_txfifo) 10481c60b24bSColin Percival uart_sched_softih(sc, SER_INT_TXIDLE); 104927d5dc18SMarcel Moolenaar return (0); 105027d5dc18SMarcel Moolenaar } 1051d76a1ef4SWarner Losh 1052d76a1ef4SWarner Losh void 1053d76a1ef4SWarner Losh ns8250_bus_grab(struct uart_softc *sc) 1054d76a1ef4SWarner Losh { 1055d76a1ef4SWarner Losh struct uart_bas *bas = &sc->sc_bas; 1056caf6d6b4SOlivier Houchard struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 10578bc9a079SOlivier Houchard u_char ier; 1058d76a1ef4SWarner Losh 1059d76a1ef4SWarner Losh /* 1060d76a1ef4SWarner Losh * turn off all interrupts to enter polling mode. Leave the 1061d76a1ef4SWarner Losh * saved mask alone. We'll restore whatever it was in ungrab. 1062453130d9SPedro F. Giffuni * All pending interrupt signals are reset when IER is set to 0. 1063d76a1ef4SWarner Losh */ 1064d76a1ef4SWarner Losh uart_lock(sc->sc_hwmtx); 10658bc9a079SOlivier Houchard ier = uart_getreg(bas, REG_IER); 10668bc9a079SOlivier Houchard uart_setreg(bas, REG_IER, ier & ns8250->ier_mask); 1067d76a1ef4SWarner Losh uart_barrier(bas); 1068d76a1ef4SWarner Losh uart_unlock(sc->sc_hwmtx); 1069d76a1ef4SWarner Losh } 1070d76a1ef4SWarner Losh 1071d76a1ef4SWarner Losh void 1072d76a1ef4SWarner Losh ns8250_bus_ungrab(struct uart_softc *sc) 1073d76a1ef4SWarner Losh { 1074d76a1ef4SWarner Losh struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 1075d76a1ef4SWarner Losh struct uart_bas *bas = &sc->sc_bas; 1076d76a1ef4SWarner Losh 1077d76a1ef4SWarner Losh /* 1078d76a1ef4SWarner Losh * Restore previous interrupt mask 1079d76a1ef4SWarner Losh */ 1080d76a1ef4SWarner Losh uart_lock(sc->sc_hwmtx); 1081d76a1ef4SWarner Losh uart_setreg(bas, REG_IER, ns8250->ier); 1082d76a1ef4SWarner Losh uart_barrier(bas); 1083d76a1ef4SWarner Losh uart_unlock(sc->sc_hwmtx); 1084d76a1ef4SWarner Losh } 1085