1098ca2bdSWarner Losh /*- 227d5dc18SMarcel Moolenaar * Copyright (c) 2003 Marcel Moolenaar 327d5dc18SMarcel Moolenaar * All rights reserved. 427d5dc18SMarcel Moolenaar * 527d5dc18SMarcel Moolenaar * Redistribution and use in source and binary forms, with or without 627d5dc18SMarcel Moolenaar * modification, are permitted provided that the following conditions 727d5dc18SMarcel Moolenaar * are met: 827d5dc18SMarcel Moolenaar * 927d5dc18SMarcel Moolenaar * 1. Redistributions of source code must retain the above copyright 1027d5dc18SMarcel Moolenaar * notice, this list of conditions and the following disclaimer. 1127d5dc18SMarcel Moolenaar * 2. Redistributions in binary form must reproduce the above copyright 1227d5dc18SMarcel Moolenaar * notice, this list of conditions and the following disclaimer in the 1327d5dc18SMarcel Moolenaar * documentation and/or other materials provided with the distribution. 1427d5dc18SMarcel Moolenaar * 1527d5dc18SMarcel Moolenaar * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 1627d5dc18SMarcel Moolenaar * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 1727d5dc18SMarcel Moolenaar * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 1827d5dc18SMarcel Moolenaar * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 1927d5dc18SMarcel Moolenaar * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 2027d5dc18SMarcel Moolenaar * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2127d5dc18SMarcel Moolenaar * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2227d5dc18SMarcel Moolenaar * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2327d5dc18SMarcel Moolenaar * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 2427d5dc18SMarcel Moolenaar * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2527d5dc18SMarcel Moolenaar */ 2627d5dc18SMarcel Moolenaar 27ac4adddfSGanbold Tsagaankhuu #include "opt_platform.h" 28ac4adddfSGanbold Tsagaankhuu 2927d5dc18SMarcel Moolenaar #include <sys/cdefs.h> 3027d5dc18SMarcel Moolenaar __FBSDID("$FreeBSD$"); 3127d5dc18SMarcel Moolenaar 3227d5dc18SMarcel Moolenaar #include <sys/param.h> 3327d5dc18SMarcel Moolenaar #include <sys/systm.h> 3427d5dc18SMarcel Moolenaar #include <sys/bus.h> 3527d5dc18SMarcel Moolenaar #include <sys/conf.h> 361c60b24bSColin Percival #include <sys/kernel.h> 371c60b24bSColin Percival #include <sys/sysctl.h> 3827d5dc18SMarcel Moolenaar #include <machine/bus.h> 3927d5dc18SMarcel Moolenaar 40ac4adddfSGanbold Tsagaankhuu #ifdef FDT 41ac4adddfSGanbold Tsagaankhuu #include <dev/fdt/fdt_common.h> 42ac4adddfSGanbold Tsagaankhuu #include <dev/ofw/ofw_bus.h> 43ac4adddfSGanbold Tsagaankhuu #include <dev/ofw/ofw_bus_subr.h> 44ac4adddfSGanbold Tsagaankhuu #endif 45ac4adddfSGanbold Tsagaankhuu 4627d5dc18SMarcel Moolenaar #include <dev/uart/uart.h> 4727d5dc18SMarcel Moolenaar #include <dev/uart/uart_cpu.h> 483bb693afSIan Lepore #ifdef FDT 493bb693afSIan Lepore #include <dev/uart/uart_cpu_fdt.h> 503bb693afSIan Lepore #endif 5127d5dc18SMarcel Moolenaar #include <dev/uart/uart_bus.h> 52167cb33fSIan Lepore #include <dev/uart/uart_dev_ns8250.h> 5376563beaSMarcel Moolenaar 5476563beaSMarcel Moolenaar #include <dev/ic/ns16550.h> 5527d5dc18SMarcel Moolenaar 5627d5dc18SMarcel Moolenaar #include "uart_if.h" 5727d5dc18SMarcel Moolenaar 5827d5dc18SMarcel Moolenaar #define DEFAULT_RCLK 1843200 5927d5dc18SMarcel Moolenaar 60ac4adddfSGanbold Tsagaankhuu static int broken_txfifo = 0; 61af3b2549SHans Petter Selasky SYSCTL_INT(_hw, OID_AUTO, broken_txfifo, CTLFLAG_RWTUN, 62ac4adddfSGanbold Tsagaankhuu &broken_txfifo, 0, "UART FIFO has QEMU emulation bug"); 63ac4adddfSGanbold Tsagaankhuu 6427d5dc18SMarcel Moolenaar /* 6527d5dc18SMarcel Moolenaar * Clear pending interrupts. THRE is cleared by reading IIR. Data 6627d5dc18SMarcel Moolenaar * that may have been received gets lost here. 6727d5dc18SMarcel Moolenaar */ 6827d5dc18SMarcel Moolenaar static void 6927d5dc18SMarcel Moolenaar ns8250_clrint(struct uart_bas *bas) 7027d5dc18SMarcel Moolenaar { 71d7ae5af5SMarcel Moolenaar uint8_t iir, lsr; 7227d5dc18SMarcel Moolenaar 7327d5dc18SMarcel Moolenaar iir = uart_getreg(bas, REG_IIR); 7427d5dc18SMarcel Moolenaar while ((iir & IIR_NOPEND) == 0) { 7527d5dc18SMarcel Moolenaar iir &= IIR_IMASK; 76d7ae5af5SMarcel Moolenaar if (iir == IIR_RLS) { 77d7ae5af5SMarcel Moolenaar lsr = uart_getreg(bas, REG_LSR); 78d7ae5af5SMarcel Moolenaar if (lsr & (LSR_BI|LSR_FE|LSR_PE)) 79d7ae5af5SMarcel Moolenaar (void)uart_getreg(bas, REG_DATA); 80d7ae5af5SMarcel Moolenaar } else if (iir == IIR_RXRDY || iir == IIR_RXTOUT) 8127d5dc18SMarcel Moolenaar (void)uart_getreg(bas, REG_DATA); 8227d5dc18SMarcel Moolenaar else if (iir == IIR_MLSC) 8327d5dc18SMarcel Moolenaar (void)uart_getreg(bas, REG_MSR); 8427d5dc18SMarcel Moolenaar uart_barrier(bas); 8527d5dc18SMarcel Moolenaar iir = uart_getreg(bas, REG_IIR); 8627d5dc18SMarcel Moolenaar } 8727d5dc18SMarcel Moolenaar } 8827d5dc18SMarcel Moolenaar 8927d5dc18SMarcel Moolenaar static int 9027d5dc18SMarcel Moolenaar ns8250_delay(struct uart_bas *bas) 9127d5dc18SMarcel Moolenaar { 9227d5dc18SMarcel Moolenaar int divisor; 9327d5dc18SMarcel Moolenaar u_char lcr; 9427d5dc18SMarcel Moolenaar 9527d5dc18SMarcel Moolenaar lcr = uart_getreg(bas, REG_LCR); 9627d5dc18SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 9727d5dc18SMarcel Moolenaar uart_barrier(bas); 9858957d87SBenno Rice divisor = uart_getreg(bas, REG_DLL) | (uart_getreg(bas, REG_DLH) << 8); 9927d5dc18SMarcel Moolenaar uart_barrier(bas); 10027d5dc18SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr); 10127d5dc18SMarcel Moolenaar uart_barrier(bas); 10227d5dc18SMarcel Moolenaar 10327d5dc18SMarcel Moolenaar /* 1/10th the time to transmit 1 character (estimate). */ 104ebecffe9SMarcel Moolenaar if (divisor <= 134) 10527d5dc18SMarcel Moolenaar return (16000000 * divisor / bas->rclk); 106ebecffe9SMarcel Moolenaar return (16000 * divisor / (bas->rclk / 1000)); 10727d5dc18SMarcel Moolenaar } 10827d5dc18SMarcel Moolenaar 10927d5dc18SMarcel Moolenaar static int 11027d5dc18SMarcel Moolenaar ns8250_divisor(int rclk, int baudrate) 11127d5dc18SMarcel Moolenaar { 11227d5dc18SMarcel Moolenaar int actual_baud, divisor; 11327d5dc18SMarcel Moolenaar int error; 11427d5dc18SMarcel Moolenaar 11527d5dc18SMarcel Moolenaar if (baudrate == 0) 11627d5dc18SMarcel Moolenaar return (0); 11727d5dc18SMarcel Moolenaar 11827d5dc18SMarcel Moolenaar divisor = (rclk / (baudrate << 3) + 1) >> 1; 11927d5dc18SMarcel Moolenaar if (divisor == 0 || divisor >= 65536) 12027d5dc18SMarcel Moolenaar return (0); 12127d5dc18SMarcel Moolenaar actual_baud = rclk / (divisor << 4); 12227d5dc18SMarcel Moolenaar 12327d5dc18SMarcel Moolenaar /* 10 times error in percent: */ 12427d5dc18SMarcel Moolenaar error = ((actual_baud - baudrate) * 2000 / baudrate + 1) >> 1; 12527d5dc18SMarcel Moolenaar 12627d5dc18SMarcel Moolenaar /* 3.0% maximum error tolerance: */ 12727d5dc18SMarcel Moolenaar if (error < -30 || error > 30) 12827d5dc18SMarcel Moolenaar return (0); 12927d5dc18SMarcel Moolenaar 13027d5dc18SMarcel Moolenaar return (divisor); 13127d5dc18SMarcel Moolenaar } 13227d5dc18SMarcel Moolenaar 13327d5dc18SMarcel Moolenaar static int 13427d5dc18SMarcel Moolenaar ns8250_drain(struct uart_bas *bas, int what) 13527d5dc18SMarcel Moolenaar { 13627d5dc18SMarcel Moolenaar int delay, limit; 13727d5dc18SMarcel Moolenaar 13827d5dc18SMarcel Moolenaar delay = ns8250_delay(bas); 13927d5dc18SMarcel Moolenaar 14027d5dc18SMarcel Moolenaar if (what & UART_DRAIN_TRANSMITTER) { 14127d5dc18SMarcel Moolenaar /* 14227d5dc18SMarcel Moolenaar * Pick an arbitrary high limit to avoid getting stuck in 14327d5dc18SMarcel Moolenaar * an infinite loop when the hardware is broken. Make the 14427d5dc18SMarcel Moolenaar * limit high enough to handle large FIFOs. 14527d5dc18SMarcel Moolenaar */ 14627d5dc18SMarcel Moolenaar limit = 10*1024; 14727d5dc18SMarcel Moolenaar while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) 14827d5dc18SMarcel Moolenaar DELAY(delay); 14927d5dc18SMarcel Moolenaar if (limit == 0) { 15027d5dc18SMarcel Moolenaar /* printf("ns8250: transmitter appears stuck... "); */ 15127d5dc18SMarcel Moolenaar return (EIO); 15227d5dc18SMarcel Moolenaar } 15327d5dc18SMarcel Moolenaar } 15427d5dc18SMarcel Moolenaar 15527d5dc18SMarcel Moolenaar if (what & UART_DRAIN_RECEIVER) { 15627d5dc18SMarcel Moolenaar /* 15727d5dc18SMarcel Moolenaar * Pick an arbitrary high limit to avoid getting stuck in 15827d5dc18SMarcel Moolenaar * an infinite loop when the hardware is broken. Make the 15927d5dc18SMarcel Moolenaar * limit high enough to handle large FIFOs and integrated 16027d5dc18SMarcel Moolenaar * UARTs. The HP rx2600 for example has 3 UARTs on the 16127d5dc18SMarcel Moolenaar * management board that tend to get a lot of data send 16227d5dc18SMarcel Moolenaar * to it when the UART is first activated. 16327d5dc18SMarcel Moolenaar */ 16427d5dc18SMarcel Moolenaar limit=10*4096; 16527d5dc18SMarcel Moolenaar while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) { 16627d5dc18SMarcel Moolenaar (void)uart_getreg(bas, REG_DATA); 16727d5dc18SMarcel Moolenaar uart_barrier(bas); 16827d5dc18SMarcel Moolenaar DELAY(delay << 2); 16927d5dc18SMarcel Moolenaar } 17027d5dc18SMarcel Moolenaar if (limit == 0) { 17127d5dc18SMarcel Moolenaar /* printf("ns8250: receiver appears broken... "); */ 17227d5dc18SMarcel Moolenaar return (EIO); 17327d5dc18SMarcel Moolenaar } 17427d5dc18SMarcel Moolenaar } 17527d5dc18SMarcel Moolenaar 17627d5dc18SMarcel Moolenaar return (0); 17727d5dc18SMarcel Moolenaar } 17827d5dc18SMarcel Moolenaar 17927d5dc18SMarcel Moolenaar /* 18027d5dc18SMarcel Moolenaar * We can only flush UARTs with FIFOs. UARTs without FIFOs should be 18127d5dc18SMarcel Moolenaar * drained. WARNING: this function clobbers the FIFO setting! 18227d5dc18SMarcel Moolenaar */ 18327d5dc18SMarcel Moolenaar static void 18427d5dc18SMarcel Moolenaar ns8250_flush(struct uart_bas *bas, int what) 18527d5dc18SMarcel Moolenaar { 18627d5dc18SMarcel Moolenaar uint8_t fcr; 18727d5dc18SMarcel Moolenaar 18827d5dc18SMarcel Moolenaar fcr = FCR_ENABLE; 18927d5dc18SMarcel Moolenaar if (what & UART_FLUSH_TRANSMITTER) 19027d5dc18SMarcel Moolenaar fcr |= FCR_XMT_RST; 19127d5dc18SMarcel Moolenaar if (what & UART_FLUSH_RECEIVER) 19227d5dc18SMarcel Moolenaar fcr |= FCR_RCV_RST; 19327d5dc18SMarcel Moolenaar uart_setreg(bas, REG_FCR, fcr); 19427d5dc18SMarcel Moolenaar uart_barrier(bas); 19527d5dc18SMarcel Moolenaar } 19627d5dc18SMarcel Moolenaar 19727d5dc18SMarcel Moolenaar static int 19827d5dc18SMarcel Moolenaar ns8250_param(struct uart_bas *bas, int baudrate, int databits, int stopbits, 19927d5dc18SMarcel Moolenaar int parity) 20027d5dc18SMarcel Moolenaar { 20127d5dc18SMarcel Moolenaar int divisor; 20227d5dc18SMarcel Moolenaar uint8_t lcr; 20327d5dc18SMarcel Moolenaar 20427d5dc18SMarcel Moolenaar lcr = 0; 20527d5dc18SMarcel Moolenaar if (databits >= 8) 20627d5dc18SMarcel Moolenaar lcr |= LCR_8BITS; 20727d5dc18SMarcel Moolenaar else if (databits == 7) 20827d5dc18SMarcel Moolenaar lcr |= LCR_7BITS; 20927d5dc18SMarcel Moolenaar else if (databits == 6) 21027d5dc18SMarcel Moolenaar lcr |= LCR_6BITS; 21127d5dc18SMarcel Moolenaar else 21227d5dc18SMarcel Moolenaar lcr |= LCR_5BITS; 21327d5dc18SMarcel Moolenaar if (stopbits > 1) 21427d5dc18SMarcel Moolenaar lcr |= LCR_STOPB; 21527d5dc18SMarcel Moolenaar lcr |= parity << 3; 21627d5dc18SMarcel Moolenaar 21727d5dc18SMarcel Moolenaar /* Set baudrate. */ 21827d5dc18SMarcel Moolenaar if (baudrate > 0) { 21927d5dc18SMarcel Moolenaar divisor = ns8250_divisor(bas->rclk, baudrate); 22027d5dc18SMarcel Moolenaar if (divisor == 0) 22127d5dc18SMarcel Moolenaar return (EINVAL); 22263f8efd3SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 22363f8efd3SMarcel Moolenaar uart_barrier(bas); 22458957d87SBenno Rice uart_setreg(bas, REG_DLL, divisor & 0xff); 22558957d87SBenno Rice uart_setreg(bas, REG_DLH, (divisor >> 8) & 0xff); 22627d5dc18SMarcel Moolenaar uart_barrier(bas); 22727d5dc18SMarcel Moolenaar } 22827d5dc18SMarcel Moolenaar 22927d5dc18SMarcel Moolenaar /* Set LCR and clear DLAB. */ 23027d5dc18SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr); 23127d5dc18SMarcel Moolenaar uart_barrier(bas); 23227d5dc18SMarcel Moolenaar return (0); 23327d5dc18SMarcel Moolenaar } 23427d5dc18SMarcel Moolenaar 23527d5dc18SMarcel Moolenaar /* 23627d5dc18SMarcel Moolenaar * Low-level UART interface. 23727d5dc18SMarcel Moolenaar */ 23827d5dc18SMarcel Moolenaar static int ns8250_probe(struct uart_bas *bas); 23927d5dc18SMarcel Moolenaar static void ns8250_init(struct uart_bas *bas, int, int, int, int); 24027d5dc18SMarcel Moolenaar static void ns8250_term(struct uart_bas *bas); 24127d5dc18SMarcel Moolenaar static void ns8250_putc(struct uart_bas *bas, int); 24297202af2SMarius Strobl static int ns8250_rxready(struct uart_bas *bas); 243634e63c9SMarcel Moolenaar static int ns8250_getc(struct uart_bas *bas, struct mtx *); 24427d5dc18SMarcel Moolenaar 245167cb33fSIan Lepore struct uart_ops uart_ns8250_ops = { 24627d5dc18SMarcel Moolenaar .probe = ns8250_probe, 24727d5dc18SMarcel Moolenaar .init = ns8250_init, 24827d5dc18SMarcel Moolenaar .term = ns8250_term, 24927d5dc18SMarcel Moolenaar .putc = ns8250_putc, 25097202af2SMarius Strobl .rxready = ns8250_rxready, 25127d5dc18SMarcel Moolenaar .getc = ns8250_getc, 25227d5dc18SMarcel Moolenaar }; 25327d5dc18SMarcel Moolenaar 25427d5dc18SMarcel Moolenaar static int 25527d5dc18SMarcel Moolenaar ns8250_probe(struct uart_bas *bas) 25627d5dc18SMarcel Moolenaar { 2578bceca4fSBenno Rice u_char val; 25827d5dc18SMarcel Moolenaar 25927d5dc18SMarcel Moolenaar /* Check known 0 bits that don't depend on DLAB. */ 26027d5dc18SMarcel Moolenaar val = uart_getreg(bas, REG_IIR); 26127d5dc18SMarcel Moolenaar if (val & 0x30) 26227d5dc18SMarcel Moolenaar return (ENXIO); 2635bdddc29SMarcel Moolenaar /* 2645bdddc29SMarcel Moolenaar * Bit 6 of the MCR (= 0x40) appears to be 1 for the Sun1699 2655bdddc29SMarcel Moolenaar * chip, but otherwise doesn't seem to have a function. In 2665bdddc29SMarcel Moolenaar * other words, uart(4) works regardless. Ignore that bit so 2675bdddc29SMarcel Moolenaar * the probe succeeds. 2685bdddc29SMarcel Moolenaar */ 26927d5dc18SMarcel Moolenaar val = uart_getreg(bas, REG_MCR); 2705bdddc29SMarcel Moolenaar if (val & 0xa0) 27127d5dc18SMarcel Moolenaar return (ENXIO); 27227d5dc18SMarcel Moolenaar 27327d5dc18SMarcel Moolenaar return (0); 27427d5dc18SMarcel Moolenaar } 27527d5dc18SMarcel Moolenaar 27627d5dc18SMarcel Moolenaar static void 27727d5dc18SMarcel Moolenaar ns8250_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, 27827d5dc18SMarcel Moolenaar int parity) 27927d5dc18SMarcel Moolenaar { 28058957d87SBenno Rice u_char ier; 28127d5dc18SMarcel Moolenaar 28227d5dc18SMarcel Moolenaar if (bas->rclk == 0) 28327d5dc18SMarcel Moolenaar bas->rclk = DEFAULT_RCLK; 28427d5dc18SMarcel Moolenaar ns8250_param(bas, baudrate, databits, stopbits, parity); 28527d5dc18SMarcel Moolenaar 28627d5dc18SMarcel Moolenaar /* Disable all interrupt sources. */ 2870aefb0a6SBenno Rice /* 2880aefb0a6SBenno Rice * We use 0xe0 instead of 0xf0 as the mask because the XScale PXA 2890aefb0a6SBenno Rice * UARTs split the receive time-out interrupt bit out separately as 2900aefb0a6SBenno Rice * 0x10. This gets handled by ier_mask and ier_rxbits below. 2910aefb0a6SBenno Rice */ 2920aefb0a6SBenno Rice ier = uart_getreg(bas, REG_IER) & 0xe0; 29358957d87SBenno Rice uart_setreg(bas, REG_IER, ier); 29427d5dc18SMarcel Moolenaar uart_barrier(bas); 29527d5dc18SMarcel Moolenaar 29627d5dc18SMarcel Moolenaar /* Disable the FIFO (if present). */ 29727d5dc18SMarcel Moolenaar uart_setreg(bas, REG_FCR, 0); 29827d5dc18SMarcel Moolenaar uart_barrier(bas); 29927d5dc18SMarcel Moolenaar 30027d5dc18SMarcel Moolenaar /* Set RTS & DTR. */ 30127d5dc18SMarcel Moolenaar uart_setreg(bas, REG_MCR, MCR_IE | MCR_RTS | MCR_DTR); 30227d5dc18SMarcel Moolenaar uart_barrier(bas); 30327d5dc18SMarcel Moolenaar 30427d5dc18SMarcel Moolenaar ns8250_clrint(bas); 30527d5dc18SMarcel Moolenaar } 30627d5dc18SMarcel Moolenaar 30727d5dc18SMarcel Moolenaar static void 30827d5dc18SMarcel Moolenaar ns8250_term(struct uart_bas *bas) 30927d5dc18SMarcel Moolenaar { 31027d5dc18SMarcel Moolenaar 31127d5dc18SMarcel Moolenaar /* Clear RTS & DTR. */ 31227d5dc18SMarcel Moolenaar uart_setreg(bas, REG_MCR, MCR_IE); 31327d5dc18SMarcel Moolenaar uart_barrier(bas); 31427d5dc18SMarcel Moolenaar } 31527d5dc18SMarcel Moolenaar 31627d5dc18SMarcel Moolenaar static void 31727d5dc18SMarcel Moolenaar ns8250_putc(struct uart_bas *bas, int c) 31827d5dc18SMarcel Moolenaar { 31935777a2aSMarcel Moolenaar int limit; 32027d5dc18SMarcel Moolenaar 32135777a2aSMarcel Moolenaar limit = 250000; 32227d5dc18SMarcel Moolenaar while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0 && --limit) 32335777a2aSMarcel Moolenaar DELAY(4); 32427d5dc18SMarcel Moolenaar uart_setreg(bas, REG_DATA, c); 3254e55f723SMarcel Moolenaar uart_barrier(bas); 32635777a2aSMarcel Moolenaar limit = 250000; 32727d5dc18SMarcel Moolenaar while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) 32835777a2aSMarcel Moolenaar DELAY(4); 32927d5dc18SMarcel Moolenaar } 33027d5dc18SMarcel Moolenaar 33127d5dc18SMarcel Moolenaar static int 33297202af2SMarius Strobl ns8250_rxready(struct uart_bas *bas) 33327d5dc18SMarcel Moolenaar { 33427d5dc18SMarcel Moolenaar 33597202af2SMarius Strobl return ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) != 0 ? 1 : 0); 33627d5dc18SMarcel Moolenaar } 33727d5dc18SMarcel Moolenaar 33827d5dc18SMarcel Moolenaar static int 339634e63c9SMarcel Moolenaar ns8250_getc(struct uart_bas *bas, struct mtx *hwmtx) 34027d5dc18SMarcel Moolenaar { 34135777a2aSMarcel Moolenaar int c; 342634e63c9SMarcel Moolenaar 343634e63c9SMarcel Moolenaar uart_lock(hwmtx); 34427d5dc18SMarcel Moolenaar 345634e63c9SMarcel Moolenaar while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0) { 346634e63c9SMarcel Moolenaar uart_unlock(hwmtx); 34735777a2aSMarcel Moolenaar DELAY(4); 348634e63c9SMarcel Moolenaar uart_lock(hwmtx); 349634e63c9SMarcel Moolenaar } 350634e63c9SMarcel Moolenaar 351634e63c9SMarcel Moolenaar c = uart_getreg(bas, REG_DATA); 352634e63c9SMarcel Moolenaar 353634e63c9SMarcel Moolenaar uart_unlock(hwmtx); 354634e63c9SMarcel Moolenaar 355634e63c9SMarcel Moolenaar return (c); 35627d5dc18SMarcel Moolenaar } 35727d5dc18SMarcel Moolenaar 35827d5dc18SMarcel Moolenaar static kobj_method_t ns8250_methods[] = { 35927d5dc18SMarcel Moolenaar KOBJMETHOD(uart_attach, ns8250_bus_attach), 36027d5dc18SMarcel Moolenaar KOBJMETHOD(uart_detach, ns8250_bus_detach), 36127d5dc18SMarcel Moolenaar KOBJMETHOD(uart_flush, ns8250_bus_flush), 36227d5dc18SMarcel Moolenaar KOBJMETHOD(uart_getsig, ns8250_bus_getsig), 36327d5dc18SMarcel Moolenaar KOBJMETHOD(uart_ioctl, ns8250_bus_ioctl), 36427d5dc18SMarcel Moolenaar KOBJMETHOD(uart_ipend, ns8250_bus_ipend), 36527d5dc18SMarcel Moolenaar KOBJMETHOD(uart_param, ns8250_bus_param), 36627d5dc18SMarcel Moolenaar KOBJMETHOD(uart_probe, ns8250_bus_probe), 36727d5dc18SMarcel Moolenaar KOBJMETHOD(uart_receive, ns8250_bus_receive), 36827d5dc18SMarcel Moolenaar KOBJMETHOD(uart_setsig, ns8250_bus_setsig), 36927d5dc18SMarcel Moolenaar KOBJMETHOD(uart_transmit, ns8250_bus_transmit), 370d76a1ef4SWarner Losh KOBJMETHOD(uart_grab, ns8250_bus_grab), 371d76a1ef4SWarner Losh KOBJMETHOD(uart_ungrab, ns8250_bus_ungrab), 37227d5dc18SMarcel Moolenaar { 0, 0 } 37327d5dc18SMarcel Moolenaar }; 37427d5dc18SMarcel Moolenaar 37527d5dc18SMarcel Moolenaar struct uart_class uart_ns8250_class = { 376f8100ce2SMarcel Moolenaar "ns8250", 37727d5dc18SMarcel Moolenaar ns8250_methods, 37827d5dc18SMarcel Moolenaar sizeof(struct ns8250_softc), 379f8100ce2SMarcel Moolenaar .uc_ops = &uart_ns8250_ops, 38027d5dc18SMarcel Moolenaar .uc_range = 8, 38127d5dc18SMarcel Moolenaar .uc_rclk = DEFAULT_RCLK 38227d5dc18SMarcel Moolenaar }; 38327d5dc18SMarcel Moolenaar 3843bb693afSIan Lepore #ifdef FDT 3853bb693afSIan Lepore static struct ofw_compat_data compat_data[] = { 3863bb693afSIan Lepore {"ns16550", (uintptr_t)&uart_ns8250_class}, 3873bb693afSIan Lepore {NULL, (uintptr_t)NULL}, 3883bb693afSIan Lepore }; 3893bb693afSIan Lepore UART_FDT_CLASS_AND_DEVICE(compat_data); 3903bb693afSIan Lepore #endif 3913bb693afSIan Lepore 39227d5dc18SMarcel Moolenaar #define SIGCHG(c, i, s, d) \ 39327d5dc18SMarcel Moolenaar if (c) { \ 39427d5dc18SMarcel Moolenaar i |= (i & s) ? s : s | d; \ 39527d5dc18SMarcel Moolenaar } else { \ 39627d5dc18SMarcel Moolenaar i = (i & s) ? (i & ~s) | d : i; \ 39727d5dc18SMarcel Moolenaar } 39827d5dc18SMarcel Moolenaar 399167cb33fSIan Lepore int 40027d5dc18SMarcel Moolenaar ns8250_bus_attach(struct uart_softc *sc) 40127d5dc18SMarcel Moolenaar { 40227d5dc18SMarcel Moolenaar struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 40327d5dc18SMarcel Moolenaar struct uart_bas *bas; 404823c77d7SSam Leffler unsigned int ivar; 405ac4adddfSGanbold Tsagaankhuu #ifdef FDT 406ac4adddfSGanbold Tsagaankhuu phandle_t node; 407ac4adddfSGanbold Tsagaankhuu pcell_t cell; 408ac4adddfSGanbold Tsagaankhuu #endif 409ac4adddfSGanbold Tsagaankhuu 410ac4adddfSGanbold Tsagaankhuu ns8250->busy_detect = 0; 411ac4adddfSGanbold Tsagaankhuu 412ac4adddfSGanbold Tsagaankhuu #ifdef FDT 413ac4adddfSGanbold Tsagaankhuu /* 414ac4adddfSGanbold Tsagaankhuu * Check whether uart requires to read USR reg when IIR_BUSY and 415ac4adddfSGanbold Tsagaankhuu * has broken txfifo. 416ac4adddfSGanbold Tsagaankhuu */ 417ac4adddfSGanbold Tsagaankhuu node = ofw_bus_get_node(sc->sc_dev); 418ac4adddfSGanbold Tsagaankhuu if ((OF_getprop(node, "busy-detect", &cell, sizeof(cell))) > 0) 419ac4adddfSGanbold Tsagaankhuu ns8250->busy_detect = 1; 420ac4adddfSGanbold Tsagaankhuu if ((OF_getprop(node, "broken-txfifo", &cell, sizeof(cell))) > 0) 421ac4adddfSGanbold Tsagaankhuu broken_txfifo = 1; 422ac4adddfSGanbold Tsagaankhuu #endif 42327d5dc18SMarcel Moolenaar 42427d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 42527d5dc18SMarcel Moolenaar 42627d5dc18SMarcel Moolenaar ns8250->mcr = uart_getreg(bas, REG_MCR); 427823c77d7SSam Leffler ns8250->fcr = FCR_ENABLE; 428823c77d7SSam Leffler if (!resource_int_value("uart", device_get_unit(sc->sc_dev), "flags", 429823c77d7SSam Leffler &ivar)) { 430823c77d7SSam Leffler if (UART_FLAGS_FCR_RX_LOW(ivar)) 431823c77d7SSam Leffler ns8250->fcr |= FCR_RX_LOW; 432823c77d7SSam Leffler else if (UART_FLAGS_FCR_RX_MEDL(ivar)) 433823c77d7SSam Leffler ns8250->fcr |= FCR_RX_MEDL; 434823c77d7SSam Leffler else if (UART_FLAGS_FCR_RX_HIGH(ivar)) 435823c77d7SSam Leffler ns8250->fcr |= FCR_RX_HIGH; 436823c77d7SSam Leffler else 437823c77d7SSam Leffler ns8250->fcr |= FCR_RX_MEDH; 438823c77d7SSam Leffler } else 439823c77d7SSam Leffler ns8250->fcr |= FCR_RX_MEDH; 4400aefb0a6SBenno Rice 4410aefb0a6SBenno Rice /* Get IER mask */ 4420aefb0a6SBenno Rice ivar = 0xf0; 4430aefb0a6SBenno Rice resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_mask", 4440aefb0a6SBenno Rice &ivar); 4450aefb0a6SBenno Rice ns8250->ier_mask = (uint8_t)(ivar & 0xff); 4460aefb0a6SBenno Rice 4470aefb0a6SBenno Rice /* Get IER RX interrupt bits */ 4480aefb0a6SBenno Rice ivar = IER_EMSC | IER_ERLS | IER_ERXRDY; 4490aefb0a6SBenno Rice resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_rxbits", 4500aefb0a6SBenno Rice &ivar); 4510aefb0a6SBenno Rice ns8250->ier_rxbits = (uint8_t)(ivar & 0xff); 4520aefb0a6SBenno Rice 45327d5dc18SMarcel Moolenaar uart_setreg(bas, REG_FCR, ns8250->fcr); 45427d5dc18SMarcel Moolenaar uart_barrier(bas); 45527d5dc18SMarcel Moolenaar ns8250_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 45627d5dc18SMarcel Moolenaar 45727d5dc18SMarcel Moolenaar if (ns8250->mcr & MCR_DTR) 45828710806SPoul-Henning Kamp sc->sc_hwsig |= SER_DTR; 45927d5dc18SMarcel Moolenaar if (ns8250->mcr & MCR_RTS) 46028710806SPoul-Henning Kamp sc->sc_hwsig |= SER_RTS; 46127d5dc18SMarcel Moolenaar ns8250_bus_getsig(sc); 46227d5dc18SMarcel Moolenaar 46327d5dc18SMarcel Moolenaar ns8250_clrint(bas); 4640aefb0a6SBenno Rice ns8250->ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 4650aefb0a6SBenno Rice ns8250->ier |= ns8250->ier_rxbits; 46627d5dc18SMarcel Moolenaar uart_setreg(bas, REG_IER, ns8250->ier); 46727d5dc18SMarcel Moolenaar uart_barrier(bas); 4680aefb0a6SBenno Rice 4694fc49975SMarcel Moolenaar /* 4704fc49975SMarcel Moolenaar * Timing of the H/W access was changed with r253161 of uart_core.c 4714fc49975SMarcel Moolenaar * It has been observed that an ITE IT8513E would signal a break 4724fc49975SMarcel Moolenaar * condition with pretty much every character it received, unless 4734fc49975SMarcel Moolenaar * it had enough time to settle between ns8250_bus_attach() and 4744fc49975SMarcel Moolenaar * ns8250_bus_ipend() -- which it accidentally had before r253161. 4754fc49975SMarcel Moolenaar * It's not understood why the UART chip behaves this way and it 4764fc49975SMarcel Moolenaar * could very well be that the DELAY make the H/W work in the same 4774fc49975SMarcel Moolenaar * accidental manner as before. More analysis is warranted, but 4784fc49975SMarcel Moolenaar * at least now we fixed a known regression. 4794fc49975SMarcel Moolenaar */ 48040a827b6SMarcel Moolenaar DELAY(200); 48127d5dc18SMarcel Moolenaar return (0); 48227d5dc18SMarcel Moolenaar } 48327d5dc18SMarcel Moolenaar 484167cb33fSIan Lepore int 48527d5dc18SMarcel Moolenaar ns8250_bus_detach(struct uart_softc *sc) 48627d5dc18SMarcel Moolenaar { 4870aefb0a6SBenno Rice struct ns8250_softc *ns8250; 48827d5dc18SMarcel Moolenaar struct uart_bas *bas; 48958957d87SBenno Rice u_char ier; 49027d5dc18SMarcel Moolenaar 4910aefb0a6SBenno Rice ns8250 = (struct ns8250_softc *)sc; 49227d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 4930aefb0a6SBenno Rice ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 49458957d87SBenno Rice uart_setreg(bas, REG_IER, ier); 49527d5dc18SMarcel Moolenaar uart_barrier(bas); 49627d5dc18SMarcel Moolenaar ns8250_clrint(bas); 49727d5dc18SMarcel Moolenaar return (0); 49827d5dc18SMarcel Moolenaar } 49927d5dc18SMarcel Moolenaar 500167cb33fSIan Lepore int 50127d5dc18SMarcel Moolenaar ns8250_bus_flush(struct uart_softc *sc, int what) 50227d5dc18SMarcel Moolenaar { 50327d5dc18SMarcel Moolenaar struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 50427d5dc18SMarcel Moolenaar struct uart_bas *bas; 50506287620SMarcel Moolenaar int error; 50627d5dc18SMarcel Moolenaar 50727d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 5088af03381SMarcel Moolenaar uart_lock(sc->sc_hwmtx); 5098d1289feSMarcel Moolenaar if (sc->sc_rxfifosz > 1) { 51027d5dc18SMarcel Moolenaar ns8250_flush(bas, what); 51127d5dc18SMarcel Moolenaar uart_setreg(bas, REG_FCR, ns8250->fcr); 51227d5dc18SMarcel Moolenaar uart_barrier(bas); 51306287620SMarcel Moolenaar error = 0; 51406287620SMarcel Moolenaar } else 51506287620SMarcel Moolenaar error = ns8250_drain(bas, what); 5168af03381SMarcel Moolenaar uart_unlock(sc->sc_hwmtx); 51706287620SMarcel Moolenaar return (error); 51827d5dc18SMarcel Moolenaar } 51927d5dc18SMarcel Moolenaar 520167cb33fSIan Lepore int 52127d5dc18SMarcel Moolenaar ns8250_bus_getsig(struct uart_softc *sc) 52227d5dc18SMarcel Moolenaar { 52327d5dc18SMarcel Moolenaar uint32_t new, old, sig; 52427d5dc18SMarcel Moolenaar uint8_t msr; 52527d5dc18SMarcel Moolenaar 52627d5dc18SMarcel Moolenaar do { 52727d5dc18SMarcel Moolenaar old = sc->sc_hwsig; 52827d5dc18SMarcel Moolenaar sig = old; 5298af03381SMarcel Moolenaar uart_lock(sc->sc_hwmtx); 53027d5dc18SMarcel Moolenaar msr = uart_getreg(&sc->sc_bas, REG_MSR); 5318af03381SMarcel Moolenaar uart_unlock(sc->sc_hwmtx); 53228710806SPoul-Henning Kamp SIGCHG(msr & MSR_DSR, sig, SER_DSR, SER_DDSR); 53328710806SPoul-Henning Kamp SIGCHG(msr & MSR_CTS, sig, SER_CTS, SER_DCTS); 53428710806SPoul-Henning Kamp SIGCHG(msr & MSR_DCD, sig, SER_DCD, SER_DDCD); 53528710806SPoul-Henning Kamp SIGCHG(msr & MSR_RI, sig, SER_RI, SER_DRI); 536ea549414SMarcel Moolenaar new = sig & ~SER_MASK_DELTA; 53727d5dc18SMarcel Moolenaar } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 53827d5dc18SMarcel Moolenaar return (sig); 53927d5dc18SMarcel Moolenaar } 54027d5dc18SMarcel Moolenaar 541167cb33fSIan Lepore int 54227d5dc18SMarcel Moolenaar ns8250_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) 54327d5dc18SMarcel Moolenaar { 54427d5dc18SMarcel Moolenaar struct uart_bas *bas; 545bfa307a3SMarcel Moolenaar int baudrate, divisor, error; 54684c7b427SMarcel Moolenaar uint8_t efr, lcr; 54727d5dc18SMarcel Moolenaar 54827d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 54906287620SMarcel Moolenaar error = 0; 5508af03381SMarcel Moolenaar uart_lock(sc->sc_hwmtx); 55127d5dc18SMarcel Moolenaar switch (request) { 55227d5dc18SMarcel Moolenaar case UART_IOCTL_BREAK: 55327d5dc18SMarcel Moolenaar lcr = uart_getreg(bas, REG_LCR); 55427d5dc18SMarcel Moolenaar if (data) 55527d5dc18SMarcel Moolenaar lcr |= LCR_SBREAK; 55627d5dc18SMarcel Moolenaar else 55727d5dc18SMarcel Moolenaar lcr &= ~LCR_SBREAK; 55827d5dc18SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr); 55927d5dc18SMarcel Moolenaar uart_barrier(bas); 56027d5dc18SMarcel Moolenaar break; 56184c7b427SMarcel Moolenaar case UART_IOCTL_IFLOW: 56284c7b427SMarcel Moolenaar lcr = uart_getreg(bas, REG_LCR); 56384c7b427SMarcel Moolenaar uart_barrier(bas); 56484c7b427SMarcel Moolenaar uart_setreg(bas, REG_LCR, 0xbf); 56584c7b427SMarcel Moolenaar uart_barrier(bas); 56684c7b427SMarcel Moolenaar efr = uart_getreg(bas, REG_EFR); 56784c7b427SMarcel Moolenaar if (data) 56884c7b427SMarcel Moolenaar efr |= EFR_RTS; 56984c7b427SMarcel Moolenaar else 57084c7b427SMarcel Moolenaar efr &= ~EFR_RTS; 57184c7b427SMarcel Moolenaar uart_setreg(bas, REG_EFR, efr); 57284c7b427SMarcel Moolenaar uart_barrier(bas); 57384c7b427SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr); 57484c7b427SMarcel Moolenaar uart_barrier(bas); 57584c7b427SMarcel Moolenaar break; 57684c7b427SMarcel Moolenaar case UART_IOCTL_OFLOW: 57784c7b427SMarcel Moolenaar lcr = uart_getreg(bas, REG_LCR); 57884c7b427SMarcel Moolenaar uart_barrier(bas); 57984c7b427SMarcel Moolenaar uart_setreg(bas, REG_LCR, 0xbf); 58084c7b427SMarcel Moolenaar uart_barrier(bas); 58184c7b427SMarcel Moolenaar efr = uart_getreg(bas, REG_EFR); 58284c7b427SMarcel Moolenaar if (data) 58384c7b427SMarcel Moolenaar efr |= EFR_CTS; 58484c7b427SMarcel Moolenaar else 58584c7b427SMarcel Moolenaar efr &= ~EFR_CTS; 58684c7b427SMarcel Moolenaar uart_setreg(bas, REG_EFR, efr); 58784c7b427SMarcel Moolenaar uart_barrier(bas); 58884c7b427SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr); 58984c7b427SMarcel Moolenaar uart_barrier(bas); 59084c7b427SMarcel Moolenaar break; 591d8518925SMarcel Moolenaar case UART_IOCTL_BAUD: 592d8518925SMarcel Moolenaar lcr = uart_getreg(bas, REG_LCR); 593d8518925SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 594d8518925SMarcel Moolenaar uart_barrier(bas); 59558957d87SBenno Rice divisor = uart_getreg(bas, REG_DLL) | 59658957d87SBenno Rice (uart_getreg(bas, REG_DLH) << 8); 597d8518925SMarcel Moolenaar uart_barrier(bas); 598d8518925SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr); 599d8518925SMarcel Moolenaar uart_barrier(bas); 600bfa307a3SMarcel Moolenaar baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0; 601bfa307a3SMarcel Moolenaar if (baudrate > 0) 602bfa307a3SMarcel Moolenaar *(int*)data = baudrate; 603bfa307a3SMarcel Moolenaar else 604bfa307a3SMarcel Moolenaar error = ENXIO; 605d8518925SMarcel Moolenaar break; 60627d5dc18SMarcel Moolenaar default: 60706287620SMarcel Moolenaar error = EINVAL; 60806287620SMarcel Moolenaar break; 60927d5dc18SMarcel Moolenaar } 6108af03381SMarcel Moolenaar uart_unlock(sc->sc_hwmtx); 61106287620SMarcel Moolenaar return (error); 61227d5dc18SMarcel Moolenaar } 61327d5dc18SMarcel Moolenaar 614167cb33fSIan Lepore int 61527d5dc18SMarcel Moolenaar ns8250_bus_ipend(struct uart_softc *sc) 61627d5dc18SMarcel Moolenaar { 61727d5dc18SMarcel Moolenaar struct uart_bas *bas; 61811e55f91SOlivier Houchard struct ns8250_softc *ns8250; 61927d5dc18SMarcel Moolenaar int ipend; 62027d5dc18SMarcel Moolenaar uint8_t iir, lsr; 62127d5dc18SMarcel Moolenaar 62211e55f91SOlivier Houchard ns8250 = (struct ns8250_softc *)sc; 62327d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 6248af03381SMarcel Moolenaar uart_lock(sc->sc_hwmtx); 62527d5dc18SMarcel Moolenaar iir = uart_getreg(bas, REG_IIR); 626ac4adddfSGanbold Tsagaankhuu 627ac4adddfSGanbold Tsagaankhuu if (ns8250->busy_detect && (iir & IIR_BUSY) == IIR_BUSY) { 628ac4adddfSGanbold Tsagaankhuu (void)uart_getreg(bas, DW_REG_USR); 629ac4adddfSGanbold Tsagaankhuu uart_unlock(sc->sc_hwmtx); 630ac4adddfSGanbold Tsagaankhuu return (0); 631ac4adddfSGanbold Tsagaankhuu } 63206287620SMarcel Moolenaar if (iir & IIR_NOPEND) { 6338af03381SMarcel Moolenaar uart_unlock(sc->sc_hwmtx); 63427d5dc18SMarcel Moolenaar return (0); 63506287620SMarcel Moolenaar } 63627d5dc18SMarcel Moolenaar ipend = 0; 63727d5dc18SMarcel Moolenaar if (iir & IIR_RXRDY) { 63827d5dc18SMarcel Moolenaar lsr = uart_getreg(bas, REG_LSR); 63927d5dc18SMarcel Moolenaar if (lsr & LSR_OE) 6402d511805SMarcel Moolenaar ipend |= SER_INT_OVERRUN; 64127d5dc18SMarcel Moolenaar if (lsr & LSR_BI) 6422d511805SMarcel Moolenaar ipend |= SER_INT_BREAK; 64327d5dc18SMarcel Moolenaar if (lsr & LSR_RXRDY) 6442d511805SMarcel Moolenaar ipend |= SER_INT_RXREADY; 64527d5dc18SMarcel Moolenaar } else { 64611e55f91SOlivier Houchard if (iir & IIR_TXRDY) { 6472d511805SMarcel Moolenaar ipend |= SER_INT_TXIDLE; 64811e55f91SOlivier Houchard uart_setreg(bas, REG_IER, ns8250->ier); 64911e55f91SOlivier Houchard } else 6502d511805SMarcel Moolenaar ipend |= SER_INT_SIGCHG; 65127d5dc18SMarcel Moolenaar } 652d7ae5af5SMarcel Moolenaar if (ipend == 0) 653d7ae5af5SMarcel Moolenaar ns8250_clrint(bas); 654d7ae5af5SMarcel Moolenaar uart_unlock(sc->sc_hwmtx); 655f6ffc3c2SMarius Strobl return (ipend); 65627d5dc18SMarcel Moolenaar } 65727d5dc18SMarcel Moolenaar 658167cb33fSIan Lepore int 65927d5dc18SMarcel Moolenaar ns8250_bus_param(struct uart_softc *sc, int baudrate, int databits, 66027d5dc18SMarcel Moolenaar int stopbits, int parity) 66127d5dc18SMarcel Moolenaar { 66249e368acSZbigniew Bodek struct ns8250_softc *ns8250; 66327d5dc18SMarcel Moolenaar struct uart_bas *bas; 66449e368acSZbigniew Bodek int error, limit; 66527d5dc18SMarcel Moolenaar 66649e368acSZbigniew Bodek ns8250 = (struct ns8250_softc*)sc; 66727d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 6688af03381SMarcel Moolenaar uart_lock(sc->sc_hwmtx); 66949e368acSZbigniew Bodek /* 67049e368acSZbigniew Bodek * When using DW UART with BUSY detection it is necessary to wait 67149e368acSZbigniew Bodek * until all serial transfers are finished before manipulating the 67249e368acSZbigniew Bodek * line control. LCR will not be affected when UART is busy. 67349e368acSZbigniew Bodek */ 67449e368acSZbigniew Bodek if (ns8250->busy_detect != 0) { 67549e368acSZbigniew Bodek /* 67649e368acSZbigniew Bodek * Pick an arbitrary high limit to avoid getting stuck in 67749e368acSZbigniew Bodek * an infinite loop in case when the hardware is broken. 67849e368acSZbigniew Bodek */ 67949e368acSZbigniew Bodek limit = 10 * 1024; 68049e368acSZbigniew Bodek while (((uart_getreg(bas, DW_REG_USR) & USR_BUSY) != 0) && 68149e368acSZbigniew Bodek --limit) 68249e368acSZbigniew Bodek DELAY(4); 68349e368acSZbigniew Bodek 68449e368acSZbigniew Bodek if (limit <= 0) { 68549e368acSZbigniew Bodek /* UART appears to be stuck */ 68649e368acSZbigniew Bodek uart_unlock(sc->sc_hwmtx); 68749e368acSZbigniew Bodek return (EIO); 68849e368acSZbigniew Bodek } 68949e368acSZbigniew Bodek } 69049e368acSZbigniew Bodek 69106287620SMarcel Moolenaar error = ns8250_param(bas, baudrate, databits, stopbits, parity); 6928af03381SMarcel Moolenaar uart_unlock(sc->sc_hwmtx); 69306287620SMarcel Moolenaar return (error); 69427d5dc18SMarcel Moolenaar } 69527d5dc18SMarcel Moolenaar 696167cb33fSIan Lepore int 69727d5dc18SMarcel Moolenaar ns8250_bus_probe(struct uart_softc *sc) 69827d5dc18SMarcel Moolenaar { 6990aefb0a6SBenno Rice struct ns8250_softc *ns8250; 70027d5dc18SMarcel Moolenaar struct uart_bas *bas; 70127d5dc18SMarcel Moolenaar int count, delay, error, limit; 70258957d87SBenno Rice uint8_t lsr, mcr, ier; 70327d5dc18SMarcel Moolenaar 7040aefb0a6SBenno Rice ns8250 = (struct ns8250_softc *)sc; 70527d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 70627d5dc18SMarcel Moolenaar 70727d5dc18SMarcel Moolenaar error = ns8250_probe(bas); 70827d5dc18SMarcel Moolenaar if (error) 70927d5dc18SMarcel Moolenaar return (error); 71027d5dc18SMarcel Moolenaar 71127d5dc18SMarcel Moolenaar mcr = MCR_IE; 71227d5dc18SMarcel Moolenaar if (sc->sc_sysdev == NULL) { 71327d5dc18SMarcel Moolenaar /* By using ns8250_init() we also set DTR and RTS. */ 714d902fb71SMarcel Moolenaar ns8250_init(bas, 115200, 8, 1, UART_PARITY_NONE); 71527d5dc18SMarcel Moolenaar } else 71627d5dc18SMarcel Moolenaar mcr |= MCR_DTR | MCR_RTS; 71727d5dc18SMarcel Moolenaar 71827d5dc18SMarcel Moolenaar error = ns8250_drain(bas, UART_DRAIN_TRANSMITTER); 71927d5dc18SMarcel Moolenaar if (error) 72027d5dc18SMarcel Moolenaar return (error); 72127d5dc18SMarcel Moolenaar 72227d5dc18SMarcel Moolenaar /* 72327d5dc18SMarcel Moolenaar * Set loopback mode. This avoids having garbage on the wire and 72427d5dc18SMarcel Moolenaar * also allows us send and receive data. We set DTR and RTS to 72527d5dc18SMarcel Moolenaar * avoid the possibility that automatic flow-control prevents 72689eef2deSThomas Moestl * any data from being sent. 72727d5dc18SMarcel Moolenaar */ 72889eef2deSThomas Moestl uart_setreg(bas, REG_MCR, MCR_LOOPBACK | MCR_IE | MCR_DTR | MCR_RTS); 72927d5dc18SMarcel Moolenaar uart_barrier(bas); 73027d5dc18SMarcel Moolenaar 73127d5dc18SMarcel Moolenaar /* 73227d5dc18SMarcel Moolenaar * Enable FIFOs. And check that the UART has them. If not, we're 73389eef2deSThomas Moestl * done. Since this is the first time we enable the FIFOs, we reset 73489eef2deSThomas Moestl * them. 73527d5dc18SMarcel Moolenaar */ 73627d5dc18SMarcel Moolenaar uart_setreg(bas, REG_FCR, FCR_ENABLE); 73727d5dc18SMarcel Moolenaar uart_barrier(bas); 7388d1289feSMarcel Moolenaar if (!(uart_getreg(bas, REG_IIR) & IIR_FIFO_MASK)) { 73927d5dc18SMarcel Moolenaar /* 74027d5dc18SMarcel Moolenaar * NS16450 or INS8250. We don't bother to differentiate 74127d5dc18SMarcel Moolenaar * between them. They're too old to be interesting. 74227d5dc18SMarcel Moolenaar */ 74327d5dc18SMarcel Moolenaar uart_setreg(bas, REG_MCR, mcr); 74427d5dc18SMarcel Moolenaar uart_barrier(bas); 7458d1289feSMarcel Moolenaar sc->sc_rxfifosz = sc->sc_txfifosz = 1; 74627d5dc18SMarcel Moolenaar device_set_desc(sc->sc_dev, "8250 or 16450 or compatible"); 74727d5dc18SMarcel Moolenaar return (0); 74827d5dc18SMarcel Moolenaar } 74927d5dc18SMarcel Moolenaar 75089eef2deSThomas Moestl uart_setreg(bas, REG_FCR, FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST); 75127d5dc18SMarcel Moolenaar uart_barrier(bas); 75227d5dc18SMarcel Moolenaar 75327d5dc18SMarcel Moolenaar count = 0; 75427d5dc18SMarcel Moolenaar delay = ns8250_delay(bas); 75527d5dc18SMarcel Moolenaar 75627d5dc18SMarcel Moolenaar /* We have FIFOs. Drain the transmitter and receiver. */ 75727d5dc18SMarcel Moolenaar error = ns8250_drain(bas, UART_DRAIN_RECEIVER|UART_DRAIN_TRANSMITTER); 75827d5dc18SMarcel Moolenaar if (error) { 75927d5dc18SMarcel Moolenaar uart_setreg(bas, REG_MCR, mcr); 76027d5dc18SMarcel Moolenaar uart_setreg(bas, REG_FCR, 0); 76127d5dc18SMarcel Moolenaar uart_barrier(bas); 76227d5dc18SMarcel Moolenaar goto describe; 76327d5dc18SMarcel Moolenaar } 76427d5dc18SMarcel Moolenaar 76527d5dc18SMarcel Moolenaar /* 76627d5dc18SMarcel Moolenaar * We should have a sufficiently clean "pipe" to determine the 76727d5dc18SMarcel Moolenaar * size of the FIFOs. We send as much characters as is reasonable 7686bccea7cSRebecca Cran * and wait for the overflow bit in the LSR register to be 76989eef2deSThomas Moestl * asserted, counting the characters as we send them. Based on 77089eef2deSThomas Moestl * that count we know the FIFO size. 77127d5dc18SMarcel Moolenaar */ 77289eef2deSThomas Moestl do { 77327d5dc18SMarcel Moolenaar uart_setreg(bas, REG_DATA, 0); 77427d5dc18SMarcel Moolenaar uart_barrier(bas); 77527d5dc18SMarcel Moolenaar count++; 77627d5dc18SMarcel Moolenaar 77727d5dc18SMarcel Moolenaar limit = 30; 77889eef2deSThomas Moestl lsr = 0; 77989eef2deSThomas Moestl /* 78089eef2deSThomas Moestl * LSR bits are cleared upon read, so we must accumulate 78189eef2deSThomas Moestl * them to be able to test LSR_OE below. 78289eef2deSThomas Moestl */ 78389eef2deSThomas Moestl while (((lsr |= uart_getreg(bas, REG_LSR)) & LSR_TEMT) == 0 && 78489eef2deSThomas Moestl --limit) 78527d5dc18SMarcel Moolenaar DELAY(delay); 78627d5dc18SMarcel Moolenaar if (limit == 0) { 7870aefb0a6SBenno Rice ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 78858957d87SBenno Rice uart_setreg(bas, REG_IER, ier); 78927d5dc18SMarcel Moolenaar uart_setreg(bas, REG_MCR, mcr); 79027d5dc18SMarcel Moolenaar uart_setreg(bas, REG_FCR, 0); 79127d5dc18SMarcel Moolenaar uart_barrier(bas); 79227d5dc18SMarcel Moolenaar count = 0; 79327d5dc18SMarcel Moolenaar goto describe; 79427d5dc18SMarcel Moolenaar } 795d882cf92SMarcel Moolenaar } while ((lsr & LSR_OE) == 0 && count < 130); 79689eef2deSThomas Moestl count--; 79727d5dc18SMarcel Moolenaar 79827d5dc18SMarcel Moolenaar uart_setreg(bas, REG_MCR, mcr); 79927d5dc18SMarcel Moolenaar 80027d5dc18SMarcel Moolenaar /* Reset FIFOs. */ 80127d5dc18SMarcel Moolenaar ns8250_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 80227d5dc18SMarcel Moolenaar 80327d5dc18SMarcel Moolenaar describe: 80489eef2deSThomas Moestl if (count >= 14 && count <= 16) { 80527d5dc18SMarcel Moolenaar sc->sc_rxfifosz = 16; 80627d5dc18SMarcel Moolenaar device_set_desc(sc->sc_dev, "16550 or compatible"); 80789eef2deSThomas Moestl } else if (count >= 28 && count <= 32) { 80827d5dc18SMarcel Moolenaar sc->sc_rxfifosz = 32; 80927d5dc18SMarcel Moolenaar device_set_desc(sc->sc_dev, "16650 or compatible"); 81089eef2deSThomas Moestl } else if (count >= 56 && count <= 64) { 81127d5dc18SMarcel Moolenaar sc->sc_rxfifosz = 64; 81227d5dc18SMarcel Moolenaar device_set_desc(sc->sc_dev, "16750 or compatible"); 81389eef2deSThomas Moestl } else if (count >= 112 && count <= 128) { 81427d5dc18SMarcel Moolenaar sc->sc_rxfifosz = 128; 81527d5dc18SMarcel Moolenaar device_set_desc(sc->sc_dev, "16950 or compatible"); 81627d5dc18SMarcel Moolenaar } else { 817c21e0da2SMarcel Moolenaar sc->sc_rxfifosz = 16; 81827d5dc18SMarcel Moolenaar device_set_desc(sc->sc_dev, 81927d5dc18SMarcel Moolenaar "Non-standard ns8250 class UART with FIFOs"); 82027d5dc18SMarcel Moolenaar } 82127d5dc18SMarcel Moolenaar 82227d5dc18SMarcel Moolenaar /* 82327d5dc18SMarcel Moolenaar * Force the Tx FIFO size to 16 bytes for now. We don't program the 82427d5dc18SMarcel Moolenaar * Tx trigger. Also, we assume that all data has been sent when the 82527d5dc18SMarcel Moolenaar * interrupt happens. 82627d5dc18SMarcel Moolenaar */ 82727d5dc18SMarcel Moolenaar sc->sc_txfifosz = 16; 82827d5dc18SMarcel Moolenaar 829dc70e792SMarcel Moolenaar #if 0 830dc70e792SMarcel Moolenaar /* 831dc70e792SMarcel Moolenaar * XXX there are some issues related to hardware flow control and 832dc70e792SMarcel Moolenaar * it's likely that uart(4) is the cause. This basicly needs more 833dc70e792SMarcel Moolenaar * investigation, but we avoid using for hardware flow control 834dc70e792SMarcel Moolenaar * until then. 835dc70e792SMarcel Moolenaar */ 83684c7b427SMarcel Moolenaar /* 16650s or higher have automatic flow control. */ 83784c7b427SMarcel Moolenaar if (sc->sc_rxfifosz > 16) { 83884c7b427SMarcel Moolenaar sc->sc_hwiflow = 1; 83984c7b427SMarcel Moolenaar sc->sc_hwoflow = 1; 84084c7b427SMarcel Moolenaar } 841dc70e792SMarcel Moolenaar #endif 84284c7b427SMarcel Moolenaar 84327d5dc18SMarcel Moolenaar return (0); 84427d5dc18SMarcel Moolenaar } 84527d5dc18SMarcel Moolenaar 846167cb33fSIan Lepore int 84727d5dc18SMarcel Moolenaar ns8250_bus_receive(struct uart_softc *sc) 84827d5dc18SMarcel Moolenaar { 84927d5dc18SMarcel Moolenaar struct uart_bas *bas; 85027d5dc18SMarcel Moolenaar int xc; 85127d5dc18SMarcel Moolenaar uint8_t lsr; 85227d5dc18SMarcel Moolenaar 85327d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 8548af03381SMarcel Moolenaar uart_lock(sc->sc_hwmtx); 85527d5dc18SMarcel Moolenaar lsr = uart_getreg(bas, REG_LSR); 85644ed791bSMarcel Moolenaar while (lsr & LSR_RXRDY) { 85744ed791bSMarcel Moolenaar if (uart_rx_full(sc)) { 85844ed791bSMarcel Moolenaar sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; 85927d5dc18SMarcel Moolenaar break; 86044ed791bSMarcel Moolenaar } 86127d5dc18SMarcel Moolenaar xc = uart_getreg(bas, REG_DATA); 86227d5dc18SMarcel Moolenaar if (lsr & LSR_FE) 86327d5dc18SMarcel Moolenaar xc |= UART_STAT_FRAMERR; 86427d5dc18SMarcel Moolenaar if (lsr & LSR_PE) 86527d5dc18SMarcel Moolenaar xc |= UART_STAT_PARERR; 86627d5dc18SMarcel Moolenaar uart_rx_put(sc, xc); 86744ed791bSMarcel Moolenaar lsr = uart_getreg(bas, REG_LSR); 86844ed791bSMarcel Moolenaar } 86944ed791bSMarcel Moolenaar /* Discard everything left in the Rx FIFO. */ 87044ed791bSMarcel Moolenaar while (lsr & LSR_RXRDY) { 87144ed791bSMarcel Moolenaar (void)uart_getreg(bas, REG_DATA); 87244ed791bSMarcel Moolenaar uart_barrier(bas); 87344ed791bSMarcel Moolenaar lsr = uart_getreg(bas, REG_LSR); 87427d5dc18SMarcel Moolenaar } 8758af03381SMarcel Moolenaar uart_unlock(sc->sc_hwmtx); 87627d5dc18SMarcel Moolenaar return (0); 87727d5dc18SMarcel Moolenaar } 87827d5dc18SMarcel Moolenaar 879167cb33fSIan Lepore int 88027d5dc18SMarcel Moolenaar ns8250_bus_setsig(struct uart_softc *sc, int sig) 88127d5dc18SMarcel Moolenaar { 88227d5dc18SMarcel Moolenaar struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 88327d5dc18SMarcel Moolenaar struct uart_bas *bas; 88427d5dc18SMarcel Moolenaar uint32_t new, old; 88527d5dc18SMarcel Moolenaar 88627d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 88727d5dc18SMarcel Moolenaar do { 88827d5dc18SMarcel Moolenaar old = sc->sc_hwsig; 88927d5dc18SMarcel Moolenaar new = old; 89028710806SPoul-Henning Kamp if (sig & SER_DDTR) { 89128710806SPoul-Henning Kamp SIGCHG(sig & SER_DTR, new, SER_DTR, 89228710806SPoul-Henning Kamp SER_DDTR); 89327d5dc18SMarcel Moolenaar } 89428710806SPoul-Henning Kamp if (sig & SER_DRTS) { 89528710806SPoul-Henning Kamp SIGCHG(sig & SER_RTS, new, SER_RTS, 89628710806SPoul-Henning Kamp SER_DRTS); 89727d5dc18SMarcel Moolenaar } 89827d5dc18SMarcel Moolenaar } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 8998af03381SMarcel Moolenaar uart_lock(sc->sc_hwmtx); 90027d5dc18SMarcel Moolenaar ns8250->mcr &= ~(MCR_DTR|MCR_RTS); 90128710806SPoul-Henning Kamp if (new & SER_DTR) 90227d5dc18SMarcel Moolenaar ns8250->mcr |= MCR_DTR; 90328710806SPoul-Henning Kamp if (new & SER_RTS) 90427d5dc18SMarcel Moolenaar ns8250->mcr |= MCR_RTS; 90527d5dc18SMarcel Moolenaar uart_setreg(bas, REG_MCR, ns8250->mcr); 90627d5dc18SMarcel Moolenaar uart_barrier(bas); 9078af03381SMarcel Moolenaar uart_unlock(sc->sc_hwmtx); 90827d5dc18SMarcel Moolenaar return (0); 90927d5dc18SMarcel Moolenaar } 91027d5dc18SMarcel Moolenaar 911167cb33fSIan Lepore int 91227d5dc18SMarcel Moolenaar ns8250_bus_transmit(struct uart_softc *sc) 91327d5dc18SMarcel Moolenaar { 91427d5dc18SMarcel Moolenaar struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 91527d5dc18SMarcel Moolenaar struct uart_bas *bas; 91627d5dc18SMarcel Moolenaar int i; 91727d5dc18SMarcel Moolenaar 91827d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 9198af03381SMarcel Moolenaar uart_lock(sc->sc_hwmtx); 92027d5dc18SMarcel Moolenaar while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0) 92127d5dc18SMarcel Moolenaar ; 92227d5dc18SMarcel Moolenaar uart_setreg(bas, REG_IER, ns8250->ier | IER_ETXRDY); 92327d5dc18SMarcel Moolenaar uart_barrier(bas); 92427d5dc18SMarcel Moolenaar for (i = 0; i < sc->sc_txdatasz; i++) { 92527d5dc18SMarcel Moolenaar uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]); 92627d5dc18SMarcel Moolenaar uart_barrier(bas); 92727d5dc18SMarcel Moolenaar } 9281c60b24bSColin Percival if (broken_txfifo) 9291c60b24bSColin Percival ns8250_drain(bas, UART_DRAIN_TRANSMITTER); 9301c60b24bSColin Percival else 93127d5dc18SMarcel Moolenaar sc->sc_txbusy = 1; 9328af03381SMarcel Moolenaar uart_unlock(sc->sc_hwmtx); 9331c60b24bSColin Percival if (broken_txfifo) 9341c60b24bSColin Percival uart_sched_softih(sc, SER_INT_TXIDLE); 93527d5dc18SMarcel Moolenaar return (0); 93627d5dc18SMarcel Moolenaar } 937d76a1ef4SWarner Losh 938d76a1ef4SWarner Losh void 939d76a1ef4SWarner Losh ns8250_bus_grab(struct uart_softc *sc) 940d76a1ef4SWarner Losh { 941d76a1ef4SWarner Losh struct uart_bas *bas = &sc->sc_bas; 942caf6d6b4SOlivier Houchard struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 9438bc9a079SOlivier Houchard u_char ier; 944d76a1ef4SWarner Losh 945d76a1ef4SWarner Losh /* 946d76a1ef4SWarner Losh * turn off all interrupts to enter polling mode. Leave the 947d76a1ef4SWarner Losh * saved mask alone. We'll restore whatever it was in ungrab. 948d76a1ef4SWarner Losh * All pending interupt signals are reset when IER is set to 0. 949d76a1ef4SWarner Losh */ 950d76a1ef4SWarner Losh uart_lock(sc->sc_hwmtx); 9518bc9a079SOlivier Houchard ier = uart_getreg(bas, REG_IER); 9528bc9a079SOlivier Houchard uart_setreg(bas, REG_IER, ier & ns8250->ier_mask); 953d76a1ef4SWarner Losh uart_barrier(bas); 954d76a1ef4SWarner Losh uart_unlock(sc->sc_hwmtx); 955d76a1ef4SWarner Losh } 956d76a1ef4SWarner Losh 957d76a1ef4SWarner Losh void 958d76a1ef4SWarner Losh ns8250_bus_ungrab(struct uart_softc *sc) 959d76a1ef4SWarner Losh { 960d76a1ef4SWarner Losh struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 961d76a1ef4SWarner Losh struct uart_bas *bas = &sc->sc_bas; 962d76a1ef4SWarner Losh 963d76a1ef4SWarner Losh /* 964d76a1ef4SWarner Losh * Restore previous interrupt mask 965d76a1ef4SWarner Losh */ 966d76a1ef4SWarner Losh uart_lock(sc->sc_hwmtx); 967d76a1ef4SWarner Losh uart_setreg(bas, REG_IER, ns8250->ier); 968d76a1ef4SWarner Losh uart_barrier(bas); 969d76a1ef4SWarner Losh uart_unlock(sc->sc_hwmtx); 970d76a1ef4SWarner Losh } 971