1098ca2bdSWarner Losh /*- 227d5dc18SMarcel Moolenaar * Copyright (c) 2003 Marcel Moolenaar 327d5dc18SMarcel Moolenaar * All rights reserved. 427d5dc18SMarcel Moolenaar * 527d5dc18SMarcel Moolenaar * Redistribution and use in source and binary forms, with or without 627d5dc18SMarcel Moolenaar * modification, are permitted provided that the following conditions 727d5dc18SMarcel Moolenaar * are met: 827d5dc18SMarcel Moolenaar * 927d5dc18SMarcel Moolenaar * 1. Redistributions of source code must retain the above copyright 1027d5dc18SMarcel Moolenaar * notice, this list of conditions and the following disclaimer. 1127d5dc18SMarcel Moolenaar * 2. Redistributions in binary form must reproduce the above copyright 1227d5dc18SMarcel Moolenaar * notice, this list of conditions and the following disclaimer in the 1327d5dc18SMarcel Moolenaar * documentation and/or other materials provided with the distribution. 1427d5dc18SMarcel Moolenaar * 1527d5dc18SMarcel Moolenaar * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 1627d5dc18SMarcel Moolenaar * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 1727d5dc18SMarcel Moolenaar * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 1827d5dc18SMarcel Moolenaar * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 1927d5dc18SMarcel Moolenaar * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 2027d5dc18SMarcel Moolenaar * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2127d5dc18SMarcel Moolenaar * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2227d5dc18SMarcel Moolenaar * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2327d5dc18SMarcel Moolenaar * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 2427d5dc18SMarcel Moolenaar * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2527d5dc18SMarcel Moolenaar */ 2627d5dc18SMarcel Moolenaar 27ac4adddfSGanbold Tsagaankhuu #include "opt_platform.h" 28e0fe7c95SAdrian Chadd #include "opt_uart.h" 29ac4adddfSGanbold Tsagaankhuu 3027d5dc18SMarcel Moolenaar #include <sys/cdefs.h> 3127d5dc18SMarcel Moolenaar __FBSDID("$FreeBSD$"); 3227d5dc18SMarcel Moolenaar 3327d5dc18SMarcel Moolenaar #include <sys/param.h> 3427d5dc18SMarcel Moolenaar #include <sys/systm.h> 3527d5dc18SMarcel Moolenaar #include <sys/bus.h> 3627d5dc18SMarcel Moolenaar #include <sys/conf.h> 371c60b24bSColin Percival #include <sys/kernel.h> 381c60b24bSColin Percival #include <sys/sysctl.h> 3927d5dc18SMarcel Moolenaar #include <machine/bus.h> 4027d5dc18SMarcel Moolenaar 41ac4adddfSGanbold Tsagaankhuu #ifdef FDT 42ac4adddfSGanbold Tsagaankhuu #include <dev/fdt/fdt_common.h> 43ac4adddfSGanbold Tsagaankhuu #include <dev/ofw/ofw_bus.h> 44ac4adddfSGanbold Tsagaankhuu #include <dev/ofw/ofw_bus_subr.h> 45ac4adddfSGanbold Tsagaankhuu #endif 46ac4adddfSGanbold Tsagaankhuu 4727d5dc18SMarcel Moolenaar #include <dev/uart/uart.h> 4827d5dc18SMarcel Moolenaar #include <dev/uart/uart_cpu.h> 493bb693afSIan Lepore #ifdef FDT 503bb693afSIan Lepore #include <dev/uart/uart_cpu_fdt.h> 513bb693afSIan Lepore #endif 5227d5dc18SMarcel Moolenaar #include <dev/uart/uart_bus.h> 53167cb33fSIan Lepore #include <dev/uart/uart_dev_ns8250.h> 54fdfbb3f5SIan Lepore #include <dev/uart/uart_ppstypes.h> 5576563beaSMarcel Moolenaar 5676563beaSMarcel Moolenaar #include <dev/ic/ns16550.h> 5727d5dc18SMarcel Moolenaar 5827d5dc18SMarcel Moolenaar #include "uart_if.h" 5927d5dc18SMarcel Moolenaar 6027d5dc18SMarcel Moolenaar #define DEFAULT_RCLK 1843200 6127d5dc18SMarcel Moolenaar 62e0fe7c95SAdrian Chadd /* 63e0fe7c95SAdrian Chadd * Set the default baudrate tolerance to 3.0%. 64e0fe7c95SAdrian Chadd * 65e0fe7c95SAdrian Chadd * Some embedded boards have odd reference clocks (eg 25MHz) 66e0fe7c95SAdrian Chadd * and we need to handle higher variances in the target baud rate. 67e0fe7c95SAdrian Chadd */ 68e0fe7c95SAdrian Chadd #ifndef UART_DEV_TOLERANCE_PCT 69e0fe7c95SAdrian Chadd #define UART_DEV_TOLERANCE_PCT 30 70e0fe7c95SAdrian Chadd #endif /* UART_DEV_TOLERANCE_PCT */ 71e0fe7c95SAdrian Chadd 72ac4adddfSGanbold Tsagaankhuu static int broken_txfifo = 0; 73af3b2549SHans Petter Selasky SYSCTL_INT(_hw, OID_AUTO, broken_txfifo, CTLFLAG_RWTUN, 74ac4adddfSGanbold Tsagaankhuu &broken_txfifo, 0, "UART FIFO has QEMU emulation bug"); 75ac4adddfSGanbold Tsagaankhuu 7627d5dc18SMarcel Moolenaar /* 7727d5dc18SMarcel Moolenaar * Clear pending interrupts. THRE is cleared by reading IIR. Data 7827d5dc18SMarcel Moolenaar * that may have been received gets lost here. 7927d5dc18SMarcel Moolenaar */ 8027d5dc18SMarcel Moolenaar static void 8127d5dc18SMarcel Moolenaar ns8250_clrint(struct uart_bas *bas) 8227d5dc18SMarcel Moolenaar { 83d7ae5af5SMarcel Moolenaar uint8_t iir, lsr; 8427d5dc18SMarcel Moolenaar 8527d5dc18SMarcel Moolenaar iir = uart_getreg(bas, REG_IIR); 8627d5dc18SMarcel Moolenaar while ((iir & IIR_NOPEND) == 0) { 8727d5dc18SMarcel Moolenaar iir &= IIR_IMASK; 88d7ae5af5SMarcel Moolenaar if (iir == IIR_RLS) { 89d7ae5af5SMarcel Moolenaar lsr = uart_getreg(bas, REG_LSR); 90d7ae5af5SMarcel Moolenaar if (lsr & (LSR_BI|LSR_FE|LSR_PE)) 91d7ae5af5SMarcel Moolenaar (void)uart_getreg(bas, REG_DATA); 92d7ae5af5SMarcel Moolenaar } else if (iir == IIR_RXRDY || iir == IIR_RXTOUT) 9327d5dc18SMarcel Moolenaar (void)uart_getreg(bas, REG_DATA); 9427d5dc18SMarcel Moolenaar else if (iir == IIR_MLSC) 9527d5dc18SMarcel Moolenaar (void)uart_getreg(bas, REG_MSR); 9627d5dc18SMarcel Moolenaar uart_barrier(bas); 9727d5dc18SMarcel Moolenaar iir = uart_getreg(bas, REG_IIR); 9827d5dc18SMarcel Moolenaar } 9927d5dc18SMarcel Moolenaar } 10027d5dc18SMarcel Moolenaar 10127d5dc18SMarcel Moolenaar static int 10227d5dc18SMarcel Moolenaar ns8250_delay(struct uart_bas *bas) 10327d5dc18SMarcel Moolenaar { 10427d5dc18SMarcel Moolenaar int divisor; 10527d5dc18SMarcel Moolenaar u_char lcr; 10627d5dc18SMarcel Moolenaar 10727d5dc18SMarcel Moolenaar lcr = uart_getreg(bas, REG_LCR); 10827d5dc18SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 10927d5dc18SMarcel Moolenaar uart_barrier(bas); 11058957d87SBenno Rice divisor = uart_getreg(bas, REG_DLL) | (uart_getreg(bas, REG_DLH) << 8); 11127d5dc18SMarcel Moolenaar uart_barrier(bas); 11227d5dc18SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr); 11327d5dc18SMarcel Moolenaar uart_barrier(bas); 11427d5dc18SMarcel Moolenaar 11527d5dc18SMarcel Moolenaar /* 1/10th the time to transmit 1 character (estimate). */ 116ebecffe9SMarcel Moolenaar if (divisor <= 134) 11727d5dc18SMarcel Moolenaar return (16000000 * divisor / bas->rclk); 118ebecffe9SMarcel Moolenaar return (16000 * divisor / (bas->rclk / 1000)); 11927d5dc18SMarcel Moolenaar } 12027d5dc18SMarcel Moolenaar 12127d5dc18SMarcel Moolenaar static int 12227d5dc18SMarcel Moolenaar ns8250_divisor(int rclk, int baudrate) 12327d5dc18SMarcel Moolenaar { 12427d5dc18SMarcel Moolenaar int actual_baud, divisor; 12527d5dc18SMarcel Moolenaar int error; 12627d5dc18SMarcel Moolenaar 12727d5dc18SMarcel Moolenaar if (baudrate == 0) 12827d5dc18SMarcel Moolenaar return (0); 12927d5dc18SMarcel Moolenaar 13027d5dc18SMarcel Moolenaar divisor = (rclk / (baudrate << 3) + 1) >> 1; 13127d5dc18SMarcel Moolenaar if (divisor == 0 || divisor >= 65536) 13227d5dc18SMarcel Moolenaar return (0); 13327d5dc18SMarcel Moolenaar actual_baud = rclk / (divisor << 4); 13427d5dc18SMarcel Moolenaar 13527d5dc18SMarcel Moolenaar /* 10 times error in percent: */ 13627d5dc18SMarcel Moolenaar error = ((actual_baud - baudrate) * 2000 / baudrate + 1) >> 1; 13727d5dc18SMarcel Moolenaar 138e0fe7c95SAdrian Chadd /* enforce maximum error tolerance: */ 139e0fe7c95SAdrian Chadd if (error < -UART_DEV_TOLERANCE_PCT || error > UART_DEV_TOLERANCE_PCT) 14027d5dc18SMarcel Moolenaar return (0); 14127d5dc18SMarcel Moolenaar 14227d5dc18SMarcel Moolenaar return (divisor); 14327d5dc18SMarcel Moolenaar } 14427d5dc18SMarcel Moolenaar 14527d5dc18SMarcel Moolenaar static int 14627d5dc18SMarcel Moolenaar ns8250_drain(struct uart_bas *bas, int what) 14727d5dc18SMarcel Moolenaar { 14827d5dc18SMarcel Moolenaar int delay, limit; 14927d5dc18SMarcel Moolenaar 15027d5dc18SMarcel Moolenaar delay = ns8250_delay(bas); 15127d5dc18SMarcel Moolenaar 15227d5dc18SMarcel Moolenaar if (what & UART_DRAIN_TRANSMITTER) { 15327d5dc18SMarcel Moolenaar /* 15427d5dc18SMarcel Moolenaar * Pick an arbitrary high limit to avoid getting stuck in 15527d5dc18SMarcel Moolenaar * an infinite loop when the hardware is broken. Make the 15627d5dc18SMarcel Moolenaar * limit high enough to handle large FIFOs. 15727d5dc18SMarcel Moolenaar */ 15827d5dc18SMarcel Moolenaar limit = 10*1024; 15927d5dc18SMarcel Moolenaar while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) 16027d5dc18SMarcel Moolenaar DELAY(delay); 16127d5dc18SMarcel Moolenaar if (limit == 0) { 16227d5dc18SMarcel Moolenaar /* printf("ns8250: transmitter appears stuck... "); */ 16327d5dc18SMarcel Moolenaar return (EIO); 16427d5dc18SMarcel Moolenaar } 16527d5dc18SMarcel Moolenaar } 16627d5dc18SMarcel Moolenaar 16727d5dc18SMarcel Moolenaar if (what & UART_DRAIN_RECEIVER) { 16827d5dc18SMarcel Moolenaar /* 16927d5dc18SMarcel Moolenaar * Pick an arbitrary high limit to avoid getting stuck in 17027d5dc18SMarcel Moolenaar * an infinite loop when the hardware is broken. Make the 17127d5dc18SMarcel Moolenaar * limit high enough to handle large FIFOs and integrated 17227d5dc18SMarcel Moolenaar * UARTs. The HP rx2600 for example has 3 UARTs on the 17327d5dc18SMarcel Moolenaar * management board that tend to get a lot of data send 17427d5dc18SMarcel Moolenaar * to it when the UART is first activated. 17527d5dc18SMarcel Moolenaar */ 17627d5dc18SMarcel Moolenaar limit=10*4096; 17727d5dc18SMarcel Moolenaar while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) { 17827d5dc18SMarcel Moolenaar (void)uart_getreg(bas, REG_DATA); 17927d5dc18SMarcel Moolenaar uart_barrier(bas); 18027d5dc18SMarcel Moolenaar DELAY(delay << 2); 18127d5dc18SMarcel Moolenaar } 18227d5dc18SMarcel Moolenaar if (limit == 0) { 18327d5dc18SMarcel Moolenaar /* printf("ns8250: receiver appears broken... "); */ 18427d5dc18SMarcel Moolenaar return (EIO); 18527d5dc18SMarcel Moolenaar } 18627d5dc18SMarcel Moolenaar } 18727d5dc18SMarcel Moolenaar 18827d5dc18SMarcel Moolenaar return (0); 18927d5dc18SMarcel Moolenaar } 19027d5dc18SMarcel Moolenaar 19127d5dc18SMarcel Moolenaar /* 19227d5dc18SMarcel Moolenaar * We can only flush UARTs with FIFOs. UARTs without FIFOs should be 19327d5dc18SMarcel Moolenaar * drained. WARNING: this function clobbers the FIFO setting! 19427d5dc18SMarcel Moolenaar */ 19527d5dc18SMarcel Moolenaar static void 19627d5dc18SMarcel Moolenaar ns8250_flush(struct uart_bas *bas, int what) 19727d5dc18SMarcel Moolenaar { 19827d5dc18SMarcel Moolenaar uint8_t fcr; 19927d5dc18SMarcel Moolenaar 20027d5dc18SMarcel Moolenaar fcr = FCR_ENABLE; 20127d5dc18SMarcel Moolenaar if (what & UART_FLUSH_TRANSMITTER) 20227d5dc18SMarcel Moolenaar fcr |= FCR_XMT_RST; 20327d5dc18SMarcel Moolenaar if (what & UART_FLUSH_RECEIVER) 20427d5dc18SMarcel Moolenaar fcr |= FCR_RCV_RST; 20527d5dc18SMarcel Moolenaar uart_setreg(bas, REG_FCR, fcr); 20627d5dc18SMarcel Moolenaar uart_barrier(bas); 20727d5dc18SMarcel Moolenaar } 20827d5dc18SMarcel Moolenaar 20927d5dc18SMarcel Moolenaar static int 21027d5dc18SMarcel Moolenaar ns8250_param(struct uart_bas *bas, int baudrate, int databits, int stopbits, 21127d5dc18SMarcel Moolenaar int parity) 21227d5dc18SMarcel Moolenaar { 21327d5dc18SMarcel Moolenaar int divisor; 21427d5dc18SMarcel Moolenaar uint8_t lcr; 21527d5dc18SMarcel Moolenaar 21627d5dc18SMarcel Moolenaar lcr = 0; 21727d5dc18SMarcel Moolenaar if (databits >= 8) 21827d5dc18SMarcel Moolenaar lcr |= LCR_8BITS; 21927d5dc18SMarcel Moolenaar else if (databits == 7) 22027d5dc18SMarcel Moolenaar lcr |= LCR_7BITS; 22127d5dc18SMarcel Moolenaar else if (databits == 6) 22227d5dc18SMarcel Moolenaar lcr |= LCR_6BITS; 22327d5dc18SMarcel Moolenaar else 22427d5dc18SMarcel Moolenaar lcr |= LCR_5BITS; 22527d5dc18SMarcel Moolenaar if (stopbits > 1) 22627d5dc18SMarcel Moolenaar lcr |= LCR_STOPB; 22727d5dc18SMarcel Moolenaar lcr |= parity << 3; 22827d5dc18SMarcel Moolenaar 22927d5dc18SMarcel Moolenaar /* Set baudrate. */ 23027d5dc18SMarcel Moolenaar if (baudrate > 0) { 23127d5dc18SMarcel Moolenaar divisor = ns8250_divisor(bas->rclk, baudrate); 23227d5dc18SMarcel Moolenaar if (divisor == 0) 23327d5dc18SMarcel Moolenaar return (EINVAL); 23463f8efd3SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 23563f8efd3SMarcel Moolenaar uart_barrier(bas); 23658957d87SBenno Rice uart_setreg(bas, REG_DLL, divisor & 0xff); 23758957d87SBenno Rice uart_setreg(bas, REG_DLH, (divisor >> 8) & 0xff); 23827d5dc18SMarcel Moolenaar uart_barrier(bas); 23927d5dc18SMarcel Moolenaar } 24027d5dc18SMarcel Moolenaar 24127d5dc18SMarcel Moolenaar /* Set LCR and clear DLAB. */ 24227d5dc18SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr); 24327d5dc18SMarcel Moolenaar uart_barrier(bas); 24427d5dc18SMarcel Moolenaar return (0); 24527d5dc18SMarcel Moolenaar } 24627d5dc18SMarcel Moolenaar 24727d5dc18SMarcel Moolenaar /* 24827d5dc18SMarcel Moolenaar * Low-level UART interface. 24927d5dc18SMarcel Moolenaar */ 25027d5dc18SMarcel Moolenaar static int ns8250_probe(struct uart_bas *bas); 25127d5dc18SMarcel Moolenaar static void ns8250_init(struct uart_bas *bas, int, int, int, int); 25227d5dc18SMarcel Moolenaar static void ns8250_term(struct uart_bas *bas); 25327d5dc18SMarcel Moolenaar static void ns8250_putc(struct uart_bas *bas, int); 25497202af2SMarius Strobl static int ns8250_rxready(struct uart_bas *bas); 255634e63c9SMarcel Moolenaar static int ns8250_getc(struct uart_bas *bas, struct mtx *); 25627d5dc18SMarcel Moolenaar 257167cb33fSIan Lepore struct uart_ops uart_ns8250_ops = { 25827d5dc18SMarcel Moolenaar .probe = ns8250_probe, 25927d5dc18SMarcel Moolenaar .init = ns8250_init, 26027d5dc18SMarcel Moolenaar .term = ns8250_term, 26127d5dc18SMarcel Moolenaar .putc = ns8250_putc, 26297202af2SMarius Strobl .rxready = ns8250_rxready, 26327d5dc18SMarcel Moolenaar .getc = ns8250_getc, 26427d5dc18SMarcel Moolenaar }; 26527d5dc18SMarcel Moolenaar 26627d5dc18SMarcel Moolenaar static int 26727d5dc18SMarcel Moolenaar ns8250_probe(struct uart_bas *bas) 26827d5dc18SMarcel Moolenaar { 2698bceca4fSBenno Rice u_char val; 27027d5dc18SMarcel Moolenaar 27127d5dc18SMarcel Moolenaar /* Check known 0 bits that don't depend on DLAB. */ 27227d5dc18SMarcel Moolenaar val = uart_getreg(bas, REG_IIR); 27327d5dc18SMarcel Moolenaar if (val & 0x30) 27427d5dc18SMarcel Moolenaar return (ENXIO); 2755bdddc29SMarcel Moolenaar /* 2765bdddc29SMarcel Moolenaar * Bit 6 of the MCR (= 0x40) appears to be 1 for the Sun1699 2775bdddc29SMarcel Moolenaar * chip, but otherwise doesn't seem to have a function. In 2785bdddc29SMarcel Moolenaar * other words, uart(4) works regardless. Ignore that bit so 2795bdddc29SMarcel Moolenaar * the probe succeeds. 2805bdddc29SMarcel Moolenaar */ 28127d5dc18SMarcel Moolenaar val = uart_getreg(bas, REG_MCR); 2825bdddc29SMarcel Moolenaar if (val & 0xa0) 28327d5dc18SMarcel Moolenaar return (ENXIO); 28427d5dc18SMarcel Moolenaar 28527d5dc18SMarcel Moolenaar return (0); 28627d5dc18SMarcel Moolenaar } 28727d5dc18SMarcel Moolenaar 28827d5dc18SMarcel Moolenaar static void 28927d5dc18SMarcel Moolenaar ns8250_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, 29027d5dc18SMarcel Moolenaar int parity) 29127d5dc18SMarcel Moolenaar { 29258957d87SBenno Rice u_char ier; 29327d5dc18SMarcel Moolenaar 29427d5dc18SMarcel Moolenaar if (bas->rclk == 0) 29527d5dc18SMarcel Moolenaar bas->rclk = DEFAULT_RCLK; 29627d5dc18SMarcel Moolenaar ns8250_param(bas, baudrate, databits, stopbits, parity); 29727d5dc18SMarcel Moolenaar 29827d5dc18SMarcel Moolenaar /* Disable all interrupt sources. */ 2990aefb0a6SBenno Rice /* 3000aefb0a6SBenno Rice * We use 0xe0 instead of 0xf0 as the mask because the XScale PXA 3010aefb0a6SBenno Rice * UARTs split the receive time-out interrupt bit out separately as 3020aefb0a6SBenno Rice * 0x10. This gets handled by ier_mask and ier_rxbits below. 3030aefb0a6SBenno Rice */ 3040aefb0a6SBenno Rice ier = uart_getreg(bas, REG_IER) & 0xe0; 30558957d87SBenno Rice uart_setreg(bas, REG_IER, ier); 30627d5dc18SMarcel Moolenaar uart_barrier(bas); 30727d5dc18SMarcel Moolenaar 30827d5dc18SMarcel Moolenaar /* Disable the FIFO (if present). */ 30927d5dc18SMarcel Moolenaar uart_setreg(bas, REG_FCR, 0); 31027d5dc18SMarcel Moolenaar uart_barrier(bas); 31127d5dc18SMarcel Moolenaar 31227d5dc18SMarcel Moolenaar /* Set RTS & DTR. */ 31327d5dc18SMarcel Moolenaar uart_setreg(bas, REG_MCR, MCR_IE | MCR_RTS | MCR_DTR); 31427d5dc18SMarcel Moolenaar uart_barrier(bas); 31527d5dc18SMarcel Moolenaar 31627d5dc18SMarcel Moolenaar ns8250_clrint(bas); 31727d5dc18SMarcel Moolenaar } 31827d5dc18SMarcel Moolenaar 31927d5dc18SMarcel Moolenaar static void 32027d5dc18SMarcel Moolenaar ns8250_term(struct uart_bas *bas) 32127d5dc18SMarcel Moolenaar { 32227d5dc18SMarcel Moolenaar 32327d5dc18SMarcel Moolenaar /* Clear RTS & DTR. */ 32427d5dc18SMarcel Moolenaar uart_setreg(bas, REG_MCR, MCR_IE); 32527d5dc18SMarcel Moolenaar uart_barrier(bas); 32627d5dc18SMarcel Moolenaar } 32727d5dc18SMarcel Moolenaar 32827d5dc18SMarcel Moolenaar static void 32927d5dc18SMarcel Moolenaar ns8250_putc(struct uart_bas *bas, int c) 33027d5dc18SMarcel Moolenaar { 33135777a2aSMarcel Moolenaar int limit; 33227d5dc18SMarcel Moolenaar 33335777a2aSMarcel Moolenaar limit = 250000; 33427d5dc18SMarcel Moolenaar while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0 && --limit) 33535777a2aSMarcel Moolenaar DELAY(4); 33627d5dc18SMarcel Moolenaar uart_setreg(bas, REG_DATA, c); 3374e55f723SMarcel Moolenaar uart_barrier(bas); 33835777a2aSMarcel Moolenaar limit = 250000; 33927d5dc18SMarcel Moolenaar while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) 34035777a2aSMarcel Moolenaar DELAY(4); 34127d5dc18SMarcel Moolenaar } 34227d5dc18SMarcel Moolenaar 34327d5dc18SMarcel Moolenaar static int 34497202af2SMarius Strobl ns8250_rxready(struct uart_bas *bas) 34527d5dc18SMarcel Moolenaar { 34627d5dc18SMarcel Moolenaar 34797202af2SMarius Strobl return ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) != 0 ? 1 : 0); 34827d5dc18SMarcel Moolenaar } 34927d5dc18SMarcel Moolenaar 35027d5dc18SMarcel Moolenaar static int 351634e63c9SMarcel Moolenaar ns8250_getc(struct uart_bas *bas, struct mtx *hwmtx) 35227d5dc18SMarcel Moolenaar { 35335777a2aSMarcel Moolenaar int c; 354634e63c9SMarcel Moolenaar 355634e63c9SMarcel Moolenaar uart_lock(hwmtx); 35627d5dc18SMarcel Moolenaar 357634e63c9SMarcel Moolenaar while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0) { 358634e63c9SMarcel Moolenaar uart_unlock(hwmtx); 35935777a2aSMarcel Moolenaar DELAY(4); 360634e63c9SMarcel Moolenaar uart_lock(hwmtx); 361634e63c9SMarcel Moolenaar } 362634e63c9SMarcel Moolenaar 363634e63c9SMarcel Moolenaar c = uart_getreg(bas, REG_DATA); 364634e63c9SMarcel Moolenaar 365634e63c9SMarcel Moolenaar uart_unlock(hwmtx); 366634e63c9SMarcel Moolenaar 367634e63c9SMarcel Moolenaar return (c); 36827d5dc18SMarcel Moolenaar } 36927d5dc18SMarcel Moolenaar 37027d5dc18SMarcel Moolenaar static kobj_method_t ns8250_methods[] = { 37127d5dc18SMarcel Moolenaar KOBJMETHOD(uart_attach, ns8250_bus_attach), 37227d5dc18SMarcel Moolenaar KOBJMETHOD(uart_detach, ns8250_bus_detach), 37327d5dc18SMarcel Moolenaar KOBJMETHOD(uart_flush, ns8250_bus_flush), 37427d5dc18SMarcel Moolenaar KOBJMETHOD(uart_getsig, ns8250_bus_getsig), 37527d5dc18SMarcel Moolenaar KOBJMETHOD(uart_ioctl, ns8250_bus_ioctl), 37627d5dc18SMarcel Moolenaar KOBJMETHOD(uart_ipend, ns8250_bus_ipend), 37727d5dc18SMarcel Moolenaar KOBJMETHOD(uart_param, ns8250_bus_param), 37827d5dc18SMarcel Moolenaar KOBJMETHOD(uart_probe, ns8250_bus_probe), 37927d5dc18SMarcel Moolenaar KOBJMETHOD(uart_receive, ns8250_bus_receive), 38027d5dc18SMarcel Moolenaar KOBJMETHOD(uart_setsig, ns8250_bus_setsig), 38127d5dc18SMarcel Moolenaar KOBJMETHOD(uart_transmit, ns8250_bus_transmit), 382d76a1ef4SWarner Losh KOBJMETHOD(uart_grab, ns8250_bus_grab), 383d76a1ef4SWarner Losh KOBJMETHOD(uart_ungrab, ns8250_bus_ungrab), 38427d5dc18SMarcel Moolenaar { 0, 0 } 38527d5dc18SMarcel Moolenaar }; 38627d5dc18SMarcel Moolenaar 38727d5dc18SMarcel Moolenaar struct uart_class uart_ns8250_class = { 388f8100ce2SMarcel Moolenaar "ns8250", 38927d5dc18SMarcel Moolenaar ns8250_methods, 39027d5dc18SMarcel Moolenaar sizeof(struct ns8250_softc), 391f8100ce2SMarcel Moolenaar .uc_ops = &uart_ns8250_ops, 39227d5dc18SMarcel Moolenaar .uc_range = 8, 393405ada37SAndrew Turner .uc_rclk = DEFAULT_RCLK, 394405ada37SAndrew Turner .uc_rshift = 0 39527d5dc18SMarcel Moolenaar }; 39627d5dc18SMarcel Moolenaar 3973bb693afSIan Lepore #ifdef FDT 3983bb693afSIan Lepore static struct ofw_compat_data compat_data[] = { 3993bb693afSIan Lepore {"ns16550", (uintptr_t)&uart_ns8250_class}, 400a6c98177SZbigniew Bodek {"snps,dw-apb-uart", (uintptr_t)&uart_ns8250_class}, 4013bb693afSIan Lepore {NULL, (uintptr_t)NULL}, 4023bb693afSIan Lepore }; 4033bb693afSIan Lepore UART_FDT_CLASS_AND_DEVICE(compat_data); 4043bb693afSIan Lepore #endif 4053bb693afSIan Lepore 406fdfbb3f5SIan Lepore /* Use token-pasting to form SER_ and MSR_ named constants. */ 407fdfbb3f5SIan Lepore #define SER(sig) SER_##sig 408fdfbb3f5SIan Lepore #define SERD(sig) SER_D##sig 409fdfbb3f5SIan Lepore #define MSR(sig) MSR_##sig 410fdfbb3f5SIan Lepore #define MSRD(sig) MSR_D##sig 411fdfbb3f5SIan Lepore 412fdfbb3f5SIan Lepore /* 413fdfbb3f5SIan Lepore * Detect signal changes using software delta detection. The previous state of 414fdfbb3f5SIan Lepore * the signals is in 'var' the new hardware state is in 'msr', and 'sig' is the 415fdfbb3f5SIan Lepore * short name (DCD, CTS, etc) of the signal bit being processed; 'var' gets the 416fdfbb3f5SIan Lepore * new state of both the signal and the delta bits. 417fdfbb3f5SIan Lepore */ 418fdfbb3f5SIan Lepore #define SIGCHGSW(var, msr, sig) \ 419fdfbb3f5SIan Lepore if ((msr) & MSR(sig)) { \ 420fdfbb3f5SIan Lepore if ((var & SER(sig)) == 0) \ 421fdfbb3f5SIan Lepore var |= SERD(sig) | SER(sig); \ 42227d5dc18SMarcel Moolenaar } else { \ 423fdfbb3f5SIan Lepore if ((var & SER(sig)) != 0) \ 424fdfbb3f5SIan Lepore var = SERD(sig) | (var & ~SER(sig)); \ 425fdfbb3f5SIan Lepore } 426fdfbb3f5SIan Lepore 427fdfbb3f5SIan Lepore /* 428fdfbb3f5SIan Lepore * Detect signal changes using the hardware msr delta bits. This is currently 429fdfbb3f5SIan Lepore * used only when PPS timing information is being captured using the "narrow 430fdfbb3f5SIan Lepore * pulse" option. With a narrow PPS pulse the signal may not still be asserted 431fdfbb3f5SIan Lepore * by time the interrupt handler is invoked. The hardware will latch the fact 432fdfbb3f5SIan Lepore * that it changed in the delta bits. 433fdfbb3f5SIan Lepore */ 434fdfbb3f5SIan Lepore #define SIGCHGHW(var, msr, sig) \ 435fdfbb3f5SIan Lepore if ((msr) & MSRD(sig)) { \ 436fdfbb3f5SIan Lepore if (((msr) & MSR(sig)) != 0) \ 437fdfbb3f5SIan Lepore var |= SERD(sig) | SER(sig); \ 438fdfbb3f5SIan Lepore else \ 439fdfbb3f5SIan Lepore var = SERD(sig) | (var & ~SER(sig)); \ 44027d5dc18SMarcel Moolenaar } 44127d5dc18SMarcel Moolenaar 442167cb33fSIan Lepore int 44327d5dc18SMarcel Moolenaar ns8250_bus_attach(struct uart_softc *sc) 44427d5dc18SMarcel Moolenaar { 44527d5dc18SMarcel Moolenaar struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 44627d5dc18SMarcel Moolenaar struct uart_bas *bas; 447823c77d7SSam Leffler unsigned int ivar; 448ac4adddfSGanbold Tsagaankhuu #ifdef FDT 449ac4adddfSGanbold Tsagaankhuu phandle_t node; 450ac4adddfSGanbold Tsagaankhuu pcell_t cell; 451ac4adddfSGanbold Tsagaankhuu #endif 452ac4adddfSGanbold Tsagaankhuu 453ac4adddfSGanbold Tsagaankhuu ns8250->busy_detect = 0; 454ac4adddfSGanbold Tsagaankhuu 455ac4adddfSGanbold Tsagaankhuu #ifdef FDT 456ac4adddfSGanbold Tsagaankhuu /* 457ac4adddfSGanbold Tsagaankhuu * Check whether uart requires to read USR reg when IIR_BUSY and 458ac4adddfSGanbold Tsagaankhuu * has broken txfifo. 459ac4adddfSGanbold Tsagaankhuu */ 4608abfc69dSZbigniew Bodek ns8250->busy_detect = ofw_bus_is_compatible(sc->sc_dev, "snps,dw-apb-uart"); 461ac4adddfSGanbold Tsagaankhuu node = ofw_bus_get_node(sc->sc_dev); 4628abfc69dSZbigniew Bodek /* XXX: This is kept for a short time for compatibility with older device trees */ 4638abfc69dSZbigniew Bodek if ((OF_getencprop(node, "busy-detect", &cell, sizeof(cell))) > 0 4648abfc69dSZbigniew Bodek && cell != 0) 4658abfc69dSZbigniew Bodek ns8250->busy_detect = 1; 466b1621f22SLuiz Otavio O Souza if ((OF_getencprop(node, "broken-txfifo", &cell, sizeof(cell))) > 0) 467b1621f22SLuiz Otavio O Souza broken_txfifo = cell ? 1 : 0; 468ac4adddfSGanbold Tsagaankhuu #endif 46927d5dc18SMarcel Moolenaar 47027d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 47127d5dc18SMarcel Moolenaar 47227d5dc18SMarcel Moolenaar ns8250->mcr = uart_getreg(bas, REG_MCR); 473823c77d7SSam Leffler ns8250->fcr = FCR_ENABLE; 474823c77d7SSam Leffler if (!resource_int_value("uart", device_get_unit(sc->sc_dev), "flags", 475823c77d7SSam Leffler &ivar)) { 476823c77d7SSam Leffler if (UART_FLAGS_FCR_RX_LOW(ivar)) 477823c77d7SSam Leffler ns8250->fcr |= FCR_RX_LOW; 478823c77d7SSam Leffler else if (UART_FLAGS_FCR_RX_MEDL(ivar)) 479823c77d7SSam Leffler ns8250->fcr |= FCR_RX_MEDL; 480823c77d7SSam Leffler else if (UART_FLAGS_FCR_RX_HIGH(ivar)) 481823c77d7SSam Leffler ns8250->fcr |= FCR_RX_HIGH; 482823c77d7SSam Leffler else 483823c77d7SSam Leffler ns8250->fcr |= FCR_RX_MEDH; 484823c77d7SSam Leffler } else 485823c77d7SSam Leffler ns8250->fcr |= FCR_RX_MEDH; 4860aefb0a6SBenno Rice 4870aefb0a6SBenno Rice /* Get IER mask */ 4880aefb0a6SBenno Rice ivar = 0xf0; 4890aefb0a6SBenno Rice resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_mask", 4900aefb0a6SBenno Rice &ivar); 4910aefb0a6SBenno Rice ns8250->ier_mask = (uint8_t)(ivar & 0xff); 4920aefb0a6SBenno Rice 4930aefb0a6SBenno Rice /* Get IER RX interrupt bits */ 4940aefb0a6SBenno Rice ivar = IER_EMSC | IER_ERLS | IER_ERXRDY; 4950aefb0a6SBenno Rice resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_rxbits", 4960aefb0a6SBenno Rice &ivar); 4970aefb0a6SBenno Rice ns8250->ier_rxbits = (uint8_t)(ivar & 0xff); 4980aefb0a6SBenno Rice 49927d5dc18SMarcel Moolenaar uart_setreg(bas, REG_FCR, ns8250->fcr); 50027d5dc18SMarcel Moolenaar uart_barrier(bas); 50127d5dc18SMarcel Moolenaar ns8250_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 50227d5dc18SMarcel Moolenaar 50327d5dc18SMarcel Moolenaar if (ns8250->mcr & MCR_DTR) 50428710806SPoul-Henning Kamp sc->sc_hwsig |= SER_DTR; 50527d5dc18SMarcel Moolenaar if (ns8250->mcr & MCR_RTS) 50628710806SPoul-Henning Kamp sc->sc_hwsig |= SER_RTS; 50727d5dc18SMarcel Moolenaar ns8250_bus_getsig(sc); 50827d5dc18SMarcel Moolenaar 50927d5dc18SMarcel Moolenaar ns8250_clrint(bas); 5100aefb0a6SBenno Rice ns8250->ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 5110aefb0a6SBenno Rice ns8250->ier |= ns8250->ier_rxbits; 51227d5dc18SMarcel Moolenaar uart_setreg(bas, REG_IER, ns8250->ier); 51327d5dc18SMarcel Moolenaar uart_barrier(bas); 5140aefb0a6SBenno Rice 5154fc49975SMarcel Moolenaar /* 5164fc49975SMarcel Moolenaar * Timing of the H/W access was changed with r253161 of uart_core.c 5174fc49975SMarcel Moolenaar * It has been observed that an ITE IT8513E would signal a break 5184fc49975SMarcel Moolenaar * condition with pretty much every character it received, unless 5194fc49975SMarcel Moolenaar * it had enough time to settle between ns8250_bus_attach() and 5204fc49975SMarcel Moolenaar * ns8250_bus_ipend() -- which it accidentally had before r253161. 5214fc49975SMarcel Moolenaar * It's not understood why the UART chip behaves this way and it 5224fc49975SMarcel Moolenaar * could very well be that the DELAY make the H/W work in the same 5234fc49975SMarcel Moolenaar * accidental manner as before. More analysis is warranted, but 5244fc49975SMarcel Moolenaar * at least now we fixed a known regression. 5254fc49975SMarcel Moolenaar */ 52640a827b6SMarcel Moolenaar DELAY(200); 52727d5dc18SMarcel Moolenaar return (0); 52827d5dc18SMarcel Moolenaar } 52927d5dc18SMarcel Moolenaar 530167cb33fSIan Lepore int 53127d5dc18SMarcel Moolenaar ns8250_bus_detach(struct uart_softc *sc) 53227d5dc18SMarcel Moolenaar { 5330aefb0a6SBenno Rice struct ns8250_softc *ns8250; 53427d5dc18SMarcel Moolenaar struct uart_bas *bas; 53558957d87SBenno Rice u_char ier; 53627d5dc18SMarcel Moolenaar 5370aefb0a6SBenno Rice ns8250 = (struct ns8250_softc *)sc; 53827d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 5390aefb0a6SBenno Rice ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 54058957d87SBenno Rice uart_setreg(bas, REG_IER, ier); 54127d5dc18SMarcel Moolenaar uart_barrier(bas); 54227d5dc18SMarcel Moolenaar ns8250_clrint(bas); 54327d5dc18SMarcel Moolenaar return (0); 54427d5dc18SMarcel Moolenaar } 54527d5dc18SMarcel Moolenaar 546167cb33fSIan Lepore int 54727d5dc18SMarcel Moolenaar ns8250_bus_flush(struct uart_softc *sc, int what) 54827d5dc18SMarcel Moolenaar { 54927d5dc18SMarcel Moolenaar struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 55027d5dc18SMarcel Moolenaar struct uart_bas *bas; 55106287620SMarcel Moolenaar int error; 55227d5dc18SMarcel Moolenaar 55327d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 5548af03381SMarcel Moolenaar uart_lock(sc->sc_hwmtx); 5558d1289feSMarcel Moolenaar if (sc->sc_rxfifosz > 1) { 55627d5dc18SMarcel Moolenaar ns8250_flush(bas, what); 55727d5dc18SMarcel Moolenaar uart_setreg(bas, REG_FCR, ns8250->fcr); 55827d5dc18SMarcel Moolenaar uart_barrier(bas); 55906287620SMarcel Moolenaar error = 0; 56006287620SMarcel Moolenaar } else 56106287620SMarcel Moolenaar error = ns8250_drain(bas, what); 5628af03381SMarcel Moolenaar uart_unlock(sc->sc_hwmtx); 56306287620SMarcel Moolenaar return (error); 56427d5dc18SMarcel Moolenaar } 56527d5dc18SMarcel Moolenaar 566167cb33fSIan Lepore int 56727d5dc18SMarcel Moolenaar ns8250_bus_getsig(struct uart_softc *sc) 56827d5dc18SMarcel Moolenaar { 569fdfbb3f5SIan Lepore uint32_t old, sig; 57027d5dc18SMarcel Moolenaar uint8_t msr; 57127d5dc18SMarcel Moolenaar 572fdfbb3f5SIan Lepore /* 573fdfbb3f5SIan Lepore * The delta bits are reputed to be broken on some hardware, so use 574fdfbb3f5SIan Lepore * software delta detection by default. Use the hardware delta bits 575fdfbb3f5SIan Lepore * when capturing PPS pulses which are too narrow for software detection 576fdfbb3f5SIan Lepore * to see the edges. Hardware delta for RI doesn't work like the 577fdfbb3f5SIan Lepore * others, so always use software for it. Other threads may be changing 578fdfbb3f5SIan Lepore * other (non-MSR) bits in sc_hwsig, so loop until it can succesfully 579fdfbb3f5SIan Lepore * update without other changes happening. Note that the SIGCHGxx() 580fdfbb3f5SIan Lepore * macros carefully preserve the delta bits when we have to loop several 581fdfbb3f5SIan Lepore * times and a signal transitions between iterations. 582fdfbb3f5SIan Lepore */ 58327d5dc18SMarcel Moolenaar do { 58427d5dc18SMarcel Moolenaar old = sc->sc_hwsig; 58527d5dc18SMarcel Moolenaar sig = old; 5868af03381SMarcel Moolenaar uart_lock(sc->sc_hwmtx); 58727d5dc18SMarcel Moolenaar msr = uart_getreg(&sc->sc_bas, REG_MSR); 5888af03381SMarcel Moolenaar uart_unlock(sc->sc_hwmtx); 589fdfbb3f5SIan Lepore if (sc->sc_pps_mode & UART_PPS_NARROW_PULSE) { 590fdfbb3f5SIan Lepore SIGCHGHW(sig, msr, DSR); 591fdfbb3f5SIan Lepore SIGCHGHW(sig, msr, CTS); 592fdfbb3f5SIan Lepore SIGCHGHW(sig, msr, DCD); 593fdfbb3f5SIan Lepore } else { 594fdfbb3f5SIan Lepore SIGCHGSW(sig, msr, DSR); 595fdfbb3f5SIan Lepore SIGCHGSW(sig, msr, CTS); 596fdfbb3f5SIan Lepore SIGCHGSW(sig, msr, DCD); 597fdfbb3f5SIan Lepore } 598fdfbb3f5SIan Lepore SIGCHGSW(sig, msr, RI); 599fdfbb3f5SIan Lepore } while (!atomic_cmpset_32(&sc->sc_hwsig, old, sig & ~SER_MASK_DELTA)); 60027d5dc18SMarcel Moolenaar return (sig); 60127d5dc18SMarcel Moolenaar } 60227d5dc18SMarcel Moolenaar 603167cb33fSIan Lepore int 60427d5dc18SMarcel Moolenaar ns8250_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) 60527d5dc18SMarcel Moolenaar { 60627d5dc18SMarcel Moolenaar struct uart_bas *bas; 607bfa307a3SMarcel Moolenaar int baudrate, divisor, error; 60884c7b427SMarcel Moolenaar uint8_t efr, lcr; 60927d5dc18SMarcel Moolenaar 61027d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 61106287620SMarcel Moolenaar error = 0; 6128af03381SMarcel Moolenaar uart_lock(sc->sc_hwmtx); 61327d5dc18SMarcel Moolenaar switch (request) { 61427d5dc18SMarcel Moolenaar case UART_IOCTL_BREAK: 61527d5dc18SMarcel Moolenaar lcr = uart_getreg(bas, REG_LCR); 61627d5dc18SMarcel Moolenaar if (data) 61727d5dc18SMarcel Moolenaar lcr |= LCR_SBREAK; 61827d5dc18SMarcel Moolenaar else 61927d5dc18SMarcel Moolenaar lcr &= ~LCR_SBREAK; 62027d5dc18SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr); 62127d5dc18SMarcel Moolenaar uart_barrier(bas); 62227d5dc18SMarcel Moolenaar break; 62384c7b427SMarcel Moolenaar case UART_IOCTL_IFLOW: 62484c7b427SMarcel Moolenaar lcr = uart_getreg(bas, REG_LCR); 62584c7b427SMarcel Moolenaar uart_barrier(bas); 62684c7b427SMarcel Moolenaar uart_setreg(bas, REG_LCR, 0xbf); 62784c7b427SMarcel Moolenaar uart_barrier(bas); 62884c7b427SMarcel Moolenaar efr = uart_getreg(bas, REG_EFR); 62984c7b427SMarcel Moolenaar if (data) 63084c7b427SMarcel Moolenaar efr |= EFR_RTS; 63184c7b427SMarcel Moolenaar else 63284c7b427SMarcel Moolenaar efr &= ~EFR_RTS; 63384c7b427SMarcel Moolenaar uart_setreg(bas, REG_EFR, efr); 63484c7b427SMarcel Moolenaar uart_barrier(bas); 63584c7b427SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr); 63684c7b427SMarcel Moolenaar uart_barrier(bas); 63784c7b427SMarcel Moolenaar break; 63884c7b427SMarcel Moolenaar case UART_IOCTL_OFLOW: 63984c7b427SMarcel Moolenaar lcr = uart_getreg(bas, REG_LCR); 64084c7b427SMarcel Moolenaar uart_barrier(bas); 64184c7b427SMarcel Moolenaar uart_setreg(bas, REG_LCR, 0xbf); 64284c7b427SMarcel Moolenaar uart_barrier(bas); 64384c7b427SMarcel Moolenaar efr = uart_getreg(bas, REG_EFR); 64484c7b427SMarcel Moolenaar if (data) 64584c7b427SMarcel Moolenaar efr |= EFR_CTS; 64684c7b427SMarcel Moolenaar else 64784c7b427SMarcel Moolenaar efr &= ~EFR_CTS; 64884c7b427SMarcel Moolenaar uart_setreg(bas, REG_EFR, efr); 64984c7b427SMarcel Moolenaar uart_barrier(bas); 65084c7b427SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr); 65184c7b427SMarcel Moolenaar uart_barrier(bas); 65284c7b427SMarcel Moolenaar break; 653d8518925SMarcel Moolenaar case UART_IOCTL_BAUD: 654d8518925SMarcel Moolenaar lcr = uart_getreg(bas, REG_LCR); 655d8518925SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 656d8518925SMarcel Moolenaar uart_barrier(bas); 65758957d87SBenno Rice divisor = uart_getreg(bas, REG_DLL) | 65858957d87SBenno Rice (uart_getreg(bas, REG_DLH) << 8); 659d8518925SMarcel Moolenaar uart_barrier(bas); 660d8518925SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr); 661d8518925SMarcel Moolenaar uart_barrier(bas); 662bfa307a3SMarcel Moolenaar baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0; 663bfa307a3SMarcel Moolenaar if (baudrate > 0) 664bfa307a3SMarcel Moolenaar *(int*)data = baudrate; 665bfa307a3SMarcel Moolenaar else 666bfa307a3SMarcel Moolenaar error = ENXIO; 667d8518925SMarcel Moolenaar break; 66827d5dc18SMarcel Moolenaar default: 66906287620SMarcel Moolenaar error = EINVAL; 67006287620SMarcel Moolenaar break; 67127d5dc18SMarcel Moolenaar } 6728af03381SMarcel Moolenaar uart_unlock(sc->sc_hwmtx); 67306287620SMarcel Moolenaar return (error); 67427d5dc18SMarcel Moolenaar } 67527d5dc18SMarcel Moolenaar 676167cb33fSIan Lepore int 67727d5dc18SMarcel Moolenaar ns8250_bus_ipend(struct uart_softc *sc) 67827d5dc18SMarcel Moolenaar { 67927d5dc18SMarcel Moolenaar struct uart_bas *bas; 68011e55f91SOlivier Houchard struct ns8250_softc *ns8250; 68127d5dc18SMarcel Moolenaar int ipend; 68227d5dc18SMarcel Moolenaar uint8_t iir, lsr; 68327d5dc18SMarcel Moolenaar 68411e55f91SOlivier Houchard ns8250 = (struct ns8250_softc *)sc; 68527d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 6868af03381SMarcel Moolenaar uart_lock(sc->sc_hwmtx); 68727d5dc18SMarcel Moolenaar iir = uart_getreg(bas, REG_IIR); 688ac4adddfSGanbold Tsagaankhuu 689ac4adddfSGanbold Tsagaankhuu if (ns8250->busy_detect && (iir & IIR_BUSY) == IIR_BUSY) { 690ac4adddfSGanbold Tsagaankhuu (void)uart_getreg(bas, DW_REG_USR); 691ac4adddfSGanbold Tsagaankhuu uart_unlock(sc->sc_hwmtx); 692ac4adddfSGanbold Tsagaankhuu return (0); 693ac4adddfSGanbold Tsagaankhuu } 69406287620SMarcel Moolenaar if (iir & IIR_NOPEND) { 6958af03381SMarcel Moolenaar uart_unlock(sc->sc_hwmtx); 69627d5dc18SMarcel Moolenaar return (0); 69706287620SMarcel Moolenaar } 69827d5dc18SMarcel Moolenaar ipend = 0; 69927d5dc18SMarcel Moolenaar if (iir & IIR_RXRDY) { 70027d5dc18SMarcel Moolenaar lsr = uart_getreg(bas, REG_LSR); 70127d5dc18SMarcel Moolenaar if (lsr & LSR_OE) 7022d511805SMarcel Moolenaar ipend |= SER_INT_OVERRUN; 70327d5dc18SMarcel Moolenaar if (lsr & LSR_BI) 7042d511805SMarcel Moolenaar ipend |= SER_INT_BREAK; 70527d5dc18SMarcel Moolenaar if (lsr & LSR_RXRDY) 7062d511805SMarcel Moolenaar ipend |= SER_INT_RXREADY; 70727d5dc18SMarcel Moolenaar } else { 70811e55f91SOlivier Houchard if (iir & IIR_TXRDY) { 7092d511805SMarcel Moolenaar ipend |= SER_INT_TXIDLE; 71011e55f91SOlivier Houchard uart_setreg(bas, REG_IER, ns8250->ier); 7113c7b9077SMichal Meloun uart_barrier(bas); 71211e55f91SOlivier Houchard } else 7132d511805SMarcel Moolenaar ipend |= SER_INT_SIGCHG; 71427d5dc18SMarcel Moolenaar } 715d7ae5af5SMarcel Moolenaar if (ipend == 0) 716d7ae5af5SMarcel Moolenaar ns8250_clrint(bas); 717d7ae5af5SMarcel Moolenaar uart_unlock(sc->sc_hwmtx); 718f6ffc3c2SMarius Strobl return (ipend); 71927d5dc18SMarcel Moolenaar } 72027d5dc18SMarcel Moolenaar 721167cb33fSIan Lepore int 72227d5dc18SMarcel Moolenaar ns8250_bus_param(struct uart_softc *sc, int baudrate, int databits, 72327d5dc18SMarcel Moolenaar int stopbits, int parity) 72427d5dc18SMarcel Moolenaar { 72549e368acSZbigniew Bodek struct ns8250_softc *ns8250; 72627d5dc18SMarcel Moolenaar struct uart_bas *bas; 72749e368acSZbigniew Bodek int error, limit; 72827d5dc18SMarcel Moolenaar 72949e368acSZbigniew Bodek ns8250 = (struct ns8250_softc*)sc; 73027d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 7318af03381SMarcel Moolenaar uart_lock(sc->sc_hwmtx); 73249e368acSZbigniew Bodek /* 73349e368acSZbigniew Bodek * When using DW UART with BUSY detection it is necessary to wait 73449e368acSZbigniew Bodek * until all serial transfers are finished before manipulating the 73549e368acSZbigniew Bodek * line control. LCR will not be affected when UART is busy. 73649e368acSZbigniew Bodek */ 73749e368acSZbigniew Bodek if (ns8250->busy_detect != 0) { 73849e368acSZbigniew Bodek /* 73949e368acSZbigniew Bodek * Pick an arbitrary high limit to avoid getting stuck in 74049e368acSZbigniew Bodek * an infinite loop in case when the hardware is broken. 74149e368acSZbigniew Bodek */ 74249e368acSZbigniew Bodek limit = 10 * 1024; 74349e368acSZbigniew Bodek while (((uart_getreg(bas, DW_REG_USR) & USR_BUSY) != 0) && 74449e368acSZbigniew Bodek --limit) 74549e368acSZbigniew Bodek DELAY(4); 74649e368acSZbigniew Bodek 74749e368acSZbigniew Bodek if (limit <= 0) { 74849e368acSZbigniew Bodek /* UART appears to be stuck */ 74949e368acSZbigniew Bodek uart_unlock(sc->sc_hwmtx); 75049e368acSZbigniew Bodek return (EIO); 75149e368acSZbigniew Bodek } 75249e368acSZbigniew Bodek } 75349e368acSZbigniew Bodek 75406287620SMarcel Moolenaar error = ns8250_param(bas, baudrate, databits, stopbits, parity); 7558af03381SMarcel Moolenaar uart_unlock(sc->sc_hwmtx); 75606287620SMarcel Moolenaar return (error); 75727d5dc18SMarcel Moolenaar } 75827d5dc18SMarcel Moolenaar 759167cb33fSIan Lepore int 76027d5dc18SMarcel Moolenaar ns8250_bus_probe(struct uart_softc *sc) 76127d5dc18SMarcel Moolenaar { 7620aefb0a6SBenno Rice struct ns8250_softc *ns8250; 76327d5dc18SMarcel Moolenaar struct uart_bas *bas; 76427d5dc18SMarcel Moolenaar int count, delay, error, limit; 76558957d87SBenno Rice uint8_t lsr, mcr, ier; 76627d5dc18SMarcel Moolenaar 7670aefb0a6SBenno Rice ns8250 = (struct ns8250_softc *)sc; 76827d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 76927d5dc18SMarcel Moolenaar 77027d5dc18SMarcel Moolenaar error = ns8250_probe(bas); 77127d5dc18SMarcel Moolenaar if (error) 77227d5dc18SMarcel Moolenaar return (error); 77327d5dc18SMarcel Moolenaar 77427d5dc18SMarcel Moolenaar mcr = MCR_IE; 77527d5dc18SMarcel Moolenaar if (sc->sc_sysdev == NULL) { 77627d5dc18SMarcel Moolenaar /* By using ns8250_init() we also set DTR and RTS. */ 777d902fb71SMarcel Moolenaar ns8250_init(bas, 115200, 8, 1, UART_PARITY_NONE); 77827d5dc18SMarcel Moolenaar } else 77927d5dc18SMarcel Moolenaar mcr |= MCR_DTR | MCR_RTS; 78027d5dc18SMarcel Moolenaar 78127d5dc18SMarcel Moolenaar error = ns8250_drain(bas, UART_DRAIN_TRANSMITTER); 78227d5dc18SMarcel Moolenaar if (error) 78327d5dc18SMarcel Moolenaar return (error); 78427d5dc18SMarcel Moolenaar 78527d5dc18SMarcel Moolenaar /* 78627d5dc18SMarcel Moolenaar * Set loopback mode. This avoids having garbage on the wire and 78727d5dc18SMarcel Moolenaar * also allows us send and receive data. We set DTR and RTS to 78827d5dc18SMarcel Moolenaar * avoid the possibility that automatic flow-control prevents 78989eef2deSThomas Moestl * any data from being sent. 79027d5dc18SMarcel Moolenaar */ 79189eef2deSThomas Moestl uart_setreg(bas, REG_MCR, MCR_LOOPBACK | MCR_IE | MCR_DTR | MCR_RTS); 79227d5dc18SMarcel Moolenaar uart_barrier(bas); 79327d5dc18SMarcel Moolenaar 79427d5dc18SMarcel Moolenaar /* 79527d5dc18SMarcel Moolenaar * Enable FIFOs. And check that the UART has them. If not, we're 79689eef2deSThomas Moestl * done. Since this is the first time we enable the FIFOs, we reset 79789eef2deSThomas Moestl * them. 79827d5dc18SMarcel Moolenaar */ 79927d5dc18SMarcel Moolenaar uart_setreg(bas, REG_FCR, FCR_ENABLE); 80027d5dc18SMarcel Moolenaar uart_barrier(bas); 8018d1289feSMarcel Moolenaar if (!(uart_getreg(bas, REG_IIR) & IIR_FIFO_MASK)) { 80227d5dc18SMarcel Moolenaar /* 80327d5dc18SMarcel Moolenaar * NS16450 or INS8250. We don't bother to differentiate 80427d5dc18SMarcel Moolenaar * between them. They're too old to be interesting. 80527d5dc18SMarcel Moolenaar */ 80627d5dc18SMarcel Moolenaar uart_setreg(bas, REG_MCR, mcr); 80727d5dc18SMarcel Moolenaar uart_barrier(bas); 8088d1289feSMarcel Moolenaar sc->sc_rxfifosz = sc->sc_txfifosz = 1; 80927d5dc18SMarcel Moolenaar device_set_desc(sc->sc_dev, "8250 or 16450 or compatible"); 81027d5dc18SMarcel Moolenaar return (0); 81127d5dc18SMarcel Moolenaar } 81227d5dc18SMarcel Moolenaar 81389eef2deSThomas Moestl uart_setreg(bas, REG_FCR, FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST); 81427d5dc18SMarcel Moolenaar uart_barrier(bas); 81527d5dc18SMarcel Moolenaar 81627d5dc18SMarcel Moolenaar count = 0; 81727d5dc18SMarcel Moolenaar delay = ns8250_delay(bas); 81827d5dc18SMarcel Moolenaar 81927d5dc18SMarcel Moolenaar /* We have FIFOs. Drain the transmitter and receiver. */ 82027d5dc18SMarcel Moolenaar error = ns8250_drain(bas, UART_DRAIN_RECEIVER|UART_DRAIN_TRANSMITTER); 82127d5dc18SMarcel Moolenaar if (error) { 82227d5dc18SMarcel Moolenaar uart_setreg(bas, REG_MCR, mcr); 82327d5dc18SMarcel Moolenaar uart_setreg(bas, REG_FCR, 0); 82427d5dc18SMarcel Moolenaar uart_barrier(bas); 82527d5dc18SMarcel Moolenaar goto describe; 82627d5dc18SMarcel Moolenaar } 82727d5dc18SMarcel Moolenaar 82827d5dc18SMarcel Moolenaar /* 82927d5dc18SMarcel Moolenaar * We should have a sufficiently clean "pipe" to determine the 83027d5dc18SMarcel Moolenaar * size of the FIFOs. We send as much characters as is reasonable 8316bccea7cSRebecca Cran * and wait for the overflow bit in the LSR register to be 83289eef2deSThomas Moestl * asserted, counting the characters as we send them. Based on 83389eef2deSThomas Moestl * that count we know the FIFO size. 83427d5dc18SMarcel Moolenaar */ 83589eef2deSThomas Moestl do { 83627d5dc18SMarcel Moolenaar uart_setreg(bas, REG_DATA, 0); 83727d5dc18SMarcel Moolenaar uart_barrier(bas); 83827d5dc18SMarcel Moolenaar count++; 83927d5dc18SMarcel Moolenaar 84027d5dc18SMarcel Moolenaar limit = 30; 84189eef2deSThomas Moestl lsr = 0; 84289eef2deSThomas Moestl /* 84389eef2deSThomas Moestl * LSR bits are cleared upon read, so we must accumulate 84489eef2deSThomas Moestl * them to be able to test LSR_OE below. 84589eef2deSThomas Moestl */ 84689eef2deSThomas Moestl while (((lsr |= uart_getreg(bas, REG_LSR)) & LSR_TEMT) == 0 && 84789eef2deSThomas Moestl --limit) 84827d5dc18SMarcel Moolenaar DELAY(delay); 84927d5dc18SMarcel Moolenaar if (limit == 0) { 8500aefb0a6SBenno Rice ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 85158957d87SBenno Rice uart_setreg(bas, REG_IER, ier); 85227d5dc18SMarcel Moolenaar uart_setreg(bas, REG_MCR, mcr); 85327d5dc18SMarcel Moolenaar uart_setreg(bas, REG_FCR, 0); 85427d5dc18SMarcel Moolenaar uart_barrier(bas); 85527d5dc18SMarcel Moolenaar count = 0; 85627d5dc18SMarcel Moolenaar goto describe; 85727d5dc18SMarcel Moolenaar } 858d882cf92SMarcel Moolenaar } while ((lsr & LSR_OE) == 0 && count < 130); 85989eef2deSThomas Moestl count--; 86027d5dc18SMarcel Moolenaar 86127d5dc18SMarcel Moolenaar uart_setreg(bas, REG_MCR, mcr); 86227d5dc18SMarcel Moolenaar 86327d5dc18SMarcel Moolenaar /* Reset FIFOs. */ 86427d5dc18SMarcel Moolenaar ns8250_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 86527d5dc18SMarcel Moolenaar 86627d5dc18SMarcel Moolenaar describe: 86789eef2deSThomas Moestl if (count >= 14 && count <= 16) { 86827d5dc18SMarcel Moolenaar sc->sc_rxfifosz = 16; 86927d5dc18SMarcel Moolenaar device_set_desc(sc->sc_dev, "16550 or compatible"); 87089eef2deSThomas Moestl } else if (count >= 28 && count <= 32) { 87127d5dc18SMarcel Moolenaar sc->sc_rxfifosz = 32; 87227d5dc18SMarcel Moolenaar device_set_desc(sc->sc_dev, "16650 or compatible"); 87389eef2deSThomas Moestl } else if (count >= 56 && count <= 64) { 87427d5dc18SMarcel Moolenaar sc->sc_rxfifosz = 64; 87527d5dc18SMarcel Moolenaar device_set_desc(sc->sc_dev, "16750 or compatible"); 87689eef2deSThomas Moestl } else if (count >= 112 && count <= 128) { 87727d5dc18SMarcel Moolenaar sc->sc_rxfifosz = 128; 87827d5dc18SMarcel Moolenaar device_set_desc(sc->sc_dev, "16950 or compatible"); 87927d5dc18SMarcel Moolenaar } else { 880c21e0da2SMarcel Moolenaar sc->sc_rxfifosz = 16; 88127d5dc18SMarcel Moolenaar device_set_desc(sc->sc_dev, 88227d5dc18SMarcel Moolenaar "Non-standard ns8250 class UART with FIFOs"); 88327d5dc18SMarcel Moolenaar } 88427d5dc18SMarcel Moolenaar 88527d5dc18SMarcel Moolenaar /* 88627d5dc18SMarcel Moolenaar * Force the Tx FIFO size to 16 bytes for now. We don't program the 88727d5dc18SMarcel Moolenaar * Tx trigger. Also, we assume that all data has been sent when the 88827d5dc18SMarcel Moolenaar * interrupt happens. 88927d5dc18SMarcel Moolenaar */ 89027d5dc18SMarcel Moolenaar sc->sc_txfifosz = 16; 89127d5dc18SMarcel Moolenaar 892dc70e792SMarcel Moolenaar #if 0 893dc70e792SMarcel Moolenaar /* 894dc70e792SMarcel Moolenaar * XXX there are some issues related to hardware flow control and 895dc70e792SMarcel Moolenaar * it's likely that uart(4) is the cause. This basicly needs more 896dc70e792SMarcel Moolenaar * investigation, but we avoid using for hardware flow control 897dc70e792SMarcel Moolenaar * until then. 898dc70e792SMarcel Moolenaar */ 89984c7b427SMarcel Moolenaar /* 16650s or higher have automatic flow control. */ 90084c7b427SMarcel Moolenaar if (sc->sc_rxfifosz > 16) { 90184c7b427SMarcel Moolenaar sc->sc_hwiflow = 1; 90284c7b427SMarcel Moolenaar sc->sc_hwoflow = 1; 90384c7b427SMarcel Moolenaar } 904dc70e792SMarcel Moolenaar #endif 90584c7b427SMarcel Moolenaar 90627d5dc18SMarcel Moolenaar return (0); 90727d5dc18SMarcel Moolenaar } 90827d5dc18SMarcel Moolenaar 909167cb33fSIan Lepore int 91027d5dc18SMarcel Moolenaar ns8250_bus_receive(struct uart_softc *sc) 91127d5dc18SMarcel Moolenaar { 91227d5dc18SMarcel Moolenaar struct uart_bas *bas; 91327d5dc18SMarcel Moolenaar int xc; 91427d5dc18SMarcel Moolenaar uint8_t lsr; 91527d5dc18SMarcel Moolenaar 91627d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 9178af03381SMarcel Moolenaar uart_lock(sc->sc_hwmtx); 91827d5dc18SMarcel Moolenaar lsr = uart_getreg(bas, REG_LSR); 91944ed791bSMarcel Moolenaar while (lsr & LSR_RXRDY) { 92044ed791bSMarcel Moolenaar if (uart_rx_full(sc)) { 92144ed791bSMarcel Moolenaar sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; 92227d5dc18SMarcel Moolenaar break; 92344ed791bSMarcel Moolenaar } 92427d5dc18SMarcel Moolenaar xc = uart_getreg(bas, REG_DATA); 92527d5dc18SMarcel Moolenaar if (lsr & LSR_FE) 92627d5dc18SMarcel Moolenaar xc |= UART_STAT_FRAMERR; 92727d5dc18SMarcel Moolenaar if (lsr & LSR_PE) 92827d5dc18SMarcel Moolenaar xc |= UART_STAT_PARERR; 92927d5dc18SMarcel Moolenaar uart_rx_put(sc, xc); 93044ed791bSMarcel Moolenaar lsr = uart_getreg(bas, REG_LSR); 93144ed791bSMarcel Moolenaar } 93244ed791bSMarcel Moolenaar /* Discard everything left in the Rx FIFO. */ 93344ed791bSMarcel Moolenaar while (lsr & LSR_RXRDY) { 93444ed791bSMarcel Moolenaar (void)uart_getreg(bas, REG_DATA); 93544ed791bSMarcel Moolenaar uart_barrier(bas); 93644ed791bSMarcel Moolenaar lsr = uart_getreg(bas, REG_LSR); 93727d5dc18SMarcel Moolenaar } 9388af03381SMarcel Moolenaar uart_unlock(sc->sc_hwmtx); 93927d5dc18SMarcel Moolenaar return (0); 94027d5dc18SMarcel Moolenaar } 94127d5dc18SMarcel Moolenaar 942167cb33fSIan Lepore int 94327d5dc18SMarcel Moolenaar ns8250_bus_setsig(struct uart_softc *sc, int sig) 94427d5dc18SMarcel Moolenaar { 94527d5dc18SMarcel Moolenaar struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 94627d5dc18SMarcel Moolenaar struct uart_bas *bas; 94727d5dc18SMarcel Moolenaar uint32_t new, old; 94827d5dc18SMarcel Moolenaar 94927d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 95027d5dc18SMarcel Moolenaar do { 95127d5dc18SMarcel Moolenaar old = sc->sc_hwsig; 95227d5dc18SMarcel Moolenaar new = old; 95328710806SPoul-Henning Kamp if (sig & SER_DDTR) { 954fdfbb3f5SIan Lepore new = (new & ~SER_DTR) | (sig & (SER_DTR | SER_DDTR)); 95527d5dc18SMarcel Moolenaar } 95628710806SPoul-Henning Kamp if (sig & SER_DRTS) { 957fdfbb3f5SIan Lepore new = (new & ~SER_RTS) | (sig & (SER_RTS | SER_DRTS)); 95827d5dc18SMarcel Moolenaar } 95927d5dc18SMarcel Moolenaar } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 9608af03381SMarcel Moolenaar uart_lock(sc->sc_hwmtx); 96127d5dc18SMarcel Moolenaar ns8250->mcr &= ~(MCR_DTR|MCR_RTS); 96228710806SPoul-Henning Kamp if (new & SER_DTR) 96327d5dc18SMarcel Moolenaar ns8250->mcr |= MCR_DTR; 96428710806SPoul-Henning Kamp if (new & SER_RTS) 96527d5dc18SMarcel Moolenaar ns8250->mcr |= MCR_RTS; 96627d5dc18SMarcel Moolenaar uart_setreg(bas, REG_MCR, ns8250->mcr); 96727d5dc18SMarcel Moolenaar uart_barrier(bas); 9688af03381SMarcel Moolenaar uart_unlock(sc->sc_hwmtx); 96927d5dc18SMarcel Moolenaar return (0); 97027d5dc18SMarcel Moolenaar } 97127d5dc18SMarcel Moolenaar 972167cb33fSIan Lepore int 97327d5dc18SMarcel Moolenaar ns8250_bus_transmit(struct uart_softc *sc) 97427d5dc18SMarcel Moolenaar { 97527d5dc18SMarcel Moolenaar struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 97627d5dc18SMarcel Moolenaar struct uart_bas *bas; 97727d5dc18SMarcel Moolenaar int i; 97827d5dc18SMarcel Moolenaar 97927d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 9808af03381SMarcel Moolenaar uart_lock(sc->sc_hwmtx); 98127d5dc18SMarcel Moolenaar while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0) 98227d5dc18SMarcel Moolenaar ; 98327d5dc18SMarcel Moolenaar for (i = 0; i < sc->sc_txdatasz; i++) { 98427d5dc18SMarcel Moolenaar uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]); 98527d5dc18SMarcel Moolenaar uart_barrier(bas); 98627d5dc18SMarcel Moolenaar } 9873c7b9077SMichal Meloun uart_setreg(bas, REG_IER, ns8250->ier | IER_ETXRDY); 9883c7b9077SMichal Meloun uart_barrier(bas); 9891c60b24bSColin Percival if (broken_txfifo) 9901c60b24bSColin Percival ns8250_drain(bas, UART_DRAIN_TRANSMITTER); 9911c60b24bSColin Percival else 99227d5dc18SMarcel Moolenaar sc->sc_txbusy = 1; 9938af03381SMarcel Moolenaar uart_unlock(sc->sc_hwmtx); 9941c60b24bSColin Percival if (broken_txfifo) 9951c60b24bSColin Percival uart_sched_softih(sc, SER_INT_TXIDLE); 99627d5dc18SMarcel Moolenaar return (0); 99727d5dc18SMarcel Moolenaar } 998d76a1ef4SWarner Losh 999d76a1ef4SWarner Losh void 1000d76a1ef4SWarner Losh ns8250_bus_grab(struct uart_softc *sc) 1001d76a1ef4SWarner Losh { 1002d76a1ef4SWarner Losh struct uart_bas *bas = &sc->sc_bas; 1003caf6d6b4SOlivier Houchard struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 10048bc9a079SOlivier Houchard u_char ier; 1005d76a1ef4SWarner Losh 1006d76a1ef4SWarner Losh /* 1007d76a1ef4SWarner Losh * turn off all interrupts to enter polling mode. Leave the 1008d76a1ef4SWarner Losh * saved mask alone. We'll restore whatever it was in ungrab. 1009d76a1ef4SWarner Losh * All pending interupt signals are reset when IER is set to 0. 1010d76a1ef4SWarner Losh */ 1011d76a1ef4SWarner Losh uart_lock(sc->sc_hwmtx); 10128bc9a079SOlivier Houchard ier = uart_getreg(bas, REG_IER); 10138bc9a079SOlivier Houchard uart_setreg(bas, REG_IER, ier & ns8250->ier_mask); 1014d76a1ef4SWarner Losh uart_barrier(bas); 1015d76a1ef4SWarner Losh uart_unlock(sc->sc_hwmtx); 1016d76a1ef4SWarner Losh } 1017d76a1ef4SWarner Losh 1018d76a1ef4SWarner Losh void 1019d76a1ef4SWarner Losh ns8250_bus_ungrab(struct uart_softc *sc) 1020d76a1ef4SWarner Losh { 1021d76a1ef4SWarner Losh struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 1022d76a1ef4SWarner Losh struct uart_bas *bas = &sc->sc_bas; 1023d76a1ef4SWarner Losh 1024d76a1ef4SWarner Losh /* 1025d76a1ef4SWarner Losh * Restore previous interrupt mask 1026d76a1ef4SWarner Losh */ 1027d76a1ef4SWarner Losh uart_lock(sc->sc_hwmtx); 1028d76a1ef4SWarner Losh uart_setreg(bas, REG_IER, ns8250->ier); 1029d76a1ef4SWarner Losh uart_barrier(bas); 1030d76a1ef4SWarner Losh uart_unlock(sc->sc_hwmtx); 1031d76a1ef4SWarner Losh } 1032