127d5dc18SMarcel Moolenaar /* 227d5dc18SMarcel Moolenaar * Copyright (c) 2003 Marcel Moolenaar 327d5dc18SMarcel Moolenaar * All rights reserved. 427d5dc18SMarcel Moolenaar * 527d5dc18SMarcel Moolenaar * Redistribution and use in source and binary forms, with or without 627d5dc18SMarcel Moolenaar * modification, are permitted provided that the following conditions 727d5dc18SMarcel Moolenaar * are met: 827d5dc18SMarcel Moolenaar * 927d5dc18SMarcel Moolenaar * 1. Redistributions of source code must retain the above copyright 1027d5dc18SMarcel Moolenaar * notice, this list of conditions and the following disclaimer. 1127d5dc18SMarcel Moolenaar * 2. Redistributions in binary form must reproduce the above copyright 1227d5dc18SMarcel Moolenaar * notice, this list of conditions and the following disclaimer in the 1327d5dc18SMarcel Moolenaar * documentation and/or other materials provided with the distribution. 1427d5dc18SMarcel Moolenaar * 1527d5dc18SMarcel Moolenaar * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 1627d5dc18SMarcel Moolenaar * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 1727d5dc18SMarcel Moolenaar * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 1827d5dc18SMarcel Moolenaar * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 1927d5dc18SMarcel Moolenaar * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 2027d5dc18SMarcel Moolenaar * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2127d5dc18SMarcel Moolenaar * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2227d5dc18SMarcel Moolenaar * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2327d5dc18SMarcel Moolenaar * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 2427d5dc18SMarcel Moolenaar * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2527d5dc18SMarcel Moolenaar */ 2627d5dc18SMarcel Moolenaar 2727d5dc18SMarcel Moolenaar #include <sys/cdefs.h> 2827d5dc18SMarcel Moolenaar __FBSDID("$FreeBSD$"); 2927d5dc18SMarcel Moolenaar 3027d5dc18SMarcel Moolenaar #include <sys/param.h> 3127d5dc18SMarcel Moolenaar #include <sys/systm.h> 3227d5dc18SMarcel Moolenaar #include <sys/bus.h> 3327d5dc18SMarcel Moolenaar #include <sys/conf.h> 3427d5dc18SMarcel Moolenaar #include <machine/bus.h> 3527d5dc18SMarcel Moolenaar 3627d5dc18SMarcel Moolenaar #include <dev/uart/uart.h> 3727d5dc18SMarcel Moolenaar #include <dev/uart/uart_cpu.h> 3827d5dc18SMarcel Moolenaar #include <dev/uart/uart_bus.h> 3927d5dc18SMarcel Moolenaar #include <dev/uart/uart_dev_ns8250.h> 4027d5dc18SMarcel Moolenaar 4127d5dc18SMarcel Moolenaar #include "uart_if.h" 4227d5dc18SMarcel Moolenaar 4327d5dc18SMarcel Moolenaar #define DEFAULT_RCLK 1843200 4427d5dc18SMarcel Moolenaar 4527d5dc18SMarcel Moolenaar /* 4627d5dc18SMarcel Moolenaar * Clear pending interrupts. THRE is cleared by reading IIR. Data 4727d5dc18SMarcel Moolenaar * that may have been received gets lost here. 4827d5dc18SMarcel Moolenaar */ 4927d5dc18SMarcel Moolenaar static void 5027d5dc18SMarcel Moolenaar ns8250_clrint(struct uart_bas *bas) 5127d5dc18SMarcel Moolenaar { 5227d5dc18SMarcel Moolenaar uint8_t iir; 5327d5dc18SMarcel Moolenaar 5427d5dc18SMarcel Moolenaar iir = uart_getreg(bas, REG_IIR); 5527d5dc18SMarcel Moolenaar while ((iir & IIR_NOPEND) == 0) { 5627d5dc18SMarcel Moolenaar iir &= IIR_IMASK; 5727d5dc18SMarcel Moolenaar if (iir == IIR_RLS) 5827d5dc18SMarcel Moolenaar (void)uart_getreg(bas, REG_LSR); 5927d5dc18SMarcel Moolenaar else if (iir == IIR_RXRDY || iir == IIR_RXTOUT) 6027d5dc18SMarcel Moolenaar (void)uart_getreg(bas, REG_DATA); 6127d5dc18SMarcel Moolenaar else if (iir == IIR_MLSC) 6227d5dc18SMarcel Moolenaar (void)uart_getreg(bas, REG_MSR); 6327d5dc18SMarcel Moolenaar uart_barrier(bas); 6427d5dc18SMarcel Moolenaar iir = uart_getreg(bas, REG_IIR); 6527d5dc18SMarcel Moolenaar } 6627d5dc18SMarcel Moolenaar } 6727d5dc18SMarcel Moolenaar 6827d5dc18SMarcel Moolenaar static int 6927d5dc18SMarcel Moolenaar ns8250_delay(struct uart_bas *bas) 7027d5dc18SMarcel Moolenaar { 7127d5dc18SMarcel Moolenaar int divisor; 7227d5dc18SMarcel Moolenaar u_char lcr; 7327d5dc18SMarcel Moolenaar 7427d5dc18SMarcel Moolenaar lcr = uart_getreg(bas, REG_LCR); 7527d5dc18SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 7627d5dc18SMarcel Moolenaar uart_barrier(bas); 7727d5dc18SMarcel Moolenaar divisor = uart_getdreg(bas, REG_DL); 7827d5dc18SMarcel Moolenaar uart_barrier(bas); 7927d5dc18SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr); 8027d5dc18SMarcel Moolenaar uart_barrier(bas); 8127d5dc18SMarcel Moolenaar 8227d5dc18SMarcel Moolenaar /* 1/10th the time to transmit 1 character (estimate). */ 8327d5dc18SMarcel Moolenaar return (16000000 * divisor / bas->rclk); 8427d5dc18SMarcel Moolenaar } 8527d5dc18SMarcel Moolenaar 8627d5dc18SMarcel Moolenaar static int 8727d5dc18SMarcel Moolenaar ns8250_divisor(int rclk, int baudrate) 8827d5dc18SMarcel Moolenaar { 8927d5dc18SMarcel Moolenaar int actual_baud, divisor; 9027d5dc18SMarcel Moolenaar int error; 9127d5dc18SMarcel Moolenaar 9227d5dc18SMarcel Moolenaar if (baudrate == 0) 9327d5dc18SMarcel Moolenaar return (0); 9427d5dc18SMarcel Moolenaar 9527d5dc18SMarcel Moolenaar divisor = (rclk / (baudrate << 3) + 1) >> 1; 9627d5dc18SMarcel Moolenaar if (divisor == 0 || divisor >= 65536) 9727d5dc18SMarcel Moolenaar return (0); 9827d5dc18SMarcel Moolenaar actual_baud = rclk / (divisor << 4); 9927d5dc18SMarcel Moolenaar 10027d5dc18SMarcel Moolenaar /* 10 times error in percent: */ 10127d5dc18SMarcel Moolenaar error = ((actual_baud - baudrate) * 2000 / baudrate + 1) >> 1; 10227d5dc18SMarcel Moolenaar 10327d5dc18SMarcel Moolenaar /* 3.0% maximum error tolerance: */ 10427d5dc18SMarcel Moolenaar if (error < -30 || error > 30) 10527d5dc18SMarcel Moolenaar return (0); 10627d5dc18SMarcel Moolenaar 10727d5dc18SMarcel Moolenaar return (divisor); 10827d5dc18SMarcel Moolenaar } 10927d5dc18SMarcel Moolenaar 11027d5dc18SMarcel Moolenaar static int 11127d5dc18SMarcel Moolenaar ns8250_drain(struct uart_bas *bas, int what) 11227d5dc18SMarcel Moolenaar { 11327d5dc18SMarcel Moolenaar int delay, limit; 11427d5dc18SMarcel Moolenaar 11527d5dc18SMarcel Moolenaar delay = ns8250_delay(bas); 11627d5dc18SMarcel Moolenaar 11727d5dc18SMarcel Moolenaar if (what & UART_DRAIN_TRANSMITTER) { 11827d5dc18SMarcel Moolenaar /* 11927d5dc18SMarcel Moolenaar * Pick an arbitrary high limit to avoid getting stuck in 12027d5dc18SMarcel Moolenaar * an infinite loop when the hardware is broken. Make the 12127d5dc18SMarcel Moolenaar * limit high enough to handle large FIFOs. 12227d5dc18SMarcel Moolenaar */ 12327d5dc18SMarcel Moolenaar limit = 10*1024; 12427d5dc18SMarcel Moolenaar while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) 12527d5dc18SMarcel Moolenaar DELAY(delay); 12627d5dc18SMarcel Moolenaar if (limit == 0) { 12727d5dc18SMarcel Moolenaar /* printf("ns8250: transmitter appears stuck... "); */ 12827d5dc18SMarcel Moolenaar return (EIO); 12927d5dc18SMarcel Moolenaar } 13027d5dc18SMarcel Moolenaar } 13127d5dc18SMarcel Moolenaar 13227d5dc18SMarcel Moolenaar if (what & UART_DRAIN_RECEIVER) { 13327d5dc18SMarcel Moolenaar /* 13427d5dc18SMarcel Moolenaar * Pick an arbitrary high limit to avoid getting stuck in 13527d5dc18SMarcel Moolenaar * an infinite loop when the hardware is broken. Make the 13627d5dc18SMarcel Moolenaar * limit high enough to handle large FIFOs and integrated 13727d5dc18SMarcel Moolenaar * UARTs. The HP rx2600 for example has 3 UARTs on the 13827d5dc18SMarcel Moolenaar * management board that tend to get a lot of data send 13927d5dc18SMarcel Moolenaar * to it when the UART is first activated. 14027d5dc18SMarcel Moolenaar */ 14127d5dc18SMarcel Moolenaar limit=10*4096; 14227d5dc18SMarcel Moolenaar while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) { 14327d5dc18SMarcel Moolenaar (void)uart_getreg(bas, REG_DATA); 14427d5dc18SMarcel Moolenaar uart_barrier(bas); 14527d5dc18SMarcel Moolenaar DELAY(delay << 2); 14627d5dc18SMarcel Moolenaar } 14727d5dc18SMarcel Moolenaar if (limit == 0) { 14827d5dc18SMarcel Moolenaar /* printf("ns8250: receiver appears broken... "); */ 14927d5dc18SMarcel Moolenaar return (EIO); 15027d5dc18SMarcel Moolenaar } 15127d5dc18SMarcel Moolenaar } 15227d5dc18SMarcel Moolenaar 15327d5dc18SMarcel Moolenaar return (0); 15427d5dc18SMarcel Moolenaar } 15527d5dc18SMarcel Moolenaar 15627d5dc18SMarcel Moolenaar /* 15727d5dc18SMarcel Moolenaar * We can only flush UARTs with FIFOs. UARTs without FIFOs should be 15827d5dc18SMarcel Moolenaar * drained. WARNING: this function clobbers the FIFO setting! 15927d5dc18SMarcel Moolenaar */ 16027d5dc18SMarcel Moolenaar static void 16127d5dc18SMarcel Moolenaar ns8250_flush(struct uart_bas *bas, int what) 16227d5dc18SMarcel Moolenaar { 16327d5dc18SMarcel Moolenaar uint8_t fcr; 16427d5dc18SMarcel Moolenaar 16527d5dc18SMarcel Moolenaar fcr = FCR_ENABLE; 16627d5dc18SMarcel Moolenaar if (what & UART_FLUSH_TRANSMITTER) 16727d5dc18SMarcel Moolenaar fcr |= FCR_XMT_RST; 16827d5dc18SMarcel Moolenaar if (what & UART_FLUSH_RECEIVER) 16927d5dc18SMarcel Moolenaar fcr |= FCR_RCV_RST; 17027d5dc18SMarcel Moolenaar uart_setreg(bas, REG_FCR, fcr); 17127d5dc18SMarcel Moolenaar uart_barrier(bas); 17227d5dc18SMarcel Moolenaar } 17327d5dc18SMarcel Moolenaar 17427d5dc18SMarcel Moolenaar static int 17527d5dc18SMarcel Moolenaar ns8250_param(struct uart_bas *bas, int baudrate, int databits, int stopbits, 17627d5dc18SMarcel Moolenaar int parity) 17727d5dc18SMarcel Moolenaar { 17827d5dc18SMarcel Moolenaar int divisor; 17927d5dc18SMarcel Moolenaar uint8_t lcr; 18027d5dc18SMarcel Moolenaar 18127d5dc18SMarcel Moolenaar lcr = 0; 18227d5dc18SMarcel Moolenaar if (databits >= 8) 18327d5dc18SMarcel Moolenaar lcr |= LCR_8BITS; 18427d5dc18SMarcel Moolenaar else if (databits == 7) 18527d5dc18SMarcel Moolenaar lcr |= LCR_7BITS; 18627d5dc18SMarcel Moolenaar else if (databits == 6) 18727d5dc18SMarcel Moolenaar lcr |= LCR_6BITS; 18827d5dc18SMarcel Moolenaar else 18927d5dc18SMarcel Moolenaar lcr |= LCR_5BITS; 19027d5dc18SMarcel Moolenaar if (stopbits > 1) 19127d5dc18SMarcel Moolenaar lcr |= LCR_STOPB; 19227d5dc18SMarcel Moolenaar lcr |= parity << 3; 19327d5dc18SMarcel Moolenaar 19427d5dc18SMarcel Moolenaar /* Set baudrate. */ 19527d5dc18SMarcel Moolenaar if (baudrate > 0) { 19627d5dc18SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 19727d5dc18SMarcel Moolenaar uart_barrier(bas); 19827d5dc18SMarcel Moolenaar divisor = ns8250_divisor(bas->rclk, baudrate); 19927d5dc18SMarcel Moolenaar if (divisor == 0) 20027d5dc18SMarcel Moolenaar return (EINVAL); 20127d5dc18SMarcel Moolenaar uart_setdreg(bas, REG_DL, divisor); 20227d5dc18SMarcel Moolenaar uart_barrier(bas); 20327d5dc18SMarcel Moolenaar } 20427d5dc18SMarcel Moolenaar 20527d5dc18SMarcel Moolenaar /* Set LCR and clear DLAB. */ 20627d5dc18SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr); 20727d5dc18SMarcel Moolenaar uart_barrier(bas); 20827d5dc18SMarcel Moolenaar return (0); 20927d5dc18SMarcel Moolenaar } 21027d5dc18SMarcel Moolenaar 21127d5dc18SMarcel Moolenaar /* 21227d5dc18SMarcel Moolenaar * Low-level UART interface. 21327d5dc18SMarcel Moolenaar */ 21427d5dc18SMarcel Moolenaar static int ns8250_probe(struct uart_bas *bas); 21527d5dc18SMarcel Moolenaar static void ns8250_init(struct uart_bas *bas, int, int, int, int); 21627d5dc18SMarcel Moolenaar static void ns8250_term(struct uart_bas *bas); 21727d5dc18SMarcel Moolenaar static void ns8250_putc(struct uart_bas *bas, int); 21827d5dc18SMarcel Moolenaar static int ns8250_poll(struct uart_bas *bas); 21927d5dc18SMarcel Moolenaar static int ns8250_getc(struct uart_bas *bas); 22027d5dc18SMarcel Moolenaar 22127d5dc18SMarcel Moolenaar struct uart_ops uart_ns8250_ops = { 22227d5dc18SMarcel Moolenaar .probe = ns8250_probe, 22327d5dc18SMarcel Moolenaar .init = ns8250_init, 22427d5dc18SMarcel Moolenaar .term = ns8250_term, 22527d5dc18SMarcel Moolenaar .putc = ns8250_putc, 22627d5dc18SMarcel Moolenaar .poll = ns8250_poll, 22727d5dc18SMarcel Moolenaar .getc = ns8250_getc, 22827d5dc18SMarcel Moolenaar }; 22927d5dc18SMarcel Moolenaar 23027d5dc18SMarcel Moolenaar static int 23127d5dc18SMarcel Moolenaar ns8250_probe(struct uart_bas *bas) 23227d5dc18SMarcel Moolenaar { 23327d5dc18SMarcel Moolenaar u_char lcr, val; 23427d5dc18SMarcel Moolenaar 23527d5dc18SMarcel Moolenaar /* Check known 0 bits that don't depend on DLAB. */ 23627d5dc18SMarcel Moolenaar val = uart_getreg(bas, REG_IIR); 23727d5dc18SMarcel Moolenaar if (val & 0x30) 23827d5dc18SMarcel Moolenaar return (ENXIO); 23927d5dc18SMarcel Moolenaar val = uart_getreg(bas, REG_MCR); 24027d5dc18SMarcel Moolenaar if (val & 0xe0) 24127d5dc18SMarcel Moolenaar return (ENXIO); 24227d5dc18SMarcel Moolenaar 24327d5dc18SMarcel Moolenaar lcr = uart_getreg(bas, REG_LCR); 24427d5dc18SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr & ~LCR_DLAB); 24527d5dc18SMarcel Moolenaar uart_barrier(bas); 24627d5dc18SMarcel Moolenaar 24727d5dc18SMarcel Moolenaar /* Check known 0 bits that depend on !DLAB. */ 24827d5dc18SMarcel Moolenaar val = uart_getreg(bas, REG_IER); 24927d5dc18SMarcel Moolenaar if (val & 0xf0) 25027d5dc18SMarcel Moolenaar goto fail; 25127d5dc18SMarcel Moolenaar 25227d5dc18SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr); 25327d5dc18SMarcel Moolenaar uart_barrier(bas); 25427d5dc18SMarcel Moolenaar return (0); 25527d5dc18SMarcel Moolenaar 25627d5dc18SMarcel Moolenaar fail: 25727d5dc18SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr); 25827d5dc18SMarcel Moolenaar uart_barrier(bas); 25927d5dc18SMarcel Moolenaar return (ENXIO); 26027d5dc18SMarcel Moolenaar } 26127d5dc18SMarcel Moolenaar 26227d5dc18SMarcel Moolenaar static void 26327d5dc18SMarcel Moolenaar ns8250_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, 26427d5dc18SMarcel Moolenaar int parity) 26527d5dc18SMarcel Moolenaar { 26627d5dc18SMarcel Moolenaar 26727d5dc18SMarcel Moolenaar if (bas->rclk == 0) 26827d5dc18SMarcel Moolenaar bas->rclk = DEFAULT_RCLK; 26927d5dc18SMarcel Moolenaar ns8250_param(bas, baudrate, databits, stopbits, parity); 27027d5dc18SMarcel Moolenaar 27127d5dc18SMarcel Moolenaar /* Disable all interrupt sources. */ 27227d5dc18SMarcel Moolenaar uart_setreg(bas, REG_IER, 0); 27327d5dc18SMarcel Moolenaar uart_barrier(bas); 27427d5dc18SMarcel Moolenaar 27527d5dc18SMarcel Moolenaar /* Disable the FIFO (if present). */ 27627d5dc18SMarcel Moolenaar uart_setreg(bas, REG_FCR, 0); 27727d5dc18SMarcel Moolenaar uart_barrier(bas); 27827d5dc18SMarcel Moolenaar 27927d5dc18SMarcel Moolenaar /* Set RTS & DTR. */ 28027d5dc18SMarcel Moolenaar uart_setreg(bas, REG_MCR, MCR_IE | MCR_RTS | MCR_DTR); 28127d5dc18SMarcel Moolenaar uart_barrier(bas); 28227d5dc18SMarcel Moolenaar 28327d5dc18SMarcel Moolenaar ns8250_clrint(bas); 28427d5dc18SMarcel Moolenaar } 28527d5dc18SMarcel Moolenaar 28627d5dc18SMarcel Moolenaar static void 28727d5dc18SMarcel Moolenaar ns8250_term(struct uart_bas *bas) 28827d5dc18SMarcel Moolenaar { 28927d5dc18SMarcel Moolenaar 29027d5dc18SMarcel Moolenaar /* Clear RTS & DTR. */ 29127d5dc18SMarcel Moolenaar uart_setreg(bas, REG_MCR, MCR_IE); 29227d5dc18SMarcel Moolenaar uart_barrier(bas); 29327d5dc18SMarcel Moolenaar } 29427d5dc18SMarcel Moolenaar 29527d5dc18SMarcel Moolenaar static void 29627d5dc18SMarcel Moolenaar ns8250_putc(struct uart_bas *bas, int c) 29727d5dc18SMarcel Moolenaar { 29827d5dc18SMarcel Moolenaar int delay, limit; 29927d5dc18SMarcel Moolenaar 30027d5dc18SMarcel Moolenaar /* 1/10th the time to transmit 1 character (estimate). */ 30127d5dc18SMarcel Moolenaar delay = ns8250_delay(bas); 30227d5dc18SMarcel Moolenaar 30327d5dc18SMarcel Moolenaar limit = 20; 30427d5dc18SMarcel Moolenaar while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0 && --limit) 30527d5dc18SMarcel Moolenaar DELAY(delay); 30627d5dc18SMarcel Moolenaar uart_setreg(bas, REG_DATA, c); 3074e55f723SMarcel Moolenaar uart_barrier(bas); 30827d5dc18SMarcel Moolenaar limit = 40; 30927d5dc18SMarcel Moolenaar while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) 31027d5dc18SMarcel Moolenaar DELAY(delay); 31127d5dc18SMarcel Moolenaar } 31227d5dc18SMarcel Moolenaar 31327d5dc18SMarcel Moolenaar static int 31427d5dc18SMarcel Moolenaar ns8250_poll(struct uart_bas *bas) 31527d5dc18SMarcel Moolenaar { 31627d5dc18SMarcel Moolenaar 31727d5dc18SMarcel Moolenaar if (uart_getreg(bas, REG_LSR) & LSR_RXRDY) 31827d5dc18SMarcel Moolenaar return (uart_getreg(bas, REG_DATA)); 31927d5dc18SMarcel Moolenaar return (-1); 32027d5dc18SMarcel Moolenaar } 32127d5dc18SMarcel Moolenaar 32227d5dc18SMarcel Moolenaar static int 32327d5dc18SMarcel Moolenaar ns8250_getc(struct uart_bas *bas) 32427d5dc18SMarcel Moolenaar { 32527d5dc18SMarcel Moolenaar int delay; 32627d5dc18SMarcel Moolenaar 32727d5dc18SMarcel Moolenaar /* 1/10th the time to transmit 1 character (estimate). */ 32827d5dc18SMarcel Moolenaar delay = ns8250_delay(bas); 32927d5dc18SMarcel Moolenaar 33027d5dc18SMarcel Moolenaar while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0) 33127d5dc18SMarcel Moolenaar DELAY(delay); 33227d5dc18SMarcel Moolenaar return (uart_getreg(bas, REG_DATA)); 33327d5dc18SMarcel Moolenaar } 33427d5dc18SMarcel Moolenaar 33527d5dc18SMarcel Moolenaar /* 33627d5dc18SMarcel Moolenaar * High-level UART interface. 33727d5dc18SMarcel Moolenaar */ 33827d5dc18SMarcel Moolenaar struct ns8250_softc { 33927d5dc18SMarcel Moolenaar struct uart_softc base; 34027d5dc18SMarcel Moolenaar uint8_t fcr; 34127d5dc18SMarcel Moolenaar uint8_t ier; 34227d5dc18SMarcel Moolenaar uint8_t mcr; 34327d5dc18SMarcel Moolenaar }; 34427d5dc18SMarcel Moolenaar 34527d5dc18SMarcel Moolenaar static int ns8250_bus_attach(struct uart_softc *); 34627d5dc18SMarcel Moolenaar static int ns8250_bus_detach(struct uart_softc *); 34727d5dc18SMarcel Moolenaar static int ns8250_bus_flush(struct uart_softc *, int); 34827d5dc18SMarcel Moolenaar static int ns8250_bus_getsig(struct uart_softc *); 34927d5dc18SMarcel Moolenaar static int ns8250_bus_ioctl(struct uart_softc *, int, intptr_t); 35027d5dc18SMarcel Moolenaar static int ns8250_bus_ipend(struct uart_softc *); 35127d5dc18SMarcel Moolenaar static int ns8250_bus_param(struct uart_softc *, int, int, int, int); 35227d5dc18SMarcel Moolenaar static int ns8250_bus_probe(struct uart_softc *); 35327d5dc18SMarcel Moolenaar static int ns8250_bus_receive(struct uart_softc *); 35427d5dc18SMarcel Moolenaar static int ns8250_bus_setsig(struct uart_softc *, int); 35527d5dc18SMarcel Moolenaar static int ns8250_bus_transmit(struct uart_softc *); 35627d5dc18SMarcel Moolenaar 35727d5dc18SMarcel Moolenaar static kobj_method_t ns8250_methods[] = { 35827d5dc18SMarcel Moolenaar KOBJMETHOD(uart_attach, ns8250_bus_attach), 35927d5dc18SMarcel Moolenaar KOBJMETHOD(uart_detach, ns8250_bus_detach), 36027d5dc18SMarcel Moolenaar KOBJMETHOD(uart_flush, ns8250_bus_flush), 36127d5dc18SMarcel Moolenaar KOBJMETHOD(uart_getsig, ns8250_bus_getsig), 36227d5dc18SMarcel Moolenaar KOBJMETHOD(uart_ioctl, ns8250_bus_ioctl), 36327d5dc18SMarcel Moolenaar KOBJMETHOD(uart_ipend, ns8250_bus_ipend), 36427d5dc18SMarcel Moolenaar KOBJMETHOD(uart_param, ns8250_bus_param), 36527d5dc18SMarcel Moolenaar KOBJMETHOD(uart_probe, ns8250_bus_probe), 36627d5dc18SMarcel Moolenaar KOBJMETHOD(uart_receive, ns8250_bus_receive), 36727d5dc18SMarcel Moolenaar KOBJMETHOD(uart_setsig, ns8250_bus_setsig), 36827d5dc18SMarcel Moolenaar KOBJMETHOD(uart_transmit, ns8250_bus_transmit), 36927d5dc18SMarcel Moolenaar { 0, 0 } 37027d5dc18SMarcel Moolenaar }; 37127d5dc18SMarcel Moolenaar 37227d5dc18SMarcel Moolenaar struct uart_class uart_ns8250_class = { 37327d5dc18SMarcel Moolenaar "ns8250 class", 37427d5dc18SMarcel Moolenaar ns8250_methods, 37527d5dc18SMarcel Moolenaar sizeof(struct ns8250_softc), 37627d5dc18SMarcel Moolenaar .uc_range = 8, 37727d5dc18SMarcel Moolenaar .uc_rclk = DEFAULT_RCLK 37827d5dc18SMarcel Moolenaar }; 37927d5dc18SMarcel Moolenaar 38027d5dc18SMarcel Moolenaar #define SIGCHG(c, i, s, d) \ 38127d5dc18SMarcel Moolenaar if (c) { \ 38227d5dc18SMarcel Moolenaar i |= (i & s) ? s : s | d; \ 38327d5dc18SMarcel Moolenaar } else { \ 38427d5dc18SMarcel Moolenaar i = (i & s) ? (i & ~s) | d : i; \ 38527d5dc18SMarcel Moolenaar } 38627d5dc18SMarcel Moolenaar 38727d5dc18SMarcel Moolenaar static int 38827d5dc18SMarcel Moolenaar ns8250_bus_attach(struct uart_softc *sc) 38927d5dc18SMarcel Moolenaar { 39027d5dc18SMarcel Moolenaar struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 39127d5dc18SMarcel Moolenaar struct uart_bas *bas; 39227d5dc18SMarcel Moolenaar 39327d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 39427d5dc18SMarcel Moolenaar 39527d5dc18SMarcel Moolenaar ns8250->mcr = uart_getreg(bas, REG_MCR); 39627d5dc18SMarcel Moolenaar ns8250->fcr = FCR_ENABLE | FCR_RX_MEDH; 39727d5dc18SMarcel Moolenaar uart_setreg(bas, REG_FCR, ns8250->fcr); 39827d5dc18SMarcel Moolenaar uart_barrier(bas); 39927d5dc18SMarcel Moolenaar ns8250_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 40027d5dc18SMarcel Moolenaar 40127d5dc18SMarcel Moolenaar if (ns8250->mcr & MCR_DTR) 40227d5dc18SMarcel Moolenaar sc->sc_hwsig |= UART_SIG_DTR; 40327d5dc18SMarcel Moolenaar if (ns8250->mcr & MCR_RTS) 40427d5dc18SMarcel Moolenaar sc->sc_hwsig |= UART_SIG_RTS; 40527d5dc18SMarcel Moolenaar ns8250_bus_getsig(sc); 40627d5dc18SMarcel Moolenaar 40727d5dc18SMarcel Moolenaar ns8250_clrint(bas); 40827d5dc18SMarcel Moolenaar ns8250->ier = IER_EMSC | IER_ERLS | IER_ERXRDY; 40927d5dc18SMarcel Moolenaar uart_setreg(bas, REG_IER, ns8250->ier); 41027d5dc18SMarcel Moolenaar uart_barrier(bas); 41127d5dc18SMarcel Moolenaar return (0); 41227d5dc18SMarcel Moolenaar } 41327d5dc18SMarcel Moolenaar 41427d5dc18SMarcel Moolenaar static int 41527d5dc18SMarcel Moolenaar ns8250_bus_detach(struct uart_softc *sc) 41627d5dc18SMarcel Moolenaar { 41727d5dc18SMarcel Moolenaar struct uart_bas *bas; 41827d5dc18SMarcel Moolenaar 41927d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 42027d5dc18SMarcel Moolenaar uart_setreg(bas, REG_IER, 0); 42127d5dc18SMarcel Moolenaar uart_barrier(bas); 42227d5dc18SMarcel Moolenaar ns8250_clrint(bas); 42327d5dc18SMarcel Moolenaar return (0); 42427d5dc18SMarcel Moolenaar } 42527d5dc18SMarcel Moolenaar 42627d5dc18SMarcel Moolenaar static int 42727d5dc18SMarcel Moolenaar ns8250_bus_flush(struct uart_softc *sc, int what) 42827d5dc18SMarcel Moolenaar { 42927d5dc18SMarcel Moolenaar struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 43027d5dc18SMarcel Moolenaar struct uart_bas *bas; 43106287620SMarcel Moolenaar int error; 43227d5dc18SMarcel Moolenaar 43327d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 43406287620SMarcel Moolenaar mtx_lock_spin(&sc->sc_hwmtx); 43527d5dc18SMarcel Moolenaar if (sc->sc_hasfifo) { 43627d5dc18SMarcel Moolenaar ns8250_flush(bas, what); 43727d5dc18SMarcel Moolenaar uart_setreg(bas, REG_FCR, ns8250->fcr); 43827d5dc18SMarcel Moolenaar uart_barrier(bas); 43906287620SMarcel Moolenaar error = 0; 44006287620SMarcel Moolenaar } else 44106287620SMarcel Moolenaar error = ns8250_drain(bas, what); 44206287620SMarcel Moolenaar mtx_unlock_spin(&sc->sc_hwmtx); 44306287620SMarcel Moolenaar return (error); 44427d5dc18SMarcel Moolenaar } 44527d5dc18SMarcel Moolenaar 44627d5dc18SMarcel Moolenaar static int 44727d5dc18SMarcel Moolenaar ns8250_bus_getsig(struct uart_softc *sc) 44827d5dc18SMarcel Moolenaar { 44927d5dc18SMarcel Moolenaar uint32_t new, old, sig; 45027d5dc18SMarcel Moolenaar uint8_t msr; 45127d5dc18SMarcel Moolenaar 45227d5dc18SMarcel Moolenaar do { 45327d5dc18SMarcel Moolenaar old = sc->sc_hwsig; 45427d5dc18SMarcel Moolenaar sig = old; 45506287620SMarcel Moolenaar mtx_lock_spin(&sc->sc_hwmtx); 45627d5dc18SMarcel Moolenaar msr = uart_getreg(&sc->sc_bas, REG_MSR); 45706287620SMarcel Moolenaar mtx_unlock_spin(&sc->sc_hwmtx); 45827d5dc18SMarcel Moolenaar SIGCHG(msr & MSR_DSR, sig, UART_SIG_DSR, UART_SIG_DDSR); 45927d5dc18SMarcel Moolenaar SIGCHG(msr & MSR_CTS, sig, UART_SIG_CTS, UART_SIG_DCTS); 46027d5dc18SMarcel Moolenaar SIGCHG(msr & MSR_DCD, sig, UART_SIG_DCD, UART_SIG_DDCD); 46127d5dc18SMarcel Moolenaar SIGCHG(msr & MSR_RI, sig, UART_SIG_RI, UART_SIG_DRI); 46227d5dc18SMarcel Moolenaar new = sig & ~UART_SIGMASK_DELTA; 46327d5dc18SMarcel Moolenaar } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 46427d5dc18SMarcel Moolenaar return (sig); 46527d5dc18SMarcel Moolenaar } 46627d5dc18SMarcel Moolenaar 46727d5dc18SMarcel Moolenaar static int 46827d5dc18SMarcel Moolenaar ns8250_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) 46927d5dc18SMarcel Moolenaar { 47027d5dc18SMarcel Moolenaar struct uart_bas *bas; 47106287620SMarcel Moolenaar int error; 47284c7b427SMarcel Moolenaar uint8_t efr, lcr; 47327d5dc18SMarcel Moolenaar 47427d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 47506287620SMarcel Moolenaar error = 0; 47606287620SMarcel Moolenaar mtx_lock_spin(&sc->sc_hwmtx); 47727d5dc18SMarcel Moolenaar switch (request) { 47827d5dc18SMarcel Moolenaar case UART_IOCTL_BREAK: 47927d5dc18SMarcel Moolenaar lcr = uart_getreg(bas, REG_LCR); 48027d5dc18SMarcel Moolenaar if (data) 48127d5dc18SMarcel Moolenaar lcr |= LCR_SBREAK; 48227d5dc18SMarcel Moolenaar else 48327d5dc18SMarcel Moolenaar lcr &= ~LCR_SBREAK; 48427d5dc18SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr); 48527d5dc18SMarcel Moolenaar uart_barrier(bas); 48627d5dc18SMarcel Moolenaar break; 48784c7b427SMarcel Moolenaar case UART_IOCTL_IFLOW: 48884c7b427SMarcel Moolenaar lcr = uart_getreg(bas, REG_LCR); 48984c7b427SMarcel Moolenaar uart_barrier(bas); 49084c7b427SMarcel Moolenaar uart_setreg(bas, REG_LCR, 0xbf); 49184c7b427SMarcel Moolenaar uart_barrier(bas); 49284c7b427SMarcel Moolenaar efr = uart_getreg(bas, REG_EFR); 49384c7b427SMarcel Moolenaar if (data) 49484c7b427SMarcel Moolenaar efr |= EFR_RTS; 49584c7b427SMarcel Moolenaar else 49684c7b427SMarcel Moolenaar efr &= ~EFR_RTS; 49784c7b427SMarcel Moolenaar uart_setreg(bas, REG_EFR, efr); 49884c7b427SMarcel Moolenaar uart_barrier(bas); 49984c7b427SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr); 50084c7b427SMarcel Moolenaar uart_barrier(bas); 50184c7b427SMarcel Moolenaar break; 50284c7b427SMarcel Moolenaar case UART_IOCTL_OFLOW: 50384c7b427SMarcel Moolenaar lcr = uart_getreg(bas, REG_LCR); 50484c7b427SMarcel Moolenaar uart_barrier(bas); 50584c7b427SMarcel Moolenaar uart_setreg(bas, REG_LCR, 0xbf); 50684c7b427SMarcel Moolenaar uart_barrier(bas); 50784c7b427SMarcel Moolenaar efr = uart_getreg(bas, REG_EFR); 50884c7b427SMarcel Moolenaar if (data) 50984c7b427SMarcel Moolenaar efr |= EFR_CTS; 51084c7b427SMarcel Moolenaar else 51184c7b427SMarcel Moolenaar efr &= ~EFR_CTS; 51284c7b427SMarcel Moolenaar uart_setreg(bas, REG_EFR, efr); 51384c7b427SMarcel Moolenaar uart_barrier(bas); 51484c7b427SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr); 51584c7b427SMarcel Moolenaar uart_barrier(bas); 51684c7b427SMarcel Moolenaar break; 51727d5dc18SMarcel Moolenaar default: 51806287620SMarcel Moolenaar error = EINVAL; 51906287620SMarcel Moolenaar break; 52027d5dc18SMarcel Moolenaar } 52106287620SMarcel Moolenaar mtx_unlock_spin(&sc->sc_hwmtx); 52206287620SMarcel Moolenaar return (error); 52327d5dc18SMarcel Moolenaar } 52427d5dc18SMarcel Moolenaar 52527d5dc18SMarcel Moolenaar static int 52627d5dc18SMarcel Moolenaar ns8250_bus_ipend(struct uart_softc *sc) 52727d5dc18SMarcel Moolenaar { 52827d5dc18SMarcel Moolenaar struct uart_bas *bas; 52927d5dc18SMarcel Moolenaar int ipend; 53027d5dc18SMarcel Moolenaar uint8_t iir, lsr; 53127d5dc18SMarcel Moolenaar 53227d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 53306287620SMarcel Moolenaar mtx_lock_spin(&sc->sc_hwmtx); 53427d5dc18SMarcel Moolenaar iir = uart_getreg(bas, REG_IIR); 53506287620SMarcel Moolenaar if (iir & IIR_NOPEND) { 53606287620SMarcel Moolenaar mtx_unlock_spin(&sc->sc_hwmtx); 53727d5dc18SMarcel Moolenaar return (0); 53806287620SMarcel Moolenaar } 53927d5dc18SMarcel Moolenaar ipend = 0; 54027d5dc18SMarcel Moolenaar if (iir & IIR_RXRDY) { 54127d5dc18SMarcel Moolenaar lsr = uart_getreg(bas, REG_LSR); 54206287620SMarcel Moolenaar mtx_unlock_spin(&sc->sc_hwmtx); 54327d5dc18SMarcel Moolenaar if (lsr & LSR_OE) 54427d5dc18SMarcel Moolenaar ipend |= UART_IPEND_OVERRUN; 54527d5dc18SMarcel Moolenaar if (lsr & LSR_BI) 54627d5dc18SMarcel Moolenaar ipend |= UART_IPEND_BREAK; 54727d5dc18SMarcel Moolenaar if (lsr & LSR_RXRDY) 54827d5dc18SMarcel Moolenaar ipend |= UART_IPEND_RXREADY; 54927d5dc18SMarcel Moolenaar } else { 55006287620SMarcel Moolenaar mtx_unlock_spin(&sc->sc_hwmtx); 55127d5dc18SMarcel Moolenaar if (iir & IIR_TXRDY) 55227d5dc18SMarcel Moolenaar ipend |= UART_IPEND_TXIDLE; 55327d5dc18SMarcel Moolenaar else 55427d5dc18SMarcel Moolenaar ipend |= UART_IPEND_SIGCHG; 55527d5dc18SMarcel Moolenaar } 55627d5dc18SMarcel Moolenaar return ((sc->sc_leaving) ? 0 : ipend); 55727d5dc18SMarcel Moolenaar } 55827d5dc18SMarcel Moolenaar 55927d5dc18SMarcel Moolenaar static int 56027d5dc18SMarcel Moolenaar ns8250_bus_param(struct uart_softc *sc, int baudrate, int databits, 56127d5dc18SMarcel Moolenaar int stopbits, int parity) 56227d5dc18SMarcel Moolenaar { 56327d5dc18SMarcel Moolenaar struct uart_bas *bas; 56406287620SMarcel Moolenaar int error; 56527d5dc18SMarcel Moolenaar 56627d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 56706287620SMarcel Moolenaar mtx_lock_spin(&sc->sc_hwmtx); 56806287620SMarcel Moolenaar error = ns8250_param(bas, baudrate, databits, stopbits, parity); 56906287620SMarcel Moolenaar mtx_unlock_spin(&sc->sc_hwmtx); 57006287620SMarcel Moolenaar return (error); 57127d5dc18SMarcel Moolenaar } 57227d5dc18SMarcel Moolenaar 57327d5dc18SMarcel Moolenaar static int 57427d5dc18SMarcel Moolenaar ns8250_bus_probe(struct uart_softc *sc) 57527d5dc18SMarcel Moolenaar { 57627d5dc18SMarcel Moolenaar struct uart_bas *bas; 57727d5dc18SMarcel Moolenaar int count, delay, error, limit; 57827d5dc18SMarcel Moolenaar uint8_t mcr; 57927d5dc18SMarcel Moolenaar 58027d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 58127d5dc18SMarcel Moolenaar 58227d5dc18SMarcel Moolenaar error = ns8250_probe(bas); 58327d5dc18SMarcel Moolenaar if (error) 58427d5dc18SMarcel Moolenaar return (error); 58527d5dc18SMarcel Moolenaar 58627d5dc18SMarcel Moolenaar mcr = MCR_IE; 58727d5dc18SMarcel Moolenaar if (sc->sc_sysdev == NULL) { 58827d5dc18SMarcel Moolenaar /* By using ns8250_init() we also set DTR and RTS. */ 58927d5dc18SMarcel Moolenaar ns8250_init(bas, 9600, 8, 1, UART_PARITY_NONE); 59027d5dc18SMarcel Moolenaar } else 59127d5dc18SMarcel Moolenaar mcr |= MCR_DTR | MCR_RTS; 59227d5dc18SMarcel Moolenaar 59327d5dc18SMarcel Moolenaar error = ns8250_drain(bas, UART_DRAIN_TRANSMITTER); 59427d5dc18SMarcel Moolenaar if (error) 59527d5dc18SMarcel Moolenaar return (error); 59627d5dc18SMarcel Moolenaar 59727d5dc18SMarcel Moolenaar /* 59827d5dc18SMarcel Moolenaar * Set loopback mode. This avoids having garbage on the wire and 59927d5dc18SMarcel Moolenaar * also allows us send and receive data. We set DTR and RTS to 60027d5dc18SMarcel Moolenaar * avoid the possibility that automatic flow-control prevents 60127d5dc18SMarcel Moolenaar * any data from being sent. We clear IE to avoid raising interrupts. 60227d5dc18SMarcel Moolenaar */ 60327d5dc18SMarcel Moolenaar uart_setreg(bas, REG_MCR, MCR_LOOPBACK | MCR_DTR | MCR_RTS); 60427d5dc18SMarcel Moolenaar uart_barrier(bas); 60527d5dc18SMarcel Moolenaar 60627d5dc18SMarcel Moolenaar /* 60727d5dc18SMarcel Moolenaar * Enable FIFOs. And check that the UART has them. If not, we're 60827d5dc18SMarcel Moolenaar * done. Otherwise we set DMA mode with the highest trigger level 60927d5dc18SMarcel Moolenaar * so that we can determine the FIFO size. Since this is the first 61027d5dc18SMarcel Moolenaar * time we enable the FIFOs, we reset them. 61127d5dc18SMarcel Moolenaar */ 61227d5dc18SMarcel Moolenaar uart_setreg(bas, REG_FCR, FCR_ENABLE); 61327d5dc18SMarcel Moolenaar uart_barrier(bas); 61427d5dc18SMarcel Moolenaar sc->sc_hasfifo = (uart_getreg(bas, REG_IIR) & IIR_FIFO_MASK) ? 1 : 0; 61527d5dc18SMarcel Moolenaar if (!sc->sc_hasfifo) { 61627d5dc18SMarcel Moolenaar /* 61727d5dc18SMarcel Moolenaar * NS16450 or INS8250. We don't bother to differentiate 61827d5dc18SMarcel Moolenaar * between them. They're too old to be interesting. 61927d5dc18SMarcel Moolenaar */ 62027d5dc18SMarcel Moolenaar uart_setreg(bas, REG_MCR, mcr); 62127d5dc18SMarcel Moolenaar uart_barrier(bas); 62227d5dc18SMarcel Moolenaar device_set_desc(sc->sc_dev, "8250 or 16450 or compatible"); 62327d5dc18SMarcel Moolenaar return (0); 62427d5dc18SMarcel Moolenaar } 62527d5dc18SMarcel Moolenaar 62627d5dc18SMarcel Moolenaar uart_setreg(bas, REG_FCR, FCR_ENABLE | FCR_DMA | FCR_RX_HIGH | 62727d5dc18SMarcel Moolenaar FCR_XMT_RST | FCR_RCV_RST); 62827d5dc18SMarcel Moolenaar uart_barrier(bas); 62927d5dc18SMarcel Moolenaar 63027d5dc18SMarcel Moolenaar count = 0; 63127d5dc18SMarcel Moolenaar delay = ns8250_delay(bas); 63227d5dc18SMarcel Moolenaar 63327d5dc18SMarcel Moolenaar /* We have FIFOs. Drain the transmitter and receiver. */ 63427d5dc18SMarcel Moolenaar error = ns8250_drain(bas, UART_DRAIN_RECEIVER|UART_DRAIN_TRANSMITTER); 63527d5dc18SMarcel Moolenaar if (error) { 63627d5dc18SMarcel Moolenaar uart_setreg(bas, REG_MCR, mcr); 63727d5dc18SMarcel Moolenaar uart_setreg(bas, REG_FCR, 0); 63827d5dc18SMarcel Moolenaar uart_barrier(bas); 63927d5dc18SMarcel Moolenaar goto describe; 64027d5dc18SMarcel Moolenaar } 64127d5dc18SMarcel Moolenaar 64227d5dc18SMarcel Moolenaar uart_setreg(bas, REG_IER, IER_ERXRDY); 64327d5dc18SMarcel Moolenaar uart_barrier(bas); 64427d5dc18SMarcel Moolenaar 64527d5dc18SMarcel Moolenaar /* 64627d5dc18SMarcel Moolenaar * We should have a sufficiently clean "pipe" to determine the 64727d5dc18SMarcel Moolenaar * size of the FIFOs. We send as much characters as is reasonable 64827d5dc18SMarcel Moolenaar * and wait for the the RX interrupt to be asserted, counting the 64927d5dc18SMarcel Moolenaar * characters as we send them. Based on that count we know the 65027d5dc18SMarcel Moolenaar * FIFO size. 65127d5dc18SMarcel Moolenaar */ 65227d5dc18SMarcel Moolenaar while ((uart_getreg(bas, REG_IIR) & IIR_RXRDY) == 0 && count < 1030) { 65327d5dc18SMarcel Moolenaar uart_setreg(bas, REG_DATA, 0); 65427d5dc18SMarcel Moolenaar uart_barrier(bas); 65527d5dc18SMarcel Moolenaar count++; 65627d5dc18SMarcel Moolenaar 65727d5dc18SMarcel Moolenaar limit = 30; 65827d5dc18SMarcel Moolenaar while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) 65927d5dc18SMarcel Moolenaar DELAY(delay); 66027d5dc18SMarcel Moolenaar if (limit == 0) { 66127d5dc18SMarcel Moolenaar uart_setreg(bas, REG_IER, 0); 66227d5dc18SMarcel Moolenaar uart_setreg(bas, REG_MCR, mcr); 66327d5dc18SMarcel Moolenaar uart_setreg(bas, REG_FCR, 0); 66427d5dc18SMarcel Moolenaar uart_barrier(bas); 66527d5dc18SMarcel Moolenaar count = 0; 66627d5dc18SMarcel Moolenaar goto describe; 66727d5dc18SMarcel Moolenaar } 66827d5dc18SMarcel Moolenaar } 66927d5dc18SMarcel Moolenaar 67027d5dc18SMarcel Moolenaar uart_setreg(bas, REG_IER, 0); 67127d5dc18SMarcel Moolenaar uart_setreg(bas, REG_MCR, mcr); 67227d5dc18SMarcel Moolenaar 67327d5dc18SMarcel Moolenaar /* Reset FIFOs. */ 67427d5dc18SMarcel Moolenaar ns8250_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 67527d5dc18SMarcel Moolenaar 67627d5dc18SMarcel Moolenaar describe: 67727d5dc18SMarcel Moolenaar if (count >= 14 && count < 16) { 67827d5dc18SMarcel Moolenaar sc->sc_rxfifosz = 16; 67927d5dc18SMarcel Moolenaar device_set_desc(sc->sc_dev, "16550 or compatible"); 68027d5dc18SMarcel Moolenaar } else if (count >= 28 && count < 32) { 68127d5dc18SMarcel Moolenaar sc->sc_rxfifosz = 32; 68227d5dc18SMarcel Moolenaar device_set_desc(sc->sc_dev, "16650 or compatible"); 68327d5dc18SMarcel Moolenaar } else if (count >= 56 && count < 64) { 68427d5dc18SMarcel Moolenaar sc->sc_rxfifosz = 64; 68527d5dc18SMarcel Moolenaar device_set_desc(sc->sc_dev, "16750 or compatible"); 68627d5dc18SMarcel Moolenaar } else if (count >= 112 && count < 128) { 68727d5dc18SMarcel Moolenaar sc->sc_rxfifosz = 128; 68827d5dc18SMarcel Moolenaar device_set_desc(sc->sc_dev, "16950 or compatible"); 68927d5dc18SMarcel Moolenaar } else { 690c21e0da2SMarcel Moolenaar sc->sc_rxfifosz = 16; 69127d5dc18SMarcel Moolenaar device_set_desc(sc->sc_dev, 69227d5dc18SMarcel Moolenaar "Non-standard ns8250 class UART with FIFOs"); 69327d5dc18SMarcel Moolenaar } 69427d5dc18SMarcel Moolenaar 69527d5dc18SMarcel Moolenaar /* 69627d5dc18SMarcel Moolenaar * Force the Tx FIFO size to 16 bytes for now. We don't program the 69727d5dc18SMarcel Moolenaar * Tx trigger. Also, we assume that all data has been sent when the 69827d5dc18SMarcel Moolenaar * interrupt happens. 69927d5dc18SMarcel Moolenaar */ 70027d5dc18SMarcel Moolenaar sc->sc_txfifosz = 16; 70127d5dc18SMarcel Moolenaar 70284c7b427SMarcel Moolenaar /* 16650s or higher have automatic flow control. */ 70384c7b427SMarcel Moolenaar if (sc->sc_rxfifosz > 16) { 70484c7b427SMarcel Moolenaar sc->sc_hwiflow = 1; 70584c7b427SMarcel Moolenaar sc->sc_hwoflow = 1; 70684c7b427SMarcel Moolenaar } 70784c7b427SMarcel Moolenaar 70827d5dc18SMarcel Moolenaar return (0); 70927d5dc18SMarcel Moolenaar } 71027d5dc18SMarcel Moolenaar 71127d5dc18SMarcel Moolenaar static int 71227d5dc18SMarcel Moolenaar ns8250_bus_receive(struct uart_softc *sc) 71327d5dc18SMarcel Moolenaar { 71427d5dc18SMarcel Moolenaar struct uart_bas *bas; 71527d5dc18SMarcel Moolenaar int xc; 71627d5dc18SMarcel Moolenaar uint8_t lsr; 71727d5dc18SMarcel Moolenaar 71827d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 71906287620SMarcel Moolenaar mtx_lock_spin(&sc->sc_hwmtx); 72027d5dc18SMarcel Moolenaar lsr = uart_getreg(bas, REG_LSR); 72144ed791bSMarcel Moolenaar while (lsr & LSR_RXRDY) { 72244ed791bSMarcel Moolenaar if (uart_rx_full(sc)) { 72344ed791bSMarcel Moolenaar sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; 72427d5dc18SMarcel Moolenaar break; 72544ed791bSMarcel Moolenaar } 72627d5dc18SMarcel Moolenaar xc = uart_getreg(bas, REG_DATA); 72727d5dc18SMarcel Moolenaar if (lsr & LSR_FE) 72827d5dc18SMarcel Moolenaar xc |= UART_STAT_FRAMERR; 72927d5dc18SMarcel Moolenaar if (lsr & LSR_PE) 73027d5dc18SMarcel Moolenaar xc |= UART_STAT_PARERR; 73127d5dc18SMarcel Moolenaar uart_rx_put(sc, xc); 73244ed791bSMarcel Moolenaar lsr = uart_getreg(bas, REG_LSR); 73344ed791bSMarcel Moolenaar } 73444ed791bSMarcel Moolenaar /* Discard everything left in the Rx FIFO. */ 73544ed791bSMarcel Moolenaar while (lsr & LSR_RXRDY) { 73644ed791bSMarcel Moolenaar (void)uart_getreg(bas, REG_DATA); 73744ed791bSMarcel Moolenaar uart_barrier(bas); 73844ed791bSMarcel Moolenaar lsr = uart_getreg(bas, REG_LSR); 73927d5dc18SMarcel Moolenaar } 74006287620SMarcel Moolenaar mtx_unlock_spin(&sc->sc_hwmtx); 74127d5dc18SMarcel Moolenaar return (0); 74227d5dc18SMarcel Moolenaar } 74327d5dc18SMarcel Moolenaar 74427d5dc18SMarcel Moolenaar static int 74527d5dc18SMarcel Moolenaar ns8250_bus_setsig(struct uart_softc *sc, int sig) 74627d5dc18SMarcel Moolenaar { 74727d5dc18SMarcel Moolenaar struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 74827d5dc18SMarcel Moolenaar struct uart_bas *bas; 74927d5dc18SMarcel Moolenaar uint32_t new, old; 75027d5dc18SMarcel Moolenaar 75127d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 75227d5dc18SMarcel Moolenaar do { 75327d5dc18SMarcel Moolenaar old = sc->sc_hwsig; 75427d5dc18SMarcel Moolenaar new = old; 75527d5dc18SMarcel Moolenaar if (sig & UART_SIG_DDTR) { 75627d5dc18SMarcel Moolenaar SIGCHG(sig & UART_SIG_DTR, new, UART_SIG_DTR, 75727d5dc18SMarcel Moolenaar UART_SIG_DDTR); 75827d5dc18SMarcel Moolenaar } 75927d5dc18SMarcel Moolenaar if (sig & UART_SIG_DRTS) { 76027d5dc18SMarcel Moolenaar SIGCHG(sig & UART_SIG_RTS, new, UART_SIG_RTS, 76127d5dc18SMarcel Moolenaar UART_SIG_DRTS); 76227d5dc18SMarcel Moolenaar } 76327d5dc18SMarcel Moolenaar } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 76406287620SMarcel Moolenaar mtx_lock_spin(&sc->sc_hwmtx); 76527d5dc18SMarcel Moolenaar ns8250->mcr &= ~(MCR_DTR|MCR_RTS); 76627d5dc18SMarcel Moolenaar if (new & UART_SIG_DTR) 76727d5dc18SMarcel Moolenaar ns8250->mcr |= MCR_DTR; 76827d5dc18SMarcel Moolenaar if (new & UART_SIG_RTS) 76927d5dc18SMarcel Moolenaar ns8250->mcr |= MCR_RTS; 77027d5dc18SMarcel Moolenaar uart_setreg(bas, REG_MCR, ns8250->mcr); 77127d5dc18SMarcel Moolenaar uart_barrier(bas); 77206287620SMarcel Moolenaar mtx_unlock_spin(&sc->sc_hwmtx); 77327d5dc18SMarcel Moolenaar return (0); 77427d5dc18SMarcel Moolenaar } 77527d5dc18SMarcel Moolenaar 77627d5dc18SMarcel Moolenaar static int 77727d5dc18SMarcel Moolenaar ns8250_bus_transmit(struct uart_softc *sc) 77827d5dc18SMarcel Moolenaar { 77927d5dc18SMarcel Moolenaar struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 78027d5dc18SMarcel Moolenaar struct uart_bas *bas; 78127d5dc18SMarcel Moolenaar int i; 78227d5dc18SMarcel Moolenaar 78327d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 78406287620SMarcel Moolenaar mtx_lock_spin(&sc->sc_hwmtx); 78527d5dc18SMarcel Moolenaar while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0) 78627d5dc18SMarcel Moolenaar ; 78727d5dc18SMarcel Moolenaar uart_setreg(bas, REG_IER, ns8250->ier | IER_ETXRDY); 78827d5dc18SMarcel Moolenaar uart_barrier(bas); 78927d5dc18SMarcel Moolenaar for (i = 0; i < sc->sc_txdatasz; i++) { 79027d5dc18SMarcel Moolenaar uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]); 79127d5dc18SMarcel Moolenaar uart_barrier(bas); 79227d5dc18SMarcel Moolenaar } 79327d5dc18SMarcel Moolenaar sc->sc_txbusy = 1; 79406287620SMarcel Moolenaar mtx_unlock_spin(&sc->sc_hwmtx); 79527d5dc18SMarcel Moolenaar return (0); 79627d5dc18SMarcel Moolenaar } 797