1098ca2bdSWarner Losh /*- 227d5dc18SMarcel Moolenaar * Copyright (c) 2003 Marcel Moolenaar 327d5dc18SMarcel Moolenaar * All rights reserved. 427d5dc18SMarcel Moolenaar * 527d5dc18SMarcel Moolenaar * Redistribution and use in source and binary forms, with or without 627d5dc18SMarcel Moolenaar * modification, are permitted provided that the following conditions 727d5dc18SMarcel Moolenaar * are met: 827d5dc18SMarcel Moolenaar * 927d5dc18SMarcel Moolenaar * 1. Redistributions of source code must retain the above copyright 1027d5dc18SMarcel Moolenaar * notice, this list of conditions and the following disclaimer. 1127d5dc18SMarcel Moolenaar * 2. Redistributions in binary form must reproduce the above copyright 1227d5dc18SMarcel Moolenaar * notice, this list of conditions and the following disclaimer in the 1327d5dc18SMarcel Moolenaar * documentation and/or other materials provided with the distribution. 1427d5dc18SMarcel Moolenaar * 1527d5dc18SMarcel Moolenaar * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 1627d5dc18SMarcel Moolenaar * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 1727d5dc18SMarcel Moolenaar * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 1827d5dc18SMarcel Moolenaar * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 1927d5dc18SMarcel Moolenaar * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 2027d5dc18SMarcel Moolenaar * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2127d5dc18SMarcel Moolenaar * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2227d5dc18SMarcel Moolenaar * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2327d5dc18SMarcel Moolenaar * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 2427d5dc18SMarcel Moolenaar * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2527d5dc18SMarcel Moolenaar */ 2627d5dc18SMarcel Moolenaar 2727d5dc18SMarcel Moolenaar #include <sys/cdefs.h> 2827d5dc18SMarcel Moolenaar __FBSDID("$FreeBSD$"); 2927d5dc18SMarcel Moolenaar 3027d5dc18SMarcel Moolenaar #include <sys/param.h> 3127d5dc18SMarcel Moolenaar #include <sys/systm.h> 3227d5dc18SMarcel Moolenaar #include <sys/bus.h> 3327d5dc18SMarcel Moolenaar #include <sys/conf.h> 3427d5dc18SMarcel Moolenaar #include <machine/bus.h> 3527d5dc18SMarcel Moolenaar 3627d5dc18SMarcel Moolenaar #include <dev/uart/uart.h> 3727d5dc18SMarcel Moolenaar #include <dev/uart/uart_cpu.h> 3827d5dc18SMarcel Moolenaar #include <dev/uart/uart_bus.h> 3976563beaSMarcel Moolenaar 4076563beaSMarcel Moolenaar #include <dev/ic/ns16550.h> 4127d5dc18SMarcel Moolenaar 4227d5dc18SMarcel Moolenaar #include "uart_if.h" 4327d5dc18SMarcel Moolenaar 4427d5dc18SMarcel Moolenaar #define DEFAULT_RCLK 1843200 4527d5dc18SMarcel Moolenaar 4627d5dc18SMarcel Moolenaar /* 4727d5dc18SMarcel Moolenaar * Clear pending interrupts. THRE is cleared by reading IIR. Data 4827d5dc18SMarcel Moolenaar * that may have been received gets lost here. 4927d5dc18SMarcel Moolenaar */ 5027d5dc18SMarcel Moolenaar static void 5127d5dc18SMarcel Moolenaar ns8250_clrint(struct uart_bas *bas) 5227d5dc18SMarcel Moolenaar { 5327d5dc18SMarcel Moolenaar uint8_t iir; 5427d5dc18SMarcel Moolenaar 5527d5dc18SMarcel Moolenaar iir = uart_getreg(bas, REG_IIR); 5627d5dc18SMarcel Moolenaar while ((iir & IIR_NOPEND) == 0) { 5727d5dc18SMarcel Moolenaar iir &= IIR_IMASK; 5827d5dc18SMarcel Moolenaar if (iir == IIR_RLS) 5927d5dc18SMarcel Moolenaar (void)uart_getreg(bas, REG_LSR); 6027d5dc18SMarcel Moolenaar else if (iir == IIR_RXRDY || iir == IIR_RXTOUT) 6127d5dc18SMarcel Moolenaar (void)uart_getreg(bas, REG_DATA); 6227d5dc18SMarcel Moolenaar else if (iir == IIR_MLSC) 6327d5dc18SMarcel Moolenaar (void)uart_getreg(bas, REG_MSR); 6427d5dc18SMarcel Moolenaar uart_barrier(bas); 6527d5dc18SMarcel Moolenaar iir = uart_getreg(bas, REG_IIR); 6627d5dc18SMarcel Moolenaar } 6727d5dc18SMarcel Moolenaar } 6827d5dc18SMarcel Moolenaar 6927d5dc18SMarcel Moolenaar static int 7027d5dc18SMarcel Moolenaar ns8250_delay(struct uart_bas *bas) 7127d5dc18SMarcel Moolenaar { 7227d5dc18SMarcel Moolenaar int divisor; 7327d5dc18SMarcel Moolenaar u_char lcr; 7427d5dc18SMarcel Moolenaar 7527d5dc18SMarcel Moolenaar lcr = uart_getreg(bas, REG_LCR); 7627d5dc18SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 7727d5dc18SMarcel Moolenaar uart_barrier(bas); 7858957d87SBenno Rice divisor = uart_getreg(bas, REG_DLL) | (uart_getreg(bas, REG_DLH) << 8); 7927d5dc18SMarcel Moolenaar uart_barrier(bas); 8027d5dc18SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr); 8127d5dc18SMarcel Moolenaar uart_barrier(bas); 8227d5dc18SMarcel Moolenaar 8327d5dc18SMarcel Moolenaar /* 1/10th the time to transmit 1 character (estimate). */ 8427d5dc18SMarcel Moolenaar return (16000000 * divisor / bas->rclk); 8527d5dc18SMarcel Moolenaar } 8627d5dc18SMarcel Moolenaar 8727d5dc18SMarcel Moolenaar static int 8827d5dc18SMarcel Moolenaar ns8250_divisor(int rclk, int baudrate) 8927d5dc18SMarcel Moolenaar { 9027d5dc18SMarcel Moolenaar int actual_baud, divisor; 9127d5dc18SMarcel Moolenaar int error; 9227d5dc18SMarcel Moolenaar 9327d5dc18SMarcel Moolenaar if (baudrate == 0) 9427d5dc18SMarcel Moolenaar return (0); 9527d5dc18SMarcel Moolenaar 9627d5dc18SMarcel Moolenaar divisor = (rclk / (baudrate << 3) + 1) >> 1; 9727d5dc18SMarcel Moolenaar if (divisor == 0 || divisor >= 65536) 9827d5dc18SMarcel Moolenaar return (0); 9927d5dc18SMarcel Moolenaar actual_baud = rclk / (divisor << 4); 10027d5dc18SMarcel Moolenaar 10127d5dc18SMarcel Moolenaar /* 10 times error in percent: */ 10227d5dc18SMarcel Moolenaar error = ((actual_baud - baudrate) * 2000 / baudrate + 1) >> 1; 10327d5dc18SMarcel Moolenaar 10427d5dc18SMarcel Moolenaar /* 3.0% maximum error tolerance: */ 10527d5dc18SMarcel Moolenaar if (error < -30 || error > 30) 10627d5dc18SMarcel Moolenaar return (0); 10727d5dc18SMarcel Moolenaar 10827d5dc18SMarcel Moolenaar return (divisor); 10927d5dc18SMarcel Moolenaar } 11027d5dc18SMarcel Moolenaar 11127d5dc18SMarcel Moolenaar static int 11227d5dc18SMarcel Moolenaar ns8250_drain(struct uart_bas *bas, int what) 11327d5dc18SMarcel Moolenaar { 11427d5dc18SMarcel Moolenaar int delay, limit; 11527d5dc18SMarcel Moolenaar 11627d5dc18SMarcel Moolenaar delay = ns8250_delay(bas); 11727d5dc18SMarcel Moolenaar 11827d5dc18SMarcel Moolenaar if (what & UART_DRAIN_TRANSMITTER) { 11927d5dc18SMarcel Moolenaar /* 12027d5dc18SMarcel Moolenaar * Pick an arbitrary high limit to avoid getting stuck in 12127d5dc18SMarcel Moolenaar * an infinite loop when the hardware is broken. Make the 12227d5dc18SMarcel Moolenaar * limit high enough to handle large FIFOs. 12327d5dc18SMarcel Moolenaar */ 12427d5dc18SMarcel Moolenaar limit = 10*1024; 12527d5dc18SMarcel Moolenaar while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) 12627d5dc18SMarcel Moolenaar DELAY(delay); 12727d5dc18SMarcel Moolenaar if (limit == 0) { 12827d5dc18SMarcel Moolenaar /* printf("ns8250: transmitter appears stuck... "); */ 12927d5dc18SMarcel Moolenaar return (EIO); 13027d5dc18SMarcel Moolenaar } 13127d5dc18SMarcel Moolenaar } 13227d5dc18SMarcel Moolenaar 13327d5dc18SMarcel Moolenaar if (what & UART_DRAIN_RECEIVER) { 13427d5dc18SMarcel Moolenaar /* 13527d5dc18SMarcel Moolenaar * Pick an arbitrary high limit to avoid getting stuck in 13627d5dc18SMarcel Moolenaar * an infinite loop when the hardware is broken. Make the 13727d5dc18SMarcel Moolenaar * limit high enough to handle large FIFOs and integrated 13827d5dc18SMarcel Moolenaar * UARTs. The HP rx2600 for example has 3 UARTs on the 13927d5dc18SMarcel Moolenaar * management board that tend to get a lot of data send 14027d5dc18SMarcel Moolenaar * to it when the UART is first activated. 14127d5dc18SMarcel Moolenaar */ 14227d5dc18SMarcel Moolenaar limit=10*4096; 14327d5dc18SMarcel Moolenaar while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) { 14427d5dc18SMarcel Moolenaar (void)uart_getreg(bas, REG_DATA); 14527d5dc18SMarcel Moolenaar uart_barrier(bas); 14627d5dc18SMarcel Moolenaar DELAY(delay << 2); 14727d5dc18SMarcel Moolenaar } 14827d5dc18SMarcel Moolenaar if (limit == 0) { 14927d5dc18SMarcel Moolenaar /* printf("ns8250: receiver appears broken... "); */ 15027d5dc18SMarcel Moolenaar return (EIO); 15127d5dc18SMarcel Moolenaar } 15227d5dc18SMarcel Moolenaar } 15327d5dc18SMarcel Moolenaar 15427d5dc18SMarcel Moolenaar return (0); 15527d5dc18SMarcel Moolenaar } 15627d5dc18SMarcel Moolenaar 15727d5dc18SMarcel Moolenaar /* 15827d5dc18SMarcel Moolenaar * We can only flush UARTs with FIFOs. UARTs without FIFOs should be 15927d5dc18SMarcel Moolenaar * drained. WARNING: this function clobbers the FIFO setting! 16027d5dc18SMarcel Moolenaar */ 16127d5dc18SMarcel Moolenaar static void 16227d5dc18SMarcel Moolenaar ns8250_flush(struct uart_bas *bas, int what) 16327d5dc18SMarcel Moolenaar { 16427d5dc18SMarcel Moolenaar uint8_t fcr; 16527d5dc18SMarcel Moolenaar 16627d5dc18SMarcel Moolenaar fcr = FCR_ENABLE; 16727d5dc18SMarcel Moolenaar if (what & UART_FLUSH_TRANSMITTER) 16827d5dc18SMarcel Moolenaar fcr |= FCR_XMT_RST; 16927d5dc18SMarcel Moolenaar if (what & UART_FLUSH_RECEIVER) 17027d5dc18SMarcel Moolenaar fcr |= FCR_RCV_RST; 17127d5dc18SMarcel Moolenaar uart_setreg(bas, REG_FCR, fcr); 17227d5dc18SMarcel Moolenaar uart_barrier(bas); 17327d5dc18SMarcel Moolenaar } 17427d5dc18SMarcel Moolenaar 17527d5dc18SMarcel Moolenaar static int 17627d5dc18SMarcel Moolenaar ns8250_param(struct uart_bas *bas, int baudrate, int databits, int stopbits, 17727d5dc18SMarcel Moolenaar int parity) 17827d5dc18SMarcel Moolenaar { 17927d5dc18SMarcel Moolenaar int divisor; 18027d5dc18SMarcel Moolenaar uint8_t lcr; 18127d5dc18SMarcel Moolenaar 18227d5dc18SMarcel Moolenaar lcr = 0; 18327d5dc18SMarcel Moolenaar if (databits >= 8) 18427d5dc18SMarcel Moolenaar lcr |= LCR_8BITS; 18527d5dc18SMarcel Moolenaar else if (databits == 7) 18627d5dc18SMarcel Moolenaar lcr |= LCR_7BITS; 18727d5dc18SMarcel Moolenaar else if (databits == 6) 18827d5dc18SMarcel Moolenaar lcr |= LCR_6BITS; 18927d5dc18SMarcel Moolenaar else 19027d5dc18SMarcel Moolenaar lcr |= LCR_5BITS; 19127d5dc18SMarcel Moolenaar if (stopbits > 1) 19227d5dc18SMarcel Moolenaar lcr |= LCR_STOPB; 19327d5dc18SMarcel Moolenaar lcr |= parity << 3; 19427d5dc18SMarcel Moolenaar 19527d5dc18SMarcel Moolenaar /* Set baudrate. */ 19627d5dc18SMarcel Moolenaar if (baudrate > 0) { 19727d5dc18SMarcel Moolenaar divisor = ns8250_divisor(bas->rclk, baudrate); 19827d5dc18SMarcel Moolenaar if (divisor == 0) 19927d5dc18SMarcel Moolenaar return (EINVAL); 20063f8efd3SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 20163f8efd3SMarcel Moolenaar uart_barrier(bas); 20258957d87SBenno Rice uart_setreg(bas, REG_DLL, divisor & 0xff); 20358957d87SBenno Rice uart_setreg(bas, REG_DLH, (divisor >> 8) & 0xff); 20427d5dc18SMarcel Moolenaar uart_barrier(bas); 20527d5dc18SMarcel Moolenaar } 20627d5dc18SMarcel Moolenaar 20727d5dc18SMarcel Moolenaar /* Set LCR and clear DLAB. */ 20827d5dc18SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr); 20927d5dc18SMarcel Moolenaar uart_barrier(bas); 21027d5dc18SMarcel Moolenaar return (0); 21127d5dc18SMarcel Moolenaar } 21227d5dc18SMarcel Moolenaar 21327d5dc18SMarcel Moolenaar /* 21427d5dc18SMarcel Moolenaar * Low-level UART interface. 21527d5dc18SMarcel Moolenaar */ 21627d5dc18SMarcel Moolenaar static int ns8250_probe(struct uart_bas *bas); 21727d5dc18SMarcel Moolenaar static void ns8250_init(struct uart_bas *bas, int, int, int, int); 21827d5dc18SMarcel Moolenaar static void ns8250_term(struct uart_bas *bas); 21927d5dc18SMarcel Moolenaar static void ns8250_putc(struct uart_bas *bas, int); 22027d5dc18SMarcel Moolenaar static int ns8250_poll(struct uart_bas *bas); 221634e63c9SMarcel Moolenaar static int ns8250_getc(struct uart_bas *bas, struct mtx *); 22227d5dc18SMarcel Moolenaar 22327d5dc18SMarcel Moolenaar struct uart_ops uart_ns8250_ops = { 22427d5dc18SMarcel Moolenaar .probe = ns8250_probe, 22527d5dc18SMarcel Moolenaar .init = ns8250_init, 22627d5dc18SMarcel Moolenaar .term = ns8250_term, 22727d5dc18SMarcel Moolenaar .putc = ns8250_putc, 22827d5dc18SMarcel Moolenaar .poll = ns8250_poll, 22927d5dc18SMarcel Moolenaar .getc = ns8250_getc, 23027d5dc18SMarcel Moolenaar }; 23127d5dc18SMarcel Moolenaar 23227d5dc18SMarcel Moolenaar static int 23327d5dc18SMarcel Moolenaar ns8250_probe(struct uart_bas *bas) 23427d5dc18SMarcel Moolenaar { 2358bceca4fSBenno Rice u_char val; 23627d5dc18SMarcel Moolenaar 23727d5dc18SMarcel Moolenaar /* Check known 0 bits that don't depend on DLAB. */ 23827d5dc18SMarcel Moolenaar val = uart_getreg(bas, REG_IIR); 23927d5dc18SMarcel Moolenaar if (val & 0x30) 24027d5dc18SMarcel Moolenaar return (ENXIO); 24127d5dc18SMarcel Moolenaar val = uart_getreg(bas, REG_MCR); 24227d5dc18SMarcel Moolenaar if (val & 0xe0) 24327d5dc18SMarcel Moolenaar return (ENXIO); 24427d5dc18SMarcel Moolenaar 24527d5dc18SMarcel Moolenaar return (0); 24627d5dc18SMarcel Moolenaar } 24727d5dc18SMarcel Moolenaar 24827d5dc18SMarcel Moolenaar static void 24927d5dc18SMarcel Moolenaar ns8250_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, 25027d5dc18SMarcel Moolenaar int parity) 25127d5dc18SMarcel Moolenaar { 25258957d87SBenno Rice u_char ier; 25327d5dc18SMarcel Moolenaar 25427d5dc18SMarcel Moolenaar if (bas->rclk == 0) 25527d5dc18SMarcel Moolenaar bas->rclk = DEFAULT_RCLK; 25627d5dc18SMarcel Moolenaar ns8250_param(bas, baudrate, databits, stopbits, parity); 25727d5dc18SMarcel Moolenaar 25827d5dc18SMarcel Moolenaar /* Disable all interrupt sources. */ 25958957d87SBenno Rice ier = uart_getreg(bas, REG_IER) & 0xf0; 26058957d87SBenno Rice uart_setreg(bas, REG_IER, ier); 26127d5dc18SMarcel Moolenaar uart_barrier(bas); 26227d5dc18SMarcel Moolenaar 26327d5dc18SMarcel Moolenaar /* Disable the FIFO (if present). */ 26427d5dc18SMarcel Moolenaar uart_setreg(bas, REG_FCR, 0); 26527d5dc18SMarcel Moolenaar uart_barrier(bas); 26627d5dc18SMarcel Moolenaar 26727d5dc18SMarcel Moolenaar /* Set RTS & DTR. */ 26827d5dc18SMarcel Moolenaar uart_setreg(bas, REG_MCR, MCR_IE | MCR_RTS | MCR_DTR); 26927d5dc18SMarcel Moolenaar uart_barrier(bas); 27027d5dc18SMarcel Moolenaar 27127d5dc18SMarcel Moolenaar ns8250_clrint(bas); 27227d5dc18SMarcel Moolenaar } 27327d5dc18SMarcel Moolenaar 27427d5dc18SMarcel Moolenaar static void 27527d5dc18SMarcel Moolenaar ns8250_term(struct uart_bas *bas) 27627d5dc18SMarcel Moolenaar { 27727d5dc18SMarcel Moolenaar 27827d5dc18SMarcel Moolenaar /* Clear RTS & DTR. */ 27927d5dc18SMarcel Moolenaar uart_setreg(bas, REG_MCR, MCR_IE); 28027d5dc18SMarcel Moolenaar uart_barrier(bas); 28127d5dc18SMarcel Moolenaar } 28227d5dc18SMarcel Moolenaar 28327d5dc18SMarcel Moolenaar static void 28427d5dc18SMarcel Moolenaar ns8250_putc(struct uart_bas *bas, int c) 28527d5dc18SMarcel Moolenaar { 28627d5dc18SMarcel Moolenaar int delay, limit; 28727d5dc18SMarcel Moolenaar 28827d5dc18SMarcel Moolenaar /* 1/10th the time to transmit 1 character (estimate). */ 28927d5dc18SMarcel Moolenaar delay = ns8250_delay(bas); 29027d5dc18SMarcel Moolenaar 29127d5dc18SMarcel Moolenaar limit = 20; 29227d5dc18SMarcel Moolenaar while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0 && --limit) 29327d5dc18SMarcel Moolenaar DELAY(delay); 29427d5dc18SMarcel Moolenaar uart_setreg(bas, REG_DATA, c); 2954e55f723SMarcel Moolenaar uart_barrier(bas); 29627d5dc18SMarcel Moolenaar limit = 40; 29727d5dc18SMarcel Moolenaar while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) 29827d5dc18SMarcel Moolenaar DELAY(delay); 29927d5dc18SMarcel Moolenaar } 30027d5dc18SMarcel Moolenaar 30127d5dc18SMarcel Moolenaar static int 30227d5dc18SMarcel Moolenaar ns8250_poll(struct uart_bas *bas) 30327d5dc18SMarcel Moolenaar { 30427d5dc18SMarcel Moolenaar 30527d5dc18SMarcel Moolenaar if (uart_getreg(bas, REG_LSR) & LSR_RXRDY) 30627d5dc18SMarcel Moolenaar return (uart_getreg(bas, REG_DATA)); 30727d5dc18SMarcel Moolenaar return (-1); 30827d5dc18SMarcel Moolenaar } 30927d5dc18SMarcel Moolenaar 31027d5dc18SMarcel Moolenaar static int 311634e63c9SMarcel Moolenaar ns8250_getc(struct uart_bas *bas, struct mtx *hwmtx) 31227d5dc18SMarcel Moolenaar { 313634e63c9SMarcel Moolenaar int c, delay; 314634e63c9SMarcel Moolenaar 315634e63c9SMarcel Moolenaar uart_lock(hwmtx); 31627d5dc18SMarcel Moolenaar 31727d5dc18SMarcel Moolenaar /* 1/10th the time to transmit 1 character (estimate). */ 31827d5dc18SMarcel Moolenaar delay = ns8250_delay(bas); 31927d5dc18SMarcel Moolenaar 320634e63c9SMarcel Moolenaar while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0) { 321634e63c9SMarcel Moolenaar uart_unlock(hwmtx); 32227d5dc18SMarcel Moolenaar DELAY(delay); 323634e63c9SMarcel Moolenaar uart_lock(hwmtx); 324634e63c9SMarcel Moolenaar } 325634e63c9SMarcel Moolenaar 326634e63c9SMarcel Moolenaar c = uart_getreg(bas, REG_DATA); 327634e63c9SMarcel Moolenaar 328634e63c9SMarcel Moolenaar uart_unlock(hwmtx); 329634e63c9SMarcel Moolenaar 330634e63c9SMarcel Moolenaar return (c); 33127d5dc18SMarcel Moolenaar } 33227d5dc18SMarcel Moolenaar 33327d5dc18SMarcel Moolenaar /* 33427d5dc18SMarcel Moolenaar * High-level UART interface. 33527d5dc18SMarcel Moolenaar */ 33627d5dc18SMarcel Moolenaar struct ns8250_softc { 33727d5dc18SMarcel Moolenaar struct uart_softc base; 33827d5dc18SMarcel Moolenaar uint8_t fcr; 33927d5dc18SMarcel Moolenaar uint8_t ier; 34027d5dc18SMarcel Moolenaar uint8_t mcr; 34127d5dc18SMarcel Moolenaar }; 34227d5dc18SMarcel Moolenaar 34327d5dc18SMarcel Moolenaar static int ns8250_bus_attach(struct uart_softc *); 34427d5dc18SMarcel Moolenaar static int ns8250_bus_detach(struct uart_softc *); 34527d5dc18SMarcel Moolenaar static int ns8250_bus_flush(struct uart_softc *, int); 34627d5dc18SMarcel Moolenaar static int ns8250_bus_getsig(struct uart_softc *); 34727d5dc18SMarcel Moolenaar static int ns8250_bus_ioctl(struct uart_softc *, int, intptr_t); 34827d5dc18SMarcel Moolenaar static int ns8250_bus_ipend(struct uart_softc *); 34927d5dc18SMarcel Moolenaar static int ns8250_bus_param(struct uart_softc *, int, int, int, int); 35027d5dc18SMarcel Moolenaar static int ns8250_bus_probe(struct uart_softc *); 35127d5dc18SMarcel Moolenaar static int ns8250_bus_receive(struct uart_softc *); 35227d5dc18SMarcel Moolenaar static int ns8250_bus_setsig(struct uart_softc *, int); 35327d5dc18SMarcel Moolenaar static int ns8250_bus_transmit(struct uart_softc *); 35427d5dc18SMarcel Moolenaar 35527d5dc18SMarcel Moolenaar static kobj_method_t ns8250_methods[] = { 35627d5dc18SMarcel Moolenaar KOBJMETHOD(uart_attach, ns8250_bus_attach), 35727d5dc18SMarcel Moolenaar KOBJMETHOD(uart_detach, ns8250_bus_detach), 35827d5dc18SMarcel Moolenaar KOBJMETHOD(uart_flush, ns8250_bus_flush), 35927d5dc18SMarcel Moolenaar KOBJMETHOD(uart_getsig, ns8250_bus_getsig), 36027d5dc18SMarcel Moolenaar KOBJMETHOD(uart_ioctl, ns8250_bus_ioctl), 36127d5dc18SMarcel Moolenaar KOBJMETHOD(uart_ipend, ns8250_bus_ipend), 36227d5dc18SMarcel Moolenaar KOBJMETHOD(uart_param, ns8250_bus_param), 36327d5dc18SMarcel Moolenaar KOBJMETHOD(uart_probe, ns8250_bus_probe), 36427d5dc18SMarcel Moolenaar KOBJMETHOD(uart_receive, ns8250_bus_receive), 36527d5dc18SMarcel Moolenaar KOBJMETHOD(uart_setsig, ns8250_bus_setsig), 36627d5dc18SMarcel Moolenaar KOBJMETHOD(uart_transmit, ns8250_bus_transmit), 36727d5dc18SMarcel Moolenaar { 0, 0 } 36827d5dc18SMarcel Moolenaar }; 36927d5dc18SMarcel Moolenaar 37027d5dc18SMarcel Moolenaar struct uart_class uart_ns8250_class = { 37127d5dc18SMarcel Moolenaar "ns8250 class", 37227d5dc18SMarcel Moolenaar ns8250_methods, 37327d5dc18SMarcel Moolenaar sizeof(struct ns8250_softc), 37427d5dc18SMarcel Moolenaar .uc_range = 8, 37527d5dc18SMarcel Moolenaar .uc_rclk = DEFAULT_RCLK 37627d5dc18SMarcel Moolenaar }; 37727d5dc18SMarcel Moolenaar 37827d5dc18SMarcel Moolenaar #define SIGCHG(c, i, s, d) \ 37927d5dc18SMarcel Moolenaar if (c) { \ 38027d5dc18SMarcel Moolenaar i |= (i & s) ? s : s | d; \ 38127d5dc18SMarcel Moolenaar } else { \ 38227d5dc18SMarcel Moolenaar i = (i & s) ? (i & ~s) | d : i; \ 38327d5dc18SMarcel Moolenaar } 38427d5dc18SMarcel Moolenaar 38527d5dc18SMarcel Moolenaar static int 38627d5dc18SMarcel Moolenaar ns8250_bus_attach(struct uart_softc *sc) 38727d5dc18SMarcel Moolenaar { 38827d5dc18SMarcel Moolenaar struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 38927d5dc18SMarcel Moolenaar struct uart_bas *bas; 39027d5dc18SMarcel Moolenaar 39127d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 39227d5dc18SMarcel Moolenaar 39327d5dc18SMarcel Moolenaar ns8250->mcr = uart_getreg(bas, REG_MCR); 39427d5dc18SMarcel Moolenaar ns8250->fcr = FCR_ENABLE | FCR_RX_MEDH; 39527d5dc18SMarcel Moolenaar uart_setreg(bas, REG_FCR, ns8250->fcr); 39627d5dc18SMarcel Moolenaar uart_barrier(bas); 39727d5dc18SMarcel Moolenaar ns8250_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 39827d5dc18SMarcel Moolenaar 39927d5dc18SMarcel Moolenaar if (ns8250->mcr & MCR_DTR) 40028710806SPoul-Henning Kamp sc->sc_hwsig |= SER_DTR; 40127d5dc18SMarcel Moolenaar if (ns8250->mcr & MCR_RTS) 40228710806SPoul-Henning Kamp sc->sc_hwsig |= SER_RTS; 40327d5dc18SMarcel Moolenaar ns8250_bus_getsig(sc); 40427d5dc18SMarcel Moolenaar 40527d5dc18SMarcel Moolenaar ns8250_clrint(bas); 40658957d87SBenno Rice ns8250->ier = uart_getreg(bas, REG_IER) & 0xf0; 40758957d87SBenno Rice ns8250->ier |= IER_EMSC | IER_ERLS | IER_ERXRDY; 40827d5dc18SMarcel Moolenaar uart_setreg(bas, REG_IER, ns8250->ier); 40927d5dc18SMarcel Moolenaar uart_barrier(bas); 41027d5dc18SMarcel Moolenaar return (0); 41127d5dc18SMarcel Moolenaar } 41227d5dc18SMarcel Moolenaar 41327d5dc18SMarcel Moolenaar static int 41427d5dc18SMarcel Moolenaar ns8250_bus_detach(struct uart_softc *sc) 41527d5dc18SMarcel Moolenaar { 41627d5dc18SMarcel Moolenaar struct uart_bas *bas; 41758957d87SBenno Rice u_char ier; 41827d5dc18SMarcel Moolenaar 41927d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 42058957d87SBenno Rice ier = uart_getreg(bas, REG_IER) & 0xf0; 42158957d87SBenno Rice uart_setreg(bas, REG_IER, ier); 42227d5dc18SMarcel Moolenaar uart_barrier(bas); 42327d5dc18SMarcel Moolenaar ns8250_clrint(bas); 42427d5dc18SMarcel Moolenaar return (0); 42527d5dc18SMarcel Moolenaar } 42627d5dc18SMarcel Moolenaar 42727d5dc18SMarcel Moolenaar static int 42827d5dc18SMarcel Moolenaar ns8250_bus_flush(struct uart_softc *sc, int what) 42927d5dc18SMarcel Moolenaar { 43027d5dc18SMarcel Moolenaar struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 43127d5dc18SMarcel Moolenaar struct uart_bas *bas; 43206287620SMarcel Moolenaar int error; 43327d5dc18SMarcel Moolenaar 43427d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 4358af03381SMarcel Moolenaar uart_lock(sc->sc_hwmtx); 4368d1289feSMarcel Moolenaar if (sc->sc_rxfifosz > 1) { 43727d5dc18SMarcel Moolenaar ns8250_flush(bas, what); 43827d5dc18SMarcel Moolenaar uart_setreg(bas, REG_FCR, ns8250->fcr); 43927d5dc18SMarcel Moolenaar uart_barrier(bas); 44006287620SMarcel Moolenaar error = 0; 44106287620SMarcel Moolenaar } else 44206287620SMarcel Moolenaar error = ns8250_drain(bas, what); 4438af03381SMarcel Moolenaar uart_unlock(sc->sc_hwmtx); 44406287620SMarcel Moolenaar return (error); 44527d5dc18SMarcel Moolenaar } 44627d5dc18SMarcel Moolenaar 44727d5dc18SMarcel Moolenaar static int 44827d5dc18SMarcel Moolenaar ns8250_bus_getsig(struct uart_softc *sc) 44927d5dc18SMarcel Moolenaar { 45027d5dc18SMarcel Moolenaar uint32_t new, old, sig; 45127d5dc18SMarcel Moolenaar uint8_t msr; 45227d5dc18SMarcel Moolenaar 45327d5dc18SMarcel Moolenaar do { 45427d5dc18SMarcel Moolenaar old = sc->sc_hwsig; 45527d5dc18SMarcel Moolenaar sig = old; 4568af03381SMarcel Moolenaar uart_lock(sc->sc_hwmtx); 45727d5dc18SMarcel Moolenaar msr = uart_getreg(&sc->sc_bas, REG_MSR); 4588af03381SMarcel Moolenaar uart_unlock(sc->sc_hwmtx); 45928710806SPoul-Henning Kamp SIGCHG(msr & MSR_DSR, sig, SER_DSR, SER_DDSR); 46028710806SPoul-Henning Kamp SIGCHG(msr & MSR_CTS, sig, SER_CTS, SER_DCTS); 46128710806SPoul-Henning Kamp SIGCHG(msr & MSR_DCD, sig, SER_DCD, SER_DDCD); 46228710806SPoul-Henning Kamp SIGCHG(msr & MSR_RI, sig, SER_RI, SER_DRI); 463ea549414SMarcel Moolenaar new = sig & ~SER_MASK_DELTA; 46427d5dc18SMarcel Moolenaar } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 46527d5dc18SMarcel Moolenaar return (sig); 46627d5dc18SMarcel Moolenaar } 46727d5dc18SMarcel Moolenaar 46827d5dc18SMarcel Moolenaar static int 46927d5dc18SMarcel Moolenaar ns8250_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) 47027d5dc18SMarcel Moolenaar { 47127d5dc18SMarcel Moolenaar struct uart_bas *bas; 472bfa307a3SMarcel Moolenaar int baudrate, divisor, error; 47384c7b427SMarcel Moolenaar uint8_t efr, lcr; 47427d5dc18SMarcel Moolenaar 47527d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 47606287620SMarcel Moolenaar error = 0; 4778af03381SMarcel Moolenaar uart_lock(sc->sc_hwmtx); 47827d5dc18SMarcel Moolenaar switch (request) { 47927d5dc18SMarcel Moolenaar case UART_IOCTL_BREAK: 48027d5dc18SMarcel Moolenaar lcr = uart_getreg(bas, REG_LCR); 48127d5dc18SMarcel Moolenaar if (data) 48227d5dc18SMarcel Moolenaar lcr |= LCR_SBREAK; 48327d5dc18SMarcel Moolenaar else 48427d5dc18SMarcel Moolenaar lcr &= ~LCR_SBREAK; 48527d5dc18SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr); 48627d5dc18SMarcel Moolenaar uart_barrier(bas); 48727d5dc18SMarcel Moolenaar break; 48884c7b427SMarcel Moolenaar case UART_IOCTL_IFLOW: 48984c7b427SMarcel Moolenaar lcr = uart_getreg(bas, REG_LCR); 49084c7b427SMarcel Moolenaar uart_barrier(bas); 49184c7b427SMarcel Moolenaar uart_setreg(bas, REG_LCR, 0xbf); 49284c7b427SMarcel Moolenaar uart_barrier(bas); 49384c7b427SMarcel Moolenaar efr = uart_getreg(bas, REG_EFR); 49484c7b427SMarcel Moolenaar if (data) 49584c7b427SMarcel Moolenaar efr |= EFR_RTS; 49684c7b427SMarcel Moolenaar else 49784c7b427SMarcel Moolenaar efr &= ~EFR_RTS; 49884c7b427SMarcel Moolenaar uart_setreg(bas, REG_EFR, efr); 49984c7b427SMarcel Moolenaar uart_barrier(bas); 50084c7b427SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr); 50184c7b427SMarcel Moolenaar uart_barrier(bas); 50284c7b427SMarcel Moolenaar break; 50384c7b427SMarcel Moolenaar case UART_IOCTL_OFLOW: 50484c7b427SMarcel Moolenaar lcr = uart_getreg(bas, REG_LCR); 50584c7b427SMarcel Moolenaar uart_barrier(bas); 50684c7b427SMarcel Moolenaar uart_setreg(bas, REG_LCR, 0xbf); 50784c7b427SMarcel Moolenaar uart_barrier(bas); 50884c7b427SMarcel Moolenaar efr = uart_getreg(bas, REG_EFR); 50984c7b427SMarcel Moolenaar if (data) 51084c7b427SMarcel Moolenaar efr |= EFR_CTS; 51184c7b427SMarcel Moolenaar else 51284c7b427SMarcel Moolenaar efr &= ~EFR_CTS; 51384c7b427SMarcel Moolenaar uart_setreg(bas, REG_EFR, efr); 51484c7b427SMarcel Moolenaar uart_barrier(bas); 51584c7b427SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr); 51684c7b427SMarcel Moolenaar uart_barrier(bas); 51784c7b427SMarcel Moolenaar break; 518d8518925SMarcel Moolenaar case UART_IOCTL_BAUD: 519d8518925SMarcel Moolenaar lcr = uart_getreg(bas, REG_LCR); 520d8518925SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 521d8518925SMarcel Moolenaar uart_barrier(bas); 52258957d87SBenno Rice divisor = uart_getreg(bas, REG_DLL) | 52358957d87SBenno Rice (uart_getreg(bas, REG_DLH) << 8); 524d8518925SMarcel Moolenaar uart_barrier(bas); 525d8518925SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr); 526d8518925SMarcel Moolenaar uart_barrier(bas); 527bfa307a3SMarcel Moolenaar baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0; 528bfa307a3SMarcel Moolenaar if (baudrate > 0) 529bfa307a3SMarcel Moolenaar *(int*)data = baudrate; 530bfa307a3SMarcel Moolenaar else 531bfa307a3SMarcel Moolenaar error = ENXIO; 532d8518925SMarcel Moolenaar break; 53327d5dc18SMarcel Moolenaar default: 53406287620SMarcel Moolenaar error = EINVAL; 53506287620SMarcel Moolenaar break; 53627d5dc18SMarcel Moolenaar } 5378af03381SMarcel Moolenaar uart_unlock(sc->sc_hwmtx); 53806287620SMarcel Moolenaar return (error); 53927d5dc18SMarcel Moolenaar } 54027d5dc18SMarcel Moolenaar 54127d5dc18SMarcel Moolenaar static int 54227d5dc18SMarcel Moolenaar ns8250_bus_ipend(struct uart_softc *sc) 54327d5dc18SMarcel Moolenaar { 54427d5dc18SMarcel Moolenaar struct uart_bas *bas; 54527d5dc18SMarcel Moolenaar int ipend; 54627d5dc18SMarcel Moolenaar uint8_t iir, lsr; 54727d5dc18SMarcel Moolenaar 54827d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 5498af03381SMarcel Moolenaar uart_lock(sc->sc_hwmtx); 55027d5dc18SMarcel Moolenaar iir = uart_getreg(bas, REG_IIR); 55106287620SMarcel Moolenaar if (iir & IIR_NOPEND) { 5528af03381SMarcel Moolenaar uart_unlock(sc->sc_hwmtx); 55327d5dc18SMarcel Moolenaar return (0); 55406287620SMarcel Moolenaar } 55527d5dc18SMarcel Moolenaar ipend = 0; 55627d5dc18SMarcel Moolenaar if (iir & IIR_RXRDY) { 55727d5dc18SMarcel Moolenaar lsr = uart_getreg(bas, REG_LSR); 5588af03381SMarcel Moolenaar uart_unlock(sc->sc_hwmtx); 55927d5dc18SMarcel Moolenaar if (lsr & LSR_OE) 5602d511805SMarcel Moolenaar ipend |= SER_INT_OVERRUN; 56127d5dc18SMarcel Moolenaar if (lsr & LSR_BI) 5622d511805SMarcel Moolenaar ipend |= SER_INT_BREAK; 56327d5dc18SMarcel Moolenaar if (lsr & LSR_RXRDY) 5642d511805SMarcel Moolenaar ipend |= SER_INT_RXREADY; 56527d5dc18SMarcel Moolenaar } else { 5668af03381SMarcel Moolenaar uart_unlock(sc->sc_hwmtx); 56727d5dc18SMarcel Moolenaar if (iir & IIR_TXRDY) 5682d511805SMarcel Moolenaar ipend |= SER_INT_TXIDLE; 56927d5dc18SMarcel Moolenaar else 5702d511805SMarcel Moolenaar ipend |= SER_INT_SIGCHG; 57127d5dc18SMarcel Moolenaar } 57227d5dc18SMarcel Moolenaar return ((sc->sc_leaving) ? 0 : ipend); 57327d5dc18SMarcel Moolenaar } 57427d5dc18SMarcel Moolenaar 57527d5dc18SMarcel Moolenaar static int 57627d5dc18SMarcel Moolenaar ns8250_bus_param(struct uart_softc *sc, int baudrate, int databits, 57727d5dc18SMarcel Moolenaar int stopbits, int parity) 57827d5dc18SMarcel Moolenaar { 57927d5dc18SMarcel Moolenaar struct uart_bas *bas; 58006287620SMarcel Moolenaar int error; 58127d5dc18SMarcel Moolenaar 58227d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 5838af03381SMarcel Moolenaar uart_lock(sc->sc_hwmtx); 58406287620SMarcel Moolenaar error = ns8250_param(bas, baudrate, databits, stopbits, parity); 5858af03381SMarcel Moolenaar uart_unlock(sc->sc_hwmtx); 58606287620SMarcel Moolenaar return (error); 58727d5dc18SMarcel Moolenaar } 58827d5dc18SMarcel Moolenaar 58927d5dc18SMarcel Moolenaar static int 59027d5dc18SMarcel Moolenaar ns8250_bus_probe(struct uart_softc *sc) 59127d5dc18SMarcel Moolenaar { 59227d5dc18SMarcel Moolenaar struct uart_bas *bas; 59327d5dc18SMarcel Moolenaar int count, delay, error, limit; 59458957d87SBenno Rice uint8_t lsr, mcr, ier; 59527d5dc18SMarcel Moolenaar 59627d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 59727d5dc18SMarcel Moolenaar 59827d5dc18SMarcel Moolenaar error = ns8250_probe(bas); 59927d5dc18SMarcel Moolenaar if (error) 60027d5dc18SMarcel Moolenaar return (error); 60127d5dc18SMarcel Moolenaar 60227d5dc18SMarcel Moolenaar mcr = MCR_IE; 60327d5dc18SMarcel Moolenaar if (sc->sc_sysdev == NULL) { 60427d5dc18SMarcel Moolenaar /* By using ns8250_init() we also set DTR and RTS. */ 605d902fb71SMarcel Moolenaar ns8250_init(bas, 115200, 8, 1, UART_PARITY_NONE); 60627d5dc18SMarcel Moolenaar } else 60727d5dc18SMarcel Moolenaar mcr |= MCR_DTR | MCR_RTS; 60827d5dc18SMarcel Moolenaar 60927d5dc18SMarcel Moolenaar error = ns8250_drain(bas, UART_DRAIN_TRANSMITTER); 61027d5dc18SMarcel Moolenaar if (error) 61127d5dc18SMarcel Moolenaar return (error); 61227d5dc18SMarcel Moolenaar 61327d5dc18SMarcel Moolenaar /* 61427d5dc18SMarcel Moolenaar * Set loopback mode. This avoids having garbage on the wire and 61527d5dc18SMarcel Moolenaar * also allows us send and receive data. We set DTR and RTS to 61627d5dc18SMarcel Moolenaar * avoid the possibility that automatic flow-control prevents 61789eef2deSThomas Moestl * any data from being sent. 61827d5dc18SMarcel Moolenaar */ 61989eef2deSThomas Moestl uart_setreg(bas, REG_MCR, MCR_LOOPBACK | MCR_IE | MCR_DTR | MCR_RTS); 62027d5dc18SMarcel Moolenaar uart_barrier(bas); 62127d5dc18SMarcel Moolenaar 62227d5dc18SMarcel Moolenaar /* 62327d5dc18SMarcel Moolenaar * Enable FIFOs. And check that the UART has them. If not, we're 62489eef2deSThomas Moestl * done. Since this is the first time we enable the FIFOs, we reset 62589eef2deSThomas Moestl * them. 62627d5dc18SMarcel Moolenaar */ 62727d5dc18SMarcel Moolenaar uart_setreg(bas, REG_FCR, FCR_ENABLE); 62827d5dc18SMarcel Moolenaar uart_barrier(bas); 6298d1289feSMarcel Moolenaar if (!(uart_getreg(bas, REG_IIR) & IIR_FIFO_MASK)) { 63027d5dc18SMarcel Moolenaar /* 63127d5dc18SMarcel Moolenaar * NS16450 or INS8250. We don't bother to differentiate 63227d5dc18SMarcel Moolenaar * between them. They're too old to be interesting. 63327d5dc18SMarcel Moolenaar */ 63427d5dc18SMarcel Moolenaar uart_setreg(bas, REG_MCR, mcr); 63527d5dc18SMarcel Moolenaar uart_barrier(bas); 6368d1289feSMarcel Moolenaar sc->sc_rxfifosz = sc->sc_txfifosz = 1; 63727d5dc18SMarcel Moolenaar device_set_desc(sc->sc_dev, "8250 or 16450 or compatible"); 63827d5dc18SMarcel Moolenaar return (0); 63927d5dc18SMarcel Moolenaar } 64027d5dc18SMarcel Moolenaar 64189eef2deSThomas Moestl uart_setreg(bas, REG_FCR, FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST); 64227d5dc18SMarcel Moolenaar uart_barrier(bas); 64327d5dc18SMarcel Moolenaar 64427d5dc18SMarcel Moolenaar count = 0; 64527d5dc18SMarcel Moolenaar delay = ns8250_delay(bas); 64627d5dc18SMarcel Moolenaar 64727d5dc18SMarcel Moolenaar /* We have FIFOs. Drain the transmitter and receiver. */ 64827d5dc18SMarcel Moolenaar error = ns8250_drain(bas, UART_DRAIN_RECEIVER|UART_DRAIN_TRANSMITTER); 64927d5dc18SMarcel Moolenaar if (error) { 65027d5dc18SMarcel Moolenaar uart_setreg(bas, REG_MCR, mcr); 65127d5dc18SMarcel Moolenaar uart_setreg(bas, REG_FCR, 0); 65227d5dc18SMarcel Moolenaar uart_barrier(bas); 65327d5dc18SMarcel Moolenaar goto describe; 65427d5dc18SMarcel Moolenaar } 65527d5dc18SMarcel Moolenaar 65627d5dc18SMarcel Moolenaar /* 65727d5dc18SMarcel Moolenaar * We should have a sufficiently clean "pipe" to determine the 65827d5dc18SMarcel Moolenaar * size of the FIFOs. We send as much characters as is reasonable 65989eef2deSThomas Moestl * and wait for the the overflow bit in the LSR register to be 66089eef2deSThomas Moestl * asserted, counting the characters as we send them. Based on 66189eef2deSThomas Moestl * that count we know the FIFO size. 66227d5dc18SMarcel Moolenaar */ 66389eef2deSThomas Moestl do { 66427d5dc18SMarcel Moolenaar uart_setreg(bas, REG_DATA, 0); 66527d5dc18SMarcel Moolenaar uart_barrier(bas); 66627d5dc18SMarcel Moolenaar count++; 66727d5dc18SMarcel Moolenaar 66827d5dc18SMarcel Moolenaar limit = 30; 66989eef2deSThomas Moestl lsr = 0; 67089eef2deSThomas Moestl /* 67189eef2deSThomas Moestl * LSR bits are cleared upon read, so we must accumulate 67289eef2deSThomas Moestl * them to be able to test LSR_OE below. 67389eef2deSThomas Moestl */ 67489eef2deSThomas Moestl while (((lsr |= uart_getreg(bas, REG_LSR)) & LSR_TEMT) == 0 && 67589eef2deSThomas Moestl --limit) 67627d5dc18SMarcel Moolenaar DELAY(delay); 67727d5dc18SMarcel Moolenaar if (limit == 0) { 67858957d87SBenno Rice ier = uart_getreg(bas, REG_IER) & 0xf0; 67958957d87SBenno Rice uart_setreg(bas, REG_IER, ier); 68027d5dc18SMarcel Moolenaar uart_setreg(bas, REG_MCR, mcr); 68127d5dc18SMarcel Moolenaar uart_setreg(bas, REG_FCR, 0); 68227d5dc18SMarcel Moolenaar uart_barrier(bas); 68327d5dc18SMarcel Moolenaar count = 0; 68427d5dc18SMarcel Moolenaar goto describe; 68527d5dc18SMarcel Moolenaar } 686d882cf92SMarcel Moolenaar } while ((lsr & LSR_OE) == 0 && count < 130); 68789eef2deSThomas Moestl count--; 68827d5dc18SMarcel Moolenaar 68927d5dc18SMarcel Moolenaar uart_setreg(bas, REG_MCR, mcr); 69027d5dc18SMarcel Moolenaar 69127d5dc18SMarcel Moolenaar /* Reset FIFOs. */ 69227d5dc18SMarcel Moolenaar ns8250_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 69327d5dc18SMarcel Moolenaar 69427d5dc18SMarcel Moolenaar describe: 69589eef2deSThomas Moestl if (count >= 14 && count <= 16) { 69627d5dc18SMarcel Moolenaar sc->sc_rxfifosz = 16; 69727d5dc18SMarcel Moolenaar device_set_desc(sc->sc_dev, "16550 or compatible"); 69889eef2deSThomas Moestl } else if (count >= 28 && count <= 32) { 69927d5dc18SMarcel Moolenaar sc->sc_rxfifosz = 32; 70027d5dc18SMarcel Moolenaar device_set_desc(sc->sc_dev, "16650 or compatible"); 70189eef2deSThomas Moestl } else if (count >= 56 && count <= 64) { 70227d5dc18SMarcel Moolenaar sc->sc_rxfifosz = 64; 70327d5dc18SMarcel Moolenaar device_set_desc(sc->sc_dev, "16750 or compatible"); 70489eef2deSThomas Moestl } else if (count >= 112 && count <= 128) { 70527d5dc18SMarcel Moolenaar sc->sc_rxfifosz = 128; 70627d5dc18SMarcel Moolenaar device_set_desc(sc->sc_dev, "16950 or compatible"); 70727d5dc18SMarcel Moolenaar } else { 708c21e0da2SMarcel Moolenaar sc->sc_rxfifosz = 16; 70927d5dc18SMarcel Moolenaar device_set_desc(sc->sc_dev, 71027d5dc18SMarcel Moolenaar "Non-standard ns8250 class UART with FIFOs"); 71127d5dc18SMarcel Moolenaar } 71227d5dc18SMarcel Moolenaar 71327d5dc18SMarcel Moolenaar /* 71427d5dc18SMarcel Moolenaar * Force the Tx FIFO size to 16 bytes for now. We don't program the 71527d5dc18SMarcel Moolenaar * Tx trigger. Also, we assume that all data has been sent when the 71627d5dc18SMarcel Moolenaar * interrupt happens. 71727d5dc18SMarcel Moolenaar */ 71827d5dc18SMarcel Moolenaar sc->sc_txfifosz = 16; 71927d5dc18SMarcel Moolenaar 720dc70e792SMarcel Moolenaar #if 0 721dc70e792SMarcel Moolenaar /* 722dc70e792SMarcel Moolenaar * XXX there are some issues related to hardware flow control and 723dc70e792SMarcel Moolenaar * it's likely that uart(4) is the cause. This basicly needs more 724dc70e792SMarcel Moolenaar * investigation, but we avoid using for hardware flow control 725dc70e792SMarcel Moolenaar * until then. 726dc70e792SMarcel Moolenaar */ 72784c7b427SMarcel Moolenaar /* 16650s or higher have automatic flow control. */ 72884c7b427SMarcel Moolenaar if (sc->sc_rxfifosz > 16) { 72984c7b427SMarcel Moolenaar sc->sc_hwiflow = 1; 73084c7b427SMarcel Moolenaar sc->sc_hwoflow = 1; 73184c7b427SMarcel Moolenaar } 732dc70e792SMarcel Moolenaar #endif 73384c7b427SMarcel Moolenaar 73427d5dc18SMarcel Moolenaar return (0); 73527d5dc18SMarcel Moolenaar } 73627d5dc18SMarcel Moolenaar 73727d5dc18SMarcel Moolenaar static int 73827d5dc18SMarcel Moolenaar ns8250_bus_receive(struct uart_softc *sc) 73927d5dc18SMarcel Moolenaar { 74027d5dc18SMarcel Moolenaar struct uart_bas *bas; 74127d5dc18SMarcel Moolenaar int xc; 74227d5dc18SMarcel Moolenaar uint8_t lsr; 74327d5dc18SMarcel Moolenaar 74427d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 7458af03381SMarcel Moolenaar uart_lock(sc->sc_hwmtx); 74627d5dc18SMarcel Moolenaar lsr = uart_getreg(bas, REG_LSR); 74744ed791bSMarcel Moolenaar while (lsr & LSR_RXRDY) { 74844ed791bSMarcel Moolenaar if (uart_rx_full(sc)) { 74944ed791bSMarcel Moolenaar sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; 75027d5dc18SMarcel Moolenaar break; 75144ed791bSMarcel Moolenaar } 75227d5dc18SMarcel Moolenaar xc = uart_getreg(bas, REG_DATA); 75327d5dc18SMarcel Moolenaar if (lsr & LSR_FE) 75427d5dc18SMarcel Moolenaar xc |= UART_STAT_FRAMERR; 75527d5dc18SMarcel Moolenaar if (lsr & LSR_PE) 75627d5dc18SMarcel Moolenaar xc |= UART_STAT_PARERR; 75727d5dc18SMarcel Moolenaar uart_rx_put(sc, xc); 75844ed791bSMarcel Moolenaar lsr = uart_getreg(bas, REG_LSR); 75944ed791bSMarcel Moolenaar } 76044ed791bSMarcel Moolenaar /* Discard everything left in the Rx FIFO. */ 76144ed791bSMarcel Moolenaar while (lsr & LSR_RXRDY) { 76244ed791bSMarcel Moolenaar (void)uart_getreg(bas, REG_DATA); 76344ed791bSMarcel Moolenaar uart_barrier(bas); 76444ed791bSMarcel Moolenaar lsr = uart_getreg(bas, REG_LSR); 76527d5dc18SMarcel Moolenaar } 7668af03381SMarcel Moolenaar uart_unlock(sc->sc_hwmtx); 76727d5dc18SMarcel Moolenaar return (0); 76827d5dc18SMarcel Moolenaar } 76927d5dc18SMarcel Moolenaar 77027d5dc18SMarcel Moolenaar static int 77127d5dc18SMarcel Moolenaar ns8250_bus_setsig(struct uart_softc *sc, int sig) 77227d5dc18SMarcel Moolenaar { 77327d5dc18SMarcel Moolenaar struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 77427d5dc18SMarcel Moolenaar struct uart_bas *bas; 77527d5dc18SMarcel Moolenaar uint32_t new, old; 77627d5dc18SMarcel Moolenaar 77727d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 77827d5dc18SMarcel Moolenaar do { 77927d5dc18SMarcel Moolenaar old = sc->sc_hwsig; 78027d5dc18SMarcel Moolenaar new = old; 78128710806SPoul-Henning Kamp if (sig & SER_DDTR) { 78228710806SPoul-Henning Kamp SIGCHG(sig & SER_DTR, new, SER_DTR, 78328710806SPoul-Henning Kamp SER_DDTR); 78427d5dc18SMarcel Moolenaar } 78528710806SPoul-Henning Kamp if (sig & SER_DRTS) { 78628710806SPoul-Henning Kamp SIGCHG(sig & SER_RTS, new, SER_RTS, 78728710806SPoul-Henning Kamp SER_DRTS); 78827d5dc18SMarcel Moolenaar } 78927d5dc18SMarcel Moolenaar } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 7908af03381SMarcel Moolenaar uart_lock(sc->sc_hwmtx); 79127d5dc18SMarcel Moolenaar ns8250->mcr &= ~(MCR_DTR|MCR_RTS); 79228710806SPoul-Henning Kamp if (new & SER_DTR) 79327d5dc18SMarcel Moolenaar ns8250->mcr |= MCR_DTR; 79428710806SPoul-Henning Kamp if (new & SER_RTS) 79527d5dc18SMarcel Moolenaar ns8250->mcr |= MCR_RTS; 79627d5dc18SMarcel Moolenaar uart_setreg(bas, REG_MCR, ns8250->mcr); 79727d5dc18SMarcel Moolenaar uart_barrier(bas); 7988af03381SMarcel Moolenaar uart_unlock(sc->sc_hwmtx); 79927d5dc18SMarcel Moolenaar return (0); 80027d5dc18SMarcel Moolenaar } 80127d5dc18SMarcel Moolenaar 80227d5dc18SMarcel Moolenaar static int 80327d5dc18SMarcel Moolenaar ns8250_bus_transmit(struct uart_softc *sc) 80427d5dc18SMarcel Moolenaar { 80527d5dc18SMarcel Moolenaar struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 80627d5dc18SMarcel Moolenaar struct uart_bas *bas; 80727d5dc18SMarcel Moolenaar int i; 80827d5dc18SMarcel Moolenaar 80927d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 8108af03381SMarcel Moolenaar uart_lock(sc->sc_hwmtx); 81127d5dc18SMarcel Moolenaar while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0) 81227d5dc18SMarcel Moolenaar ; 81327d5dc18SMarcel Moolenaar uart_setreg(bas, REG_IER, ns8250->ier | IER_ETXRDY); 81427d5dc18SMarcel Moolenaar uart_barrier(bas); 81527d5dc18SMarcel Moolenaar for (i = 0; i < sc->sc_txdatasz; i++) { 81627d5dc18SMarcel Moolenaar uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]); 81727d5dc18SMarcel Moolenaar uart_barrier(bas); 81827d5dc18SMarcel Moolenaar } 81927d5dc18SMarcel Moolenaar sc->sc_txbusy = 1; 8208af03381SMarcel Moolenaar uart_unlock(sc->sc_hwmtx); 82127d5dc18SMarcel Moolenaar return (0); 82227d5dc18SMarcel Moolenaar } 823