1098ca2bdSWarner Losh /*- 227d5dc18SMarcel Moolenaar * Copyright (c) 2003 Marcel Moolenaar 327d5dc18SMarcel Moolenaar * All rights reserved. 427d5dc18SMarcel Moolenaar * 527d5dc18SMarcel Moolenaar * Redistribution and use in source and binary forms, with or without 627d5dc18SMarcel Moolenaar * modification, are permitted provided that the following conditions 727d5dc18SMarcel Moolenaar * are met: 827d5dc18SMarcel Moolenaar * 927d5dc18SMarcel Moolenaar * 1. Redistributions of source code must retain the above copyright 1027d5dc18SMarcel Moolenaar * notice, this list of conditions and the following disclaimer. 1127d5dc18SMarcel Moolenaar * 2. Redistributions in binary form must reproduce the above copyright 1227d5dc18SMarcel Moolenaar * notice, this list of conditions and the following disclaimer in the 1327d5dc18SMarcel Moolenaar * documentation and/or other materials provided with the distribution. 1427d5dc18SMarcel Moolenaar * 1527d5dc18SMarcel Moolenaar * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 1627d5dc18SMarcel Moolenaar * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 1727d5dc18SMarcel Moolenaar * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 1827d5dc18SMarcel Moolenaar * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 1927d5dc18SMarcel Moolenaar * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 2027d5dc18SMarcel Moolenaar * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2127d5dc18SMarcel Moolenaar * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2227d5dc18SMarcel Moolenaar * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2327d5dc18SMarcel Moolenaar * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 2427d5dc18SMarcel Moolenaar * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2527d5dc18SMarcel Moolenaar */ 2627d5dc18SMarcel Moolenaar 27ac4adddfSGanbold Tsagaankhuu #include "opt_platform.h" 28ac4adddfSGanbold Tsagaankhuu 2927d5dc18SMarcel Moolenaar #include <sys/cdefs.h> 3027d5dc18SMarcel Moolenaar __FBSDID("$FreeBSD$"); 3127d5dc18SMarcel Moolenaar 3227d5dc18SMarcel Moolenaar #include <sys/param.h> 3327d5dc18SMarcel Moolenaar #include <sys/systm.h> 3427d5dc18SMarcel Moolenaar #include <sys/bus.h> 3527d5dc18SMarcel Moolenaar #include <sys/conf.h> 361c60b24bSColin Percival #include <sys/kernel.h> 371c60b24bSColin Percival #include <sys/sysctl.h> 3827d5dc18SMarcel Moolenaar #include <machine/bus.h> 3927d5dc18SMarcel Moolenaar 40ac4adddfSGanbold Tsagaankhuu #ifdef FDT 41ac4adddfSGanbold Tsagaankhuu #include <dev/fdt/fdt_common.h> 42ac4adddfSGanbold Tsagaankhuu #include <dev/ofw/ofw_bus.h> 43ac4adddfSGanbold Tsagaankhuu #include <dev/ofw/ofw_bus_subr.h> 44ac4adddfSGanbold Tsagaankhuu #endif 45ac4adddfSGanbold Tsagaankhuu 4627d5dc18SMarcel Moolenaar #include <dev/uart/uart.h> 4727d5dc18SMarcel Moolenaar #include <dev/uart/uart_cpu.h> 4827d5dc18SMarcel Moolenaar #include <dev/uart/uart_bus.h> 49167cb33fSIan Lepore #include <dev/uart/uart_dev_ns8250.h> 5076563beaSMarcel Moolenaar 5176563beaSMarcel Moolenaar #include <dev/ic/ns16550.h> 5227d5dc18SMarcel Moolenaar 5327d5dc18SMarcel Moolenaar #include "uart_if.h" 5427d5dc18SMarcel Moolenaar 5527d5dc18SMarcel Moolenaar #define DEFAULT_RCLK 1843200 5627d5dc18SMarcel Moolenaar 57ac4adddfSGanbold Tsagaankhuu static int broken_txfifo = 0; 58af3b2549SHans Petter Selasky SYSCTL_INT(_hw, OID_AUTO, broken_txfifo, CTLFLAG_RWTUN, 59ac4adddfSGanbold Tsagaankhuu &broken_txfifo, 0, "UART FIFO has QEMU emulation bug"); 60ac4adddfSGanbold Tsagaankhuu 6127d5dc18SMarcel Moolenaar /* 6227d5dc18SMarcel Moolenaar * Clear pending interrupts. THRE is cleared by reading IIR. Data 6327d5dc18SMarcel Moolenaar * that may have been received gets lost here. 6427d5dc18SMarcel Moolenaar */ 6527d5dc18SMarcel Moolenaar static void 6627d5dc18SMarcel Moolenaar ns8250_clrint(struct uart_bas *bas) 6727d5dc18SMarcel Moolenaar { 68d7ae5af5SMarcel Moolenaar uint8_t iir, lsr; 6927d5dc18SMarcel Moolenaar 7027d5dc18SMarcel Moolenaar iir = uart_getreg(bas, REG_IIR); 7127d5dc18SMarcel Moolenaar while ((iir & IIR_NOPEND) == 0) { 7227d5dc18SMarcel Moolenaar iir &= IIR_IMASK; 73d7ae5af5SMarcel Moolenaar if (iir == IIR_RLS) { 74d7ae5af5SMarcel Moolenaar lsr = uart_getreg(bas, REG_LSR); 75d7ae5af5SMarcel Moolenaar if (lsr & (LSR_BI|LSR_FE|LSR_PE)) 76d7ae5af5SMarcel Moolenaar (void)uart_getreg(bas, REG_DATA); 77d7ae5af5SMarcel Moolenaar } else if (iir == IIR_RXRDY || iir == IIR_RXTOUT) 7827d5dc18SMarcel Moolenaar (void)uart_getreg(bas, REG_DATA); 7927d5dc18SMarcel Moolenaar else if (iir == IIR_MLSC) 8027d5dc18SMarcel Moolenaar (void)uart_getreg(bas, REG_MSR); 8127d5dc18SMarcel Moolenaar uart_barrier(bas); 8227d5dc18SMarcel Moolenaar iir = uart_getreg(bas, REG_IIR); 8327d5dc18SMarcel Moolenaar } 8427d5dc18SMarcel Moolenaar } 8527d5dc18SMarcel Moolenaar 8627d5dc18SMarcel Moolenaar static int 8727d5dc18SMarcel Moolenaar ns8250_delay(struct uart_bas *bas) 8827d5dc18SMarcel Moolenaar { 8927d5dc18SMarcel Moolenaar int divisor; 9027d5dc18SMarcel Moolenaar u_char lcr; 9127d5dc18SMarcel Moolenaar 9227d5dc18SMarcel Moolenaar lcr = uart_getreg(bas, REG_LCR); 9327d5dc18SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 9427d5dc18SMarcel Moolenaar uart_barrier(bas); 9558957d87SBenno Rice divisor = uart_getreg(bas, REG_DLL) | (uart_getreg(bas, REG_DLH) << 8); 9627d5dc18SMarcel Moolenaar uart_barrier(bas); 9727d5dc18SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr); 9827d5dc18SMarcel Moolenaar uart_barrier(bas); 9927d5dc18SMarcel Moolenaar 10027d5dc18SMarcel Moolenaar /* 1/10th the time to transmit 1 character (estimate). */ 101ebecffe9SMarcel Moolenaar if (divisor <= 134) 10227d5dc18SMarcel Moolenaar return (16000000 * divisor / bas->rclk); 103ebecffe9SMarcel Moolenaar return (16000 * divisor / (bas->rclk / 1000)); 10427d5dc18SMarcel Moolenaar } 10527d5dc18SMarcel Moolenaar 10627d5dc18SMarcel Moolenaar static int 10727d5dc18SMarcel Moolenaar ns8250_divisor(int rclk, int baudrate) 10827d5dc18SMarcel Moolenaar { 10927d5dc18SMarcel Moolenaar int actual_baud, divisor; 11027d5dc18SMarcel Moolenaar int error; 11127d5dc18SMarcel Moolenaar 11227d5dc18SMarcel Moolenaar if (baudrate == 0) 11327d5dc18SMarcel Moolenaar return (0); 11427d5dc18SMarcel Moolenaar 11527d5dc18SMarcel Moolenaar divisor = (rclk / (baudrate << 3) + 1) >> 1; 11627d5dc18SMarcel Moolenaar if (divisor == 0 || divisor >= 65536) 11727d5dc18SMarcel Moolenaar return (0); 11827d5dc18SMarcel Moolenaar actual_baud = rclk / (divisor << 4); 11927d5dc18SMarcel Moolenaar 12027d5dc18SMarcel Moolenaar /* 10 times error in percent: */ 12127d5dc18SMarcel Moolenaar error = ((actual_baud - baudrate) * 2000 / baudrate + 1) >> 1; 12227d5dc18SMarcel Moolenaar 12327d5dc18SMarcel Moolenaar /* 3.0% maximum error tolerance: */ 12427d5dc18SMarcel Moolenaar if (error < -30 || error > 30) 12527d5dc18SMarcel Moolenaar return (0); 12627d5dc18SMarcel Moolenaar 12727d5dc18SMarcel Moolenaar return (divisor); 12827d5dc18SMarcel Moolenaar } 12927d5dc18SMarcel Moolenaar 13027d5dc18SMarcel Moolenaar static int 13127d5dc18SMarcel Moolenaar ns8250_drain(struct uart_bas *bas, int what) 13227d5dc18SMarcel Moolenaar { 13327d5dc18SMarcel Moolenaar int delay, limit; 13427d5dc18SMarcel Moolenaar 13527d5dc18SMarcel Moolenaar delay = ns8250_delay(bas); 13627d5dc18SMarcel Moolenaar 13727d5dc18SMarcel Moolenaar if (what & UART_DRAIN_TRANSMITTER) { 13827d5dc18SMarcel Moolenaar /* 13927d5dc18SMarcel Moolenaar * Pick an arbitrary high limit to avoid getting stuck in 14027d5dc18SMarcel Moolenaar * an infinite loop when the hardware is broken. Make the 14127d5dc18SMarcel Moolenaar * limit high enough to handle large FIFOs. 14227d5dc18SMarcel Moolenaar */ 14327d5dc18SMarcel Moolenaar limit = 10*1024; 14427d5dc18SMarcel Moolenaar while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) 14527d5dc18SMarcel Moolenaar DELAY(delay); 14627d5dc18SMarcel Moolenaar if (limit == 0) { 14727d5dc18SMarcel Moolenaar /* printf("ns8250: transmitter appears stuck... "); */ 14827d5dc18SMarcel Moolenaar return (EIO); 14927d5dc18SMarcel Moolenaar } 15027d5dc18SMarcel Moolenaar } 15127d5dc18SMarcel Moolenaar 15227d5dc18SMarcel Moolenaar if (what & UART_DRAIN_RECEIVER) { 15327d5dc18SMarcel Moolenaar /* 15427d5dc18SMarcel Moolenaar * Pick an arbitrary high limit to avoid getting stuck in 15527d5dc18SMarcel Moolenaar * an infinite loop when the hardware is broken. Make the 15627d5dc18SMarcel Moolenaar * limit high enough to handle large FIFOs and integrated 15727d5dc18SMarcel Moolenaar * UARTs. The HP rx2600 for example has 3 UARTs on the 15827d5dc18SMarcel Moolenaar * management board that tend to get a lot of data send 15927d5dc18SMarcel Moolenaar * to it when the UART is first activated. 16027d5dc18SMarcel Moolenaar */ 16127d5dc18SMarcel Moolenaar limit=10*4096; 16227d5dc18SMarcel Moolenaar while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) { 16327d5dc18SMarcel Moolenaar (void)uart_getreg(bas, REG_DATA); 16427d5dc18SMarcel Moolenaar uart_barrier(bas); 16527d5dc18SMarcel Moolenaar DELAY(delay << 2); 16627d5dc18SMarcel Moolenaar } 16727d5dc18SMarcel Moolenaar if (limit == 0) { 16827d5dc18SMarcel Moolenaar /* printf("ns8250: receiver appears broken... "); */ 16927d5dc18SMarcel Moolenaar return (EIO); 17027d5dc18SMarcel Moolenaar } 17127d5dc18SMarcel Moolenaar } 17227d5dc18SMarcel Moolenaar 17327d5dc18SMarcel Moolenaar return (0); 17427d5dc18SMarcel Moolenaar } 17527d5dc18SMarcel Moolenaar 17627d5dc18SMarcel Moolenaar /* 17727d5dc18SMarcel Moolenaar * We can only flush UARTs with FIFOs. UARTs without FIFOs should be 17827d5dc18SMarcel Moolenaar * drained. WARNING: this function clobbers the FIFO setting! 17927d5dc18SMarcel Moolenaar */ 18027d5dc18SMarcel Moolenaar static void 18127d5dc18SMarcel Moolenaar ns8250_flush(struct uart_bas *bas, int what) 18227d5dc18SMarcel Moolenaar { 18327d5dc18SMarcel Moolenaar uint8_t fcr; 18427d5dc18SMarcel Moolenaar 18527d5dc18SMarcel Moolenaar fcr = FCR_ENABLE; 18627d5dc18SMarcel Moolenaar if (what & UART_FLUSH_TRANSMITTER) 18727d5dc18SMarcel Moolenaar fcr |= FCR_XMT_RST; 18827d5dc18SMarcel Moolenaar if (what & UART_FLUSH_RECEIVER) 18927d5dc18SMarcel Moolenaar fcr |= FCR_RCV_RST; 19027d5dc18SMarcel Moolenaar uart_setreg(bas, REG_FCR, fcr); 19127d5dc18SMarcel Moolenaar uart_barrier(bas); 19227d5dc18SMarcel Moolenaar } 19327d5dc18SMarcel Moolenaar 19427d5dc18SMarcel Moolenaar static int 19527d5dc18SMarcel Moolenaar ns8250_param(struct uart_bas *bas, int baudrate, int databits, int stopbits, 19627d5dc18SMarcel Moolenaar int parity) 19727d5dc18SMarcel Moolenaar { 19827d5dc18SMarcel Moolenaar int divisor; 19927d5dc18SMarcel Moolenaar uint8_t lcr; 20027d5dc18SMarcel Moolenaar 20127d5dc18SMarcel Moolenaar lcr = 0; 20227d5dc18SMarcel Moolenaar if (databits >= 8) 20327d5dc18SMarcel Moolenaar lcr |= LCR_8BITS; 20427d5dc18SMarcel Moolenaar else if (databits == 7) 20527d5dc18SMarcel Moolenaar lcr |= LCR_7BITS; 20627d5dc18SMarcel Moolenaar else if (databits == 6) 20727d5dc18SMarcel Moolenaar lcr |= LCR_6BITS; 20827d5dc18SMarcel Moolenaar else 20927d5dc18SMarcel Moolenaar lcr |= LCR_5BITS; 21027d5dc18SMarcel Moolenaar if (stopbits > 1) 21127d5dc18SMarcel Moolenaar lcr |= LCR_STOPB; 21227d5dc18SMarcel Moolenaar lcr |= parity << 3; 21327d5dc18SMarcel Moolenaar 21427d5dc18SMarcel Moolenaar /* Set baudrate. */ 21527d5dc18SMarcel Moolenaar if (baudrate > 0) { 21627d5dc18SMarcel Moolenaar divisor = ns8250_divisor(bas->rclk, baudrate); 21727d5dc18SMarcel Moolenaar if (divisor == 0) 21827d5dc18SMarcel Moolenaar return (EINVAL); 21963f8efd3SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 22063f8efd3SMarcel Moolenaar uart_barrier(bas); 22158957d87SBenno Rice uart_setreg(bas, REG_DLL, divisor & 0xff); 22258957d87SBenno Rice uart_setreg(bas, REG_DLH, (divisor >> 8) & 0xff); 22327d5dc18SMarcel Moolenaar uart_barrier(bas); 22427d5dc18SMarcel Moolenaar } 22527d5dc18SMarcel Moolenaar 22627d5dc18SMarcel Moolenaar /* Set LCR and clear DLAB. */ 22727d5dc18SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr); 22827d5dc18SMarcel Moolenaar uart_barrier(bas); 22927d5dc18SMarcel Moolenaar return (0); 23027d5dc18SMarcel Moolenaar } 23127d5dc18SMarcel Moolenaar 23227d5dc18SMarcel Moolenaar /* 23327d5dc18SMarcel Moolenaar * Low-level UART interface. 23427d5dc18SMarcel Moolenaar */ 23527d5dc18SMarcel Moolenaar static int ns8250_probe(struct uart_bas *bas); 23627d5dc18SMarcel Moolenaar static void ns8250_init(struct uart_bas *bas, int, int, int, int); 23727d5dc18SMarcel Moolenaar static void ns8250_term(struct uart_bas *bas); 23827d5dc18SMarcel Moolenaar static void ns8250_putc(struct uart_bas *bas, int); 23997202af2SMarius Strobl static int ns8250_rxready(struct uart_bas *bas); 240634e63c9SMarcel Moolenaar static int ns8250_getc(struct uart_bas *bas, struct mtx *); 24127d5dc18SMarcel Moolenaar 242167cb33fSIan Lepore struct uart_ops uart_ns8250_ops = { 24327d5dc18SMarcel Moolenaar .probe = ns8250_probe, 24427d5dc18SMarcel Moolenaar .init = ns8250_init, 24527d5dc18SMarcel Moolenaar .term = ns8250_term, 24627d5dc18SMarcel Moolenaar .putc = ns8250_putc, 24797202af2SMarius Strobl .rxready = ns8250_rxready, 24827d5dc18SMarcel Moolenaar .getc = ns8250_getc, 24927d5dc18SMarcel Moolenaar }; 25027d5dc18SMarcel Moolenaar 25127d5dc18SMarcel Moolenaar static int 25227d5dc18SMarcel Moolenaar ns8250_probe(struct uart_bas *bas) 25327d5dc18SMarcel Moolenaar { 2548bceca4fSBenno Rice u_char val; 25527d5dc18SMarcel Moolenaar 25627d5dc18SMarcel Moolenaar /* Check known 0 bits that don't depend on DLAB. */ 25727d5dc18SMarcel Moolenaar val = uart_getreg(bas, REG_IIR); 25827d5dc18SMarcel Moolenaar if (val & 0x30) 25927d5dc18SMarcel Moolenaar return (ENXIO); 2605bdddc29SMarcel Moolenaar /* 2615bdddc29SMarcel Moolenaar * Bit 6 of the MCR (= 0x40) appears to be 1 for the Sun1699 2625bdddc29SMarcel Moolenaar * chip, but otherwise doesn't seem to have a function. In 2635bdddc29SMarcel Moolenaar * other words, uart(4) works regardless. Ignore that bit so 2645bdddc29SMarcel Moolenaar * the probe succeeds. 2655bdddc29SMarcel Moolenaar */ 26627d5dc18SMarcel Moolenaar val = uart_getreg(bas, REG_MCR); 2675bdddc29SMarcel Moolenaar if (val & 0xa0) 26827d5dc18SMarcel Moolenaar return (ENXIO); 26927d5dc18SMarcel Moolenaar 27027d5dc18SMarcel Moolenaar return (0); 27127d5dc18SMarcel Moolenaar } 27227d5dc18SMarcel Moolenaar 27327d5dc18SMarcel Moolenaar static void 27427d5dc18SMarcel Moolenaar ns8250_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, 27527d5dc18SMarcel Moolenaar int parity) 27627d5dc18SMarcel Moolenaar { 27758957d87SBenno Rice u_char ier; 27827d5dc18SMarcel Moolenaar 27927d5dc18SMarcel Moolenaar if (bas->rclk == 0) 28027d5dc18SMarcel Moolenaar bas->rclk = DEFAULT_RCLK; 28127d5dc18SMarcel Moolenaar ns8250_param(bas, baudrate, databits, stopbits, parity); 28227d5dc18SMarcel Moolenaar 28327d5dc18SMarcel Moolenaar /* Disable all interrupt sources. */ 2840aefb0a6SBenno Rice /* 2850aefb0a6SBenno Rice * We use 0xe0 instead of 0xf0 as the mask because the XScale PXA 2860aefb0a6SBenno Rice * UARTs split the receive time-out interrupt bit out separately as 2870aefb0a6SBenno Rice * 0x10. This gets handled by ier_mask and ier_rxbits below. 2880aefb0a6SBenno Rice */ 2890aefb0a6SBenno Rice ier = uart_getreg(bas, REG_IER) & 0xe0; 29058957d87SBenno Rice uart_setreg(bas, REG_IER, ier); 29127d5dc18SMarcel Moolenaar uart_barrier(bas); 29227d5dc18SMarcel Moolenaar 29327d5dc18SMarcel Moolenaar /* Disable the FIFO (if present). */ 29427d5dc18SMarcel Moolenaar uart_setreg(bas, REG_FCR, 0); 29527d5dc18SMarcel Moolenaar uart_barrier(bas); 29627d5dc18SMarcel Moolenaar 29727d5dc18SMarcel Moolenaar /* Set RTS & DTR. */ 29827d5dc18SMarcel Moolenaar uart_setreg(bas, REG_MCR, MCR_IE | MCR_RTS | MCR_DTR); 29927d5dc18SMarcel Moolenaar uart_barrier(bas); 30027d5dc18SMarcel Moolenaar 30127d5dc18SMarcel Moolenaar ns8250_clrint(bas); 30227d5dc18SMarcel Moolenaar } 30327d5dc18SMarcel Moolenaar 30427d5dc18SMarcel Moolenaar static void 30527d5dc18SMarcel Moolenaar ns8250_term(struct uart_bas *bas) 30627d5dc18SMarcel Moolenaar { 30727d5dc18SMarcel Moolenaar 30827d5dc18SMarcel Moolenaar /* Clear RTS & DTR. */ 30927d5dc18SMarcel Moolenaar uart_setreg(bas, REG_MCR, MCR_IE); 31027d5dc18SMarcel Moolenaar uart_barrier(bas); 31127d5dc18SMarcel Moolenaar } 31227d5dc18SMarcel Moolenaar 31327d5dc18SMarcel Moolenaar static void 31427d5dc18SMarcel Moolenaar ns8250_putc(struct uart_bas *bas, int c) 31527d5dc18SMarcel Moolenaar { 31635777a2aSMarcel Moolenaar int limit; 31727d5dc18SMarcel Moolenaar 31835777a2aSMarcel Moolenaar limit = 250000; 31927d5dc18SMarcel Moolenaar while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0 && --limit) 32035777a2aSMarcel Moolenaar DELAY(4); 32127d5dc18SMarcel Moolenaar uart_setreg(bas, REG_DATA, c); 3224e55f723SMarcel Moolenaar uart_barrier(bas); 32335777a2aSMarcel Moolenaar limit = 250000; 32427d5dc18SMarcel Moolenaar while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) 32535777a2aSMarcel Moolenaar DELAY(4); 32627d5dc18SMarcel Moolenaar } 32727d5dc18SMarcel Moolenaar 32827d5dc18SMarcel Moolenaar static int 32997202af2SMarius Strobl ns8250_rxready(struct uart_bas *bas) 33027d5dc18SMarcel Moolenaar { 33127d5dc18SMarcel Moolenaar 33297202af2SMarius Strobl return ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) != 0 ? 1 : 0); 33327d5dc18SMarcel Moolenaar } 33427d5dc18SMarcel Moolenaar 33527d5dc18SMarcel Moolenaar static int 336634e63c9SMarcel Moolenaar ns8250_getc(struct uart_bas *bas, struct mtx *hwmtx) 33727d5dc18SMarcel Moolenaar { 33835777a2aSMarcel Moolenaar int c; 339634e63c9SMarcel Moolenaar 340634e63c9SMarcel Moolenaar uart_lock(hwmtx); 34127d5dc18SMarcel Moolenaar 342634e63c9SMarcel Moolenaar while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0) { 343634e63c9SMarcel Moolenaar uart_unlock(hwmtx); 34435777a2aSMarcel Moolenaar DELAY(4); 345634e63c9SMarcel Moolenaar uart_lock(hwmtx); 346634e63c9SMarcel Moolenaar } 347634e63c9SMarcel Moolenaar 348634e63c9SMarcel Moolenaar c = uart_getreg(bas, REG_DATA); 349634e63c9SMarcel Moolenaar 350634e63c9SMarcel Moolenaar uart_unlock(hwmtx); 351634e63c9SMarcel Moolenaar 352634e63c9SMarcel Moolenaar return (c); 35327d5dc18SMarcel Moolenaar } 35427d5dc18SMarcel Moolenaar 35527d5dc18SMarcel Moolenaar static kobj_method_t ns8250_methods[] = { 35627d5dc18SMarcel Moolenaar KOBJMETHOD(uart_attach, ns8250_bus_attach), 35727d5dc18SMarcel Moolenaar KOBJMETHOD(uart_detach, ns8250_bus_detach), 35827d5dc18SMarcel Moolenaar KOBJMETHOD(uart_flush, ns8250_bus_flush), 35927d5dc18SMarcel Moolenaar KOBJMETHOD(uart_getsig, ns8250_bus_getsig), 36027d5dc18SMarcel Moolenaar KOBJMETHOD(uart_ioctl, ns8250_bus_ioctl), 36127d5dc18SMarcel Moolenaar KOBJMETHOD(uart_ipend, ns8250_bus_ipend), 36227d5dc18SMarcel Moolenaar KOBJMETHOD(uart_param, ns8250_bus_param), 36327d5dc18SMarcel Moolenaar KOBJMETHOD(uart_probe, ns8250_bus_probe), 36427d5dc18SMarcel Moolenaar KOBJMETHOD(uart_receive, ns8250_bus_receive), 36527d5dc18SMarcel Moolenaar KOBJMETHOD(uart_setsig, ns8250_bus_setsig), 36627d5dc18SMarcel Moolenaar KOBJMETHOD(uart_transmit, ns8250_bus_transmit), 367d76a1ef4SWarner Losh KOBJMETHOD(uart_grab, ns8250_bus_grab), 368d76a1ef4SWarner Losh KOBJMETHOD(uart_ungrab, ns8250_bus_ungrab), 36927d5dc18SMarcel Moolenaar { 0, 0 } 37027d5dc18SMarcel Moolenaar }; 37127d5dc18SMarcel Moolenaar 37227d5dc18SMarcel Moolenaar struct uart_class uart_ns8250_class = { 373f8100ce2SMarcel Moolenaar "ns8250", 37427d5dc18SMarcel Moolenaar ns8250_methods, 37527d5dc18SMarcel Moolenaar sizeof(struct ns8250_softc), 376f8100ce2SMarcel Moolenaar .uc_ops = &uart_ns8250_ops, 37727d5dc18SMarcel Moolenaar .uc_range = 8, 37827d5dc18SMarcel Moolenaar .uc_rclk = DEFAULT_RCLK 37927d5dc18SMarcel Moolenaar }; 38027d5dc18SMarcel Moolenaar 38127d5dc18SMarcel Moolenaar #define SIGCHG(c, i, s, d) \ 38227d5dc18SMarcel Moolenaar if (c) { \ 38327d5dc18SMarcel Moolenaar i |= (i & s) ? s : s | d; \ 38427d5dc18SMarcel Moolenaar } else { \ 38527d5dc18SMarcel Moolenaar i = (i & s) ? (i & ~s) | d : i; \ 38627d5dc18SMarcel Moolenaar } 38727d5dc18SMarcel Moolenaar 388167cb33fSIan Lepore int 38927d5dc18SMarcel Moolenaar ns8250_bus_attach(struct uart_softc *sc) 39027d5dc18SMarcel Moolenaar { 39127d5dc18SMarcel Moolenaar struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 39227d5dc18SMarcel Moolenaar struct uart_bas *bas; 393823c77d7SSam Leffler unsigned int ivar; 394ac4adddfSGanbold Tsagaankhuu #ifdef FDT 395ac4adddfSGanbold Tsagaankhuu phandle_t node; 396ac4adddfSGanbold Tsagaankhuu pcell_t cell; 397ac4adddfSGanbold Tsagaankhuu #endif 398ac4adddfSGanbold Tsagaankhuu 399ac4adddfSGanbold Tsagaankhuu ns8250->busy_detect = 0; 400ac4adddfSGanbold Tsagaankhuu 401ac4adddfSGanbold Tsagaankhuu #ifdef FDT 402ac4adddfSGanbold Tsagaankhuu /* 403ac4adddfSGanbold Tsagaankhuu * Check whether uart requires to read USR reg when IIR_BUSY and 404ac4adddfSGanbold Tsagaankhuu * has broken txfifo. 405ac4adddfSGanbold Tsagaankhuu */ 406ac4adddfSGanbold Tsagaankhuu node = ofw_bus_get_node(sc->sc_dev); 407ac4adddfSGanbold Tsagaankhuu if ((OF_getprop(node, "busy-detect", &cell, sizeof(cell))) > 0) 408ac4adddfSGanbold Tsagaankhuu ns8250->busy_detect = 1; 409ac4adddfSGanbold Tsagaankhuu if ((OF_getprop(node, "broken-txfifo", &cell, sizeof(cell))) > 0) 410ac4adddfSGanbold Tsagaankhuu broken_txfifo = 1; 411ac4adddfSGanbold Tsagaankhuu #endif 41227d5dc18SMarcel Moolenaar 41327d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 41427d5dc18SMarcel Moolenaar 41527d5dc18SMarcel Moolenaar ns8250->mcr = uart_getreg(bas, REG_MCR); 416823c77d7SSam Leffler ns8250->fcr = FCR_ENABLE; 417823c77d7SSam Leffler if (!resource_int_value("uart", device_get_unit(sc->sc_dev), "flags", 418823c77d7SSam Leffler &ivar)) { 419823c77d7SSam Leffler if (UART_FLAGS_FCR_RX_LOW(ivar)) 420823c77d7SSam Leffler ns8250->fcr |= FCR_RX_LOW; 421823c77d7SSam Leffler else if (UART_FLAGS_FCR_RX_MEDL(ivar)) 422823c77d7SSam Leffler ns8250->fcr |= FCR_RX_MEDL; 423823c77d7SSam Leffler else if (UART_FLAGS_FCR_RX_HIGH(ivar)) 424823c77d7SSam Leffler ns8250->fcr |= FCR_RX_HIGH; 425823c77d7SSam Leffler else 426823c77d7SSam Leffler ns8250->fcr |= FCR_RX_MEDH; 427823c77d7SSam Leffler } else 428823c77d7SSam Leffler ns8250->fcr |= FCR_RX_MEDH; 4290aefb0a6SBenno Rice 4300aefb0a6SBenno Rice /* Get IER mask */ 4310aefb0a6SBenno Rice ivar = 0xf0; 4320aefb0a6SBenno Rice resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_mask", 4330aefb0a6SBenno Rice &ivar); 4340aefb0a6SBenno Rice ns8250->ier_mask = (uint8_t)(ivar & 0xff); 4350aefb0a6SBenno Rice 4360aefb0a6SBenno Rice /* Get IER RX interrupt bits */ 4370aefb0a6SBenno Rice ivar = IER_EMSC | IER_ERLS | IER_ERXRDY; 4380aefb0a6SBenno Rice resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_rxbits", 4390aefb0a6SBenno Rice &ivar); 4400aefb0a6SBenno Rice ns8250->ier_rxbits = (uint8_t)(ivar & 0xff); 4410aefb0a6SBenno Rice 44227d5dc18SMarcel Moolenaar uart_setreg(bas, REG_FCR, ns8250->fcr); 44327d5dc18SMarcel Moolenaar uart_barrier(bas); 44427d5dc18SMarcel Moolenaar ns8250_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 44527d5dc18SMarcel Moolenaar 44627d5dc18SMarcel Moolenaar if (ns8250->mcr & MCR_DTR) 44728710806SPoul-Henning Kamp sc->sc_hwsig |= SER_DTR; 44827d5dc18SMarcel Moolenaar if (ns8250->mcr & MCR_RTS) 44928710806SPoul-Henning Kamp sc->sc_hwsig |= SER_RTS; 45027d5dc18SMarcel Moolenaar ns8250_bus_getsig(sc); 45127d5dc18SMarcel Moolenaar 45227d5dc18SMarcel Moolenaar ns8250_clrint(bas); 4530aefb0a6SBenno Rice ns8250->ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 4540aefb0a6SBenno Rice ns8250->ier |= ns8250->ier_rxbits; 45527d5dc18SMarcel Moolenaar uart_setreg(bas, REG_IER, ns8250->ier); 45627d5dc18SMarcel Moolenaar uart_barrier(bas); 4570aefb0a6SBenno Rice 4584fc49975SMarcel Moolenaar /* 4594fc49975SMarcel Moolenaar * Timing of the H/W access was changed with r253161 of uart_core.c 4604fc49975SMarcel Moolenaar * It has been observed that an ITE IT8513E would signal a break 4614fc49975SMarcel Moolenaar * condition with pretty much every character it received, unless 4624fc49975SMarcel Moolenaar * it had enough time to settle between ns8250_bus_attach() and 4634fc49975SMarcel Moolenaar * ns8250_bus_ipend() -- which it accidentally had before r253161. 4644fc49975SMarcel Moolenaar * It's not understood why the UART chip behaves this way and it 4654fc49975SMarcel Moolenaar * could very well be that the DELAY make the H/W work in the same 4664fc49975SMarcel Moolenaar * accidental manner as before. More analysis is warranted, but 4674fc49975SMarcel Moolenaar * at least now we fixed a known regression. 4684fc49975SMarcel Moolenaar */ 46940a827b6SMarcel Moolenaar DELAY(200); 47027d5dc18SMarcel Moolenaar return (0); 47127d5dc18SMarcel Moolenaar } 47227d5dc18SMarcel Moolenaar 473167cb33fSIan Lepore int 47427d5dc18SMarcel Moolenaar ns8250_bus_detach(struct uart_softc *sc) 47527d5dc18SMarcel Moolenaar { 4760aefb0a6SBenno Rice struct ns8250_softc *ns8250; 47727d5dc18SMarcel Moolenaar struct uart_bas *bas; 47858957d87SBenno Rice u_char ier; 47927d5dc18SMarcel Moolenaar 4800aefb0a6SBenno Rice ns8250 = (struct ns8250_softc *)sc; 48127d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 4820aefb0a6SBenno Rice ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 48358957d87SBenno Rice uart_setreg(bas, REG_IER, ier); 48427d5dc18SMarcel Moolenaar uart_barrier(bas); 48527d5dc18SMarcel Moolenaar ns8250_clrint(bas); 48627d5dc18SMarcel Moolenaar return (0); 48727d5dc18SMarcel Moolenaar } 48827d5dc18SMarcel Moolenaar 489167cb33fSIan Lepore int 49027d5dc18SMarcel Moolenaar ns8250_bus_flush(struct uart_softc *sc, int what) 49127d5dc18SMarcel Moolenaar { 49227d5dc18SMarcel Moolenaar struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 49327d5dc18SMarcel Moolenaar struct uart_bas *bas; 49406287620SMarcel Moolenaar int error; 49527d5dc18SMarcel Moolenaar 49627d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 4978af03381SMarcel Moolenaar uart_lock(sc->sc_hwmtx); 4988d1289feSMarcel Moolenaar if (sc->sc_rxfifosz > 1) { 49927d5dc18SMarcel Moolenaar ns8250_flush(bas, what); 50027d5dc18SMarcel Moolenaar uart_setreg(bas, REG_FCR, ns8250->fcr); 50127d5dc18SMarcel Moolenaar uart_barrier(bas); 50206287620SMarcel Moolenaar error = 0; 50306287620SMarcel Moolenaar } else 50406287620SMarcel Moolenaar error = ns8250_drain(bas, what); 5058af03381SMarcel Moolenaar uart_unlock(sc->sc_hwmtx); 50606287620SMarcel Moolenaar return (error); 50727d5dc18SMarcel Moolenaar } 50827d5dc18SMarcel Moolenaar 509167cb33fSIan Lepore int 51027d5dc18SMarcel Moolenaar ns8250_bus_getsig(struct uart_softc *sc) 51127d5dc18SMarcel Moolenaar { 51227d5dc18SMarcel Moolenaar uint32_t new, old, sig; 51327d5dc18SMarcel Moolenaar uint8_t msr; 51427d5dc18SMarcel Moolenaar 51527d5dc18SMarcel Moolenaar do { 51627d5dc18SMarcel Moolenaar old = sc->sc_hwsig; 51727d5dc18SMarcel Moolenaar sig = old; 5188af03381SMarcel Moolenaar uart_lock(sc->sc_hwmtx); 51927d5dc18SMarcel Moolenaar msr = uart_getreg(&sc->sc_bas, REG_MSR); 5208af03381SMarcel Moolenaar uart_unlock(sc->sc_hwmtx); 52128710806SPoul-Henning Kamp SIGCHG(msr & MSR_DSR, sig, SER_DSR, SER_DDSR); 52228710806SPoul-Henning Kamp SIGCHG(msr & MSR_CTS, sig, SER_CTS, SER_DCTS); 52328710806SPoul-Henning Kamp SIGCHG(msr & MSR_DCD, sig, SER_DCD, SER_DDCD); 52428710806SPoul-Henning Kamp SIGCHG(msr & MSR_RI, sig, SER_RI, SER_DRI); 525ea549414SMarcel Moolenaar new = sig & ~SER_MASK_DELTA; 52627d5dc18SMarcel Moolenaar } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 52727d5dc18SMarcel Moolenaar return (sig); 52827d5dc18SMarcel Moolenaar } 52927d5dc18SMarcel Moolenaar 530167cb33fSIan Lepore int 53127d5dc18SMarcel Moolenaar ns8250_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) 53227d5dc18SMarcel Moolenaar { 53327d5dc18SMarcel Moolenaar struct uart_bas *bas; 534bfa307a3SMarcel Moolenaar int baudrate, divisor, error; 53584c7b427SMarcel Moolenaar uint8_t efr, lcr; 53627d5dc18SMarcel Moolenaar 53727d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 53806287620SMarcel Moolenaar error = 0; 5398af03381SMarcel Moolenaar uart_lock(sc->sc_hwmtx); 54027d5dc18SMarcel Moolenaar switch (request) { 54127d5dc18SMarcel Moolenaar case UART_IOCTL_BREAK: 54227d5dc18SMarcel Moolenaar lcr = uart_getreg(bas, REG_LCR); 54327d5dc18SMarcel Moolenaar if (data) 54427d5dc18SMarcel Moolenaar lcr |= LCR_SBREAK; 54527d5dc18SMarcel Moolenaar else 54627d5dc18SMarcel Moolenaar lcr &= ~LCR_SBREAK; 54727d5dc18SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr); 54827d5dc18SMarcel Moolenaar uart_barrier(bas); 54927d5dc18SMarcel Moolenaar break; 55084c7b427SMarcel Moolenaar case UART_IOCTL_IFLOW: 55184c7b427SMarcel Moolenaar lcr = uart_getreg(bas, REG_LCR); 55284c7b427SMarcel Moolenaar uart_barrier(bas); 55384c7b427SMarcel Moolenaar uart_setreg(bas, REG_LCR, 0xbf); 55484c7b427SMarcel Moolenaar uart_barrier(bas); 55584c7b427SMarcel Moolenaar efr = uart_getreg(bas, REG_EFR); 55684c7b427SMarcel Moolenaar if (data) 55784c7b427SMarcel Moolenaar efr |= EFR_RTS; 55884c7b427SMarcel Moolenaar else 55984c7b427SMarcel Moolenaar efr &= ~EFR_RTS; 56084c7b427SMarcel Moolenaar uart_setreg(bas, REG_EFR, efr); 56184c7b427SMarcel Moolenaar uart_barrier(bas); 56284c7b427SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr); 56384c7b427SMarcel Moolenaar uart_barrier(bas); 56484c7b427SMarcel Moolenaar break; 56584c7b427SMarcel Moolenaar case UART_IOCTL_OFLOW: 56684c7b427SMarcel Moolenaar lcr = uart_getreg(bas, REG_LCR); 56784c7b427SMarcel Moolenaar uart_barrier(bas); 56884c7b427SMarcel Moolenaar uart_setreg(bas, REG_LCR, 0xbf); 56984c7b427SMarcel Moolenaar uart_barrier(bas); 57084c7b427SMarcel Moolenaar efr = uart_getreg(bas, REG_EFR); 57184c7b427SMarcel Moolenaar if (data) 57284c7b427SMarcel Moolenaar efr |= EFR_CTS; 57384c7b427SMarcel Moolenaar else 57484c7b427SMarcel Moolenaar efr &= ~EFR_CTS; 57584c7b427SMarcel Moolenaar uart_setreg(bas, REG_EFR, efr); 57684c7b427SMarcel Moolenaar uart_barrier(bas); 57784c7b427SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr); 57884c7b427SMarcel Moolenaar uart_barrier(bas); 57984c7b427SMarcel Moolenaar break; 580d8518925SMarcel Moolenaar case UART_IOCTL_BAUD: 581d8518925SMarcel Moolenaar lcr = uart_getreg(bas, REG_LCR); 582d8518925SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 583d8518925SMarcel Moolenaar uart_barrier(bas); 58458957d87SBenno Rice divisor = uart_getreg(bas, REG_DLL) | 58558957d87SBenno Rice (uart_getreg(bas, REG_DLH) << 8); 586d8518925SMarcel Moolenaar uart_barrier(bas); 587d8518925SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr); 588d8518925SMarcel Moolenaar uart_barrier(bas); 589bfa307a3SMarcel Moolenaar baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0; 590bfa307a3SMarcel Moolenaar if (baudrate > 0) 591bfa307a3SMarcel Moolenaar *(int*)data = baudrate; 592bfa307a3SMarcel Moolenaar else 593bfa307a3SMarcel Moolenaar error = ENXIO; 594d8518925SMarcel Moolenaar break; 59527d5dc18SMarcel Moolenaar default: 59606287620SMarcel Moolenaar error = EINVAL; 59706287620SMarcel Moolenaar break; 59827d5dc18SMarcel Moolenaar } 5998af03381SMarcel Moolenaar uart_unlock(sc->sc_hwmtx); 60006287620SMarcel Moolenaar return (error); 60127d5dc18SMarcel Moolenaar } 60227d5dc18SMarcel Moolenaar 603167cb33fSIan Lepore int 60427d5dc18SMarcel Moolenaar ns8250_bus_ipend(struct uart_softc *sc) 60527d5dc18SMarcel Moolenaar { 60627d5dc18SMarcel Moolenaar struct uart_bas *bas; 60711e55f91SOlivier Houchard struct ns8250_softc *ns8250; 60827d5dc18SMarcel Moolenaar int ipend; 60927d5dc18SMarcel Moolenaar uint8_t iir, lsr; 61027d5dc18SMarcel Moolenaar 61111e55f91SOlivier Houchard ns8250 = (struct ns8250_softc *)sc; 61227d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 6138af03381SMarcel Moolenaar uart_lock(sc->sc_hwmtx); 61427d5dc18SMarcel Moolenaar iir = uart_getreg(bas, REG_IIR); 615ac4adddfSGanbold Tsagaankhuu 616ac4adddfSGanbold Tsagaankhuu if (ns8250->busy_detect && (iir & IIR_BUSY) == IIR_BUSY) { 617ac4adddfSGanbold Tsagaankhuu (void)uart_getreg(bas, DW_REG_USR); 618ac4adddfSGanbold Tsagaankhuu uart_unlock(sc->sc_hwmtx); 619ac4adddfSGanbold Tsagaankhuu return (0); 620ac4adddfSGanbold Tsagaankhuu } 62106287620SMarcel Moolenaar if (iir & IIR_NOPEND) { 6228af03381SMarcel Moolenaar uart_unlock(sc->sc_hwmtx); 62327d5dc18SMarcel Moolenaar return (0); 62406287620SMarcel Moolenaar } 62527d5dc18SMarcel Moolenaar ipend = 0; 62627d5dc18SMarcel Moolenaar if (iir & IIR_RXRDY) { 62727d5dc18SMarcel Moolenaar lsr = uart_getreg(bas, REG_LSR); 62827d5dc18SMarcel Moolenaar if (lsr & LSR_OE) 6292d511805SMarcel Moolenaar ipend |= SER_INT_OVERRUN; 63027d5dc18SMarcel Moolenaar if (lsr & LSR_BI) 6312d511805SMarcel Moolenaar ipend |= SER_INT_BREAK; 63227d5dc18SMarcel Moolenaar if (lsr & LSR_RXRDY) 6332d511805SMarcel Moolenaar ipend |= SER_INT_RXREADY; 63427d5dc18SMarcel Moolenaar } else { 63511e55f91SOlivier Houchard if (iir & IIR_TXRDY) { 6362d511805SMarcel Moolenaar ipend |= SER_INT_TXIDLE; 63711e55f91SOlivier Houchard uart_setreg(bas, REG_IER, ns8250->ier); 63811e55f91SOlivier Houchard } else 6392d511805SMarcel Moolenaar ipend |= SER_INT_SIGCHG; 64027d5dc18SMarcel Moolenaar } 641d7ae5af5SMarcel Moolenaar if (ipend == 0) 642d7ae5af5SMarcel Moolenaar ns8250_clrint(bas); 643d7ae5af5SMarcel Moolenaar uart_unlock(sc->sc_hwmtx); 644f6ffc3c2SMarius Strobl return (ipend); 64527d5dc18SMarcel Moolenaar } 64627d5dc18SMarcel Moolenaar 647167cb33fSIan Lepore int 64827d5dc18SMarcel Moolenaar ns8250_bus_param(struct uart_softc *sc, int baudrate, int databits, 64927d5dc18SMarcel Moolenaar int stopbits, int parity) 65027d5dc18SMarcel Moolenaar { 65149e368acSZbigniew Bodek struct ns8250_softc *ns8250; 65227d5dc18SMarcel Moolenaar struct uart_bas *bas; 65349e368acSZbigniew Bodek int error, limit; 65427d5dc18SMarcel Moolenaar 65549e368acSZbigniew Bodek ns8250 = (struct ns8250_softc*)sc; 65627d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 6578af03381SMarcel Moolenaar uart_lock(sc->sc_hwmtx); 65849e368acSZbigniew Bodek /* 65949e368acSZbigniew Bodek * When using DW UART with BUSY detection it is necessary to wait 66049e368acSZbigniew Bodek * until all serial transfers are finished before manipulating the 66149e368acSZbigniew Bodek * line control. LCR will not be affected when UART is busy. 66249e368acSZbigniew Bodek */ 66349e368acSZbigniew Bodek if (ns8250->busy_detect != 0) { 66449e368acSZbigniew Bodek /* 66549e368acSZbigniew Bodek * Pick an arbitrary high limit to avoid getting stuck in 66649e368acSZbigniew Bodek * an infinite loop in case when the hardware is broken. 66749e368acSZbigniew Bodek */ 66849e368acSZbigniew Bodek limit = 10 * 1024; 66949e368acSZbigniew Bodek while (((uart_getreg(bas, DW_REG_USR) & USR_BUSY) != 0) && 67049e368acSZbigniew Bodek --limit) 67149e368acSZbigniew Bodek DELAY(4); 67249e368acSZbigniew Bodek 67349e368acSZbigniew Bodek if (limit <= 0) { 67449e368acSZbigniew Bodek /* UART appears to be stuck */ 67549e368acSZbigniew Bodek uart_unlock(sc->sc_hwmtx); 67649e368acSZbigniew Bodek return (EIO); 67749e368acSZbigniew Bodek } 67849e368acSZbigniew Bodek } 67949e368acSZbigniew Bodek 68006287620SMarcel Moolenaar error = ns8250_param(bas, baudrate, databits, stopbits, parity); 6818af03381SMarcel Moolenaar uart_unlock(sc->sc_hwmtx); 68206287620SMarcel Moolenaar return (error); 68327d5dc18SMarcel Moolenaar } 68427d5dc18SMarcel Moolenaar 685167cb33fSIan Lepore int 68627d5dc18SMarcel Moolenaar ns8250_bus_probe(struct uart_softc *sc) 68727d5dc18SMarcel Moolenaar { 6880aefb0a6SBenno Rice struct ns8250_softc *ns8250; 68927d5dc18SMarcel Moolenaar struct uart_bas *bas; 69027d5dc18SMarcel Moolenaar int count, delay, error, limit; 69158957d87SBenno Rice uint8_t lsr, mcr, ier; 69227d5dc18SMarcel Moolenaar 6930aefb0a6SBenno Rice ns8250 = (struct ns8250_softc *)sc; 69427d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 69527d5dc18SMarcel Moolenaar 69627d5dc18SMarcel Moolenaar error = ns8250_probe(bas); 69727d5dc18SMarcel Moolenaar if (error) 69827d5dc18SMarcel Moolenaar return (error); 69927d5dc18SMarcel Moolenaar 70027d5dc18SMarcel Moolenaar mcr = MCR_IE; 70127d5dc18SMarcel Moolenaar if (sc->sc_sysdev == NULL) { 70227d5dc18SMarcel Moolenaar /* By using ns8250_init() we also set DTR and RTS. */ 703d902fb71SMarcel Moolenaar ns8250_init(bas, 115200, 8, 1, UART_PARITY_NONE); 70427d5dc18SMarcel Moolenaar } else 70527d5dc18SMarcel Moolenaar mcr |= MCR_DTR | MCR_RTS; 70627d5dc18SMarcel Moolenaar 70727d5dc18SMarcel Moolenaar error = ns8250_drain(bas, UART_DRAIN_TRANSMITTER); 70827d5dc18SMarcel Moolenaar if (error) 70927d5dc18SMarcel Moolenaar return (error); 71027d5dc18SMarcel Moolenaar 71127d5dc18SMarcel Moolenaar /* 71227d5dc18SMarcel Moolenaar * Set loopback mode. This avoids having garbage on the wire and 71327d5dc18SMarcel Moolenaar * also allows us send and receive data. We set DTR and RTS to 71427d5dc18SMarcel Moolenaar * avoid the possibility that automatic flow-control prevents 71589eef2deSThomas Moestl * any data from being sent. 71627d5dc18SMarcel Moolenaar */ 71789eef2deSThomas Moestl uart_setreg(bas, REG_MCR, MCR_LOOPBACK | MCR_IE | MCR_DTR | MCR_RTS); 71827d5dc18SMarcel Moolenaar uart_barrier(bas); 71927d5dc18SMarcel Moolenaar 72027d5dc18SMarcel Moolenaar /* 72127d5dc18SMarcel Moolenaar * Enable FIFOs. And check that the UART has them. If not, we're 72289eef2deSThomas Moestl * done. Since this is the first time we enable the FIFOs, we reset 72389eef2deSThomas Moestl * them. 72427d5dc18SMarcel Moolenaar */ 72527d5dc18SMarcel Moolenaar uart_setreg(bas, REG_FCR, FCR_ENABLE); 72627d5dc18SMarcel Moolenaar uart_barrier(bas); 7278d1289feSMarcel Moolenaar if (!(uart_getreg(bas, REG_IIR) & IIR_FIFO_MASK)) { 72827d5dc18SMarcel Moolenaar /* 72927d5dc18SMarcel Moolenaar * NS16450 or INS8250. We don't bother to differentiate 73027d5dc18SMarcel Moolenaar * between them. They're too old to be interesting. 73127d5dc18SMarcel Moolenaar */ 73227d5dc18SMarcel Moolenaar uart_setreg(bas, REG_MCR, mcr); 73327d5dc18SMarcel Moolenaar uart_barrier(bas); 7348d1289feSMarcel Moolenaar sc->sc_rxfifosz = sc->sc_txfifosz = 1; 73527d5dc18SMarcel Moolenaar device_set_desc(sc->sc_dev, "8250 or 16450 or compatible"); 73627d5dc18SMarcel Moolenaar return (0); 73727d5dc18SMarcel Moolenaar } 73827d5dc18SMarcel Moolenaar 73989eef2deSThomas Moestl uart_setreg(bas, REG_FCR, FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST); 74027d5dc18SMarcel Moolenaar uart_barrier(bas); 74127d5dc18SMarcel Moolenaar 74227d5dc18SMarcel Moolenaar count = 0; 74327d5dc18SMarcel Moolenaar delay = ns8250_delay(bas); 74427d5dc18SMarcel Moolenaar 74527d5dc18SMarcel Moolenaar /* We have FIFOs. Drain the transmitter and receiver. */ 74627d5dc18SMarcel Moolenaar error = ns8250_drain(bas, UART_DRAIN_RECEIVER|UART_DRAIN_TRANSMITTER); 74727d5dc18SMarcel Moolenaar if (error) { 74827d5dc18SMarcel Moolenaar uart_setreg(bas, REG_MCR, mcr); 74927d5dc18SMarcel Moolenaar uart_setreg(bas, REG_FCR, 0); 75027d5dc18SMarcel Moolenaar uart_barrier(bas); 75127d5dc18SMarcel Moolenaar goto describe; 75227d5dc18SMarcel Moolenaar } 75327d5dc18SMarcel Moolenaar 75427d5dc18SMarcel Moolenaar /* 75527d5dc18SMarcel Moolenaar * We should have a sufficiently clean "pipe" to determine the 75627d5dc18SMarcel Moolenaar * size of the FIFOs. We send as much characters as is reasonable 7576bccea7cSRebecca Cran * and wait for the overflow bit in the LSR register to be 75889eef2deSThomas Moestl * asserted, counting the characters as we send them. Based on 75989eef2deSThomas Moestl * that count we know the FIFO size. 76027d5dc18SMarcel Moolenaar */ 76189eef2deSThomas Moestl do { 76227d5dc18SMarcel Moolenaar uart_setreg(bas, REG_DATA, 0); 76327d5dc18SMarcel Moolenaar uart_barrier(bas); 76427d5dc18SMarcel Moolenaar count++; 76527d5dc18SMarcel Moolenaar 76627d5dc18SMarcel Moolenaar limit = 30; 76789eef2deSThomas Moestl lsr = 0; 76889eef2deSThomas Moestl /* 76989eef2deSThomas Moestl * LSR bits are cleared upon read, so we must accumulate 77089eef2deSThomas Moestl * them to be able to test LSR_OE below. 77189eef2deSThomas Moestl */ 77289eef2deSThomas Moestl while (((lsr |= uart_getreg(bas, REG_LSR)) & LSR_TEMT) == 0 && 77389eef2deSThomas Moestl --limit) 77427d5dc18SMarcel Moolenaar DELAY(delay); 77527d5dc18SMarcel Moolenaar if (limit == 0) { 7760aefb0a6SBenno Rice ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 77758957d87SBenno Rice uart_setreg(bas, REG_IER, ier); 77827d5dc18SMarcel Moolenaar uart_setreg(bas, REG_MCR, mcr); 77927d5dc18SMarcel Moolenaar uart_setreg(bas, REG_FCR, 0); 78027d5dc18SMarcel Moolenaar uart_barrier(bas); 78127d5dc18SMarcel Moolenaar count = 0; 78227d5dc18SMarcel Moolenaar goto describe; 78327d5dc18SMarcel Moolenaar } 784d882cf92SMarcel Moolenaar } while ((lsr & LSR_OE) == 0 && count < 130); 78589eef2deSThomas Moestl count--; 78627d5dc18SMarcel Moolenaar 78727d5dc18SMarcel Moolenaar uart_setreg(bas, REG_MCR, mcr); 78827d5dc18SMarcel Moolenaar 78927d5dc18SMarcel Moolenaar /* Reset FIFOs. */ 79027d5dc18SMarcel Moolenaar ns8250_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 79127d5dc18SMarcel Moolenaar 79227d5dc18SMarcel Moolenaar describe: 79389eef2deSThomas Moestl if (count >= 14 && count <= 16) { 79427d5dc18SMarcel Moolenaar sc->sc_rxfifosz = 16; 79527d5dc18SMarcel Moolenaar device_set_desc(sc->sc_dev, "16550 or compatible"); 79689eef2deSThomas Moestl } else if (count >= 28 && count <= 32) { 79727d5dc18SMarcel Moolenaar sc->sc_rxfifosz = 32; 79827d5dc18SMarcel Moolenaar device_set_desc(sc->sc_dev, "16650 or compatible"); 79989eef2deSThomas Moestl } else if (count >= 56 && count <= 64) { 80027d5dc18SMarcel Moolenaar sc->sc_rxfifosz = 64; 80127d5dc18SMarcel Moolenaar device_set_desc(sc->sc_dev, "16750 or compatible"); 80289eef2deSThomas Moestl } else if (count >= 112 && count <= 128) { 80327d5dc18SMarcel Moolenaar sc->sc_rxfifosz = 128; 80427d5dc18SMarcel Moolenaar device_set_desc(sc->sc_dev, "16950 or compatible"); 80527d5dc18SMarcel Moolenaar } else { 806c21e0da2SMarcel Moolenaar sc->sc_rxfifosz = 16; 80727d5dc18SMarcel Moolenaar device_set_desc(sc->sc_dev, 80827d5dc18SMarcel Moolenaar "Non-standard ns8250 class UART with FIFOs"); 80927d5dc18SMarcel Moolenaar } 81027d5dc18SMarcel Moolenaar 81127d5dc18SMarcel Moolenaar /* 81227d5dc18SMarcel Moolenaar * Force the Tx FIFO size to 16 bytes for now. We don't program the 81327d5dc18SMarcel Moolenaar * Tx trigger. Also, we assume that all data has been sent when the 81427d5dc18SMarcel Moolenaar * interrupt happens. 81527d5dc18SMarcel Moolenaar */ 81627d5dc18SMarcel Moolenaar sc->sc_txfifosz = 16; 81727d5dc18SMarcel Moolenaar 818dc70e792SMarcel Moolenaar #if 0 819dc70e792SMarcel Moolenaar /* 820dc70e792SMarcel Moolenaar * XXX there are some issues related to hardware flow control and 821dc70e792SMarcel Moolenaar * it's likely that uart(4) is the cause. This basicly needs more 822dc70e792SMarcel Moolenaar * investigation, but we avoid using for hardware flow control 823dc70e792SMarcel Moolenaar * until then. 824dc70e792SMarcel Moolenaar */ 82584c7b427SMarcel Moolenaar /* 16650s or higher have automatic flow control. */ 82684c7b427SMarcel Moolenaar if (sc->sc_rxfifosz > 16) { 82784c7b427SMarcel Moolenaar sc->sc_hwiflow = 1; 82884c7b427SMarcel Moolenaar sc->sc_hwoflow = 1; 82984c7b427SMarcel Moolenaar } 830dc70e792SMarcel Moolenaar #endif 83184c7b427SMarcel Moolenaar 83227d5dc18SMarcel Moolenaar return (0); 83327d5dc18SMarcel Moolenaar } 83427d5dc18SMarcel Moolenaar 835167cb33fSIan Lepore int 83627d5dc18SMarcel Moolenaar ns8250_bus_receive(struct uart_softc *sc) 83727d5dc18SMarcel Moolenaar { 83827d5dc18SMarcel Moolenaar struct uart_bas *bas; 83927d5dc18SMarcel Moolenaar int xc; 84027d5dc18SMarcel Moolenaar uint8_t lsr; 84127d5dc18SMarcel Moolenaar 84227d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 8438af03381SMarcel Moolenaar uart_lock(sc->sc_hwmtx); 84427d5dc18SMarcel Moolenaar lsr = uart_getreg(bas, REG_LSR); 84544ed791bSMarcel Moolenaar while (lsr & LSR_RXRDY) { 84644ed791bSMarcel Moolenaar if (uart_rx_full(sc)) { 84744ed791bSMarcel Moolenaar sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; 84827d5dc18SMarcel Moolenaar break; 84944ed791bSMarcel Moolenaar } 85027d5dc18SMarcel Moolenaar xc = uart_getreg(bas, REG_DATA); 85127d5dc18SMarcel Moolenaar if (lsr & LSR_FE) 85227d5dc18SMarcel Moolenaar xc |= UART_STAT_FRAMERR; 85327d5dc18SMarcel Moolenaar if (lsr & LSR_PE) 85427d5dc18SMarcel Moolenaar xc |= UART_STAT_PARERR; 85527d5dc18SMarcel Moolenaar uart_rx_put(sc, xc); 85644ed791bSMarcel Moolenaar lsr = uart_getreg(bas, REG_LSR); 85744ed791bSMarcel Moolenaar } 85844ed791bSMarcel Moolenaar /* Discard everything left in the Rx FIFO. */ 85944ed791bSMarcel Moolenaar while (lsr & LSR_RXRDY) { 86044ed791bSMarcel Moolenaar (void)uart_getreg(bas, REG_DATA); 86144ed791bSMarcel Moolenaar uart_barrier(bas); 86244ed791bSMarcel Moolenaar lsr = uart_getreg(bas, REG_LSR); 86327d5dc18SMarcel Moolenaar } 8648af03381SMarcel Moolenaar uart_unlock(sc->sc_hwmtx); 86527d5dc18SMarcel Moolenaar return (0); 86627d5dc18SMarcel Moolenaar } 86727d5dc18SMarcel Moolenaar 868167cb33fSIan Lepore int 86927d5dc18SMarcel Moolenaar ns8250_bus_setsig(struct uart_softc *sc, int sig) 87027d5dc18SMarcel Moolenaar { 87127d5dc18SMarcel Moolenaar struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 87227d5dc18SMarcel Moolenaar struct uart_bas *bas; 87327d5dc18SMarcel Moolenaar uint32_t new, old; 87427d5dc18SMarcel Moolenaar 87527d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 87627d5dc18SMarcel Moolenaar do { 87727d5dc18SMarcel Moolenaar old = sc->sc_hwsig; 87827d5dc18SMarcel Moolenaar new = old; 87928710806SPoul-Henning Kamp if (sig & SER_DDTR) { 88028710806SPoul-Henning Kamp SIGCHG(sig & SER_DTR, new, SER_DTR, 88128710806SPoul-Henning Kamp SER_DDTR); 88227d5dc18SMarcel Moolenaar } 88328710806SPoul-Henning Kamp if (sig & SER_DRTS) { 88428710806SPoul-Henning Kamp SIGCHG(sig & SER_RTS, new, SER_RTS, 88528710806SPoul-Henning Kamp SER_DRTS); 88627d5dc18SMarcel Moolenaar } 88727d5dc18SMarcel Moolenaar } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 8888af03381SMarcel Moolenaar uart_lock(sc->sc_hwmtx); 88927d5dc18SMarcel Moolenaar ns8250->mcr &= ~(MCR_DTR|MCR_RTS); 89028710806SPoul-Henning Kamp if (new & SER_DTR) 89127d5dc18SMarcel Moolenaar ns8250->mcr |= MCR_DTR; 89228710806SPoul-Henning Kamp if (new & SER_RTS) 89327d5dc18SMarcel Moolenaar ns8250->mcr |= MCR_RTS; 89427d5dc18SMarcel Moolenaar uart_setreg(bas, REG_MCR, ns8250->mcr); 89527d5dc18SMarcel Moolenaar uart_barrier(bas); 8968af03381SMarcel Moolenaar uart_unlock(sc->sc_hwmtx); 89727d5dc18SMarcel Moolenaar return (0); 89827d5dc18SMarcel Moolenaar } 89927d5dc18SMarcel Moolenaar 900167cb33fSIan Lepore int 90127d5dc18SMarcel Moolenaar ns8250_bus_transmit(struct uart_softc *sc) 90227d5dc18SMarcel Moolenaar { 90327d5dc18SMarcel Moolenaar struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 90427d5dc18SMarcel Moolenaar struct uart_bas *bas; 90527d5dc18SMarcel Moolenaar int i; 90627d5dc18SMarcel Moolenaar 90727d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 9088af03381SMarcel Moolenaar uart_lock(sc->sc_hwmtx); 90927d5dc18SMarcel Moolenaar while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0) 91027d5dc18SMarcel Moolenaar ; 91127d5dc18SMarcel Moolenaar uart_setreg(bas, REG_IER, ns8250->ier | IER_ETXRDY); 91227d5dc18SMarcel Moolenaar uart_barrier(bas); 91327d5dc18SMarcel Moolenaar for (i = 0; i < sc->sc_txdatasz; i++) { 91427d5dc18SMarcel Moolenaar uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]); 91527d5dc18SMarcel Moolenaar uart_barrier(bas); 91627d5dc18SMarcel Moolenaar } 9171c60b24bSColin Percival if (broken_txfifo) 9181c60b24bSColin Percival ns8250_drain(bas, UART_DRAIN_TRANSMITTER); 9191c60b24bSColin Percival else 92027d5dc18SMarcel Moolenaar sc->sc_txbusy = 1; 9218af03381SMarcel Moolenaar uart_unlock(sc->sc_hwmtx); 9221c60b24bSColin Percival if (broken_txfifo) 9231c60b24bSColin Percival uart_sched_softih(sc, SER_INT_TXIDLE); 92427d5dc18SMarcel Moolenaar return (0); 92527d5dc18SMarcel Moolenaar } 926d76a1ef4SWarner Losh 927d76a1ef4SWarner Losh void 928d76a1ef4SWarner Losh ns8250_bus_grab(struct uart_softc *sc) 929d76a1ef4SWarner Losh { 930d76a1ef4SWarner Losh struct uart_bas *bas = &sc->sc_bas; 931caf6d6b4SOlivier Houchard struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 9328bc9a079SOlivier Houchard u_char ier; 933d76a1ef4SWarner Losh 934d76a1ef4SWarner Losh /* 935d76a1ef4SWarner Losh * turn off all interrupts to enter polling mode. Leave the 936d76a1ef4SWarner Losh * saved mask alone. We'll restore whatever it was in ungrab. 937d76a1ef4SWarner Losh * All pending interupt signals are reset when IER is set to 0. 938d76a1ef4SWarner Losh */ 939d76a1ef4SWarner Losh uart_lock(sc->sc_hwmtx); 9408bc9a079SOlivier Houchard ier = uart_getreg(bas, REG_IER); 9418bc9a079SOlivier Houchard uart_setreg(bas, REG_IER, ier & ns8250->ier_mask); 942d76a1ef4SWarner Losh uart_barrier(bas); 943d76a1ef4SWarner Losh uart_unlock(sc->sc_hwmtx); 944d76a1ef4SWarner Losh } 945d76a1ef4SWarner Losh 946d76a1ef4SWarner Losh void 947d76a1ef4SWarner Losh ns8250_bus_ungrab(struct uart_softc *sc) 948d76a1ef4SWarner Losh { 949d76a1ef4SWarner Losh struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 950d76a1ef4SWarner Losh struct uart_bas *bas = &sc->sc_bas; 951d76a1ef4SWarner Losh 952d76a1ef4SWarner Losh /* 953d76a1ef4SWarner Losh * Restore previous interrupt mask 954d76a1ef4SWarner Losh */ 955d76a1ef4SWarner Losh uart_lock(sc->sc_hwmtx); 956d76a1ef4SWarner Losh uart_setreg(bas, REG_IER, ns8250->ier); 957d76a1ef4SWarner Losh uart_barrier(bas); 958d76a1ef4SWarner Losh uart_unlock(sc->sc_hwmtx); 959d76a1ef4SWarner Losh } 960