1098ca2bdSWarner Losh /*- 227d5dc18SMarcel Moolenaar * Copyright (c) 2003 Marcel Moolenaar 327d5dc18SMarcel Moolenaar * All rights reserved. 427d5dc18SMarcel Moolenaar * 527d5dc18SMarcel Moolenaar * Redistribution and use in source and binary forms, with or without 627d5dc18SMarcel Moolenaar * modification, are permitted provided that the following conditions 727d5dc18SMarcel Moolenaar * are met: 827d5dc18SMarcel Moolenaar * 927d5dc18SMarcel Moolenaar * 1. Redistributions of source code must retain the above copyright 1027d5dc18SMarcel Moolenaar * notice, this list of conditions and the following disclaimer. 1127d5dc18SMarcel Moolenaar * 2. Redistributions in binary form must reproduce the above copyright 1227d5dc18SMarcel Moolenaar * notice, this list of conditions and the following disclaimer in the 1327d5dc18SMarcel Moolenaar * documentation and/or other materials provided with the distribution. 1427d5dc18SMarcel Moolenaar * 1527d5dc18SMarcel Moolenaar * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 1627d5dc18SMarcel Moolenaar * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 1727d5dc18SMarcel Moolenaar * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 1827d5dc18SMarcel Moolenaar * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 1927d5dc18SMarcel Moolenaar * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 2027d5dc18SMarcel Moolenaar * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2127d5dc18SMarcel Moolenaar * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2227d5dc18SMarcel Moolenaar * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2327d5dc18SMarcel Moolenaar * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 2427d5dc18SMarcel Moolenaar * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2527d5dc18SMarcel Moolenaar */ 2627d5dc18SMarcel Moolenaar 27ac4adddfSGanbold Tsagaankhuu #include "opt_platform.h" 28e0fe7c95SAdrian Chadd #include "opt_uart.h" 29ac4adddfSGanbold Tsagaankhuu 3027d5dc18SMarcel Moolenaar #include <sys/cdefs.h> 3127d5dc18SMarcel Moolenaar __FBSDID("$FreeBSD$"); 3227d5dc18SMarcel Moolenaar 3327d5dc18SMarcel Moolenaar #include <sys/param.h> 3427d5dc18SMarcel Moolenaar #include <sys/systm.h> 3527d5dc18SMarcel Moolenaar #include <sys/bus.h> 3627d5dc18SMarcel Moolenaar #include <sys/conf.h> 371c60b24bSColin Percival #include <sys/kernel.h> 381c60b24bSColin Percival #include <sys/sysctl.h> 3927d5dc18SMarcel Moolenaar #include <machine/bus.h> 4027d5dc18SMarcel Moolenaar 41ac4adddfSGanbold Tsagaankhuu #ifdef FDT 42ac4adddfSGanbold Tsagaankhuu #include <dev/fdt/fdt_common.h> 43ac4adddfSGanbold Tsagaankhuu #include <dev/ofw/ofw_bus.h> 44ac4adddfSGanbold Tsagaankhuu #include <dev/ofw/ofw_bus_subr.h> 45ac4adddfSGanbold Tsagaankhuu #endif 46ac4adddfSGanbold Tsagaankhuu 4727d5dc18SMarcel Moolenaar #include <dev/uart/uart.h> 4827d5dc18SMarcel Moolenaar #include <dev/uart/uart_cpu.h> 493bb693afSIan Lepore #ifdef FDT 503bb693afSIan Lepore #include <dev/uart/uart_cpu_fdt.h> 513bb693afSIan Lepore #endif 5227d5dc18SMarcel Moolenaar #include <dev/uart/uart_bus.h> 53167cb33fSIan Lepore #include <dev/uart/uart_dev_ns8250.h> 54fdfbb3f5SIan Lepore #include <dev/uart/uart_ppstypes.h> 5576563beaSMarcel Moolenaar 5676563beaSMarcel Moolenaar #include <dev/ic/ns16550.h> 5727d5dc18SMarcel Moolenaar 5827d5dc18SMarcel Moolenaar #include "uart_if.h" 5927d5dc18SMarcel Moolenaar 6027d5dc18SMarcel Moolenaar #define DEFAULT_RCLK 1843200 6127d5dc18SMarcel Moolenaar 62e0fe7c95SAdrian Chadd /* 63e0fe7c95SAdrian Chadd * Set the default baudrate tolerance to 3.0%. 64e0fe7c95SAdrian Chadd * 65e0fe7c95SAdrian Chadd * Some embedded boards have odd reference clocks (eg 25MHz) 66e0fe7c95SAdrian Chadd * and we need to handle higher variances in the target baud rate. 67e0fe7c95SAdrian Chadd */ 68e0fe7c95SAdrian Chadd #ifndef UART_DEV_TOLERANCE_PCT 69e0fe7c95SAdrian Chadd #define UART_DEV_TOLERANCE_PCT 30 70e0fe7c95SAdrian Chadd #endif /* UART_DEV_TOLERANCE_PCT */ 71e0fe7c95SAdrian Chadd 72ac4adddfSGanbold Tsagaankhuu static int broken_txfifo = 0; 73af3b2549SHans Petter Selasky SYSCTL_INT(_hw, OID_AUTO, broken_txfifo, CTLFLAG_RWTUN, 74ac4adddfSGanbold Tsagaankhuu &broken_txfifo, 0, "UART FIFO has QEMU emulation bug"); 75ac4adddfSGanbold Tsagaankhuu 7627d5dc18SMarcel Moolenaar /* 7727d5dc18SMarcel Moolenaar * Clear pending interrupts. THRE is cleared by reading IIR. Data 7827d5dc18SMarcel Moolenaar * that may have been received gets lost here. 7927d5dc18SMarcel Moolenaar */ 8027d5dc18SMarcel Moolenaar static void 8127d5dc18SMarcel Moolenaar ns8250_clrint(struct uart_bas *bas) 8227d5dc18SMarcel Moolenaar { 83d7ae5af5SMarcel Moolenaar uint8_t iir, lsr; 8427d5dc18SMarcel Moolenaar 8527d5dc18SMarcel Moolenaar iir = uart_getreg(bas, REG_IIR); 8627d5dc18SMarcel Moolenaar while ((iir & IIR_NOPEND) == 0) { 8727d5dc18SMarcel Moolenaar iir &= IIR_IMASK; 88d7ae5af5SMarcel Moolenaar if (iir == IIR_RLS) { 89d7ae5af5SMarcel Moolenaar lsr = uart_getreg(bas, REG_LSR); 90d7ae5af5SMarcel Moolenaar if (lsr & (LSR_BI|LSR_FE|LSR_PE)) 91d7ae5af5SMarcel Moolenaar (void)uart_getreg(bas, REG_DATA); 92d7ae5af5SMarcel Moolenaar } else if (iir == IIR_RXRDY || iir == IIR_RXTOUT) 9327d5dc18SMarcel Moolenaar (void)uart_getreg(bas, REG_DATA); 9427d5dc18SMarcel Moolenaar else if (iir == IIR_MLSC) 9527d5dc18SMarcel Moolenaar (void)uart_getreg(bas, REG_MSR); 9627d5dc18SMarcel Moolenaar uart_barrier(bas); 9727d5dc18SMarcel Moolenaar iir = uart_getreg(bas, REG_IIR); 9827d5dc18SMarcel Moolenaar } 9927d5dc18SMarcel Moolenaar } 10027d5dc18SMarcel Moolenaar 10127d5dc18SMarcel Moolenaar static int 10227d5dc18SMarcel Moolenaar ns8250_delay(struct uart_bas *bas) 10327d5dc18SMarcel Moolenaar { 10427d5dc18SMarcel Moolenaar int divisor; 10527d5dc18SMarcel Moolenaar u_char lcr; 10627d5dc18SMarcel Moolenaar 10727d5dc18SMarcel Moolenaar lcr = uart_getreg(bas, REG_LCR); 10827d5dc18SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 10927d5dc18SMarcel Moolenaar uart_barrier(bas); 11058957d87SBenno Rice divisor = uart_getreg(bas, REG_DLL) | (uart_getreg(bas, REG_DLH) << 8); 11127d5dc18SMarcel Moolenaar uart_barrier(bas); 11227d5dc18SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr); 11327d5dc18SMarcel Moolenaar uart_barrier(bas); 11427d5dc18SMarcel Moolenaar 11527d5dc18SMarcel Moolenaar /* 1/10th the time to transmit 1 character (estimate). */ 116ebecffe9SMarcel Moolenaar if (divisor <= 134) 11727d5dc18SMarcel Moolenaar return (16000000 * divisor / bas->rclk); 118ebecffe9SMarcel Moolenaar return (16000 * divisor / (bas->rclk / 1000)); 11927d5dc18SMarcel Moolenaar } 12027d5dc18SMarcel Moolenaar 12127d5dc18SMarcel Moolenaar static int 12227d5dc18SMarcel Moolenaar ns8250_divisor(int rclk, int baudrate) 12327d5dc18SMarcel Moolenaar { 12427d5dc18SMarcel Moolenaar int actual_baud, divisor; 12527d5dc18SMarcel Moolenaar int error; 12627d5dc18SMarcel Moolenaar 12727d5dc18SMarcel Moolenaar if (baudrate == 0) 12827d5dc18SMarcel Moolenaar return (0); 12927d5dc18SMarcel Moolenaar 13027d5dc18SMarcel Moolenaar divisor = (rclk / (baudrate << 3) + 1) >> 1; 13127d5dc18SMarcel Moolenaar if (divisor == 0 || divisor >= 65536) 13227d5dc18SMarcel Moolenaar return (0); 13327d5dc18SMarcel Moolenaar actual_baud = rclk / (divisor << 4); 13427d5dc18SMarcel Moolenaar 13527d5dc18SMarcel Moolenaar /* 10 times error in percent: */ 13627d5dc18SMarcel Moolenaar error = ((actual_baud - baudrate) * 2000 / baudrate + 1) >> 1; 13727d5dc18SMarcel Moolenaar 138e0fe7c95SAdrian Chadd /* enforce maximum error tolerance: */ 139e0fe7c95SAdrian Chadd if (error < -UART_DEV_TOLERANCE_PCT || error > UART_DEV_TOLERANCE_PCT) 14027d5dc18SMarcel Moolenaar return (0); 14127d5dc18SMarcel Moolenaar 14227d5dc18SMarcel Moolenaar return (divisor); 14327d5dc18SMarcel Moolenaar } 14427d5dc18SMarcel Moolenaar 14527d5dc18SMarcel Moolenaar static int 14627d5dc18SMarcel Moolenaar ns8250_drain(struct uart_bas *bas, int what) 14727d5dc18SMarcel Moolenaar { 14827d5dc18SMarcel Moolenaar int delay, limit; 14927d5dc18SMarcel Moolenaar 15027d5dc18SMarcel Moolenaar delay = ns8250_delay(bas); 15127d5dc18SMarcel Moolenaar 15227d5dc18SMarcel Moolenaar if (what & UART_DRAIN_TRANSMITTER) { 15327d5dc18SMarcel Moolenaar /* 15427d5dc18SMarcel Moolenaar * Pick an arbitrary high limit to avoid getting stuck in 15527d5dc18SMarcel Moolenaar * an infinite loop when the hardware is broken. Make the 15627d5dc18SMarcel Moolenaar * limit high enough to handle large FIFOs. 15727d5dc18SMarcel Moolenaar */ 15827d5dc18SMarcel Moolenaar limit = 10*1024; 15927d5dc18SMarcel Moolenaar while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) 16027d5dc18SMarcel Moolenaar DELAY(delay); 16127d5dc18SMarcel Moolenaar if (limit == 0) { 16227d5dc18SMarcel Moolenaar /* printf("ns8250: transmitter appears stuck... "); */ 16327d5dc18SMarcel Moolenaar return (EIO); 16427d5dc18SMarcel Moolenaar } 16527d5dc18SMarcel Moolenaar } 16627d5dc18SMarcel Moolenaar 16727d5dc18SMarcel Moolenaar if (what & UART_DRAIN_RECEIVER) { 16827d5dc18SMarcel Moolenaar /* 16927d5dc18SMarcel Moolenaar * Pick an arbitrary high limit to avoid getting stuck in 17027d5dc18SMarcel Moolenaar * an infinite loop when the hardware is broken. Make the 17127d5dc18SMarcel Moolenaar * limit high enough to handle large FIFOs and integrated 17227d5dc18SMarcel Moolenaar * UARTs. The HP rx2600 for example has 3 UARTs on the 17327d5dc18SMarcel Moolenaar * management board that tend to get a lot of data send 17427d5dc18SMarcel Moolenaar * to it when the UART is first activated. 17527d5dc18SMarcel Moolenaar */ 17627d5dc18SMarcel Moolenaar limit=10*4096; 17727d5dc18SMarcel Moolenaar while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) { 17827d5dc18SMarcel Moolenaar (void)uart_getreg(bas, REG_DATA); 17927d5dc18SMarcel Moolenaar uart_barrier(bas); 18027d5dc18SMarcel Moolenaar DELAY(delay << 2); 18127d5dc18SMarcel Moolenaar } 18227d5dc18SMarcel Moolenaar if (limit == 0) { 18327d5dc18SMarcel Moolenaar /* printf("ns8250: receiver appears broken... "); */ 18427d5dc18SMarcel Moolenaar return (EIO); 18527d5dc18SMarcel Moolenaar } 18627d5dc18SMarcel Moolenaar } 18727d5dc18SMarcel Moolenaar 18827d5dc18SMarcel Moolenaar return (0); 18927d5dc18SMarcel Moolenaar } 19027d5dc18SMarcel Moolenaar 19127d5dc18SMarcel Moolenaar /* 19227d5dc18SMarcel Moolenaar * We can only flush UARTs with FIFOs. UARTs without FIFOs should be 19327d5dc18SMarcel Moolenaar * drained. WARNING: this function clobbers the FIFO setting! 19427d5dc18SMarcel Moolenaar */ 19527d5dc18SMarcel Moolenaar static void 19627d5dc18SMarcel Moolenaar ns8250_flush(struct uart_bas *bas, int what) 19727d5dc18SMarcel Moolenaar { 19827d5dc18SMarcel Moolenaar uint8_t fcr; 19927d5dc18SMarcel Moolenaar 20027d5dc18SMarcel Moolenaar fcr = FCR_ENABLE; 20127d5dc18SMarcel Moolenaar if (what & UART_FLUSH_TRANSMITTER) 20227d5dc18SMarcel Moolenaar fcr |= FCR_XMT_RST; 20327d5dc18SMarcel Moolenaar if (what & UART_FLUSH_RECEIVER) 20427d5dc18SMarcel Moolenaar fcr |= FCR_RCV_RST; 20527d5dc18SMarcel Moolenaar uart_setreg(bas, REG_FCR, fcr); 20627d5dc18SMarcel Moolenaar uart_barrier(bas); 20727d5dc18SMarcel Moolenaar } 20827d5dc18SMarcel Moolenaar 20927d5dc18SMarcel Moolenaar static int 21027d5dc18SMarcel Moolenaar ns8250_param(struct uart_bas *bas, int baudrate, int databits, int stopbits, 21127d5dc18SMarcel Moolenaar int parity) 21227d5dc18SMarcel Moolenaar { 21327d5dc18SMarcel Moolenaar int divisor; 21427d5dc18SMarcel Moolenaar uint8_t lcr; 21527d5dc18SMarcel Moolenaar 21627d5dc18SMarcel Moolenaar lcr = 0; 21727d5dc18SMarcel Moolenaar if (databits >= 8) 21827d5dc18SMarcel Moolenaar lcr |= LCR_8BITS; 21927d5dc18SMarcel Moolenaar else if (databits == 7) 22027d5dc18SMarcel Moolenaar lcr |= LCR_7BITS; 22127d5dc18SMarcel Moolenaar else if (databits == 6) 22227d5dc18SMarcel Moolenaar lcr |= LCR_6BITS; 22327d5dc18SMarcel Moolenaar else 22427d5dc18SMarcel Moolenaar lcr |= LCR_5BITS; 22527d5dc18SMarcel Moolenaar if (stopbits > 1) 22627d5dc18SMarcel Moolenaar lcr |= LCR_STOPB; 22727d5dc18SMarcel Moolenaar lcr |= parity << 3; 22827d5dc18SMarcel Moolenaar 22927d5dc18SMarcel Moolenaar /* Set baudrate. */ 23027d5dc18SMarcel Moolenaar if (baudrate > 0) { 23127d5dc18SMarcel Moolenaar divisor = ns8250_divisor(bas->rclk, baudrate); 23227d5dc18SMarcel Moolenaar if (divisor == 0) 23327d5dc18SMarcel Moolenaar return (EINVAL); 23463f8efd3SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 23563f8efd3SMarcel Moolenaar uart_barrier(bas); 23658957d87SBenno Rice uart_setreg(bas, REG_DLL, divisor & 0xff); 23758957d87SBenno Rice uart_setreg(bas, REG_DLH, (divisor >> 8) & 0xff); 23827d5dc18SMarcel Moolenaar uart_barrier(bas); 23927d5dc18SMarcel Moolenaar } 24027d5dc18SMarcel Moolenaar 24127d5dc18SMarcel Moolenaar /* Set LCR and clear DLAB. */ 24227d5dc18SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr); 24327d5dc18SMarcel Moolenaar uart_barrier(bas); 24427d5dc18SMarcel Moolenaar return (0); 24527d5dc18SMarcel Moolenaar } 24627d5dc18SMarcel Moolenaar 24727d5dc18SMarcel Moolenaar /* 24827d5dc18SMarcel Moolenaar * Low-level UART interface. 24927d5dc18SMarcel Moolenaar */ 25027d5dc18SMarcel Moolenaar static int ns8250_probe(struct uart_bas *bas); 25127d5dc18SMarcel Moolenaar static void ns8250_init(struct uart_bas *bas, int, int, int, int); 25227d5dc18SMarcel Moolenaar static void ns8250_term(struct uart_bas *bas); 25327d5dc18SMarcel Moolenaar static void ns8250_putc(struct uart_bas *bas, int); 25497202af2SMarius Strobl static int ns8250_rxready(struct uart_bas *bas); 255634e63c9SMarcel Moolenaar static int ns8250_getc(struct uart_bas *bas, struct mtx *); 25627d5dc18SMarcel Moolenaar 257167cb33fSIan Lepore struct uart_ops uart_ns8250_ops = { 25827d5dc18SMarcel Moolenaar .probe = ns8250_probe, 25927d5dc18SMarcel Moolenaar .init = ns8250_init, 26027d5dc18SMarcel Moolenaar .term = ns8250_term, 26127d5dc18SMarcel Moolenaar .putc = ns8250_putc, 26297202af2SMarius Strobl .rxready = ns8250_rxready, 26327d5dc18SMarcel Moolenaar .getc = ns8250_getc, 26427d5dc18SMarcel Moolenaar }; 26527d5dc18SMarcel Moolenaar 26627d5dc18SMarcel Moolenaar static int 26727d5dc18SMarcel Moolenaar ns8250_probe(struct uart_bas *bas) 26827d5dc18SMarcel Moolenaar { 2698bceca4fSBenno Rice u_char val; 27027d5dc18SMarcel Moolenaar 27127d5dc18SMarcel Moolenaar /* Check known 0 bits that don't depend on DLAB. */ 27227d5dc18SMarcel Moolenaar val = uart_getreg(bas, REG_IIR); 27327d5dc18SMarcel Moolenaar if (val & 0x30) 27427d5dc18SMarcel Moolenaar return (ENXIO); 2755bdddc29SMarcel Moolenaar /* 2765bdddc29SMarcel Moolenaar * Bit 6 of the MCR (= 0x40) appears to be 1 for the Sun1699 2775bdddc29SMarcel Moolenaar * chip, but otherwise doesn't seem to have a function. In 2785bdddc29SMarcel Moolenaar * other words, uart(4) works regardless. Ignore that bit so 2795bdddc29SMarcel Moolenaar * the probe succeeds. 2805bdddc29SMarcel Moolenaar */ 28127d5dc18SMarcel Moolenaar val = uart_getreg(bas, REG_MCR); 2825bdddc29SMarcel Moolenaar if (val & 0xa0) 28327d5dc18SMarcel Moolenaar return (ENXIO); 28427d5dc18SMarcel Moolenaar 28527d5dc18SMarcel Moolenaar return (0); 28627d5dc18SMarcel Moolenaar } 28727d5dc18SMarcel Moolenaar 28827d5dc18SMarcel Moolenaar static void 28927d5dc18SMarcel Moolenaar ns8250_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, 29027d5dc18SMarcel Moolenaar int parity) 29127d5dc18SMarcel Moolenaar { 29258957d87SBenno Rice u_char ier; 29327d5dc18SMarcel Moolenaar 29427d5dc18SMarcel Moolenaar if (bas->rclk == 0) 29527d5dc18SMarcel Moolenaar bas->rclk = DEFAULT_RCLK; 29627d5dc18SMarcel Moolenaar ns8250_param(bas, baudrate, databits, stopbits, parity); 29727d5dc18SMarcel Moolenaar 29827d5dc18SMarcel Moolenaar /* Disable all interrupt sources. */ 2990aefb0a6SBenno Rice /* 3000aefb0a6SBenno Rice * We use 0xe0 instead of 0xf0 as the mask because the XScale PXA 3010aefb0a6SBenno Rice * UARTs split the receive time-out interrupt bit out separately as 3020aefb0a6SBenno Rice * 0x10. This gets handled by ier_mask and ier_rxbits below. 3030aefb0a6SBenno Rice */ 3040aefb0a6SBenno Rice ier = uart_getreg(bas, REG_IER) & 0xe0; 30558957d87SBenno Rice uart_setreg(bas, REG_IER, ier); 30627d5dc18SMarcel Moolenaar uart_barrier(bas); 30727d5dc18SMarcel Moolenaar 30827d5dc18SMarcel Moolenaar /* Disable the FIFO (if present). */ 30927d5dc18SMarcel Moolenaar uart_setreg(bas, REG_FCR, 0); 31027d5dc18SMarcel Moolenaar uart_barrier(bas); 31127d5dc18SMarcel Moolenaar 31227d5dc18SMarcel Moolenaar /* Set RTS & DTR. */ 31327d5dc18SMarcel Moolenaar uart_setreg(bas, REG_MCR, MCR_IE | MCR_RTS | MCR_DTR); 31427d5dc18SMarcel Moolenaar uart_barrier(bas); 31527d5dc18SMarcel Moolenaar 31627d5dc18SMarcel Moolenaar ns8250_clrint(bas); 31727d5dc18SMarcel Moolenaar } 31827d5dc18SMarcel Moolenaar 31927d5dc18SMarcel Moolenaar static void 32027d5dc18SMarcel Moolenaar ns8250_term(struct uart_bas *bas) 32127d5dc18SMarcel Moolenaar { 32227d5dc18SMarcel Moolenaar 32327d5dc18SMarcel Moolenaar /* Clear RTS & DTR. */ 32427d5dc18SMarcel Moolenaar uart_setreg(bas, REG_MCR, MCR_IE); 32527d5dc18SMarcel Moolenaar uart_barrier(bas); 32627d5dc18SMarcel Moolenaar } 32727d5dc18SMarcel Moolenaar 32827d5dc18SMarcel Moolenaar static void 32927d5dc18SMarcel Moolenaar ns8250_putc(struct uart_bas *bas, int c) 33027d5dc18SMarcel Moolenaar { 33135777a2aSMarcel Moolenaar int limit; 33227d5dc18SMarcel Moolenaar 33335777a2aSMarcel Moolenaar limit = 250000; 33427d5dc18SMarcel Moolenaar while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0 && --limit) 33535777a2aSMarcel Moolenaar DELAY(4); 33627d5dc18SMarcel Moolenaar uart_setreg(bas, REG_DATA, c); 3374e55f723SMarcel Moolenaar uart_barrier(bas); 33835777a2aSMarcel Moolenaar limit = 250000; 33927d5dc18SMarcel Moolenaar while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) 34035777a2aSMarcel Moolenaar DELAY(4); 34127d5dc18SMarcel Moolenaar } 34227d5dc18SMarcel Moolenaar 34327d5dc18SMarcel Moolenaar static int 34497202af2SMarius Strobl ns8250_rxready(struct uart_bas *bas) 34527d5dc18SMarcel Moolenaar { 34627d5dc18SMarcel Moolenaar 34797202af2SMarius Strobl return ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) != 0 ? 1 : 0); 34827d5dc18SMarcel Moolenaar } 34927d5dc18SMarcel Moolenaar 35027d5dc18SMarcel Moolenaar static int 351634e63c9SMarcel Moolenaar ns8250_getc(struct uart_bas *bas, struct mtx *hwmtx) 35227d5dc18SMarcel Moolenaar { 35335777a2aSMarcel Moolenaar int c; 354634e63c9SMarcel Moolenaar 355634e63c9SMarcel Moolenaar uart_lock(hwmtx); 35627d5dc18SMarcel Moolenaar 357634e63c9SMarcel Moolenaar while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0) { 358634e63c9SMarcel Moolenaar uart_unlock(hwmtx); 35935777a2aSMarcel Moolenaar DELAY(4); 360634e63c9SMarcel Moolenaar uart_lock(hwmtx); 361634e63c9SMarcel Moolenaar } 362634e63c9SMarcel Moolenaar 363634e63c9SMarcel Moolenaar c = uart_getreg(bas, REG_DATA); 364634e63c9SMarcel Moolenaar 365634e63c9SMarcel Moolenaar uart_unlock(hwmtx); 366634e63c9SMarcel Moolenaar 367634e63c9SMarcel Moolenaar return (c); 36827d5dc18SMarcel Moolenaar } 36927d5dc18SMarcel Moolenaar 37027d5dc18SMarcel Moolenaar static kobj_method_t ns8250_methods[] = { 37127d5dc18SMarcel Moolenaar KOBJMETHOD(uart_attach, ns8250_bus_attach), 37227d5dc18SMarcel Moolenaar KOBJMETHOD(uart_detach, ns8250_bus_detach), 37327d5dc18SMarcel Moolenaar KOBJMETHOD(uart_flush, ns8250_bus_flush), 37427d5dc18SMarcel Moolenaar KOBJMETHOD(uart_getsig, ns8250_bus_getsig), 37527d5dc18SMarcel Moolenaar KOBJMETHOD(uart_ioctl, ns8250_bus_ioctl), 37627d5dc18SMarcel Moolenaar KOBJMETHOD(uart_ipend, ns8250_bus_ipend), 37727d5dc18SMarcel Moolenaar KOBJMETHOD(uart_param, ns8250_bus_param), 37827d5dc18SMarcel Moolenaar KOBJMETHOD(uart_probe, ns8250_bus_probe), 37927d5dc18SMarcel Moolenaar KOBJMETHOD(uart_receive, ns8250_bus_receive), 38027d5dc18SMarcel Moolenaar KOBJMETHOD(uart_setsig, ns8250_bus_setsig), 38127d5dc18SMarcel Moolenaar KOBJMETHOD(uart_transmit, ns8250_bus_transmit), 382d76a1ef4SWarner Losh KOBJMETHOD(uart_grab, ns8250_bus_grab), 383d76a1ef4SWarner Losh KOBJMETHOD(uart_ungrab, ns8250_bus_ungrab), 38427d5dc18SMarcel Moolenaar { 0, 0 } 38527d5dc18SMarcel Moolenaar }; 38627d5dc18SMarcel Moolenaar 38727d5dc18SMarcel Moolenaar struct uart_class uart_ns8250_class = { 388f8100ce2SMarcel Moolenaar "ns8250", 38927d5dc18SMarcel Moolenaar ns8250_methods, 39027d5dc18SMarcel Moolenaar sizeof(struct ns8250_softc), 391f8100ce2SMarcel Moolenaar .uc_ops = &uart_ns8250_ops, 39227d5dc18SMarcel Moolenaar .uc_range = 8, 393405ada37SAndrew Turner .uc_rclk = DEFAULT_RCLK, 394405ada37SAndrew Turner .uc_rshift = 0 39527d5dc18SMarcel Moolenaar }; 39627d5dc18SMarcel Moolenaar 3973bb693afSIan Lepore #ifdef FDT 3983bb693afSIan Lepore static struct ofw_compat_data compat_data[] = { 3993bb693afSIan Lepore {"ns16550", (uintptr_t)&uart_ns8250_class}, 4003b654e08SWojciech Macek {"ns16550a", (uintptr_t)&uart_ns8250_class}, 4013bb693afSIan Lepore {NULL, (uintptr_t)NULL}, 4023bb693afSIan Lepore }; 4033bb693afSIan Lepore UART_FDT_CLASS_AND_DEVICE(compat_data); 4043bb693afSIan Lepore #endif 4053bb693afSIan Lepore 406fdfbb3f5SIan Lepore /* Use token-pasting to form SER_ and MSR_ named constants. */ 407fdfbb3f5SIan Lepore #define SER(sig) SER_##sig 408fdfbb3f5SIan Lepore #define SERD(sig) SER_D##sig 409fdfbb3f5SIan Lepore #define MSR(sig) MSR_##sig 410fdfbb3f5SIan Lepore #define MSRD(sig) MSR_D##sig 411fdfbb3f5SIan Lepore 412fdfbb3f5SIan Lepore /* 413fdfbb3f5SIan Lepore * Detect signal changes using software delta detection. The previous state of 414fdfbb3f5SIan Lepore * the signals is in 'var' the new hardware state is in 'msr', and 'sig' is the 415fdfbb3f5SIan Lepore * short name (DCD, CTS, etc) of the signal bit being processed; 'var' gets the 416fdfbb3f5SIan Lepore * new state of both the signal and the delta bits. 417fdfbb3f5SIan Lepore */ 418fdfbb3f5SIan Lepore #define SIGCHGSW(var, msr, sig) \ 419fdfbb3f5SIan Lepore if ((msr) & MSR(sig)) { \ 420fdfbb3f5SIan Lepore if ((var & SER(sig)) == 0) \ 421fdfbb3f5SIan Lepore var |= SERD(sig) | SER(sig); \ 42227d5dc18SMarcel Moolenaar } else { \ 423fdfbb3f5SIan Lepore if ((var & SER(sig)) != 0) \ 424fdfbb3f5SIan Lepore var = SERD(sig) | (var & ~SER(sig)); \ 425fdfbb3f5SIan Lepore } 426fdfbb3f5SIan Lepore 427fdfbb3f5SIan Lepore /* 428fdfbb3f5SIan Lepore * Detect signal changes using the hardware msr delta bits. This is currently 429fdfbb3f5SIan Lepore * used only when PPS timing information is being captured using the "narrow 430fdfbb3f5SIan Lepore * pulse" option. With a narrow PPS pulse the signal may not still be asserted 431fdfbb3f5SIan Lepore * by time the interrupt handler is invoked. The hardware will latch the fact 432fdfbb3f5SIan Lepore * that it changed in the delta bits. 433fdfbb3f5SIan Lepore */ 434fdfbb3f5SIan Lepore #define SIGCHGHW(var, msr, sig) \ 435fdfbb3f5SIan Lepore if ((msr) & MSRD(sig)) { \ 436fdfbb3f5SIan Lepore if (((msr) & MSR(sig)) != 0) \ 437fdfbb3f5SIan Lepore var |= SERD(sig) | SER(sig); \ 438fdfbb3f5SIan Lepore else \ 439fdfbb3f5SIan Lepore var = SERD(sig) | (var & ~SER(sig)); \ 44027d5dc18SMarcel Moolenaar } 44127d5dc18SMarcel Moolenaar 442167cb33fSIan Lepore int 44327d5dc18SMarcel Moolenaar ns8250_bus_attach(struct uart_softc *sc) 44427d5dc18SMarcel Moolenaar { 44527d5dc18SMarcel Moolenaar struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 44627d5dc18SMarcel Moolenaar struct uart_bas *bas; 447823c77d7SSam Leffler unsigned int ivar; 448ac4adddfSGanbold Tsagaankhuu #ifdef FDT 449ac4adddfSGanbold Tsagaankhuu phandle_t node; 450ac4adddfSGanbold Tsagaankhuu pcell_t cell; 451ac4adddfSGanbold Tsagaankhuu #endif 452ac4adddfSGanbold Tsagaankhuu 453ac4adddfSGanbold Tsagaankhuu #ifdef FDT 454b738dafdSJared McNeill /* Check whether uart has a broken txfifo. */ 455ac4adddfSGanbold Tsagaankhuu node = ofw_bus_get_node(sc->sc_dev); 456b1621f22SLuiz Otavio O Souza if ((OF_getencprop(node, "broken-txfifo", &cell, sizeof(cell))) > 0) 457b1621f22SLuiz Otavio O Souza broken_txfifo = cell ? 1 : 0; 458ac4adddfSGanbold Tsagaankhuu #endif 45927d5dc18SMarcel Moolenaar 46027d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 46127d5dc18SMarcel Moolenaar 46227d5dc18SMarcel Moolenaar ns8250->mcr = uart_getreg(bas, REG_MCR); 463823c77d7SSam Leffler ns8250->fcr = FCR_ENABLE; 464823c77d7SSam Leffler if (!resource_int_value("uart", device_get_unit(sc->sc_dev), "flags", 465823c77d7SSam Leffler &ivar)) { 466823c77d7SSam Leffler if (UART_FLAGS_FCR_RX_LOW(ivar)) 467823c77d7SSam Leffler ns8250->fcr |= FCR_RX_LOW; 468823c77d7SSam Leffler else if (UART_FLAGS_FCR_RX_MEDL(ivar)) 469823c77d7SSam Leffler ns8250->fcr |= FCR_RX_MEDL; 470823c77d7SSam Leffler else if (UART_FLAGS_FCR_RX_HIGH(ivar)) 471823c77d7SSam Leffler ns8250->fcr |= FCR_RX_HIGH; 472823c77d7SSam Leffler else 473823c77d7SSam Leffler ns8250->fcr |= FCR_RX_MEDH; 474823c77d7SSam Leffler } else 475823c77d7SSam Leffler ns8250->fcr |= FCR_RX_MEDH; 4760aefb0a6SBenno Rice 4770aefb0a6SBenno Rice /* Get IER mask */ 4780aefb0a6SBenno Rice ivar = 0xf0; 4790aefb0a6SBenno Rice resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_mask", 4800aefb0a6SBenno Rice &ivar); 4810aefb0a6SBenno Rice ns8250->ier_mask = (uint8_t)(ivar & 0xff); 4820aefb0a6SBenno Rice 4830aefb0a6SBenno Rice /* Get IER RX interrupt bits */ 4840aefb0a6SBenno Rice ivar = IER_EMSC | IER_ERLS | IER_ERXRDY; 4850aefb0a6SBenno Rice resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_rxbits", 4860aefb0a6SBenno Rice &ivar); 4870aefb0a6SBenno Rice ns8250->ier_rxbits = (uint8_t)(ivar & 0xff); 4880aefb0a6SBenno Rice 48927d5dc18SMarcel Moolenaar uart_setreg(bas, REG_FCR, ns8250->fcr); 49027d5dc18SMarcel Moolenaar uart_barrier(bas); 49127d5dc18SMarcel Moolenaar ns8250_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 49227d5dc18SMarcel Moolenaar 49327d5dc18SMarcel Moolenaar if (ns8250->mcr & MCR_DTR) 49428710806SPoul-Henning Kamp sc->sc_hwsig |= SER_DTR; 49527d5dc18SMarcel Moolenaar if (ns8250->mcr & MCR_RTS) 49628710806SPoul-Henning Kamp sc->sc_hwsig |= SER_RTS; 49727d5dc18SMarcel Moolenaar ns8250_bus_getsig(sc); 49827d5dc18SMarcel Moolenaar 49927d5dc18SMarcel Moolenaar ns8250_clrint(bas); 5000aefb0a6SBenno Rice ns8250->ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 5010aefb0a6SBenno Rice ns8250->ier |= ns8250->ier_rxbits; 50227d5dc18SMarcel Moolenaar uart_setreg(bas, REG_IER, ns8250->ier); 50327d5dc18SMarcel Moolenaar uart_barrier(bas); 5040aefb0a6SBenno Rice 5054fc49975SMarcel Moolenaar /* 5064fc49975SMarcel Moolenaar * Timing of the H/W access was changed with r253161 of uart_core.c 5074fc49975SMarcel Moolenaar * It has been observed that an ITE IT8513E would signal a break 5084fc49975SMarcel Moolenaar * condition with pretty much every character it received, unless 5094fc49975SMarcel Moolenaar * it had enough time to settle between ns8250_bus_attach() and 5104fc49975SMarcel Moolenaar * ns8250_bus_ipend() -- which it accidentally had before r253161. 5114fc49975SMarcel Moolenaar * It's not understood why the UART chip behaves this way and it 5124fc49975SMarcel Moolenaar * could very well be that the DELAY make the H/W work in the same 5134fc49975SMarcel Moolenaar * accidental manner as before. More analysis is warranted, but 5144fc49975SMarcel Moolenaar * at least now we fixed a known regression. 5154fc49975SMarcel Moolenaar */ 51640a827b6SMarcel Moolenaar DELAY(200); 51727d5dc18SMarcel Moolenaar return (0); 51827d5dc18SMarcel Moolenaar } 51927d5dc18SMarcel Moolenaar 520167cb33fSIan Lepore int 52127d5dc18SMarcel Moolenaar ns8250_bus_detach(struct uart_softc *sc) 52227d5dc18SMarcel Moolenaar { 5230aefb0a6SBenno Rice struct ns8250_softc *ns8250; 52427d5dc18SMarcel Moolenaar struct uart_bas *bas; 52558957d87SBenno Rice u_char ier; 52627d5dc18SMarcel Moolenaar 5270aefb0a6SBenno Rice ns8250 = (struct ns8250_softc *)sc; 52827d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 5290aefb0a6SBenno Rice ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 53058957d87SBenno Rice uart_setreg(bas, REG_IER, ier); 53127d5dc18SMarcel Moolenaar uart_barrier(bas); 53227d5dc18SMarcel Moolenaar ns8250_clrint(bas); 53327d5dc18SMarcel Moolenaar return (0); 53427d5dc18SMarcel Moolenaar } 53527d5dc18SMarcel Moolenaar 536167cb33fSIan Lepore int 53727d5dc18SMarcel Moolenaar ns8250_bus_flush(struct uart_softc *sc, int what) 53827d5dc18SMarcel Moolenaar { 53927d5dc18SMarcel Moolenaar struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 54027d5dc18SMarcel Moolenaar struct uart_bas *bas; 54106287620SMarcel Moolenaar int error; 54227d5dc18SMarcel Moolenaar 54327d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 5448af03381SMarcel Moolenaar uart_lock(sc->sc_hwmtx); 5458d1289feSMarcel Moolenaar if (sc->sc_rxfifosz > 1) { 54627d5dc18SMarcel Moolenaar ns8250_flush(bas, what); 54727d5dc18SMarcel Moolenaar uart_setreg(bas, REG_FCR, ns8250->fcr); 54827d5dc18SMarcel Moolenaar uart_barrier(bas); 54906287620SMarcel Moolenaar error = 0; 55006287620SMarcel Moolenaar } else 55106287620SMarcel Moolenaar error = ns8250_drain(bas, what); 5528af03381SMarcel Moolenaar uart_unlock(sc->sc_hwmtx); 55306287620SMarcel Moolenaar return (error); 55427d5dc18SMarcel Moolenaar } 55527d5dc18SMarcel Moolenaar 556167cb33fSIan Lepore int 55727d5dc18SMarcel Moolenaar ns8250_bus_getsig(struct uart_softc *sc) 55827d5dc18SMarcel Moolenaar { 559fdfbb3f5SIan Lepore uint32_t old, sig; 56027d5dc18SMarcel Moolenaar uint8_t msr; 56127d5dc18SMarcel Moolenaar 562fdfbb3f5SIan Lepore /* 563fdfbb3f5SIan Lepore * The delta bits are reputed to be broken on some hardware, so use 564fdfbb3f5SIan Lepore * software delta detection by default. Use the hardware delta bits 565fdfbb3f5SIan Lepore * when capturing PPS pulses which are too narrow for software detection 566fdfbb3f5SIan Lepore * to see the edges. Hardware delta for RI doesn't work like the 567fdfbb3f5SIan Lepore * others, so always use software for it. Other threads may be changing 568fdfbb3f5SIan Lepore * other (non-MSR) bits in sc_hwsig, so loop until it can succesfully 569fdfbb3f5SIan Lepore * update without other changes happening. Note that the SIGCHGxx() 570fdfbb3f5SIan Lepore * macros carefully preserve the delta bits when we have to loop several 571fdfbb3f5SIan Lepore * times and a signal transitions between iterations. 572fdfbb3f5SIan Lepore */ 57327d5dc18SMarcel Moolenaar do { 57427d5dc18SMarcel Moolenaar old = sc->sc_hwsig; 57527d5dc18SMarcel Moolenaar sig = old; 5768af03381SMarcel Moolenaar uart_lock(sc->sc_hwmtx); 57727d5dc18SMarcel Moolenaar msr = uart_getreg(&sc->sc_bas, REG_MSR); 5788af03381SMarcel Moolenaar uart_unlock(sc->sc_hwmtx); 579fdfbb3f5SIan Lepore if (sc->sc_pps_mode & UART_PPS_NARROW_PULSE) { 580fdfbb3f5SIan Lepore SIGCHGHW(sig, msr, DSR); 581fdfbb3f5SIan Lepore SIGCHGHW(sig, msr, CTS); 582fdfbb3f5SIan Lepore SIGCHGHW(sig, msr, DCD); 583fdfbb3f5SIan Lepore } else { 584fdfbb3f5SIan Lepore SIGCHGSW(sig, msr, DSR); 585fdfbb3f5SIan Lepore SIGCHGSW(sig, msr, CTS); 586fdfbb3f5SIan Lepore SIGCHGSW(sig, msr, DCD); 587fdfbb3f5SIan Lepore } 588fdfbb3f5SIan Lepore SIGCHGSW(sig, msr, RI); 589fdfbb3f5SIan Lepore } while (!atomic_cmpset_32(&sc->sc_hwsig, old, sig & ~SER_MASK_DELTA)); 59027d5dc18SMarcel Moolenaar return (sig); 59127d5dc18SMarcel Moolenaar } 59227d5dc18SMarcel Moolenaar 593167cb33fSIan Lepore int 59427d5dc18SMarcel Moolenaar ns8250_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) 59527d5dc18SMarcel Moolenaar { 59627d5dc18SMarcel Moolenaar struct uart_bas *bas; 597bfa307a3SMarcel Moolenaar int baudrate, divisor, error; 59884c7b427SMarcel Moolenaar uint8_t efr, lcr; 59927d5dc18SMarcel Moolenaar 60027d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 60106287620SMarcel Moolenaar error = 0; 6028af03381SMarcel Moolenaar uart_lock(sc->sc_hwmtx); 60327d5dc18SMarcel Moolenaar switch (request) { 60427d5dc18SMarcel Moolenaar case UART_IOCTL_BREAK: 60527d5dc18SMarcel Moolenaar lcr = uart_getreg(bas, REG_LCR); 60627d5dc18SMarcel Moolenaar if (data) 60727d5dc18SMarcel Moolenaar lcr |= LCR_SBREAK; 60827d5dc18SMarcel Moolenaar else 60927d5dc18SMarcel Moolenaar lcr &= ~LCR_SBREAK; 61027d5dc18SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr); 61127d5dc18SMarcel Moolenaar uart_barrier(bas); 61227d5dc18SMarcel Moolenaar break; 61384c7b427SMarcel Moolenaar case UART_IOCTL_IFLOW: 61484c7b427SMarcel Moolenaar lcr = uart_getreg(bas, REG_LCR); 61584c7b427SMarcel Moolenaar uart_barrier(bas); 61684c7b427SMarcel Moolenaar uart_setreg(bas, REG_LCR, 0xbf); 61784c7b427SMarcel Moolenaar uart_barrier(bas); 61884c7b427SMarcel Moolenaar efr = uart_getreg(bas, REG_EFR); 61984c7b427SMarcel Moolenaar if (data) 62084c7b427SMarcel Moolenaar efr |= EFR_RTS; 62184c7b427SMarcel Moolenaar else 62284c7b427SMarcel Moolenaar efr &= ~EFR_RTS; 62384c7b427SMarcel Moolenaar uart_setreg(bas, REG_EFR, efr); 62484c7b427SMarcel Moolenaar uart_barrier(bas); 62584c7b427SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr); 62684c7b427SMarcel Moolenaar uart_barrier(bas); 62784c7b427SMarcel Moolenaar break; 62884c7b427SMarcel Moolenaar case UART_IOCTL_OFLOW: 62984c7b427SMarcel Moolenaar lcr = uart_getreg(bas, REG_LCR); 63084c7b427SMarcel Moolenaar uart_barrier(bas); 63184c7b427SMarcel Moolenaar uart_setreg(bas, REG_LCR, 0xbf); 63284c7b427SMarcel Moolenaar uart_barrier(bas); 63384c7b427SMarcel Moolenaar efr = uart_getreg(bas, REG_EFR); 63484c7b427SMarcel Moolenaar if (data) 63584c7b427SMarcel Moolenaar efr |= EFR_CTS; 63684c7b427SMarcel Moolenaar else 63784c7b427SMarcel Moolenaar efr &= ~EFR_CTS; 63884c7b427SMarcel Moolenaar uart_setreg(bas, REG_EFR, efr); 63984c7b427SMarcel Moolenaar uart_barrier(bas); 64084c7b427SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr); 64184c7b427SMarcel Moolenaar uart_barrier(bas); 64284c7b427SMarcel Moolenaar break; 643d8518925SMarcel Moolenaar case UART_IOCTL_BAUD: 644d8518925SMarcel Moolenaar lcr = uart_getreg(bas, REG_LCR); 645d8518925SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 646d8518925SMarcel Moolenaar uart_barrier(bas); 64758957d87SBenno Rice divisor = uart_getreg(bas, REG_DLL) | 64858957d87SBenno Rice (uart_getreg(bas, REG_DLH) << 8); 649d8518925SMarcel Moolenaar uart_barrier(bas); 650d8518925SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr); 651d8518925SMarcel Moolenaar uart_barrier(bas); 652bfa307a3SMarcel Moolenaar baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0; 653bfa307a3SMarcel Moolenaar if (baudrate > 0) 654bfa307a3SMarcel Moolenaar *(int*)data = baudrate; 655bfa307a3SMarcel Moolenaar else 656bfa307a3SMarcel Moolenaar error = ENXIO; 657d8518925SMarcel Moolenaar break; 65827d5dc18SMarcel Moolenaar default: 65906287620SMarcel Moolenaar error = EINVAL; 66006287620SMarcel Moolenaar break; 66127d5dc18SMarcel Moolenaar } 6628af03381SMarcel Moolenaar uart_unlock(sc->sc_hwmtx); 66306287620SMarcel Moolenaar return (error); 66427d5dc18SMarcel Moolenaar } 66527d5dc18SMarcel Moolenaar 666167cb33fSIan Lepore int 66727d5dc18SMarcel Moolenaar ns8250_bus_ipend(struct uart_softc *sc) 66827d5dc18SMarcel Moolenaar { 66927d5dc18SMarcel Moolenaar struct uart_bas *bas; 67011e55f91SOlivier Houchard struct ns8250_softc *ns8250; 67127d5dc18SMarcel Moolenaar int ipend; 67227d5dc18SMarcel Moolenaar uint8_t iir, lsr; 67327d5dc18SMarcel Moolenaar 67411e55f91SOlivier Houchard ns8250 = (struct ns8250_softc *)sc; 67527d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 6768af03381SMarcel Moolenaar uart_lock(sc->sc_hwmtx); 67727d5dc18SMarcel Moolenaar iir = uart_getreg(bas, REG_IIR); 678ac4adddfSGanbold Tsagaankhuu 679ac4adddfSGanbold Tsagaankhuu if (ns8250->busy_detect && (iir & IIR_BUSY) == IIR_BUSY) { 680ac4adddfSGanbold Tsagaankhuu (void)uart_getreg(bas, DW_REG_USR); 681ac4adddfSGanbold Tsagaankhuu uart_unlock(sc->sc_hwmtx); 682ac4adddfSGanbold Tsagaankhuu return (0); 683ac4adddfSGanbold Tsagaankhuu } 68406287620SMarcel Moolenaar if (iir & IIR_NOPEND) { 6858af03381SMarcel Moolenaar uart_unlock(sc->sc_hwmtx); 68627d5dc18SMarcel Moolenaar return (0); 68706287620SMarcel Moolenaar } 68827d5dc18SMarcel Moolenaar ipend = 0; 68927d5dc18SMarcel Moolenaar if (iir & IIR_RXRDY) { 69027d5dc18SMarcel Moolenaar lsr = uart_getreg(bas, REG_LSR); 69127d5dc18SMarcel Moolenaar if (lsr & LSR_OE) 6922d511805SMarcel Moolenaar ipend |= SER_INT_OVERRUN; 69327d5dc18SMarcel Moolenaar if (lsr & LSR_BI) 6942d511805SMarcel Moolenaar ipend |= SER_INT_BREAK; 69527d5dc18SMarcel Moolenaar if (lsr & LSR_RXRDY) 6962d511805SMarcel Moolenaar ipend |= SER_INT_RXREADY; 69727d5dc18SMarcel Moolenaar } else { 69811e55f91SOlivier Houchard if (iir & IIR_TXRDY) { 6992d511805SMarcel Moolenaar ipend |= SER_INT_TXIDLE; 70011e55f91SOlivier Houchard uart_setreg(bas, REG_IER, ns8250->ier); 7013c7b9077SMichal Meloun uart_barrier(bas); 70211e55f91SOlivier Houchard } else 7032d511805SMarcel Moolenaar ipend |= SER_INT_SIGCHG; 70427d5dc18SMarcel Moolenaar } 705d7ae5af5SMarcel Moolenaar if (ipend == 0) 706d7ae5af5SMarcel Moolenaar ns8250_clrint(bas); 707d7ae5af5SMarcel Moolenaar uart_unlock(sc->sc_hwmtx); 708f6ffc3c2SMarius Strobl return (ipend); 70927d5dc18SMarcel Moolenaar } 71027d5dc18SMarcel Moolenaar 711167cb33fSIan Lepore int 71227d5dc18SMarcel Moolenaar ns8250_bus_param(struct uart_softc *sc, int baudrate, int databits, 71327d5dc18SMarcel Moolenaar int stopbits, int parity) 71427d5dc18SMarcel Moolenaar { 71549e368acSZbigniew Bodek struct ns8250_softc *ns8250; 71627d5dc18SMarcel Moolenaar struct uart_bas *bas; 71749e368acSZbigniew Bodek int error, limit; 71827d5dc18SMarcel Moolenaar 71949e368acSZbigniew Bodek ns8250 = (struct ns8250_softc*)sc; 72027d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 7218af03381SMarcel Moolenaar uart_lock(sc->sc_hwmtx); 72249e368acSZbigniew Bodek /* 72349e368acSZbigniew Bodek * When using DW UART with BUSY detection it is necessary to wait 72449e368acSZbigniew Bodek * until all serial transfers are finished before manipulating the 72549e368acSZbigniew Bodek * line control. LCR will not be affected when UART is busy. 72649e368acSZbigniew Bodek */ 72749e368acSZbigniew Bodek if (ns8250->busy_detect != 0) { 72849e368acSZbigniew Bodek /* 72949e368acSZbigniew Bodek * Pick an arbitrary high limit to avoid getting stuck in 73049e368acSZbigniew Bodek * an infinite loop in case when the hardware is broken. 73149e368acSZbigniew Bodek */ 73249e368acSZbigniew Bodek limit = 10 * 1024; 73349e368acSZbigniew Bodek while (((uart_getreg(bas, DW_REG_USR) & USR_BUSY) != 0) && 73449e368acSZbigniew Bodek --limit) 73549e368acSZbigniew Bodek DELAY(4); 73649e368acSZbigniew Bodek 73749e368acSZbigniew Bodek if (limit <= 0) { 73849e368acSZbigniew Bodek /* UART appears to be stuck */ 73949e368acSZbigniew Bodek uart_unlock(sc->sc_hwmtx); 74049e368acSZbigniew Bodek return (EIO); 74149e368acSZbigniew Bodek } 74249e368acSZbigniew Bodek } 74349e368acSZbigniew Bodek 74406287620SMarcel Moolenaar error = ns8250_param(bas, baudrate, databits, stopbits, parity); 7458af03381SMarcel Moolenaar uart_unlock(sc->sc_hwmtx); 74606287620SMarcel Moolenaar return (error); 74727d5dc18SMarcel Moolenaar } 74827d5dc18SMarcel Moolenaar 749167cb33fSIan Lepore int 75027d5dc18SMarcel Moolenaar ns8250_bus_probe(struct uart_softc *sc) 75127d5dc18SMarcel Moolenaar { 7520aefb0a6SBenno Rice struct ns8250_softc *ns8250; 75327d5dc18SMarcel Moolenaar struct uart_bas *bas; 75427d5dc18SMarcel Moolenaar int count, delay, error, limit; 75558957d87SBenno Rice uint8_t lsr, mcr, ier; 75627d5dc18SMarcel Moolenaar 7570aefb0a6SBenno Rice ns8250 = (struct ns8250_softc *)sc; 75827d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 75927d5dc18SMarcel Moolenaar 76027d5dc18SMarcel Moolenaar error = ns8250_probe(bas); 76127d5dc18SMarcel Moolenaar if (error) 76227d5dc18SMarcel Moolenaar return (error); 76327d5dc18SMarcel Moolenaar 76427d5dc18SMarcel Moolenaar mcr = MCR_IE; 76527d5dc18SMarcel Moolenaar if (sc->sc_sysdev == NULL) { 76627d5dc18SMarcel Moolenaar /* By using ns8250_init() we also set DTR and RTS. */ 767d902fb71SMarcel Moolenaar ns8250_init(bas, 115200, 8, 1, UART_PARITY_NONE); 76827d5dc18SMarcel Moolenaar } else 76927d5dc18SMarcel Moolenaar mcr |= MCR_DTR | MCR_RTS; 77027d5dc18SMarcel Moolenaar 77127d5dc18SMarcel Moolenaar error = ns8250_drain(bas, UART_DRAIN_TRANSMITTER); 77227d5dc18SMarcel Moolenaar if (error) 77327d5dc18SMarcel Moolenaar return (error); 77427d5dc18SMarcel Moolenaar 77527d5dc18SMarcel Moolenaar /* 77627d5dc18SMarcel Moolenaar * Set loopback mode. This avoids having garbage on the wire and 77727d5dc18SMarcel Moolenaar * also allows us send and receive data. We set DTR and RTS to 77827d5dc18SMarcel Moolenaar * avoid the possibility that automatic flow-control prevents 77989eef2deSThomas Moestl * any data from being sent. 78027d5dc18SMarcel Moolenaar */ 78189eef2deSThomas Moestl uart_setreg(bas, REG_MCR, MCR_LOOPBACK | MCR_IE | MCR_DTR | MCR_RTS); 78227d5dc18SMarcel Moolenaar uart_barrier(bas); 78327d5dc18SMarcel Moolenaar 78427d5dc18SMarcel Moolenaar /* 78527d5dc18SMarcel Moolenaar * Enable FIFOs. And check that the UART has them. If not, we're 78689eef2deSThomas Moestl * done. Since this is the first time we enable the FIFOs, we reset 78789eef2deSThomas Moestl * them. 78827d5dc18SMarcel Moolenaar */ 78927d5dc18SMarcel Moolenaar uart_setreg(bas, REG_FCR, FCR_ENABLE); 79027d5dc18SMarcel Moolenaar uart_barrier(bas); 7918d1289feSMarcel Moolenaar if (!(uart_getreg(bas, REG_IIR) & IIR_FIFO_MASK)) { 79227d5dc18SMarcel Moolenaar /* 79327d5dc18SMarcel Moolenaar * NS16450 or INS8250. We don't bother to differentiate 79427d5dc18SMarcel Moolenaar * between them. They're too old to be interesting. 79527d5dc18SMarcel Moolenaar */ 79627d5dc18SMarcel Moolenaar uart_setreg(bas, REG_MCR, mcr); 79727d5dc18SMarcel Moolenaar uart_barrier(bas); 7988d1289feSMarcel Moolenaar sc->sc_rxfifosz = sc->sc_txfifosz = 1; 79927d5dc18SMarcel Moolenaar device_set_desc(sc->sc_dev, "8250 or 16450 or compatible"); 80027d5dc18SMarcel Moolenaar return (0); 80127d5dc18SMarcel Moolenaar } 80227d5dc18SMarcel Moolenaar 80389eef2deSThomas Moestl uart_setreg(bas, REG_FCR, FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST); 80427d5dc18SMarcel Moolenaar uart_barrier(bas); 80527d5dc18SMarcel Moolenaar 80627d5dc18SMarcel Moolenaar count = 0; 80727d5dc18SMarcel Moolenaar delay = ns8250_delay(bas); 80827d5dc18SMarcel Moolenaar 80927d5dc18SMarcel Moolenaar /* We have FIFOs. Drain the transmitter and receiver. */ 81027d5dc18SMarcel Moolenaar error = ns8250_drain(bas, UART_DRAIN_RECEIVER|UART_DRAIN_TRANSMITTER); 81127d5dc18SMarcel Moolenaar if (error) { 81227d5dc18SMarcel Moolenaar uart_setreg(bas, REG_MCR, mcr); 81327d5dc18SMarcel Moolenaar uart_setreg(bas, REG_FCR, 0); 81427d5dc18SMarcel Moolenaar uart_barrier(bas); 81527d5dc18SMarcel Moolenaar goto describe; 81627d5dc18SMarcel Moolenaar } 81727d5dc18SMarcel Moolenaar 81827d5dc18SMarcel Moolenaar /* 81927d5dc18SMarcel Moolenaar * We should have a sufficiently clean "pipe" to determine the 82027d5dc18SMarcel Moolenaar * size of the FIFOs. We send as much characters as is reasonable 8216bccea7cSRebecca Cran * and wait for the overflow bit in the LSR register to be 82289eef2deSThomas Moestl * asserted, counting the characters as we send them. Based on 82389eef2deSThomas Moestl * that count we know the FIFO size. 82427d5dc18SMarcel Moolenaar */ 82589eef2deSThomas Moestl do { 82627d5dc18SMarcel Moolenaar uart_setreg(bas, REG_DATA, 0); 82727d5dc18SMarcel Moolenaar uart_barrier(bas); 82827d5dc18SMarcel Moolenaar count++; 82927d5dc18SMarcel Moolenaar 83027d5dc18SMarcel Moolenaar limit = 30; 83189eef2deSThomas Moestl lsr = 0; 83289eef2deSThomas Moestl /* 83389eef2deSThomas Moestl * LSR bits are cleared upon read, so we must accumulate 83489eef2deSThomas Moestl * them to be able to test LSR_OE below. 83589eef2deSThomas Moestl */ 83689eef2deSThomas Moestl while (((lsr |= uart_getreg(bas, REG_LSR)) & LSR_TEMT) == 0 && 83789eef2deSThomas Moestl --limit) 83827d5dc18SMarcel Moolenaar DELAY(delay); 83927d5dc18SMarcel Moolenaar if (limit == 0) { 8400aefb0a6SBenno Rice ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 84158957d87SBenno Rice uart_setreg(bas, REG_IER, ier); 84227d5dc18SMarcel Moolenaar uart_setreg(bas, REG_MCR, mcr); 84327d5dc18SMarcel Moolenaar uart_setreg(bas, REG_FCR, 0); 84427d5dc18SMarcel Moolenaar uart_barrier(bas); 84527d5dc18SMarcel Moolenaar count = 0; 84627d5dc18SMarcel Moolenaar goto describe; 84727d5dc18SMarcel Moolenaar } 848d882cf92SMarcel Moolenaar } while ((lsr & LSR_OE) == 0 && count < 130); 84989eef2deSThomas Moestl count--; 85027d5dc18SMarcel Moolenaar 85127d5dc18SMarcel Moolenaar uart_setreg(bas, REG_MCR, mcr); 85227d5dc18SMarcel Moolenaar 85327d5dc18SMarcel Moolenaar /* Reset FIFOs. */ 85427d5dc18SMarcel Moolenaar ns8250_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 85527d5dc18SMarcel Moolenaar 85627d5dc18SMarcel Moolenaar describe: 85789eef2deSThomas Moestl if (count >= 14 && count <= 16) { 85827d5dc18SMarcel Moolenaar sc->sc_rxfifosz = 16; 85927d5dc18SMarcel Moolenaar device_set_desc(sc->sc_dev, "16550 or compatible"); 86089eef2deSThomas Moestl } else if (count >= 28 && count <= 32) { 86127d5dc18SMarcel Moolenaar sc->sc_rxfifosz = 32; 86227d5dc18SMarcel Moolenaar device_set_desc(sc->sc_dev, "16650 or compatible"); 86389eef2deSThomas Moestl } else if (count >= 56 && count <= 64) { 86427d5dc18SMarcel Moolenaar sc->sc_rxfifosz = 64; 86527d5dc18SMarcel Moolenaar device_set_desc(sc->sc_dev, "16750 or compatible"); 86689eef2deSThomas Moestl } else if (count >= 112 && count <= 128) { 86727d5dc18SMarcel Moolenaar sc->sc_rxfifosz = 128; 86827d5dc18SMarcel Moolenaar device_set_desc(sc->sc_dev, "16950 or compatible"); 86927d5dc18SMarcel Moolenaar } else { 870c21e0da2SMarcel Moolenaar sc->sc_rxfifosz = 16; 87127d5dc18SMarcel Moolenaar device_set_desc(sc->sc_dev, 87227d5dc18SMarcel Moolenaar "Non-standard ns8250 class UART with FIFOs"); 87327d5dc18SMarcel Moolenaar } 87427d5dc18SMarcel Moolenaar 87527d5dc18SMarcel Moolenaar /* 87627d5dc18SMarcel Moolenaar * Force the Tx FIFO size to 16 bytes for now. We don't program the 87727d5dc18SMarcel Moolenaar * Tx trigger. Also, we assume that all data has been sent when the 87827d5dc18SMarcel Moolenaar * interrupt happens. 87927d5dc18SMarcel Moolenaar */ 88027d5dc18SMarcel Moolenaar sc->sc_txfifosz = 16; 88127d5dc18SMarcel Moolenaar 882dc70e792SMarcel Moolenaar #if 0 883dc70e792SMarcel Moolenaar /* 884dc70e792SMarcel Moolenaar * XXX there are some issues related to hardware flow control and 885dc70e792SMarcel Moolenaar * it's likely that uart(4) is the cause. This basicly needs more 886dc70e792SMarcel Moolenaar * investigation, but we avoid using for hardware flow control 887dc70e792SMarcel Moolenaar * until then. 888dc70e792SMarcel Moolenaar */ 88984c7b427SMarcel Moolenaar /* 16650s or higher have automatic flow control. */ 89084c7b427SMarcel Moolenaar if (sc->sc_rxfifosz > 16) { 89184c7b427SMarcel Moolenaar sc->sc_hwiflow = 1; 89284c7b427SMarcel Moolenaar sc->sc_hwoflow = 1; 89384c7b427SMarcel Moolenaar } 894dc70e792SMarcel Moolenaar #endif 89584c7b427SMarcel Moolenaar 89627d5dc18SMarcel Moolenaar return (0); 89727d5dc18SMarcel Moolenaar } 89827d5dc18SMarcel Moolenaar 899167cb33fSIan Lepore int 90027d5dc18SMarcel Moolenaar ns8250_bus_receive(struct uart_softc *sc) 90127d5dc18SMarcel Moolenaar { 90227d5dc18SMarcel Moolenaar struct uart_bas *bas; 90327d5dc18SMarcel Moolenaar int xc; 90427d5dc18SMarcel Moolenaar uint8_t lsr; 90527d5dc18SMarcel Moolenaar 90627d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 9078af03381SMarcel Moolenaar uart_lock(sc->sc_hwmtx); 90827d5dc18SMarcel Moolenaar lsr = uart_getreg(bas, REG_LSR); 90944ed791bSMarcel Moolenaar while (lsr & LSR_RXRDY) { 91044ed791bSMarcel Moolenaar if (uart_rx_full(sc)) { 91144ed791bSMarcel Moolenaar sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; 91227d5dc18SMarcel Moolenaar break; 91344ed791bSMarcel Moolenaar } 91427d5dc18SMarcel Moolenaar xc = uart_getreg(bas, REG_DATA); 91527d5dc18SMarcel Moolenaar if (lsr & LSR_FE) 91627d5dc18SMarcel Moolenaar xc |= UART_STAT_FRAMERR; 91727d5dc18SMarcel Moolenaar if (lsr & LSR_PE) 91827d5dc18SMarcel Moolenaar xc |= UART_STAT_PARERR; 91927d5dc18SMarcel Moolenaar uart_rx_put(sc, xc); 92044ed791bSMarcel Moolenaar lsr = uart_getreg(bas, REG_LSR); 92144ed791bSMarcel Moolenaar } 92244ed791bSMarcel Moolenaar /* Discard everything left in the Rx FIFO. */ 92344ed791bSMarcel Moolenaar while (lsr & LSR_RXRDY) { 92444ed791bSMarcel Moolenaar (void)uart_getreg(bas, REG_DATA); 92544ed791bSMarcel Moolenaar uart_barrier(bas); 92644ed791bSMarcel Moolenaar lsr = uart_getreg(bas, REG_LSR); 92727d5dc18SMarcel Moolenaar } 9288af03381SMarcel Moolenaar uart_unlock(sc->sc_hwmtx); 92927d5dc18SMarcel Moolenaar return (0); 93027d5dc18SMarcel Moolenaar } 93127d5dc18SMarcel Moolenaar 932167cb33fSIan Lepore int 93327d5dc18SMarcel Moolenaar ns8250_bus_setsig(struct uart_softc *sc, int sig) 93427d5dc18SMarcel Moolenaar { 93527d5dc18SMarcel Moolenaar struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 93627d5dc18SMarcel Moolenaar struct uart_bas *bas; 93727d5dc18SMarcel Moolenaar uint32_t new, old; 93827d5dc18SMarcel Moolenaar 93927d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 94027d5dc18SMarcel Moolenaar do { 94127d5dc18SMarcel Moolenaar old = sc->sc_hwsig; 94227d5dc18SMarcel Moolenaar new = old; 94328710806SPoul-Henning Kamp if (sig & SER_DDTR) { 944fdfbb3f5SIan Lepore new = (new & ~SER_DTR) | (sig & (SER_DTR | SER_DDTR)); 94527d5dc18SMarcel Moolenaar } 94628710806SPoul-Henning Kamp if (sig & SER_DRTS) { 947fdfbb3f5SIan Lepore new = (new & ~SER_RTS) | (sig & (SER_RTS | SER_DRTS)); 94827d5dc18SMarcel Moolenaar } 94927d5dc18SMarcel Moolenaar } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 9508af03381SMarcel Moolenaar uart_lock(sc->sc_hwmtx); 95127d5dc18SMarcel Moolenaar ns8250->mcr &= ~(MCR_DTR|MCR_RTS); 95228710806SPoul-Henning Kamp if (new & SER_DTR) 95327d5dc18SMarcel Moolenaar ns8250->mcr |= MCR_DTR; 95428710806SPoul-Henning Kamp if (new & SER_RTS) 95527d5dc18SMarcel Moolenaar ns8250->mcr |= MCR_RTS; 95627d5dc18SMarcel Moolenaar uart_setreg(bas, REG_MCR, ns8250->mcr); 95727d5dc18SMarcel Moolenaar uart_barrier(bas); 9588af03381SMarcel Moolenaar uart_unlock(sc->sc_hwmtx); 95927d5dc18SMarcel Moolenaar return (0); 96027d5dc18SMarcel Moolenaar } 96127d5dc18SMarcel Moolenaar 962167cb33fSIan Lepore int 96327d5dc18SMarcel Moolenaar ns8250_bus_transmit(struct uart_softc *sc) 96427d5dc18SMarcel Moolenaar { 96527d5dc18SMarcel Moolenaar struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 96627d5dc18SMarcel Moolenaar struct uart_bas *bas; 96727d5dc18SMarcel Moolenaar int i; 96827d5dc18SMarcel Moolenaar 96927d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 9708af03381SMarcel Moolenaar uart_lock(sc->sc_hwmtx); 97127d5dc18SMarcel Moolenaar while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0) 97227d5dc18SMarcel Moolenaar ; 97327d5dc18SMarcel Moolenaar for (i = 0; i < sc->sc_txdatasz; i++) { 97427d5dc18SMarcel Moolenaar uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]); 97527d5dc18SMarcel Moolenaar uart_barrier(bas); 97627d5dc18SMarcel Moolenaar } 9773c7b9077SMichal Meloun uart_setreg(bas, REG_IER, ns8250->ier | IER_ETXRDY); 9783c7b9077SMichal Meloun uart_barrier(bas); 9791c60b24bSColin Percival if (broken_txfifo) 9801c60b24bSColin Percival ns8250_drain(bas, UART_DRAIN_TRANSMITTER); 9811c60b24bSColin Percival else 98227d5dc18SMarcel Moolenaar sc->sc_txbusy = 1; 9838af03381SMarcel Moolenaar uart_unlock(sc->sc_hwmtx); 9841c60b24bSColin Percival if (broken_txfifo) 9851c60b24bSColin Percival uart_sched_softih(sc, SER_INT_TXIDLE); 98627d5dc18SMarcel Moolenaar return (0); 98727d5dc18SMarcel Moolenaar } 988d76a1ef4SWarner Losh 989d76a1ef4SWarner Losh void 990d76a1ef4SWarner Losh ns8250_bus_grab(struct uart_softc *sc) 991d76a1ef4SWarner Losh { 992d76a1ef4SWarner Losh struct uart_bas *bas = &sc->sc_bas; 993caf6d6b4SOlivier Houchard struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 9948bc9a079SOlivier Houchard u_char ier; 995d76a1ef4SWarner Losh 996d76a1ef4SWarner Losh /* 997d76a1ef4SWarner Losh * turn off all interrupts to enter polling mode. Leave the 998d76a1ef4SWarner Losh * saved mask alone. We'll restore whatever it was in ungrab. 999d76a1ef4SWarner Losh * All pending interupt signals are reset when IER is set to 0. 1000d76a1ef4SWarner Losh */ 1001d76a1ef4SWarner Losh uart_lock(sc->sc_hwmtx); 10028bc9a079SOlivier Houchard ier = uart_getreg(bas, REG_IER); 10038bc9a079SOlivier Houchard uart_setreg(bas, REG_IER, ier & ns8250->ier_mask); 1004d76a1ef4SWarner Losh uart_barrier(bas); 1005d76a1ef4SWarner Losh uart_unlock(sc->sc_hwmtx); 1006d76a1ef4SWarner Losh } 1007d76a1ef4SWarner Losh 1008d76a1ef4SWarner Losh void 1009d76a1ef4SWarner Losh ns8250_bus_ungrab(struct uart_softc *sc) 1010d76a1ef4SWarner Losh { 1011d76a1ef4SWarner Losh struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 1012d76a1ef4SWarner Losh struct uart_bas *bas = &sc->sc_bas; 1013d76a1ef4SWarner Losh 1014d76a1ef4SWarner Losh /* 1015d76a1ef4SWarner Losh * Restore previous interrupt mask 1016d76a1ef4SWarner Losh */ 1017d76a1ef4SWarner Losh uart_lock(sc->sc_hwmtx); 1018d76a1ef4SWarner Losh uart_setreg(bas, REG_IER, ns8250->ier); 1019d76a1ef4SWarner Losh uart_barrier(bas); 1020d76a1ef4SWarner Losh uart_unlock(sc->sc_hwmtx); 1021d76a1ef4SWarner Losh } 1022