1098ca2bdSWarner Losh /*- 2718cf2ccSPedro F. Giffuni * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3718cf2ccSPedro F. Giffuni * 427d5dc18SMarcel Moolenaar * Copyright (c) 2003 Marcel Moolenaar 527d5dc18SMarcel Moolenaar * All rights reserved. 627d5dc18SMarcel Moolenaar * 727d5dc18SMarcel Moolenaar * Redistribution and use in source and binary forms, with or without 827d5dc18SMarcel Moolenaar * modification, are permitted provided that the following conditions 927d5dc18SMarcel Moolenaar * are met: 1027d5dc18SMarcel Moolenaar * 1127d5dc18SMarcel Moolenaar * 1. Redistributions of source code must retain the above copyright 1227d5dc18SMarcel Moolenaar * notice, this list of conditions and the following disclaimer. 1327d5dc18SMarcel Moolenaar * 2. Redistributions in binary form must reproduce the above copyright 1427d5dc18SMarcel Moolenaar * notice, this list of conditions and the following disclaimer in the 1527d5dc18SMarcel Moolenaar * documentation and/or other materials provided with the distribution. 1627d5dc18SMarcel Moolenaar * 1727d5dc18SMarcel Moolenaar * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 1827d5dc18SMarcel Moolenaar * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 1927d5dc18SMarcel Moolenaar * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 2027d5dc18SMarcel Moolenaar * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 2127d5dc18SMarcel Moolenaar * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 2227d5dc18SMarcel Moolenaar * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2327d5dc18SMarcel Moolenaar * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2427d5dc18SMarcel Moolenaar * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2527d5dc18SMarcel Moolenaar * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 2627d5dc18SMarcel Moolenaar * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2727d5dc18SMarcel Moolenaar */ 2827d5dc18SMarcel Moolenaar 29381388b9SMatt Macy #include "opt_acpi.h" 30ac4adddfSGanbold Tsagaankhuu #include "opt_platform.h" 31e0fe7c95SAdrian Chadd #include "opt_uart.h" 32ac4adddfSGanbold Tsagaankhuu 3327d5dc18SMarcel Moolenaar #include <sys/cdefs.h> 3427d5dc18SMarcel Moolenaar __FBSDID("$FreeBSD$"); 3527d5dc18SMarcel Moolenaar 3627d5dc18SMarcel Moolenaar #include <sys/param.h> 3727d5dc18SMarcel Moolenaar #include <sys/systm.h> 3827d5dc18SMarcel Moolenaar #include <sys/bus.h> 3927d5dc18SMarcel Moolenaar #include <sys/conf.h> 401c60b24bSColin Percival #include <sys/kernel.h> 411c60b24bSColin Percival #include <sys/sysctl.h> 4227d5dc18SMarcel Moolenaar #include <machine/bus.h> 4327d5dc18SMarcel Moolenaar 44ac4adddfSGanbold Tsagaankhuu #ifdef FDT 45ac4adddfSGanbold Tsagaankhuu #include <dev/fdt/fdt_common.h> 46ac4adddfSGanbold Tsagaankhuu #include <dev/ofw/ofw_bus.h> 47ac4adddfSGanbold Tsagaankhuu #include <dev/ofw/ofw_bus_subr.h> 48ac4adddfSGanbold Tsagaankhuu #endif 49ac4adddfSGanbold Tsagaankhuu 5027d5dc18SMarcel Moolenaar #include <dev/uart/uart.h> 5127d5dc18SMarcel Moolenaar #include <dev/uart/uart_cpu.h> 523bb693afSIan Lepore #ifdef FDT 533bb693afSIan Lepore #include <dev/uart/uart_cpu_fdt.h> 543bb693afSIan Lepore #endif 5527d5dc18SMarcel Moolenaar #include <dev/uart/uart_bus.h> 56167cb33fSIan Lepore #include <dev/uart/uart_dev_ns8250.h> 57fdfbb3f5SIan Lepore #include <dev/uart/uart_ppstypes.h> 58381388b9SMatt Macy #ifdef DEV_ACPI 59381388b9SMatt Macy #include <dev/uart/uart_cpu_acpi.h> 609cf66a04SMarcin Wojtas #include <contrib/dev/acpica/include/acpi.h> 61381388b9SMatt Macy #endif 6276563beaSMarcel Moolenaar 6376563beaSMarcel Moolenaar #include <dev/ic/ns16550.h> 6427d5dc18SMarcel Moolenaar 6527d5dc18SMarcel Moolenaar #include "uart_if.h" 6627d5dc18SMarcel Moolenaar 6727d5dc18SMarcel Moolenaar #define DEFAULT_RCLK 1843200 6827d5dc18SMarcel Moolenaar 69e0fe7c95SAdrian Chadd /* 70e0fe7c95SAdrian Chadd * Set the default baudrate tolerance to 3.0%. 71e0fe7c95SAdrian Chadd * 72e0fe7c95SAdrian Chadd * Some embedded boards have odd reference clocks (eg 25MHz) 73e0fe7c95SAdrian Chadd * and we need to handle higher variances in the target baud rate. 74e0fe7c95SAdrian Chadd */ 75e0fe7c95SAdrian Chadd #ifndef UART_DEV_TOLERANCE_PCT 76e0fe7c95SAdrian Chadd #define UART_DEV_TOLERANCE_PCT 30 77e0fe7c95SAdrian Chadd #endif /* UART_DEV_TOLERANCE_PCT */ 78e0fe7c95SAdrian Chadd 79ac4adddfSGanbold Tsagaankhuu static int broken_txfifo = 0; 80af3b2549SHans Petter Selasky SYSCTL_INT(_hw, OID_AUTO, broken_txfifo, CTLFLAG_RWTUN, 81ac4adddfSGanbold Tsagaankhuu &broken_txfifo, 0, "UART FIFO has QEMU emulation bug"); 82ac4adddfSGanbold Tsagaankhuu 8327d5dc18SMarcel Moolenaar /* 8427d5dc18SMarcel Moolenaar * Clear pending interrupts. THRE is cleared by reading IIR. Data 8527d5dc18SMarcel Moolenaar * that may have been received gets lost here. 8627d5dc18SMarcel Moolenaar */ 8727d5dc18SMarcel Moolenaar static void 8827d5dc18SMarcel Moolenaar ns8250_clrint(struct uart_bas *bas) 8927d5dc18SMarcel Moolenaar { 90d7ae5af5SMarcel Moolenaar uint8_t iir, lsr; 9127d5dc18SMarcel Moolenaar 9227d5dc18SMarcel Moolenaar iir = uart_getreg(bas, REG_IIR); 9327d5dc18SMarcel Moolenaar while ((iir & IIR_NOPEND) == 0) { 9427d5dc18SMarcel Moolenaar iir &= IIR_IMASK; 95d7ae5af5SMarcel Moolenaar if (iir == IIR_RLS) { 96d7ae5af5SMarcel Moolenaar lsr = uart_getreg(bas, REG_LSR); 97d7ae5af5SMarcel Moolenaar if (lsr & (LSR_BI|LSR_FE|LSR_PE)) 98d7ae5af5SMarcel Moolenaar (void)uart_getreg(bas, REG_DATA); 99d7ae5af5SMarcel Moolenaar } else if (iir == IIR_RXRDY || iir == IIR_RXTOUT) 10027d5dc18SMarcel Moolenaar (void)uart_getreg(bas, REG_DATA); 10127d5dc18SMarcel Moolenaar else if (iir == IIR_MLSC) 10227d5dc18SMarcel Moolenaar (void)uart_getreg(bas, REG_MSR); 10327d5dc18SMarcel Moolenaar uart_barrier(bas); 10427d5dc18SMarcel Moolenaar iir = uart_getreg(bas, REG_IIR); 10527d5dc18SMarcel Moolenaar } 10627d5dc18SMarcel Moolenaar } 10727d5dc18SMarcel Moolenaar 10827d5dc18SMarcel Moolenaar static int 10927d5dc18SMarcel Moolenaar ns8250_delay(struct uart_bas *bas) 11027d5dc18SMarcel Moolenaar { 11127d5dc18SMarcel Moolenaar int divisor; 11227d5dc18SMarcel Moolenaar u_char lcr; 11327d5dc18SMarcel Moolenaar 11427d5dc18SMarcel Moolenaar lcr = uart_getreg(bas, REG_LCR); 11527d5dc18SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 11627d5dc18SMarcel Moolenaar uart_barrier(bas); 11758957d87SBenno Rice divisor = uart_getreg(bas, REG_DLL) | (uart_getreg(bas, REG_DLH) << 8); 11827d5dc18SMarcel Moolenaar uart_barrier(bas); 11927d5dc18SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr); 12027d5dc18SMarcel Moolenaar uart_barrier(bas); 12127d5dc18SMarcel Moolenaar 12227d5dc18SMarcel Moolenaar /* 1/10th the time to transmit 1 character (estimate). */ 123ebecffe9SMarcel Moolenaar if (divisor <= 134) 12427d5dc18SMarcel Moolenaar return (16000000 * divisor / bas->rclk); 125ebecffe9SMarcel Moolenaar return (16000 * divisor / (bas->rclk / 1000)); 12627d5dc18SMarcel Moolenaar } 12727d5dc18SMarcel Moolenaar 12827d5dc18SMarcel Moolenaar static int 12927d5dc18SMarcel Moolenaar ns8250_divisor(int rclk, int baudrate) 13027d5dc18SMarcel Moolenaar { 13127d5dc18SMarcel Moolenaar int actual_baud, divisor; 13227d5dc18SMarcel Moolenaar int error; 13327d5dc18SMarcel Moolenaar 13427d5dc18SMarcel Moolenaar if (baudrate == 0) 13527d5dc18SMarcel Moolenaar return (0); 13627d5dc18SMarcel Moolenaar 13727d5dc18SMarcel Moolenaar divisor = (rclk / (baudrate << 3) + 1) >> 1; 13827d5dc18SMarcel Moolenaar if (divisor == 0 || divisor >= 65536) 13927d5dc18SMarcel Moolenaar return (0); 14027d5dc18SMarcel Moolenaar actual_baud = rclk / (divisor << 4); 14127d5dc18SMarcel Moolenaar 14227d5dc18SMarcel Moolenaar /* 10 times error in percent: */ 143b47c1edaSJohn Baldwin error = ((actual_baud - baudrate) * 2000 / baudrate + 1) / 2; 14427d5dc18SMarcel Moolenaar 145e0fe7c95SAdrian Chadd /* enforce maximum error tolerance: */ 146e0fe7c95SAdrian Chadd if (error < -UART_DEV_TOLERANCE_PCT || error > UART_DEV_TOLERANCE_PCT) 14727d5dc18SMarcel Moolenaar return (0); 14827d5dc18SMarcel Moolenaar 14927d5dc18SMarcel Moolenaar return (divisor); 15027d5dc18SMarcel Moolenaar } 15127d5dc18SMarcel Moolenaar 15227d5dc18SMarcel Moolenaar static int 15327d5dc18SMarcel Moolenaar ns8250_drain(struct uart_bas *bas, int what) 15427d5dc18SMarcel Moolenaar { 15527d5dc18SMarcel Moolenaar int delay, limit; 15627d5dc18SMarcel Moolenaar 15727d5dc18SMarcel Moolenaar delay = ns8250_delay(bas); 15827d5dc18SMarcel Moolenaar 15927d5dc18SMarcel Moolenaar if (what & UART_DRAIN_TRANSMITTER) { 16027d5dc18SMarcel Moolenaar /* 16127d5dc18SMarcel Moolenaar * Pick an arbitrary high limit to avoid getting stuck in 16227d5dc18SMarcel Moolenaar * an infinite loop when the hardware is broken. Make the 16327d5dc18SMarcel Moolenaar * limit high enough to handle large FIFOs. 16427d5dc18SMarcel Moolenaar */ 16527d5dc18SMarcel Moolenaar limit = 10*1024; 16627d5dc18SMarcel Moolenaar while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) 16727d5dc18SMarcel Moolenaar DELAY(delay); 16827d5dc18SMarcel Moolenaar if (limit == 0) { 16927d5dc18SMarcel Moolenaar /* printf("ns8250: transmitter appears stuck... "); */ 17027d5dc18SMarcel Moolenaar return (EIO); 17127d5dc18SMarcel Moolenaar } 17227d5dc18SMarcel Moolenaar } 17327d5dc18SMarcel Moolenaar 17427d5dc18SMarcel Moolenaar if (what & UART_DRAIN_RECEIVER) { 17527d5dc18SMarcel Moolenaar /* 17627d5dc18SMarcel Moolenaar * Pick an arbitrary high limit to avoid getting stuck in 17727d5dc18SMarcel Moolenaar * an infinite loop when the hardware is broken. Make the 17827d5dc18SMarcel Moolenaar * limit high enough to handle large FIFOs and integrated 17927d5dc18SMarcel Moolenaar * UARTs. The HP rx2600 for example has 3 UARTs on the 18027d5dc18SMarcel Moolenaar * management board that tend to get a lot of data send 18139d6144dSColin Percival * to it when the UART is first activated. Assume that we 18239d6144dSColin Percival * have finished draining if LSR_RXRDY is not asserted both 18339d6144dSColin Percival * prior to and after a DELAY; but as long as LSR_RXRDY is 18439d6144dSColin Percival * asserted, read (and discard) characters as quickly as 18539d6144dSColin Percival * possible. 18627d5dc18SMarcel Moolenaar */ 18727d5dc18SMarcel Moolenaar limit=10*4096; 18839d6144dSColin Percival while (limit && (uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) { 18939d6144dSColin Percival do { 19027d5dc18SMarcel Moolenaar (void)uart_getreg(bas, REG_DATA); 19127d5dc18SMarcel Moolenaar uart_barrier(bas); 19239d6144dSColin Percival } while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit); 19339d6144dSColin Percival uart_barrier(bas); 19427d5dc18SMarcel Moolenaar DELAY(delay << 2); 19527d5dc18SMarcel Moolenaar } 19627d5dc18SMarcel Moolenaar if (limit == 0) { 19727d5dc18SMarcel Moolenaar /* printf("ns8250: receiver appears broken... "); */ 19827d5dc18SMarcel Moolenaar return (EIO); 19927d5dc18SMarcel Moolenaar } 20027d5dc18SMarcel Moolenaar } 20127d5dc18SMarcel Moolenaar 20227d5dc18SMarcel Moolenaar return (0); 20327d5dc18SMarcel Moolenaar } 20427d5dc18SMarcel Moolenaar 20527d5dc18SMarcel Moolenaar /* 20627d5dc18SMarcel Moolenaar * We can only flush UARTs with FIFOs. UARTs without FIFOs should be 20727d5dc18SMarcel Moolenaar * drained. WARNING: this function clobbers the FIFO setting! 20827d5dc18SMarcel Moolenaar */ 20927d5dc18SMarcel Moolenaar static void 21027d5dc18SMarcel Moolenaar ns8250_flush(struct uart_bas *bas, int what) 21127d5dc18SMarcel Moolenaar { 21227d5dc18SMarcel Moolenaar uint8_t fcr; 213c4b68e7eSColin Percival uint8_t lsr; 214c4b68e7eSColin Percival int drain = 0; 21527d5dc18SMarcel Moolenaar 21627d5dc18SMarcel Moolenaar fcr = FCR_ENABLE; 217b192bae6SRuslan Bukin #ifdef CPU_XBURST 218b192bae6SRuslan Bukin fcr |= FCR_UART_ON; 219b192bae6SRuslan Bukin #endif 22027d5dc18SMarcel Moolenaar if (what & UART_FLUSH_TRANSMITTER) 22127d5dc18SMarcel Moolenaar fcr |= FCR_XMT_RST; 22227d5dc18SMarcel Moolenaar if (what & UART_FLUSH_RECEIVER) 22327d5dc18SMarcel Moolenaar fcr |= FCR_RCV_RST; 22427d5dc18SMarcel Moolenaar uart_setreg(bas, REG_FCR, fcr); 22527d5dc18SMarcel Moolenaar uart_barrier(bas); 226c4b68e7eSColin Percival 227c4b68e7eSColin Percival /* 228c4b68e7eSColin Percival * Detect and work around emulated UARTs which don't implement the 229c4b68e7eSColin Percival * FCR register; on these systems we need to drain the FIFO since 230c4b68e7eSColin Percival * the flush we request doesn't happen. One such system is the 231c4b68e7eSColin Percival * Firecracker VMM, aka. the rust-vmm/vm-superio emulation code: 232c4b68e7eSColin Percival * https://github.com/rust-vmm/vm-superio/issues/83 233c4b68e7eSColin Percival */ 234c4b68e7eSColin Percival lsr = uart_getreg(bas, REG_LSR); 235c4b68e7eSColin Percival if ((lsr & LSR_TEMT) && (what & UART_FLUSH_TRANSMITTER)) 236c4b68e7eSColin Percival drain |= UART_DRAIN_TRANSMITTER; 237c4b68e7eSColin Percival if ((lsr & LSR_RXRDY) && (what & UART_FLUSH_RECEIVER)) 238c4b68e7eSColin Percival drain |= UART_DRAIN_RECEIVER; 239c4b68e7eSColin Percival if (drain != 0) { 240c4b68e7eSColin Percival printf("ns8250: UART FCR is broken\n"); 241c4b68e7eSColin Percival ns8250_drain(bas, drain); 242c4b68e7eSColin Percival } 24327d5dc18SMarcel Moolenaar } 24427d5dc18SMarcel Moolenaar 24527d5dc18SMarcel Moolenaar static int 24627d5dc18SMarcel Moolenaar ns8250_param(struct uart_bas *bas, int baudrate, int databits, int stopbits, 24727d5dc18SMarcel Moolenaar int parity) 24827d5dc18SMarcel Moolenaar { 24927d5dc18SMarcel Moolenaar int divisor; 25027d5dc18SMarcel Moolenaar uint8_t lcr; 25127d5dc18SMarcel Moolenaar 25227d5dc18SMarcel Moolenaar lcr = 0; 25327d5dc18SMarcel Moolenaar if (databits >= 8) 25427d5dc18SMarcel Moolenaar lcr |= LCR_8BITS; 25527d5dc18SMarcel Moolenaar else if (databits == 7) 25627d5dc18SMarcel Moolenaar lcr |= LCR_7BITS; 25727d5dc18SMarcel Moolenaar else if (databits == 6) 25827d5dc18SMarcel Moolenaar lcr |= LCR_6BITS; 25927d5dc18SMarcel Moolenaar else 26027d5dc18SMarcel Moolenaar lcr |= LCR_5BITS; 26127d5dc18SMarcel Moolenaar if (stopbits > 1) 26227d5dc18SMarcel Moolenaar lcr |= LCR_STOPB; 26327d5dc18SMarcel Moolenaar lcr |= parity << 3; 26427d5dc18SMarcel Moolenaar 26527d5dc18SMarcel Moolenaar /* Set baudrate. */ 26627d5dc18SMarcel Moolenaar if (baudrate > 0) { 26727d5dc18SMarcel Moolenaar divisor = ns8250_divisor(bas->rclk, baudrate); 26827d5dc18SMarcel Moolenaar if (divisor == 0) 26927d5dc18SMarcel Moolenaar return (EINVAL); 27063f8efd3SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 27163f8efd3SMarcel Moolenaar uart_barrier(bas); 27258957d87SBenno Rice uart_setreg(bas, REG_DLL, divisor & 0xff); 27358957d87SBenno Rice uart_setreg(bas, REG_DLH, (divisor >> 8) & 0xff); 27427d5dc18SMarcel Moolenaar uart_barrier(bas); 27527d5dc18SMarcel Moolenaar } 27627d5dc18SMarcel Moolenaar 27727d5dc18SMarcel Moolenaar /* Set LCR and clear DLAB. */ 27827d5dc18SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr); 27927d5dc18SMarcel Moolenaar uart_barrier(bas); 28027d5dc18SMarcel Moolenaar return (0); 28127d5dc18SMarcel Moolenaar } 28227d5dc18SMarcel Moolenaar 28327d5dc18SMarcel Moolenaar /* 28427d5dc18SMarcel Moolenaar * Low-level UART interface. 28527d5dc18SMarcel Moolenaar */ 28627d5dc18SMarcel Moolenaar static int ns8250_probe(struct uart_bas *bas); 28727d5dc18SMarcel Moolenaar static void ns8250_init(struct uart_bas *bas, int, int, int, int); 28827d5dc18SMarcel Moolenaar static void ns8250_term(struct uart_bas *bas); 28927d5dc18SMarcel Moolenaar static void ns8250_putc(struct uart_bas *bas, int); 29097202af2SMarius Strobl static int ns8250_rxready(struct uart_bas *bas); 291634e63c9SMarcel Moolenaar static int ns8250_getc(struct uart_bas *bas, struct mtx *); 29227d5dc18SMarcel Moolenaar 293167cb33fSIan Lepore struct uart_ops uart_ns8250_ops = { 29427d5dc18SMarcel Moolenaar .probe = ns8250_probe, 29527d5dc18SMarcel Moolenaar .init = ns8250_init, 29627d5dc18SMarcel Moolenaar .term = ns8250_term, 29727d5dc18SMarcel Moolenaar .putc = ns8250_putc, 29897202af2SMarius Strobl .rxready = ns8250_rxready, 29927d5dc18SMarcel Moolenaar .getc = ns8250_getc, 30027d5dc18SMarcel Moolenaar }; 30127d5dc18SMarcel Moolenaar 30227d5dc18SMarcel Moolenaar static int 30327d5dc18SMarcel Moolenaar ns8250_probe(struct uart_bas *bas) 30427d5dc18SMarcel Moolenaar { 3058bceca4fSBenno Rice u_char val; 30627d5dc18SMarcel Moolenaar 307b192bae6SRuslan Bukin #ifdef CPU_XBURST 308b192bae6SRuslan Bukin uart_setreg(bas, REG_FCR, FCR_UART_ON); 309b192bae6SRuslan Bukin #endif 310b192bae6SRuslan Bukin 31127d5dc18SMarcel Moolenaar /* Check known 0 bits that don't depend on DLAB. */ 31227d5dc18SMarcel Moolenaar val = uart_getreg(bas, REG_IIR); 31327d5dc18SMarcel Moolenaar if (val & 0x30) 31427d5dc18SMarcel Moolenaar return (ENXIO); 3155bdddc29SMarcel Moolenaar /* 3165bdddc29SMarcel Moolenaar * Bit 6 of the MCR (= 0x40) appears to be 1 for the Sun1699 3175bdddc29SMarcel Moolenaar * chip, but otherwise doesn't seem to have a function. In 3185bdddc29SMarcel Moolenaar * other words, uart(4) works regardless. Ignore that bit so 3195bdddc29SMarcel Moolenaar * the probe succeeds. 3205bdddc29SMarcel Moolenaar */ 32127d5dc18SMarcel Moolenaar val = uart_getreg(bas, REG_MCR); 3225bdddc29SMarcel Moolenaar if (val & 0xa0) 32327d5dc18SMarcel Moolenaar return (ENXIO); 32427d5dc18SMarcel Moolenaar 32527d5dc18SMarcel Moolenaar return (0); 32627d5dc18SMarcel Moolenaar } 32727d5dc18SMarcel Moolenaar 32827d5dc18SMarcel Moolenaar static void 32927d5dc18SMarcel Moolenaar ns8250_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, 33027d5dc18SMarcel Moolenaar int parity) 33127d5dc18SMarcel Moolenaar { 332b192bae6SRuslan Bukin u_char ier, val; 33327d5dc18SMarcel Moolenaar 33427d5dc18SMarcel Moolenaar if (bas->rclk == 0) 33527d5dc18SMarcel Moolenaar bas->rclk = DEFAULT_RCLK; 33627d5dc18SMarcel Moolenaar ns8250_param(bas, baudrate, databits, stopbits, parity); 33727d5dc18SMarcel Moolenaar 33827d5dc18SMarcel Moolenaar /* Disable all interrupt sources. */ 3390aefb0a6SBenno Rice /* 3400aefb0a6SBenno Rice * We use 0xe0 instead of 0xf0 as the mask because the XScale PXA 3410aefb0a6SBenno Rice * UARTs split the receive time-out interrupt bit out separately as 3420aefb0a6SBenno Rice * 0x10. This gets handled by ier_mask and ier_rxbits below. 3430aefb0a6SBenno Rice */ 3440aefb0a6SBenno Rice ier = uart_getreg(bas, REG_IER) & 0xe0; 34558957d87SBenno Rice uart_setreg(bas, REG_IER, ier); 34627d5dc18SMarcel Moolenaar uart_barrier(bas); 34727d5dc18SMarcel Moolenaar 34827d5dc18SMarcel Moolenaar /* Disable the FIFO (if present). */ 349b192bae6SRuslan Bukin val = 0; 350b192bae6SRuslan Bukin #ifdef CPU_XBURST 3514e352a45SAlexander Motin val |= FCR_UART_ON; 352b192bae6SRuslan Bukin #endif 353b192bae6SRuslan Bukin uart_setreg(bas, REG_FCR, val); 35427d5dc18SMarcel Moolenaar uart_barrier(bas); 35527d5dc18SMarcel Moolenaar 35627d5dc18SMarcel Moolenaar /* Set RTS & DTR. */ 35727d5dc18SMarcel Moolenaar uart_setreg(bas, REG_MCR, MCR_IE | MCR_RTS | MCR_DTR); 35827d5dc18SMarcel Moolenaar uart_barrier(bas); 35927d5dc18SMarcel Moolenaar 36027d5dc18SMarcel Moolenaar ns8250_clrint(bas); 36127d5dc18SMarcel Moolenaar } 36227d5dc18SMarcel Moolenaar 36327d5dc18SMarcel Moolenaar static void 36427d5dc18SMarcel Moolenaar ns8250_term(struct uart_bas *bas) 36527d5dc18SMarcel Moolenaar { 36627d5dc18SMarcel Moolenaar 36727d5dc18SMarcel Moolenaar /* Clear RTS & DTR. */ 36827d5dc18SMarcel Moolenaar uart_setreg(bas, REG_MCR, MCR_IE); 36927d5dc18SMarcel Moolenaar uart_barrier(bas); 37027d5dc18SMarcel Moolenaar } 37127d5dc18SMarcel Moolenaar 37227d5dc18SMarcel Moolenaar static void 37327d5dc18SMarcel Moolenaar ns8250_putc(struct uart_bas *bas, int c) 37427d5dc18SMarcel Moolenaar { 37535777a2aSMarcel Moolenaar int limit; 37627d5dc18SMarcel Moolenaar 37735777a2aSMarcel Moolenaar limit = 250000; 37827d5dc18SMarcel Moolenaar while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0 && --limit) 37935777a2aSMarcel Moolenaar DELAY(4); 38027d5dc18SMarcel Moolenaar uart_setreg(bas, REG_DATA, c); 3814e55f723SMarcel Moolenaar uart_barrier(bas); 38227d5dc18SMarcel Moolenaar } 38327d5dc18SMarcel Moolenaar 38427d5dc18SMarcel Moolenaar static int 38597202af2SMarius Strobl ns8250_rxready(struct uart_bas *bas) 38627d5dc18SMarcel Moolenaar { 38727d5dc18SMarcel Moolenaar 38897202af2SMarius Strobl return ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) != 0 ? 1 : 0); 38927d5dc18SMarcel Moolenaar } 39027d5dc18SMarcel Moolenaar 39127d5dc18SMarcel Moolenaar static int 392634e63c9SMarcel Moolenaar ns8250_getc(struct uart_bas *bas, struct mtx *hwmtx) 39327d5dc18SMarcel Moolenaar { 39435777a2aSMarcel Moolenaar int c; 395634e63c9SMarcel Moolenaar 396634e63c9SMarcel Moolenaar uart_lock(hwmtx); 39727d5dc18SMarcel Moolenaar 398634e63c9SMarcel Moolenaar while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0) { 399634e63c9SMarcel Moolenaar uart_unlock(hwmtx); 40035777a2aSMarcel Moolenaar DELAY(4); 401634e63c9SMarcel Moolenaar uart_lock(hwmtx); 402634e63c9SMarcel Moolenaar } 403634e63c9SMarcel Moolenaar 404634e63c9SMarcel Moolenaar c = uart_getreg(bas, REG_DATA); 405634e63c9SMarcel Moolenaar 406634e63c9SMarcel Moolenaar uart_unlock(hwmtx); 407634e63c9SMarcel Moolenaar 408634e63c9SMarcel Moolenaar return (c); 40927d5dc18SMarcel Moolenaar } 41027d5dc18SMarcel Moolenaar 41127d5dc18SMarcel Moolenaar static kobj_method_t ns8250_methods[] = { 41227d5dc18SMarcel Moolenaar KOBJMETHOD(uart_attach, ns8250_bus_attach), 41327d5dc18SMarcel Moolenaar KOBJMETHOD(uart_detach, ns8250_bus_detach), 41427d5dc18SMarcel Moolenaar KOBJMETHOD(uart_flush, ns8250_bus_flush), 41527d5dc18SMarcel Moolenaar KOBJMETHOD(uart_getsig, ns8250_bus_getsig), 41627d5dc18SMarcel Moolenaar KOBJMETHOD(uart_ioctl, ns8250_bus_ioctl), 41727d5dc18SMarcel Moolenaar KOBJMETHOD(uart_ipend, ns8250_bus_ipend), 41827d5dc18SMarcel Moolenaar KOBJMETHOD(uart_param, ns8250_bus_param), 41927d5dc18SMarcel Moolenaar KOBJMETHOD(uart_probe, ns8250_bus_probe), 42027d5dc18SMarcel Moolenaar KOBJMETHOD(uart_receive, ns8250_bus_receive), 42127d5dc18SMarcel Moolenaar KOBJMETHOD(uart_setsig, ns8250_bus_setsig), 42227d5dc18SMarcel Moolenaar KOBJMETHOD(uart_transmit, ns8250_bus_transmit), 423d76a1ef4SWarner Losh KOBJMETHOD(uart_grab, ns8250_bus_grab), 424d76a1ef4SWarner Losh KOBJMETHOD(uart_ungrab, ns8250_bus_ungrab), 42527d5dc18SMarcel Moolenaar { 0, 0 } 42627d5dc18SMarcel Moolenaar }; 42727d5dc18SMarcel Moolenaar 42827d5dc18SMarcel Moolenaar struct uart_class uart_ns8250_class = { 429f8100ce2SMarcel Moolenaar "ns8250", 43027d5dc18SMarcel Moolenaar ns8250_methods, 43127d5dc18SMarcel Moolenaar sizeof(struct ns8250_softc), 432f8100ce2SMarcel Moolenaar .uc_ops = &uart_ns8250_ops, 43327d5dc18SMarcel Moolenaar .uc_range = 8, 434405ada37SAndrew Turner .uc_rclk = DEFAULT_RCLK, 435405ada37SAndrew Turner .uc_rshift = 0 43627d5dc18SMarcel Moolenaar }; 43727d5dc18SMarcel Moolenaar 438381388b9SMatt Macy /* 439381388b9SMatt Macy * XXX -- refactor out ACPI and FDT ifdefs 440381388b9SMatt Macy */ 441381388b9SMatt Macy #ifdef DEV_ACPI 442381388b9SMatt Macy static struct acpi_uart_compat_data acpi_compat_data[] = { 443381388b9SMatt Macy {"AMD0020", &uart_ns8250_class, 0, 2, 0, 48000000, UART_F_BUSY_DETECT, "AMD / Synopsys Designware UART"}, 444381388b9SMatt Macy {"AMDI0020", &uart_ns8250_class, 0, 2, 0, 48000000, UART_F_BUSY_DETECT, "AMD / Synopsys Designware UART"}, 4459cf66a04SMarcin Wojtas {"MRVL0001", &uart_ns8250_class, ACPI_DBG2_16550_SUBSET, 2, 0, 200000000, UART_F_BUSY_DETECT, "Marvell / Synopsys Designware UART"}, 446a852cb95SRebecca Cran {"SCX0006", &uart_ns8250_class, 0, 2, 0, 62500000, UART_F_BUSY_DETECT, "SynQuacer / Synopsys Designware UART"}, 447a852cb95SRebecca Cran {"HISI0031", &uart_ns8250_class, 0, 2, 0, 200000000, UART_F_BUSY_DETECT, "HiSilicon / Synopsys Designware UART"}, 4487cb73f65SMateusz Kozyra {"NXP0018", &uart_ns8250_class, 0, 0, 0, 350000000, UART_F_BUSY_DETECT, "NXP / Synopsys Designware UART"}, 449381388b9SMatt Macy {"PNP0500", &uart_ns8250_class, 0, 0, 0, 0, 0, "Standard PC COM port"}, 450381388b9SMatt Macy {"PNP0501", &uart_ns8250_class, 0, 0, 0, 0, 0, "16550A-compatible COM port"}, 451381388b9SMatt Macy {"PNP0502", &uart_ns8250_class, 0, 0, 0, 0, 0, "Multiport serial device (non-intelligent 16550)"}, 452381388b9SMatt Macy {"PNP0510", &uart_ns8250_class, 0, 0, 0, 0, 0, "Generic IRDA-compatible device"}, 453381388b9SMatt Macy {"PNP0511", &uart_ns8250_class, 0, 0, 0, 0, 0, "Generic IRDA-compatible device"}, 454381388b9SMatt Macy {"WACF004", &uart_ns8250_class, 0, 0, 0, 0, 0, "Wacom Tablet PC Screen"}, 455381388b9SMatt Macy {"WACF00E", &uart_ns8250_class, 0, 0, 0, 0, 0, "Wacom Tablet PC Screen 00e"}, 456381388b9SMatt Macy {"FUJ02E5", &uart_ns8250_class, 0, 0, 0, 0, 0, "Wacom Tablet at FuS Lifebook T"}, 457381388b9SMatt Macy {NULL, NULL, 0, 0 , 0, 0, 0, NULL}, 458381388b9SMatt Macy }; 459381388b9SMatt Macy UART_ACPI_CLASS_AND_DEVICE(acpi_compat_data); 460381388b9SMatt Macy #endif 461381388b9SMatt Macy 4623bb693afSIan Lepore #ifdef FDT 4633bb693afSIan Lepore static struct ofw_compat_data compat_data[] = { 4643bb693afSIan Lepore {"ns16550", (uintptr_t)&uart_ns8250_class}, 4653b654e08SWojciech Macek {"ns16550a", (uintptr_t)&uart_ns8250_class}, 4663bb693afSIan Lepore {NULL, (uintptr_t)NULL}, 4673bb693afSIan Lepore }; 4683bb693afSIan Lepore UART_FDT_CLASS_AND_DEVICE(compat_data); 4693bb693afSIan Lepore #endif 4703bb693afSIan Lepore 471fdfbb3f5SIan Lepore /* Use token-pasting to form SER_ and MSR_ named constants. */ 472fdfbb3f5SIan Lepore #define SER(sig) SER_##sig 473fdfbb3f5SIan Lepore #define SERD(sig) SER_D##sig 474fdfbb3f5SIan Lepore #define MSR(sig) MSR_##sig 475fdfbb3f5SIan Lepore #define MSRD(sig) MSR_D##sig 476fdfbb3f5SIan Lepore 477fdfbb3f5SIan Lepore /* 478fdfbb3f5SIan Lepore * Detect signal changes using software delta detection. The previous state of 479fdfbb3f5SIan Lepore * the signals is in 'var' the new hardware state is in 'msr', and 'sig' is the 480fdfbb3f5SIan Lepore * short name (DCD, CTS, etc) of the signal bit being processed; 'var' gets the 481fdfbb3f5SIan Lepore * new state of both the signal and the delta bits. 482fdfbb3f5SIan Lepore */ 483fdfbb3f5SIan Lepore #define SIGCHGSW(var, msr, sig) \ 484fdfbb3f5SIan Lepore if ((msr) & MSR(sig)) { \ 485fdfbb3f5SIan Lepore if ((var & SER(sig)) == 0) \ 486fdfbb3f5SIan Lepore var |= SERD(sig) | SER(sig); \ 48727d5dc18SMarcel Moolenaar } else { \ 488fdfbb3f5SIan Lepore if ((var & SER(sig)) != 0) \ 489fdfbb3f5SIan Lepore var = SERD(sig) | (var & ~SER(sig)); \ 490fdfbb3f5SIan Lepore } 491fdfbb3f5SIan Lepore 492fdfbb3f5SIan Lepore /* 493fdfbb3f5SIan Lepore * Detect signal changes using the hardware msr delta bits. This is currently 494fdfbb3f5SIan Lepore * used only when PPS timing information is being captured using the "narrow 495fdfbb3f5SIan Lepore * pulse" option. With a narrow PPS pulse the signal may not still be asserted 496fdfbb3f5SIan Lepore * by time the interrupt handler is invoked. The hardware will latch the fact 497fdfbb3f5SIan Lepore * that it changed in the delta bits. 498fdfbb3f5SIan Lepore */ 499fdfbb3f5SIan Lepore #define SIGCHGHW(var, msr, sig) \ 500fdfbb3f5SIan Lepore if ((msr) & MSRD(sig)) { \ 501fdfbb3f5SIan Lepore if (((msr) & MSR(sig)) != 0) \ 502fdfbb3f5SIan Lepore var |= SERD(sig) | SER(sig); \ 503fdfbb3f5SIan Lepore else \ 504fdfbb3f5SIan Lepore var = SERD(sig) | (var & ~SER(sig)); \ 50527d5dc18SMarcel Moolenaar } 50627d5dc18SMarcel Moolenaar 507167cb33fSIan Lepore int 50827d5dc18SMarcel Moolenaar ns8250_bus_attach(struct uart_softc *sc) 50927d5dc18SMarcel Moolenaar { 51027d5dc18SMarcel Moolenaar struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 51127d5dc18SMarcel Moolenaar struct uart_bas *bas; 512823c77d7SSam Leffler unsigned int ivar; 513ac4adddfSGanbold Tsagaankhuu #ifdef FDT 514ac4adddfSGanbold Tsagaankhuu phandle_t node; 515ac4adddfSGanbold Tsagaankhuu pcell_t cell; 516ac4adddfSGanbold Tsagaankhuu #endif 517ac4adddfSGanbold Tsagaankhuu 518ac4adddfSGanbold Tsagaankhuu #ifdef FDT 519b738dafdSJared McNeill /* Check whether uart has a broken txfifo. */ 520ac4adddfSGanbold Tsagaankhuu node = ofw_bus_get_node(sc->sc_dev); 521b1621f22SLuiz Otavio O Souza if ((OF_getencprop(node, "broken-txfifo", &cell, sizeof(cell))) > 0) 522b1621f22SLuiz Otavio O Souza broken_txfifo = cell ? 1 : 0; 523ac4adddfSGanbold Tsagaankhuu #endif 52427d5dc18SMarcel Moolenaar 52527d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 52627d5dc18SMarcel Moolenaar 527f30f0f2bSMatt Macy ns8250->busy_detect = bas->busy_detect; 52827d5dc18SMarcel Moolenaar ns8250->mcr = uart_getreg(bas, REG_MCR); 529823c77d7SSam Leffler ns8250->fcr = FCR_ENABLE; 530b192bae6SRuslan Bukin #ifdef CPU_XBURST 531b192bae6SRuslan Bukin ns8250->fcr |= FCR_UART_ON; 532b192bae6SRuslan Bukin #endif 533823c77d7SSam Leffler if (!resource_int_value("uart", device_get_unit(sc->sc_dev), "flags", 534823c77d7SSam Leffler &ivar)) { 535823c77d7SSam Leffler if (UART_FLAGS_FCR_RX_LOW(ivar)) 536823c77d7SSam Leffler ns8250->fcr |= FCR_RX_LOW; 537823c77d7SSam Leffler else if (UART_FLAGS_FCR_RX_MEDL(ivar)) 538823c77d7SSam Leffler ns8250->fcr |= FCR_RX_MEDL; 539823c77d7SSam Leffler else if (UART_FLAGS_FCR_RX_HIGH(ivar)) 540823c77d7SSam Leffler ns8250->fcr |= FCR_RX_HIGH; 541823c77d7SSam Leffler else 542823c77d7SSam Leffler ns8250->fcr |= FCR_RX_MEDH; 543823c77d7SSam Leffler } else 544823c77d7SSam Leffler ns8250->fcr |= FCR_RX_MEDH; 5450aefb0a6SBenno Rice 5460aefb0a6SBenno Rice /* Get IER mask */ 5470aefb0a6SBenno Rice ivar = 0xf0; 5480aefb0a6SBenno Rice resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_mask", 5490aefb0a6SBenno Rice &ivar); 5500aefb0a6SBenno Rice ns8250->ier_mask = (uint8_t)(ivar & 0xff); 5510aefb0a6SBenno Rice 5520aefb0a6SBenno Rice /* Get IER RX interrupt bits */ 5530aefb0a6SBenno Rice ivar = IER_EMSC | IER_ERLS | IER_ERXRDY; 5540aefb0a6SBenno Rice resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_rxbits", 5550aefb0a6SBenno Rice &ivar); 5560aefb0a6SBenno Rice ns8250->ier_rxbits = (uint8_t)(ivar & 0xff); 5570aefb0a6SBenno Rice 55827d5dc18SMarcel Moolenaar uart_setreg(bas, REG_FCR, ns8250->fcr); 55927d5dc18SMarcel Moolenaar uart_barrier(bas); 56027d5dc18SMarcel Moolenaar ns8250_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 56127d5dc18SMarcel Moolenaar 56227d5dc18SMarcel Moolenaar if (ns8250->mcr & MCR_DTR) 56328710806SPoul-Henning Kamp sc->sc_hwsig |= SER_DTR; 56427d5dc18SMarcel Moolenaar if (ns8250->mcr & MCR_RTS) 56528710806SPoul-Henning Kamp sc->sc_hwsig |= SER_RTS; 56627d5dc18SMarcel Moolenaar ns8250_bus_getsig(sc); 56727d5dc18SMarcel Moolenaar 56827d5dc18SMarcel Moolenaar ns8250_clrint(bas); 5690aefb0a6SBenno Rice ns8250->ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 5700aefb0a6SBenno Rice ns8250->ier |= ns8250->ier_rxbits; 57127d5dc18SMarcel Moolenaar uart_setreg(bas, REG_IER, ns8250->ier); 57227d5dc18SMarcel Moolenaar uart_barrier(bas); 5730aefb0a6SBenno Rice 5744fc49975SMarcel Moolenaar /* 5754fc49975SMarcel Moolenaar * Timing of the H/W access was changed with r253161 of uart_core.c 5764fc49975SMarcel Moolenaar * It has been observed that an ITE IT8513E would signal a break 5774fc49975SMarcel Moolenaar * condition with pretty much every character it received, unless 5784fc49975SMarcel Moolenaar * it had enough time to settle between ns8250_bus_attach() and 5794fc49975SMarcel Moolenaar * ns8250_bus_ipend() -- which it accidentally had before r253161. 5804fc49975SMarcel Moolenaar * It's not understood why the UART chip behaves this way and it 5814fc49975SMarcel Moolenaar * could very well be that the DELAY make the H/W work in the same 5824fc49975SMarcel Moolenaar * accidental manner as before. More analysis is warranted, but 5834fc49975SMarcel Moolenaar * at least now we fixed a known regression. 5844fc49975SMarcel Moolenaar */ 58540a827b6SMarcel Moolenaar DELAY(200); 58627d5dc18SMarcel Moolenaar return (0); 58727d5dc18SMarcel Moolenaar } 58827d5dc18SMarcel Moolenaar 589167cb33fSIan Lepore int 59027d5dc18SMarcel Moolenaar ns8250_bus_detach(struct uart_softc *sc) 59127d5dc18SMarcel Moolenaar { 5920aefb0a6SBenno Rice struct ns8250_softc *ns8250; 59327d5dc18SMarcel Moolenaar struct uart_bas *bas; 59458957d87SBenno Rice u_char ier; 59527d5dc18SMarcel Moolenaar 5960aefb0a6SBenno Rice ns8250 = (struct ns8250_softc *)sc; 59727d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 5980aefb0a6SBenno Rice ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 59958957d87SBenno Rice uart_setreg(bas, REG_IER, ier); 60027d5dc18SMarcel Moolenaar uart_barrier(bas); 60127d5dc18SMarcel Moolenaar ns8250_clrint(bas); 60227d5dc18SMarcel Moolenaar return (0); 60327d5dc18SMarcel Moolenaar } 60427d5dc18SMarcel Moolenaar 605167cb33fSIan Lepore int 60627d5dc18SMarcel Moolenaar ns8250_bus_flush(struct uart_softc *sc, int what) 60727d5dc18SMarcel Moolenaar { 60827d5dc18SMarcel Moolenaar struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 60927d5dc18SMarcel Moolenaar struct uart_bas *bas; 61006287620SMarcel Moolenaar int error; 61127d5dc18SMarcel Moolenaar 61227d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 6138af03381SMarcel Moolenaar uart_lock(sc->sc_hwmtx); 6148d1289feSMarcel Moolenaar if (sc->sc_rxfifosz > 1) { 61527d5dc18SMarcel Moolenaar ns8250_flush(bas, what); 61627d5dc18SMarcel Moolenaar uart_setreg(bas, REG_FCR, ns8250->fcr); 61727d5dc18SMarcel Moolenaar uart_barrier(bas); 61806287620SMarcel Moolenaar error = 0; 61906287620SMarcel Moolenaar } else 62006287620SMarcel Moolenaar error = ns8250_drain(bas, what); 6218af03381SMarcel Moolenaar uart_unlock(sc->sc_hwmtx); 62206287620SMarcel Moolenaar return (error); 62327d5dc18SMarcel Moolenaar } 62427d5dc18SMarcel Moolenaar 625167cb33fSIan Lepore int 62627d5dc18SMarcel Moolenaar ns8250_bus_getsig(struct uart_softc *sc) 62727d5dc18SMarcel Moolenaar { 628fdfbb3f5SIan Lepore uint32_t old, sig; 62927d5dc18SMarcel Moolenaar uint8_t msr; 63027d5dc18SMarcel Moolenaar 631fdfbb3f5SIan Lepore /* 632fdfbb3f5SIan Lepore * The delta bits are reputed to be broken on some hardware, so use 633fdfbb3f5SIan Lepore * software delta detection by default. Use the hardware delta bits 634fdfbb3f5SIan Lepore * when capturing PPS pulses which are too narrow for software detection 635fdfbb3f5SIan Lepore * to see the edges. Hardware delta for RI doesn't work like the 636fdfbb3f5SIan Lepore * others, so always use software for it. Other threads may be changing 637453130d9SPedro F. Giffuni * other (non-MSR) bits in sc_hwsig, so loop until it can successfully 638fdfbb3f5SIan Lepore * update without other changes happening. Note that the SIGCHGxx() 639fdfbb3f5SIan Lepore * macros carefully preserve the delta bits when we have to loop several 640fdfbb3f5SIan Lepore * times and a signal transitions between iterations. 641fdfbb3f5SIan Lepore */ 64227d5dc18SMarcel Moolenaar do { 64327d5dc18SMarcel Moolenaar old = sc->sc_hwsig; 64427d5dc18SMarcel Moolenaar sig = old; 6458af03381SMarcel Moolenaar uart_lock(sc->sc_hwmtx); 64627d5dc18SMarcel Moolenaar msr = uart_getreg(&sc->sc_bas, REG_MSR); 6478af03381SMarcel Moolenaar uart_unlock(sc->sc_hwmtx); 648fdfbb3f5SIan Lepore if (sc->sc_pps_mode & UART_PPS_NARROW_PULSE) { 649fdfbb3f5SIan Lepore SIGCHGHW(sig, msr, DSR); 650fdfbb3f5SIan Lepore SIGCHGHW(sig, msr, CTS); 651fdfbb3f5SIan Lepore SIGCHGHW(sig, msr, DCD); 652fdfbb3f5SIan Lepore } else { 653fdfbb3f5SIan Lepore SIGCHGSW(sig, msr, DSR); 654fdfbb3f5SIan Lepore SIGCHGSW(sig, msr, CTS); 655fdfbb3f5SIan Lepore SIGCHGSW(sig, msr, DCD); 656fdfbb3f5SIan Lepore } 657fdfbb3f5SIan Lepore SIGCHGSW(sig, msr, RI); 658fdfbb3f5SIan Lepore } while (!atomic_cmpset_32(&sc->sc_hwsig, old, sig & ~SER_MASK_DELTA)); 65927d5dc18SMarcel Moolenaar return (sig); 66027d5dc18SMarcel Moolenaar } 66127d5dc18SMarcel Moolenaar 662167cb33fSIan Lepore int 66327d5dc18SMarcel Moolenaar ns8250_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) 66427d5dc18SMarcel Moolenaar { 66527d5dc18SMarcel Moolenaar struct uart_bas *bas; 666bfa307a3SMarcel Moolenaar int baudrate, divisor, error; 66784c7b427SMarcel Moolenaar uint8_t efr, lcr; 66827d5dc18SMarcel Moolenaar 66927d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 67006287620SMarcel Moolenaar error = 0; 6718af03381SMarcel Moolenaar uart_lock(sc->sc_hwmtx); 67227d5dc18SMarcel Moolenaar switch (request) { 67327d5dc18SMarcel Moolenaar case UART_IOCTL_BREAK: 67427d5dc18SMarcel Moolenaar lcr = uart_getreg(bas, REG_LCR); 67527d5dc18SMarcel Moolenaar if (data) 67627d5dc18SMarcel Moolenaar lcr |= LCR_SBREAK; 67727d5dc18SMarcel Moolenaar else 67827d5dc18SMarcel Moolenaar lcr &= ~LCR_SBREAK; 67927d5dc18SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr); 68027d5dc18SMarcel Moolenaar uart_barrier(bas); 68127d5dc18SMarcel Moolenaar break; 68284c7b427SMarcel Moolenaar case UART_IOCTL_IFLOW: 68384c7b427SMarcel Moolenaar lcr = uart_getreg(bas, REG_LCR); 68484c7b427SMarcel Moolenaar uart_barrier(bas); 68584c7b427SMarcel Moolenaar uart_setreg(bas, REG_LCR, 0xbf); 68684c7b427SMarcel Moolenaar uart_barrier(bas); 68784c7b427SMarcel Moolenaar efr = uart_getreg(bas, REG_EFR); 68884c7b427SMarcel Moolenaar if (data) 68984c7b427SMarcel Moolenaar efr |= EFR_RTS; 69084c7b427SMarcel Moolenaar else 69184c7b427SMarcel Moolenaar efr &= ~EFR_RTS; 69284c7b427SMarcel Moolenaar uart_setreg(bas, REG_EFR, efr); 69384c7b427SMarcel Moolenaar uart_barrier(bas); 69484c7b427SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr); 69584c7b427SMarcel Moolenaar uart_barrier(bas); 69684c7b427SMarcel Moolenaar break; 69784c7b427SMarcel Moolenaar case UART_IOCTL_OFLOW: 69884c7b427SMarcel Moolenaar lcr = uart_getreg(bas, REG_LCR); 69984c7b427SMarcel Moolenaar uart_barrier(bas); 70084c7b427SMarcel Moolenaar uart_setreg(bas, REG_LCR, 0xbf); 70184c7b427SMarcel Moolenaar uart_barrier(bas); 70284c7b427SMarcel Moolenaar efr = uart_getreg(bas, REG_EFR); 70384c7b427SMarcel Moolenaar if (data) 70484c7b427SMarcel Moolenaar efr |= EFR_CTS; 70584c7b427SMarcel Moolenaar else 70684c7b427SMarcel Moolenaar efr &= ~EFR_CTS; 70784c7b427SMarcel Moolenaar uart_setreg(bas, REG_EFR, efr); 70884c7b427SMarcel Moolenaar uart_barrier(bas); 70984c7b427SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr); 71084c7b427SMarcel Moolenaar uart_barrier(bas); 71184c7b427SMarcel Moolenaar break; 712d8518925SMarcel Moolenaar case UART_IOCTL_BAUD: 713d8518925SMarcel Moolenaar lcr = uart_getreg(bas, REG_LCR); 714d8518925SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 715d8518925SMarcel Moolenaar uart_barrier(bas); 71658957d87SBenno Rice divisor = uart_getreg(bas, REG_DLL) | 71758957d87SBenno Rice (uart_getreg(bas, REG_DLH) << 8); 718d8518925SMarcel Moolenaar uart_barrier(bas); 719d8518925SMarcel Moolenaar uart_setreg(bas, REG_LCR, lcr); 720d8518925SMarcel Moolenaar uart_barrier(bas); 721bfa307a3SMarcel Moolenaar baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0; 722bfa307a3SMarcel Moolenaar if (baudrate > 0) 723bfa307a3SMarcel Moolenaar *(int*)data = baudrate; 724bfa307a3SMarcel Moolenaar else 725bfa307a3SMarcel Moolenaar error = ENXIO; 726d8518925SMarcel Moolenaar break; 72727d5dc18SMarcel Moolenaar default: 72806287620SMarcel Moolenaar error = EINVAL; 72906287620SMarcel Moolenaar break; 73027d5dc18SMarcel Moolenaar } 7318af03381SMarcel Moolenaar uart_unlock(sc->sc_hwmtx); 73206287620SMarcel Moolenaar return (error); 73327d5dc18SMarcel Moolenaar } 73427d5dc18SMarcel Moolenaar 735167cb33fSIan Lepore int 73627d5dc18SMarcel Moolenaar ns8250_bus_ipend(struct uart_softc *sc) 73727d5dc18SMarcel Moolenaar { 73827d5dc18SMarcel Moolenaar struct uart_bas *bas; 73911e55f91SOlivier Houchard struct ns8250_softc *ns8250; 74027d5dc18SMarcel Moolenaar int ipend; 74127d5dc18SMarcel Moolenaar uint8_t iir, lsr; 74227d5dc18SMarcel Moolenaar 74311e55f91SOlivier Houchard ns8250 = (struct ns8250_softc *)sc; 74427d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 7458af03381SMarcel Moolenaar uart_lock(sc->sc_hwmtx); 74627d5dc18SMarcel Moolenaar iir = uart_getreg(bas, REG_IIR); 747ac4adddfSGanbold Tsagaankhuu 748ac4adddfSGanbold Tsagaankhuu if (ns8250->busy_detect && (iir & IIR_BUSY) == IIR_BUSY) { 749ac4adddfSGanbold Tsagaankhuu (void)uart_getreg(bas, DW_REG_USR); 750ac4adddfSGanbold Tsagaankhuu uart_unlock(sc->sc_hwmtx); 751ac4adddfSGanbold Tsagaankhuu return (0); 752ac4adddfSGanbold Tsagaankhuu } 75306287620SMarcel Moolenaar if (iir & IIR_NOPEND) { 7548af03381SMarcel Moolenaar uart_unlock(sc->sc_hwmtx); 75527d5dc18SMarcel Moolenaar return (0); 75606287620SMarcel Moolenaar } 75727d5dc18SMarcel Moolenaar ipend = 0; 75827d5dc18SMarcel Moolenaar if (iir & IIR_RXRDY) { 75927d5dc18SMarcel Moolenaar lsr = uart_getreg(bas, REG_LSR); 76027d5dc18SMarcel Moolenaar if (lsr & LSR_OE) 7612d511805SMarcel Moolenaar ipend |= SER_INT_OVERRUN; 76227d5dc18SMarcel Moolenaar if (lsr & LSR_BI) 7632d511805SMarcel Moolenaar ipend |= SER_INT_BREAK; 76427d5dc18SMarcel Moolenaar if (lsr & LSR_RXRDY) 7652d511805SMarcel Moolenaar ipend |= SER_INT_RXREADY; 76627d5dc18SMarcel Moolenaar } else { 76711e55f91SOlivier Houchard if (iir & IIR_TXRDY) { 7682d511805SMarcel Moolenaar ipend |= SER_INT_TXIDLE; 7697e7f7beeSMitchell Horne ns8250->ier &= ~IER_ETXRDY; 77011e55f91SOlivier Houchard uart_setreg(bas, REG_IER, ns8250->ier); 7713c7b9077SMichal Meloun uart_barrier(bas); 77211e55f91SOlivier Houchard } else 7732d511805SMarcel Moolenaar ipend |= SER_INT_SIGCHG; 77427d5dc18SMarcel Moolenaar } 775d7ae5af5SMarcel Moolenaar if (ipend == 0) 776d7ae5af5SMarcel Moolenaar ns8250_clrint(bas); 777d7ae5af5SMarcel Moolenaar uart_unlock(sc->sc_hwmtx); 778f6ffc3c2SMarius Strobl return (ipend); 77927d5dc18SMarcel Moolenaar } 78027d5dc18SMarcel Moolenaar 781167cb33fSIan Lepore int 78227d5dc18SMarcel Moolenaar ns8250_bus_param(struct uart_softc *sc, int baudrate, int databits, 78327d5dc18SMarcel Moolenaar int stopbits, int parity) 78427d5dc18SMarcel Moolenaar { 78549e368acSZbigniew Bodek struct ns8250_softc *ns8250; 78627d5dc18SMarcel Moolenaar struct uart_bas *bas; 78749e368acSZbigniew Bodek int error, limit; 78827d5dc18SMarcel Moolenaar 78949e368acSZbigniew Bodek ns8250 = (struct ns8250_softc*)sc; 79027d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 7918af03381SMarcel Moolenaar uart_lock(sc->sc_hwmtx); 79249e368acSZbigniew Bodek /* 79349e368acSZbigniew Bodek * When using DW UART with BUSY detection it is necessary to wait 79449e368acSZbigniew Bodek * until all serial transfers are finished before manipulating the 79549e368acSZbigniew Bodek * line control. LCR will not be affected when UART is busy. 79649e368acSZbigniew Bodek */ 79749e368acSZbigniew Bodek if (ns8250->busy_detect != 0) { 79849e368acSZbigniew Bodek /* 79949e368acSZbigniew Bodek * Pick an arbitrary high limit to avoid getting stuck in 80049e368acSZbigniew Bodek * an infinite loop in case when the hardware is broken. 80149e368acSZbigniew Bodek */ 80249e368acSZbigniew Bodek limit = 10 * 1024; 80349e368acSZbigniew Bodek while (((uart_getreg(bas, DW_REG_USR) & USR_BUSY) != 0) && 80449e368acSZbigniew Bodek --limit) 80549e368acSZbigniew Bodek DELAY(4); 80649e368acSZbigniew Bodek 80749e368acSZbigniew Bodek if (limit <= 0) { 80849e368acSZbigniew Bodek /* UART appears to be stuck */ 80949e368acSZbigniew Bodek uart_unlock(sc->sc_hwmtx); 81049e368acSZbigniew Bodek return (EIO); 81149e368acSZbigniew Bodek } 81249e368acSZbigniew Bodek } 81349e368acSZbigniew Bodek 81406287620SMarcel Moolenaar error = ns8250_param(bas, baudrate, databits, stopbits, parity); 8158af03381SMarcel Moolenaar uart_unlock(sc->sc_hwmtx); 81606287620SMarcel Moolenaar return (error); 81727d5dc18SMarcel Moolenaar } 81827d5dc18SMarcel Moolenaar 819167cb33fSIan Lepore int 82027d5dc18SMarcel Moolenaar ns8250_bus_probe(struct uart_softc *sc) 82127d5dc18SMarcel Moolenaar { 82227d5dc18SMarcel Moolenaar struct uart_bas *bas; 82327d5dc18SMarcel Moolenaar int count, delay, error, limit; 82458957d87SBenno Rice uint8_t lsr, mcr, ier; 825b192bae6SRuslan Bukin uint8_t val; 82627d5dc18SMarcel Moolenaar 82727d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 82827d5dc18SMarcel Moolenaar 82927d5dc18SMarcel Moolenaar error = ns8250_probe(bas); 83027d5dc18SMarcel Moolenaar if (error) 83127d5dc18SMarcel Moolenaar return (error); 83227d5dc18SMarcel Moolenaar 83327d5dc18SMarcel Moolenaar mcr = MCR_IE; 83427d5dc18SMarcel Moolenaar if (sc->sc_sysdev == NULL) { 83527d5dc18SMarcel Moolenaar /* By using ns8250_init() we also set DTR and RTS. */ 836d902fb71SMarcel Moolenaar ns8250_init(bas, 115200, 8, 1, UART_PARITY_NONE); 83727d5dc18SMarcel Moolenaar } else 83827d5dc18SMarcel Moolenaar mcr |= MCR_DTR | MCR_RTS; 83927d5dc18SMarcel Moolenaar 84027d5dc18SMarcel Moolenaar error = ns8250_drain(bas, UART_DRAIN_TRANSMITTER); 84127d5dc18SMarcel Moolenaar if (error) 84227d5dc18SMarcel Moolenaar return (error); 84327d5dc18SMarcel Moolenaar 84427d5dc18SMarcel Moolenaar /* 84527d5dc18SMarcel Moolenaar * Set loopback mode. This avoids having garbage on the wire and 84627d5dc18SMarcel Moolenaar * also allows us send and receive data. We set DTR and RTS to 84727d5dc18SMarcel Moolenaar * avoid the possibility that automatic flow-control prevents 84889eef2deSThomas Moestl * any data from being sent. 84927d5dc18SMarcel Moolenaar */ 85089eef2deSThomas Moestl uart_setreg(bas, REG_MCR, MCR_LOOPBACK | MCR_IE | MCR_DTR | MCR_RTS); 85127d5dc18SMarcel Moolenaar uart_barrier(bas); 85227d5dc18SMarcel Moolenaar 85327d5dc18SMarcel Moolenaar /* 85427d5dc18SMarcel Moolenaar * Enable FIFOs. And check that the UART has them. If not, we're 85589eef2deSThomas Moestl * done. Since this is the first time we enable the FIFOs, we reset 85689eef2deSThomas Moestl * them. 85727d5dc18SMarcel Moolenaar */ 858b192bae6SRuslan Bukin val = FCR_ENABLE; 859b192bae6SRuslan Bukin #ifdef CPU_XBURST 860b192bae6SRuslan Bukin val |= FCR_UART_ON; 861b192bae6SRuslan Bukin #endif 862b192bae6SRuslan Bukin uart_setreg(bas, REG_FCR, val); 86327d5dc18SMarcel Moolenaar uart_barrier(bas); 8648d1289feSMarcel Moolenaar if (!(uart_getreg(bas, REG_IIR) & IIR_FIFO_MASK)) { 86527d5dc18SMarcel Moolenaar /* 86627d5dc18SMarcel Moolenaar * NS16450 or INS8250. We don't bother to differentiate 86727d5dc18SMarcel Moolenaar * between them. They're too old to be interesting. 86827d5dc18SMarcel Moolenaar */ 86927d5dc18SMarcel Moolenaar uart_setreg(bas, REG_MCR, mcr); 87027d5dc18SMarcel Moolenaar uart_barrier(bas); 8718d1289feSMarcel Moolenaar sc->sc_rxfifosz = sc->sc_txfifosz = 1; 87227d5dc18SMarcel Moolenaar device_set_desc(sc->sc_dev, "8250 or 16450 or compatible"); 87327d5dc18SMarcel Moolenaar return (0); 87427d5dc18SMarcel Moolenaar } 87527d5dc18SMarcel Moolenaar 876b192bae6SRuslan Bukin val = FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST; 877b192bae6SRuslan Bukin #ifdef CPU_XBURST 878b192bae6SRuslan Bukin val |= FCR_UART_ON; 879b192bae6SRuslan Bukin #endif 880b192bae6SRuslan Bukin uart_setreg(bas, REG_FCR, val); 88127d5dc18SMarcel Moolenaar uart_barrier(bas); 88227d5dc18SMarcel Moolenaar 88327d5dc18SMarcel Moolenaar count = 0; 88427d5dc18SMarcel Moolenaar delay = ns8250_delay(bas); 88527d5dc18SMarcel Moolenaar 88627d5dc18SMarcel Moolenaar /* We have FIFOs. Drain the transmitter and receiver. */ 88727d5dc18SMarcel Moolenaar error = ns8250_drain(bas, UART_DRAIN_RECEIVER|UART_DRAIN_TRANSMITTER); 88827d5dc18SMarcel Moolenaar if (error) { 88927d5dc18SMarcel Moolenaar uart_setreg(bas, REG_MCR, mcr); 890b192bae6SRuslan Bukin val = 0; 891b192bae6SRuslan Bukin #ifdef CPU_XBURST 892b192bae6SRuslan Bukin val |= FCR_UART_ON; 893b192bae6SRuslan Bukin #endif 894b192bae6SRuslan Bukin uart_setreg(bas, REG_FCR, val); 89527d5dc18SMarcel Moolenaar uart_barrier(bas); 89627d5dc18SMarcel Moolenaar goto describe; 89727d5dc18SMarcel Moolenaar } 89827d5dc18SMarcel Moolenaar 89927d5dc18SMarcel Moolenaar /* 90027d5dc18SMarcel Moolenaar * We should have a sufficiently clean "pipe" to determine the 90127d5dc18SMarcel Moolenaar * size of the FIFOs. We send as much characters as is reasonable 9026bccea7cSRebecca Cran * and wait for the overflow bit in the LSR register to be 90389eef2deSThomas Moestl * asserted, counting the characters as we send them. Based on 90489eef2deSThomas Moestl * that count we know the FIFO size. 90527d5dc18SMarcel Moolenaar */ 90689eef2deSThomas Moestl do { 90727d5dc18SMarcel Moolenaar uart_setreg(bas, REG_DATA, 0); 90827d5dc18SMarcel Moolenaar uart_barrier(bas); 90927d5dc18SMarcel Moolenaar count++; 91027d5dc18SMarcel Moolenaar 91127d5dc18SMarcel Moolenaar limit = 30; 91289eef2deSThomas Moestl lsr = 0; 91389eef2deSThomas Moestl /* 91489eef2deSThomas Moestl * LSR bits are cleared upon read, so we must accumulate 91589eef2deSThomas Moestl * them to be able to test LSR_OE below. 91689eef2deSThomas Moestl */ 91789eef2deSThomas Moestl while (((lsr |= uart_getreg(bas, REG_LSR)) & LSR_TEMT) == 0 && 91889eef2deSThomas Moestl --limit) 91927d5dc18SMarcel Moolenaar DELAY(delay); 92027d5dc18SMarcel Moolenaar if (limit == 0) { 9214a9a4165SMark Johnston /* See the comment in ns8250_init(). */ 9224a9a4165SMark Johnston ier = uart_getreg(bas, REG_IER) & 0xe0; 92358957d87SBenno Rice uart_setreg(bas, REG_IER, ier); 92427d5dc18SMarcel Moolenaar uart_setreg(bas, REG_MCR, mcr); 925b192bae6SRuslan Bukin val = 0; 926b192bae6SRuslan Bukin #ifdef CPU_XBURST 927b192bae6SRuslan Bukin val |= FCR_UART_ON; 928b192bae6SRuslan Bukin #endif 929b192bae6SRuslan Bukin uart_setreg(bas, REG_FCR, val); 93027d5dc18SMarcel Moolenaar uart_barrier(bas); 93127d5dc18SMarcel Moolenaar count = 0; 93227d5dc18SMarcel Moolenaar goto describe; 93327d5dc18SMarcel Moolenaar } 9346e71b3c3SEd Maste } while ((lsr & LSR_OE) == 0 && count < 260); 93589eef2deSThomas Moestl count--; 93627d5dc18SMarcel Moolenaar 93727d5dc18SMarcel Moolenaar uart_setreg(bas, REG_MCR, mcr); 93827d5dc18SMarcel Moolenaar 93927d5dc18SMarcel Moolenaar /* Reset FIFOs. */ 94027d5dc18SMarcel Moolenaar ns8250_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 94127d5dc18SMarcel Moolenaar 94227d5dc18SMarcel Moolenaar describe: 94389eef2deSThomas Moestl if (count >= 14 && count <= 16) { 94427d5dc18SMarcel Moolenaar sc->sc_rxfifosz = 16; 94527d5dc18SMarcel Moolenaar device_set_desc(sc->sc_dev, "16550 or compatible"); 94689eef2deSThomas Moestl } else if (count >= 28 && count <= 32) { 94727d5dc18SMarcel Moolenaar sc->sc_rxfifosz = 32; 94827d5dc18SMarcel Moolenaar device_set_desc(sc->sc_dev, "16650 or compatible"); 94989eef2deSThomas Moestl } else if (count >= 56 && count <= 64) { 95027d5dc18SMarcel Moolenaar sc->sc_rxfifosz = 64; 95127d5dc18SMarcel Moolenaar device_set_desc(sc->sc_dev, "16750 or compatible"); 95289eef2deSThomas Moestl } else if (count >= 112 && count <= 128) { 95327d5dc18SMarcel Moolenaar sc->sc_rxfifosz = 128; 95427d5dc18SMarcel Moolenaar device_set_desc(sc->sc_dev, "16950 or compatible"); 9556e71b3c3SEd Maste } else if (count >= 224 && count <= 256) { 9566e71b3c3SEd Maste sc->sc_rxfifosz = 256; 9576e71b3c3SEd Maste device_set_desc(sc->sc_dev, "16x50 with 256 byte FIFO"); 95827d5dc18SMarcel Moolenaar } else { 959c21e0da2SMarcel Moolenaar sc->sc_rxfifosz = 16; 96027d5dc18SMarcel Moolenaar device_set_desc(sc->sc_dev, 96127d5dc18SMarcel Moolenaar "Non-standard ns8250 class UART with FIFOs"); 96227d5dc18SMarcel Moolenaar } 96327d5dc18SMarcel Moolenaar 96427d5dc18SMarcel Moolenaar /* 96527d5dc18SMarcel Moolenaar * Force the Tx FIFO size to 16 bytes for now. We don't program the 96627d5dc18SMarcel Moolenaar * Tx trigger. Also, we assume that all data has been sent when the 96727d5dc18SMarcel Moolenaar * interrupt happens. 96827d5dc18SMarcel Moolenaar */ 96927d5dc18SMarcel Moolenaar sc->sc_txfifosz = 16; 97027d5dc18SMarcel Moolenaar 971dc70e792SMarcel Moolenaar #if 0 972dc70e792SMarcel Moolenaar /* 973dc70e792SMarcel Moolenaar * XXX there are some issues related to hardware flow control and 974453130d9SPedro F. Giffuni * it's likely that uart(4) is the cause. This basically needs more 975dc70e792SMarcel Moolenaar * investigation, but we avoid using for hardware flow control 976dc70e792SMarcel Moolenaar * until then. 977dc70e792SMarcel Moolenaar */ 97884c7b427SMarcel Moolenaar /* 16650s or higher have automatic flow control. */ 97984c7b427SMarcel Moolenaar if (sc->sc_rxfifosz > 16) { 98084c7b427SMarcel Moolenaar sc->sc_hwiflow = 1; 98184c7b427SMarcel Moolenaar sc->sc_hwoflow = 1; 98284c7b427SMarcel Moolenaar } 983dc70e792SMarcel Moolenaar #endif 98484c7b427SMarcel Moolenaar 98527d5dc18SMarcel Moolenaar return (0); 98627d5dc18SMarcel Moolenaar } 98727d5dc18SMarcel Moolenaar 988167cb33fSIan Lepore int 98927d5dc18SMarcel Moolenaar ns8250_bus_receive(struct uart_softc *sc) 99027d5dc18SMarcel Moolenaar { 99127d5dc18SMarcel Moolenaar struct uart_bas *bas; 99227d5dc18SMarcel Moolenaar int xc; 99327d5dc18SMarcel Moolenaar uint8_t lsr; 99427d5dc18SMarcel Moolenaar 99527d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 9968af03381SMarcel Moolenaar uart_lock(sc->sc_hwmtx); 99727d5dc18SMarcel Moolenaar lsr = uart_getreg(bas, REG_LSR); 99844ed791bSMarcel Moolenaar while (lsr & LSR_RXRDY) { 99944ed791bSMarcel Moolenaar if (uart_rx_full(sc)) { 100044ed791bSMarcel Moolenaar sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; 100127d5dc18SMarcel Moolenaar break; 100244ed791bSMarcel Moolenaar } 100327d5dc18SMarcel Moolenaar xc = uart_getreg(bas, REG_DATA); 100427d5dc18SMarcel Moolenaar if (lsr & LSR_FE) 100527d5dc18SMarcel Moolenaar xc |= UART_STAT_FRAMERR; 100627d5dc18SMarcel Moolenaar if (lsr & LSR_PE) 100727d5dc18SMarcel Moolenaar xc |= UART_STAT_PARERR; 100827d5dc18SMarcel Moolenaar uart_rx_put(sc, xc); 100944ed791bSMarcel Moolenaar lsr = uart_getreg(bas, REG_LSR); 101044ed791bSMarcel Moolenaar } 101144ed791bSMarcel Moolenaar /* Discard everything left in the Rx FIFO. */ 101244ed791bSMarcel Moolenaar while (lsr & LSR_RXRDY) { 101344ed791bSMarcel Moolenaar (void)uart_getreg(bas, REG_DATA); 101444ed791bSMarcel Moolenaar uart_barrier(bas); 101544ed791bSMarcel Moolenaar lsr = uart_getreg(bas, REG_LSR); 101627d5dc18SMarcel Moolenaar } 10178af03381SMarcel Moolenaar uart_unlock(sc->sc_hwmtx); 101827d5dc18SMarcel Moolenaar return (0); 101927d5dc18SMarcel Moolenaar } 102027d5dc18SMarcel Moolenaar 1021167cb33fSIan Lepore int 102227d5dc18SMarcel Moolenaar ns8250_bus_setsig(struct uart_softc *sc, int sig) 102327d5dc18SMarcel Moolenaar { 102427d5dc18SMarcel Moolenaar struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 102527d5dc18SMarcel Moolenaar struct uart_bas *bas; 102627d5dc18SMarcel Moolenaar uint32_t new, old; 102727d5dc18SMarcel Moolenaar 102827d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 102927d5dc18SMarcel Moolenaar do { 103027d5dc18SMarcel Moolenaar old = sc->sc_hwsig; 103127d5dc18SMarcel Moolenaar new = old; 103228710806SPoul-Henning Kamp if (sig & SER_DDTR) { 1033fdfbb3f5SIan Lepore new = (new & ~SER_DTR) | (sig & (SER_DTR | SER_DDTR)); 103427d5dc18SMarcel Moolenaar } 103528710806SPoul-Henning Kamp if (sig & SER_DRTS) { 1036fdfbb3f5SIan Lepore new = (new & ~SER_RTS) | (sig & (SER_RTS | SER_DRTS)); 103727d5dc18SMarcel Moolenaar } 103827d5dc18SMarcel Moolenaar } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 10398af03381SMarcel Moolenaar uart_lock(sc->sc_hwmtx); 104027d5dc18SMarcel Moolenaar ns8250->mcr &= ~(MCR_DTR|MCR_RTS); 104128710806SPoul-Henning Kamp if (new & SER_DTR) 104227d5dc18SMarcel Moolenaar ns8250->mcr |= MCR_DTR; 104328710806SPoul-Henning Kamp if (new & SER_RTS) 104427d5dc18SMarcel Moolenaar ns8250->mcr |= MCR_RTS; 104527d5dc18SMarcel Moolenaar uart_setreg(bas, REG_MCR, ns8250->mcr); 104627d5dc18SMarcel Moolenaar uart_barrier(bas); 10478af03381SMarcel Moolenaar uart_unlock(sc->sc_hwmtx); 104827d5dc18SMarcel Moolenaar return (0); 104927d5dc18SMarcel Moolenaar } 105027d5dc18SMarcel Moolenaar 1051167cb33fSIan Lepore int 105227d5dc18SMarcel Moolenaar ns8250_bus_transmit(struct uart_softc *sc) 105327d5dc18SMarcel Moolenaar { 105427d5dc18SMarcel Moolenaar struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 105527d5dc18SMarcel Moolenaar struct uart_bas *bas; 105627d5dc18SMarcel Moolenaar int i; 105727d5dc18SMarcel Moolenaar 105827d5dc18SMarcel Moolenaar bas = &sc->sc_bas; 10598af03381SMarcel Moolenaar uart_lock(sc->sc_hwmtx); 106027d5dc18SMarcel Moolenaar while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0) 10614e352a45SAlexander Motin DELAY(4); 106227d5dc18SMarcel Moolenaar for (i = 0; i < sc->sc_txdatasz; i++) { 106327d5dc18SMarcel Moolenaar uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]); 106427d5dc18SMarcel Moolenaar uart_barrier(bas); 106527d5dc18SMarcel Moolenaar } 10667e7f7beeSMitchell Horne if (!broken_txfifo) 10677e7f7beeSMitchell Horne ns8250->ier |= IER_ETXRDY; 10687e7f7beeSMitchell Horne uart_setreg(bas, REG_IER, ns8250->ier); 10693c7b9077SMichal Meloun uart_barrier(bas); 10701c60b24bSColin Percival if (broken_txfifo) 10711c60b24bSColin Percival ns8250_drain(bas, UART_DRAIN_TRANSMITTER); 10721c60b24bSColin Percival else 107327d5dc18SMarcel Moolenaar sc->sc_txbusy = 1; 10748af03381SMarcel Moolenaar uart_unlock(sc->sc_hwmtx); 10751c60b24bSColin Percival if (broken_txfifo) 10761c60b24bSColin Percival uart_sched_softih(sc, SER_INT_TXIDLE); 107727d5dc18SMarcel Moolenaar return (0); 107827d5dc18SMarcel Moolenaar } 1079d76a1ef4SWarner Losh 1080d76a1ef4SWarner Losh void 1081d76a1ef4SWarner Losh ns8250_bus_grab(struct uart_softc *sc) 1082d76a1ef4SWarner Losh { 1083d76a1ef4SWarner Losh struct uart_bas *bas = &sc->sc_bas; 1084caf6d6b4SOlivier Houchard struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 10858bc9a079SOlivier Houchard u_char ier; 1086d76a1ef4SWarner Losh 1087d76a1ef4SWarner Losh /* 1088d76a1ef4SWarner Losh * turn off all interrupts to enter polling mode. Leave the 1089d76a1ef4SWarner Losh * saved mask alone. We'll restore whatever it was in ungrab. 1090453130d9SPedro F. Giffuni * All pending interrupt signals are reset when IER is set to 0. 1091d76a1ef4SWarner Losh */ 1092d76a1ef4SWarner Losh uart_lock(sc->sc_hwmtx); 10938bc9a079SOlivier Houchard ier = uart_getreg(bas, REG_IER); 10948bc9a079SOlivier Houchard uart_setreg(bas, REG_IER, ier & ns8250->ier_mask); 1095d76a1ef4SWarner Losh uart_barrier(bas); 1096d76a1ef4SWarner Losh uart_unlock(sc->sc_hwmtx); 1097d76a1ef4SWarner Losh } 1098d76a1ef4SWarner Losh 1099d76a1ef4SWarner Losh void 1100d76a1ef4SWarner Losh ns8250_bus_ungrab(struct uart_softc *sc) 1101d76a1ef4SWarner Losh { 1102d76a1ef4SWarner Losh struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 1103d76a1ef4SWarner Losh struct uart_bas *bas = &sc->sc_bas; 1104d76a1ef4SWarner Losh 1105d76a1ef4SWarner Losh /* 1106d76a1ef4SWarner Losh * Restore previous interrupt mask 1107d76a1ef4SWarner Losh */ 1108d76a1ef4SWarner Losh uart_lock(sc->sc_hwmtx); 1109d76a1ef4SWarner Losh uart_setreg(bas, REG_IER, ns8250->ier); 1110d76a1ef4SWarner Losh uart_barrier(bas); 1111d76a1ef4SWarner Losh uart_unlock(sc->sc_hwmtx); 1112d76a1ef4SWarner Losh } 1113