1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2003 Marcel Moolenaar 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include "opt_acpi.h" 30 #include "opt_platform.h" 31 #include "opt_uart.h" 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 #include <sys/conf.h> 37 #include <sys/kernel.h> 38 #include <sys/sysctl.h> 39 #include <machine/bus.h> 40 41 #ifdef FDT 42 #include <dev/fdt/fdt_common.h> 43 #include <dev/ofw/ofw_bus.h> 44 #include <dev/ofw/ofw_bus_subr.h> 45 #endif 46 47 #include <dev/uart/uart.h> 48 #include <dev/uart/uart_cpu.h> 49 #ifdef FDT 50 #include <dev/uart/uart_cpu_fdt.h> 51 #endif 52 #include <dev/uart/uart_bus.h> 53 #include <dev/uart/uart_dev_ns8250.h> 54 #include <dev/uart/uart_ppstypes.h> 55 #ifdef DEV_ACPI 56 #include <dev/uart/uart_cpu_acpi.h> 57 #include <contrib/dev/acpica/include/acpi.h> 58 #endif 59 60 #include <dev/ic/ns16550.h> 61 62 #include "uart_if.h" 63 64 #define DEFAULT_RCLK 1843200 65 66 /* 67 * Set the default baudrate tolerance to 3.0%. 68 * 69 * Some embedded boards have odd reference clocks (eg 25MHz) 70 * and we need to handle higher variances in the target baud rate. 71 */ 72 #ifndef UART_DEV_TOLERANCE_PCT 73 #define UART_DEV_TOLERANCE_PCT 30 74 #endif /* UART_DEV_TOLERANCE_PCT */ 75 76 static int broken_txfifo = 0; 77 SYSCTL_INT(_hw, OID_AUTO, broken_txfifo, CTLFLAG_RWTUN, 78 &broken_txfifo, 0, "UART FIFO has QEMU emulation bug"); 79 80 /* 81 * To use early printf on x86, add the following to your kernel config: 82 * 83 * options UART_NS8250_EARLY_PORT=0x3f8 84 * options EARLY_PRINTF 85 */ 86 #if defined(EARLY_PRINTF) && (defined(__amd64__) || defined(__i386__)) 87 static void 88 uart_ns8250_early_putc(int c) 89 { 90 u_int stat = UART_NS8250_EARLY_PORT + REG_LSR; 91 u_int tx = UART_NS8250_EARLY_PORT + REG_DATA; 92 int limit = 10000; /* 10ms is plenty of time */ 93 94 while ((inb(stat) & LSR_THRE) == 0 && --limit > 0) 95 continue; 96 outb(tx, c); 97 } 98 early_putc_t *early_putc = uart_ns8250_early_putc; 99 #endif /* EARLY_PRINTF */ 100 101 /* 102 * Clear pending interrupts. THRE is cleared by reading IIR. Data 103 * that may have been received gets lost here. 104 */ 105 static void 106 ns8250_clrint(struct uart_bas *bas) 107 { 108 uint8_t iir, lsr; 109 110 iir = uart_getreg(bas, REG_IIR); 111 while ((iir & IIR_NOPEND) == 0) { 112 iir &= IIR_IMASK; 113 if (iir == IIR_RLS) { 114 lsr = uart_getreg(bas, REG_LSR); 115 if (lsr & (LSR_BI|LSR_FE|LSR_PE)) 116 (void)uart_getreg(bas, REG_DATA); 117 } else if (iir == IIR_RXRDY || iir == IIR_RXTOUT) 118 (void)uart_getreg(bas, REG_DATA); 119 else if (iir == IIR_MLSC) 120 (void)uart_getreg(bas, REG_MSR); 121 uart_barrier(bas); 122 iir = uart_getreg(bas, REG_IIR); 123 } 124 } 125 126 static int 127 ns8250_delay(struct uart_bas *bas) 128 { 129 int divisor; 130 u_char lcr; 131 132 lcr = uart_getreg(bas, REG_LCR); 133 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 134 uart_barrier(bas); 135 divisor = uart_getreg(bas, REG_DLL) | (uart_getreg(bas, REG_DLH) << 8); 136 uart_barrier(bas); 137 uart_setreg(bas, REG_LCR, lcr); 138 uart_barrier(bas); 139 140 /* 1/10th the time to transmit 1 character (estimate). */ 141 if (divisor <= 134) 142 return (16000000 * divisor / bas->rclk); 143 return (16000 * divisor / (bas->rclk / 1000)); 144 } 145 146 static int 147 ns8250_divisor(int rclk, int baudrate) 148 { 149 int actual_baud, divisor; 150 int error; 151 152 if (baudrate == 0) 153 return (0); 154 155 divisor = (rclk / (baudrate << 3) + 1) >> 1; 156 if (divisor == 0 || divisor >= 65536) 157 return (0); 158 actual_baud = rclk / (divisor << 4); 159 160 /* 10 times error in percent: */ 161 error = ((actual_baud - baudrate) * 2000 / baudrate + 1) / 2; 162 163 /* enforce maximum error tolerance: */ 164 if (error < -UART_DEV_TOLERANCE_PCT || error > UART_DEV_TOLERANCE_PCT) 165 return (0); 166 167 return (divisor); 168 } 169 170 static int 171 ns8250_drain(struct uart_bas *bas, int what) 172 { 173 int delay, limit; 174 175 delay = ns8250_delay(bas); 176 177 if (what & UART_DRAIN_TRANSMITTER) { 178 /* 179 * Pick an arbitrary high limit to avoid getting stuck in 180 * an infinite loop when the hardware is broken. Make the 181 * limit high enough to handle large FIFOs. 182 */ 183 limit = 10*1024; 184 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) 185 DELAY(delay); 186 if (limit == 0) { 187 /* printf("ns8250: transmitter appears stuck... "); */ 188 return (EIO); 189 } 190 } 191 192 if (what & UART_DRAIN_RECEIVER) { 193 /* 194 * Pick an arbitrary high limit to avoid getting stuck in 195 * an infinite loop when the hardware is broken. Make the 196 * limit high enough to handle large FIFOs and integrated 197 * UARTs. The HP rx2600 for example has 3 UARTs on the 198 * management board that tend to get a lot of data send 199 * to it when the UART is first activated. Assume that we 200 * have finished draining if LSR_RXRDY is not asserted both 201 * prior to and after a DELAY; but as long as LSR_RXRDY is 202 * asserted, read (and discard) characters as quickly as 203 * possible. 204 */ 205 limit=10*4096; 206 while (limit && (uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) { 207 do { 208 (void)uart_getreg(bas, REG_DATA); 209 uart_barrier(bas); 210 } while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit); 211 uart_barrier(bas); 212 DELAY(delay << 2); 213 } 214 if (limit == 0) { 215 /* printf("ns8250: receiver appears broken... "); */ 216 return (EIO); 217 } 218 } 219 220 return (0); 221 } 222 223 /* 224 * We can only flush UARTs with FIFOs. UARTs without FIFOs should be 225 * drained. WARNING: this function clobbers the FIFO setting! 226 */ 227 static void 228 ns8250_flush(struct uart_bas *bas, int what) 229 { 230 uint8_t fcr; 231 uint8_t lsr; 232 int drain = 0; 233 234 fcr = FCR_ENABLE; 235 if (what & UART_FLUSH_TRANSMITTER) 236 fcr |= FCR_XMT_RST; 237 if (what & UART_FLUSH_RECEIVER) 238 fcr |= FCR_RCV_RST; 239 uart_setreg(bas, REG_FCR, fcr); 240 uart_barrier(bas); 241 242 /* 243 * Detect and work around emulated UARTs which don't implement the 244 * FCR register; on these systems we need to drain the FIFO since 245 * the flush we request doesn't happen. One such system is the 246 * Firecracker VMM, aka. the rust-vmm/vm-superio emulation code: 247 * https://github.com/rust-vmm/vm-superio/issues/83 248 */ 249 lsr = uart_getreg(bas, REG_LSR); 250 if (((lsr & LSR_TEMT) == 0) && (what & UART_FLUSH_TRANSMITTER)) 251 drain |= UART_DRAIN_TRANSMITTER; 252 if ((lsr & LSR_RXRDY) && (what & UART_FLUSH_RECEIVER)) 253 drain |= UART_DRAIN_RECEIVER; 254 if (drain != 0) { 255 printf("ns8250: UART FCR is broken\n"); 256 ns8250_drain(bas, drain); 257 } 258 } 259 260 static int 261 ns8250_param(struct uart_bas *bas, int baudrate, int databits, int stopbits, 262 int parity) 263 { 264 int divisor; 265 uint8_t lcr; 266 267 /* Don't change settings when running on Hyper-V */ 268 if (vm_guest == VM_GUEST_HV) 269 return (0); 270 271 lcr = 0; 272 if (databits >= 8) 273 lcr |= LCR_8BITS; 274 else if (databits == 7) 275 lcr |= LCR_7BITS; 276 else if (databits == 6) 277 lcr |= LCR_6BITS; 278 else 279 lcr |= LCR_5BITS; 280 if (stopbits > 1) 281 lcr |= LCR_STOPB; 282 lcr |= parity << 3; 283 284 /* Set baudrate. */ 285 if (baudrate > 0) { 286 divisor = ns8250_divisor(bas->rclk, baudrate); 287 if (divisor == 0) 288 return (EINVAL); 289 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 290 uart_barrier(bas); 291 uart_setreg(bas, REG_DLL, divisor & 0xff); 292 uart_setreg(bas, REG_DLH, (divisor >> 8) & 0xff); 293 uart_barrier(bas); 294 } 295 296 /* Set LCR and clear DLAB. */ 297 uart_setreg(bas, REG_LCR, lcr); 298 uart_barrier(bas); 299 return (0); 300 } 301 302 /* 303 * Low-level UART interface. 304 */ 305 static int ns8250_probe(struct uart_bas *bas); 306 static void ns8250_init(struct uart_bas *bas, int, int, int, int); 307 static void ns8250_term(struct uart_bas *bas); 308 static void ns8250_putc(struct uart_bas *bas, int); 309 static int ns8250_rxready(struct uart_bas *bas); 310 static int ns8250_getc(struct uart_bas *bas, struct mtx *); 311 312 struct uart_ops uart_ns8250_ops = { 313 .probe = ns8250_probe, 314 .init = ns8250_init, 315 .term = ns8250_term, 316 .putc = ns8250_putc, 317 .rxready = ns8250_rxready, 318 .getc = ns8250_getc, 319 }; 320 321 static int 322 ns8250_probe(struct uart_bas *bas) 323 { 324 u_char val; 325 326 /* Check known 0 bits that don't depend on DLAB. */ 327 val = uart_getreg(bas, REG_IIR); 328 if (val & 0x30) 329 return (ENXIO); 330 /* 331 * Bit 6 of the MCR (= 0x40) appears to be 1 for the Sun1699 332 * chip, but otherwise doesn't seem to have a function. In 333 * other words, uart(4) works regardless. Ignore that bit so 334 * the probe succeeds. 335 */ 336 val = uart_getreg(bas, REG_MCR); 337 if (val & 0xa0) 338 return (ENXIO); 339 340 return (0); 341 } 342 343 static void 344 ns8250_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, 345 int parity) 346 { 347 u_char ier; 348 349 if (bas->rclk == 0) 350 bas->rclk = DEFAULT_RCLK; 351 ns8250_param(bas, baudrate, databits, stopbits, parity); 352 353 /* Disable all interrupt sources. */ 354 /* 355 * We use 0xe0 instead of 0xf0 as the mask because the XScale PXA 356 * UARTs split the receive time-out interrupt bit out separately as 357 * 0x10. This gets handled by ier_mask and ier_rxbits below. 358 */ 359 ier = uart_getreg(bas, REG_IER) & 0xe0; 360 uart_setreg(bas, REG_IER, ier); 361 uart_barrier(bas); 362 363 /* Disable the FIFO (if present). */ 364 uart_setreg(bas, REG_FCR, 0); 365 uart_barrier(bas); 366 367 /* Set RTS & DTR. */ 368 uart_setreg(bas, REG_MCR, MCR_IE | MCR_RTS | MCR_DTR); 369 uart_barrier(bas); 370 371 ns8250_clrint(bas); 372 } 373 374 static void 375 ns8250_term(struct uart_bas *bas) 376 { 377 378 /* Clear RTS & DTR. */ 379 uart_setreg(bas, REG_MCR, MCR_IE); 380 uart_barrier(bas); 381 } 382 383 static void 384 ns8250_putc(struct uart_bas *bas, int c) 385 { 386 int limit; 387 388 if (vm_guest != VM_GUEST_HV) { 389 limit = 250000; 390 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0 && --limit) 391 DELAY(4); 392 } 393 uart_setreg(bas, REG_DATA, c); 394 uart_barrier(bas); 395 } 396 397 static int 398 ns8250_rxready(struct uart_bas *bas) 399 { 400 401 return ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) != 0 ? 1 : 0); 402 } 403 404 static int 405 ns8250_getc(struct uart_bas *bas, struct mtx *hwmtx) 406 { 407 int c; 408 409 uart_lock(hwmtx); 410 411 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0) { 412 uart_unlock(hwmtx); 413 DELAY(4); 414 uart_lock(hwmtx); 415 } 416 417 c = uart_getreg(bas, REG_DATA); 418 419 uart_unlock(hwmtx); 420 421 return (c); 422 } 423 424 static kobj_method_t ns8250_methods[] = { 425 KOBJMETHOD(uart_attach, ns8250_bus_attach), 426 KOBJMETHOD(uart_detach, ns8250_bus_detach), 427 KOBJMETHOD(uart_flush, ns8250_bus_flush), 428 KOBJMETHOD(uart_getsig, ns8250_bus_getsig), 429 KOBJMETHOD(uart_ioctl, ns8250_bus_ioctl), 430 KOBJMETHOD(uart_ipend, ns8250_bus_ipend), 431 KOBJMETHOD(uart_param, ns8250_bus_param), 432 KOBJMETHOD(uart_probe, ns8250_bus_probe), 433 KOBJMETHOD(uart_receive, ns8250_bus_receive), 434 KOBJMETHOD(uart_setsig, ns8250_bus_setsig), 435 KOBJMETHOD(uart_transmit, ns8250_bus_transmit), 436 KOBJMETHOD(uart_grab, ns8250_bus_grab), 437 KOBJMETHOD(uart_ungrab, ns8250_bus_ungrab), 438 { 0, 0 } 439 }; 440 441 struct uart_class uart_ns8250_class = { 442 "ns8250", 443 ns8250_methods, 444 sizeof(struct ns8250_softc), 445 .uc_ops = &uart_ns8250_ops, 446 .uc_range = 8, 447 .uc_rclk = DEFAULT_RCLK, 448 .uc_rshift = 0 449 }; 450 451 /* 452 * XXX -- refactor out ACPI and FDT ifdefs 453 */ 454 #ifdef DEV_ACPI 455 static struct acpi_uart_compat_data acpi_compat_data[] = { 456 {"AMD0020", &uart_ns8250_class, 0, 2, 0, 48000000, UART_F_BUSY_DETECT, "AMD / Synopsys Designware UART"}, 457 {"AMDI0020", &uart_ns8250_class, 0, 2, 0, 48000000, UART_F_BUSY_DETECT, "AMD / Synopsys Designware UART"}, 458 {"MRVL0001", &uart_ns8250_class, ACPI_DBG2_16550_SUBSET, 2, 0, 200000000, UART_F_BUSY_DETECT, "Marvell / Synopsys Designware UART"}, 459 {"SCX0006", &uart_ns8250_class, 0, 2, 0, 62500000, UART_F_BUSY_DETECT, "SynQuacer / Synopsys Designware UART"}, 460 {"HISI0031", &uart_ns8250_class, 0, 2, 0, 200000000, UART_F_BUSY_DETECT, "HiSilicon / Synopsys Designware UART"}, 461 {"NXP0018", &uart_ns8250_class, 0, 0, 0, 350000000, UART_F_BUSY_DETECT, "NXP / Synopsys Designware UART"}, 462 {"PNP0500", &uart_ns8250_class, 0, 0, 0, 0, 0, "Standard PC COM port"}, 463 {"PNP0501", &uart_ns8250_class, 0, 0, 0, 0, 0, "16550A-compatible COM port"}, 464 {"PNP0502", &uart_ns8250_class, 0, 0, 0, 0, 0, "Multiport serial device (non-intelligent 16550)"}, 465 {"PNP0510", &uart_ns8250_class, 0, 0, 0, 0, 0, "Generic IRDA-compatible device"}, 466 {"PNP0511", &uart_ns8250_class, 0, 0, 0, 0, 0, "Generic IRDA-compatible device"}, 467 {"WACF004", &uart_ns8250_class, 0, 0, 0, 0, 0, "Wacom Tablet PC Screen"}, 468 {"WACF00E", &uart_ns8250_class, 0, 0, 0, 0, 0, "Wacom Tablet PC Screen 00e"}, 469 {"FUJ02E5", &uart_ns8250_class, 0, 0, 0, 0, 0, "Wacom Tablet at FuS Lifebook T"}, 470 {NULL, NULL, 0, 0 , 0, 0, 0, NULL}, 471 }; 472 UART_ACPI_CLASS_AND_DEVICE(acpi_compat_data); 473 #endif 474 475 #ifdef FDT 476 static struct ofw_compat_data compat_data[] = { 477 {"ns16550", (uintptr_t)&uart_ns8250_class}, 478 {"ns16550a", (uintptr_t)&uart_ns8250_class}, 479 {NULL, (uintptr_t)NULL}, 480 }; 481 UART_FDT_CLASS_AND_DEVICE(compat_data); 482 #endif 483 484 /* Use token-pasting to form SER_ and MSR_ named constants. */ 485 #define SER(sig) SER_##sig 486 #define SERD(sig) SER_D##sig 487 #define MSR(sig) MSR_##sig 488 #define MSRD(sig) MSR_D##sig 489 490 /* 491 * Detect signal changes using software delta detection. The previous state of 492 * the signals is in 'var' the new hardware state is in 'msr', and 'sig' is the 493 * short name (DCD, CTS, etc) of the signal bit being processed; 'var' gets the 494 * new state of both the signal and the delta bits. 495 */ 496 #define SIGCHGSW(var, msr, sig) \ 497 if ((msr) & MSR(sig)) { \ 498 if ((var & SER(sig)) == 0) \ 499 var |= SERD(sig) | SER(sig); \ 500 } else { \ 501 if ((var & SER(sig)) != 0) \ 502 var = SERD(sig) | (var & ~SER(sig)); \ 503 } 504 505 /* 506 * Detect signal changes using the hardware msr delta bits. This is currently 507 * used only when PPS timing information is being captured using the "narrow 508 * pulse" option. With a narrow PPS pulse the signal may not still be asserted 509 * by time the interrupt handler is invoked. The hardware will latch the fact 510 * that it changed in the delta bits. 511 */ 512 #define SIGCHGHW(var, msr, sig) \ 513 if ((msr) & MSRD(sig)) { \ 514 if (((msr) & MSR(sig)) != 0) \ 515 var |= SERD(sig) | SER(sig); \ 516 else \ 517 var = SERD(sig) | (var & ~SER(sig)); \ 518 } 519 520 int 521 ns8250_bus_attach(struct uart_softc *sc) 522 { 523 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 524 struct uart_bas *bas; 525 unsigned int ivar; 526 #ifdef FDT 527 phandle_t node; 528 pcell_t cell; 529 #endif 530 531 #ifdef FDT 532 /* Check whether uart has a broken txfifo. */ 533 node = ofw_bus_get_node(sc->sc_dev); 534 if ((OF_getencprop(node, "broken-txfifo", &cell, sizeof(cell))) > 0) 535 broken_txfifo = cell ? 1 : 0; 536 #endif 537 538 bas = &sc->sc_bas; 539 540 ns8250->busy_detect = bas->busy_detect; 541 ns8250->mcr = uart_getreg(bas, REG_MCR); 542 ns8250->fcr = FCR_ENABLE; 543 if (!resource_int_value("uart", device_get_unit(sc->sc_dev), "flags", 544 &ivar)) { 545 if (UART_FLAGS_FCR_RX_LOW(ivar)) 546 ns8250->fcr |= FCR_RX_LOW; 547 else if (UART_FLAGS_FCR_RX_MEDL(ivar)) 548 ns8250->fcr |= FCR_RX_MEDL; 549 else if (UART_FLAGS_FCR_RX_HIGH(ivar)) 550 ns8250->fcr |= FCR_RX_HIGH; 551 else 552 ns8250->fcr |= FCR_RX_MEDH; 553 } else 554 ns8250->fcr |= FCR_RX_MEDH; 555 556 /* Get IER mask */ 557 ivar = 0xf0; 558 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_mask", 559 &ivar); 560 ns8250->ier_mask = (uint8_t)(ivar & 0xff); 561 562 /* Get IER RX interrupt bits */ 563 ivar = IER_EMSC | IER_ERLS | IER_ERXRDY; 564 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_rxbits", 565 &ivar); 566 ns8250->ier_rxbits = (uint8_t)(ivar & 0xff); 567 568 uart_setreg(bas, REG_FCR, ns8250->fcr); 569 uart_barrier(bas); 570 ns8250_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 571 572 if (ns8250->mcr & MCR_DTR) 573 sc->sc_hwsig |= SER_DTR; 574 if (ns8250->mcr & MCR_RTS) 575 sc->sc_hwsig |= SER_RTS; 576 ns8250_bus_getsig(sc); 577 578 ns8250_clrint(bas); 579 ns8250->ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 580 ns8250->ier |= ns8250->ier_rxbits; 581 uart_setreg(bas, REG_IER, ns8250->ier); 582 uart_barrier(bas); 583 584 /* 585 * Timing of the H/W access was changed with r253161 of uart_core.c 586 * It has been observed that an ITE IT8513E would signal a break 587 * condition with pretty much every character it received, unless 588 * it had enough time to settle between ns8250_bus_attach() and 589 * ns8250_bus_ipend() -- which it accidentally had before r253161. 590 * It's not understood why the UART chip behaves this way and it 591 * could very well be that the DELAY make the H/W work in the same 592 * accidental manner as before. More analysis is warranted, but 593 * at least now we fixed a known regression. 594 */ 595 DELAY(200); 596 return (0); 597 } 598 599 int 600 ns8250_bus_detach(struct uart_softc *sc) 601 { 602 struct ns8250_softc *ns8250; 603 struct uart_bas *bas; 604 u_char ier; 605 606 ns8250 = (struct ns8250_softc *)sc; 607 bas = &sc->sc_bas; 608 ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 609 uart_setreg(bas, REG_IER, ier); 610 uart_barrier(bas); 611 ns8250_clrint(bas); 612 return (0); 613 } 614 615 int 616 ns8250_bus_flush(struct uart_softc *sc, int what) 617 { 618 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 619 struct uart_bas *bas; 620 int error; 621 622 bas = &sc->sc_bas; 623 uart_lock(sc->sc_hwmtx); 624 if (sc->sc_rxfifosz > 1) { 625 ns8250_flush(bas, what); 626 uart_setreg(bas, REG_FCR, ns8250->fcr); 627 uart_barrier(bas); 628 error = 0; 629 } else 630 error = ns8250_drain(bas, what); 631 uart_unlock(sc->sc_hwmtx); 632 return (error); 633 } 634 635 int 636 ns8250_bus_getsig(struct uart_softc *sc) 637 { 638 uint32_t old, sig; 639 uint8_t msr; 640 641 /* 642 * The delta bits are reputed to be broken on some hardware, so use 643 * software delta detection by default. Use the hardware delta bits 644 * when capturing PPS pulses which are too narrow for software detection 645 * to see the edges. Hardware delta for RI doesn't work like the 646 * others, so always use software for it. Other threads may be changing 647 * other (non-MSR) bits in sc_hwsig, so loop until it can successfully 648 * update without other changes happening. Note that the SIGCHGxx() 649 * macros carefully preserve the delta bits when we have to loop several 650 * times and a signal transitions between iterations. 651 */ 652 do { 653 old = sc->sc_hwsig; 654 sig = old; 655 uart_lock(sc->sc_hwmtx); 656 msr = uart_getreg(&sc->sc_bas, REG_MSR); 657 uart_unlock(sc->sc_hwmtx); 658 if (sc->sc_pps_mode & UART_PPS_NARROW_PULSE) { 659 SIGCHGHW(sig, msr, DSR); 660 SIGCHGHW(sig, msr, CTS); 661 SIGCHGHW(sig, msr, DCD); 662 } else { 663 SIGCHGSW(sig, msr, DSR); 664 SIGCHGSW(sig, msr, CTS); 665 SIGCHGSW(sig, msr, DCD); 666 } 667 SIGCHGSW(sig, msr, RI); 668 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, sig & ~SER_MASK_DELTA)); 669 return (sig); 670 } 671 672 int 673 ns8250_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) 674 { 675 struct uart_bas *bas; 676 int baudrate, divisor, error; 677 uint8_t efr, lcr; 678 679 bas = &sc->sc_bas; 680 error = 0; 681 uart_lock(sc->sc_hwmtx); 682 switch (request) { 683 case UART_IOCTL_BREAK: 684 lcr = uart_getreg(bas, REG_LCR); 685 if (data) 686 lcr |= LCR_SBREAK; 687 else 688 lcr &= ~LCR_SBREAK; 689 uart_setreg(bas, REG_LCR, lcr); 690 uart_barrier(bas); 691 break; 692 case UART_IOCTL_IFLOW: 693 lcr = uart_getreg(bas, REG_LCR); 694 uart_barrier(bas); 695 uart_setreg(bas, REG_LCR, 0xbf); 696 uart_barrier(bas); 697 efr = uart_getreg(bas, REG_EFR); 698 if (data) 699 efr |= EFR_RTS; 700 else 701 efr &= ~EFR_RTS; 702 uart_setreg(bas, REG_EFR, efr); 703 uart_barrier(bas); 704 uart_setreg(bas, REG_LCR, lcr); 705 uart_barrier(bas); 706 break; 707 case UART_IOCTL_OFLOW: 708 lcr = uart_getreg(bas, REG_LCR); 709 uart_barrier(bas); 710 uart_setreg(bas, REG_LCR, 0xbf); 711 uart_barrier(bas); 712 efr = uart_getreg(bas, REG_EFR); 713 if (data) 714 efr |= EFR_CTS; 715 else 716 efr &= ~EFR_CTS; 717 uart_setreg(bas, REG_EFR, efr); 718 uart_barrier(bas); 719 uart_setreg(bas, REG_LCR, lcr); 720 uart_barrier(bas); 721 break; 722 case UART_IOCTL_BAUD: 723 lcr = uart_getreg(bas, REG_LCR); 724 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 725 uart_barrier(bas); 726 divisor = uart_getreg(bas, REG_DLL) | 727 (uart_getreg(bas, REG_DLH) << 8); 728 uart_barrier(bas); 729 uart_setreg(bas, REG_LCR, lcr); 730 uart_barrier(bas); 731 baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0; 732 if (baudrate > 0) 733 *(int*)data = baudrate; 734 else 735 error = ENXIO; 736 break; 737 default: 738 error = EINVAL; 739 break; 740 } 741 uart_unlock(sc->sc_hwmtx); 742 return (error); 743 } 744 745 int 746 ns8250_bus_ipend(struct uart_softc *sc) 747 { 748 struct uart_bas *bas; 749 struct ns8250_softc *ns8250; 750 int ipend; 751 uint8_t iir, lsr; 752 753 ns8250 = (struct ns8250_softc *)sc; 754 bas = &sc->sc_bas; 755 uart_lock(sc->sc_hwmtx); 756 iir = uart_getreg(bas, REG_IIR); 757 758 if (ns8250->busy_detect && (iir & IIR_BUSY) == IIR_BUSY) { 759 (void)uart_getreg(bas, DW_REG_USR); 760 uart_unlock(sc->sc_hwmtx); 761 return (0); 762 } 763 if (iir & IIR_NOPEND) { 764 uart_unlock(sc->sc_hwmtx); 765 return (0); 766 } 767 ipend = 0; 768 if (iir & IIR_RXRDY) { 769 lsr = uart_getreg(bas, REG_LSR); 770 if (lsr & LSR_OE) 771 ipend |= SER_INT_OVERRUN; 772 if (lsr & LSR_BI) 773 ipend |= SER_INT_BREAK; 774 if (lsr & LSR_RXRDY) 775 ipend |= SER_INT_RXREADY; 776 } else { 777 if (iir & IIR_TXRDY) { 778 ipend |= SER_INT_TXIDLE; 779 ns8250->ier &= ~IER_ETXRDY; 780 uart_setreg(bas, REG_IER, ns8250->ier); 781 uart_barrier(bas); 782 } else 783 ipend |= SER_INT_SIGCHG; 784 } 785 if (ipend == 0) 786 ns8250_clrint(bas); 787 uart_unlock(sc->sc_hwmtx); 788 return (ipend); 789 } 790 791 int 792 ns8250_bus_param(struct uart_softc *sc, int baudrate, int databits, 793 int stopbits, int parity) 794 { 795 struct ns8250_softc *ns8250; 796 struct uart_bas *bas; 797 int error, limit; 798 799 ns8250 = (struct ns8250_softc*)sc; 800 bas = &sc->sc_bas; 801 uart_lock(sc->sc_hwmtx); 802 /* 803 * When using DW UART with BUSY detection it is necessary to wait 804 * until all serial transfers are finished before manipulating the 805 * line control. LCR will not be affected when UART is busy. 806 */ 807 if (ns8250->busy_detect != 0) { 808 /* 809 * Pick an arbitrary high limit to avoid getting stuck in 810 * an infinite loop in case when the hardware is broken. 811 */ 812 limit = 10 * 1024; 813 while (((uart_getreg(bas, DW_REG_USR) & USR_BUSY) != 0) && 814 --limit) 815 DELAY(4); 816 817 if (limit <= 0) { 818 /* UART appears to be stuck */ 819 uart_unlock(sc->sc_hwmtx); 820 return (EIO); 821 } 822 } 823 824 error = ns8250_param(bas, baudrate, databits, stopbits, parity); 825 uart_unlock(sc->sc_hwmtx); 826 return (error); 827 } 828 829 int 830 ns8250_bus_probe(struct uart_softc *sc) 831 { 832 struct uart_bas *bas; 833 int count, delay, error, limit; 834 uint8_t lsr, mcr, ier; 835 836 bas = &sc->sc_bas; 837 838 error = ns8250_probe(bas); 839 if (error) 840 return (error); 841 842 mcr = MCR_IE; 843 if (sc->sc_sysdev == NULL) { 844 /* By using ns8250_init() we also set DTR and RTS. */ 845 ns8250_init(bas, 115200, 8, 1, UART_PARITY_NONE); 846 } else 847 mcr |= MCR_DTR | MCR_RTS; 848 849 error = ns8250_drain(bas, UART_DRAIN_TRANSMITTER); 850 if (error) 851 return (error); 852 853 /* 854 * Set loopback mode. This avoids having garbage on the wire and 855 * also allows us send and receive data. We set DTR and RTS to 856 * avoid the possibility that automatic flow-control prevents 857 * any data from being sent. 858 */ 859 uart_setreg(bas, REG_MCR, MCR_LOOPBACK | MCR_IE | MCR_DTR | MCR_RTS); 860 uart_barrier(bas); 861 862 /* 863 * Enable FIFOs. And check that the UART has them. If not, we're 864 * done. Since this is the first time we enable the FIFOs, we reset 865 * them. 866 */ 867 uart_setreg(bas, REG_FCR, FCR_ENABLE); 868 uart_barrier(bas); 869 if (!(uart_getreg(bas, REG_IIR) & IIR_FIFO_MASK)) { 870 /* 871 * NS16450 or INS8250. We don't bother to differentiate 872 * between them. They're too old to be interesting. 873 */ 874 uart_setreg(bas, REG_MCR, mcr); 875 uart_barrier(bas); 876 sc->sc_rxfifosz = sc->sc_txfifosz = 1; 877 device_set_desc(sc->sc_dev, "8250 or 16450 or compatible"); 878 return (0); 879 } 880 881 uart_setreg(bas, REG_FCR, FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST); 882 uart_barrier(bas); 883 884 count = 0; 885 delay = ns8250_delay(bas); 886 887 /* We have FIFOs. Drain the transmitter and receiver. */ 888 error = ns8250_drain(bas, UART_DRAIN_RECEIVER|UART_DRAIN_TRANSMITTER); 889 if (error) { 890 uart_setreg(bas, REG_MCR, mcr); 891 uart_setreg(bas, REG_FCR, 0); 892 uart_barrier(bas); 893 goto describe; 894 } 895 896 /* 897 * We should have a sufficiently clean "pipe" to determine the 898 * size of the FIFOs. We send as much characters as is reasonable 899 * and wait for the overflow bit in the LSR register to be 900 * asserted, counting the characters as we send them. Based on 901 * that count we know the FIFO size. 902 */ 903 do { 904 uart_setreg(bas, REG_DATA, 0); 905 uart_barrier(bas); 906 count++; 907 908 limit = 30; 909 lsr = 0; 910 /* 911 * LSR bits are cleared upon read, so we must accumulate 912 * them to be able to test LSR_OE below. 913 */ 914 while (((lsr |= uart_getreg(bas, REG_LSR)) & LSR_TEMT) == 0 && 915 --limit) 916 DELAY(delay); 917 if (limit == 0) { 918 /* See the comment in ns8250_init(). */ 919 ier = uart_getreg(bas, REG_IER) & 0xe0; 920 uart_setreg(bas, REG_IER, ier); 921 uart_setreg(bas, REG_MCR, mcr); 922 uart_setreg(bas, REG_FCR, 0); 923 uart_barrier(bas); 924 count = 0; 925 goto describe; 926 } 927 } while ((lsr & LSR_OE) == 0 && count < 260); 928 count--; 929 930 uart_setreg(bas, REG_MCR, mcr); 931 932 /* Reset FIFOs. */ 933 ns8250_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 934 935 describe: 936 if (count >= 14 && count <= 16) { 937 sc->sc_rxfifosz = 16; 938 device_set_desc(sc->sc_dev, "16550 or compatible"); 939 } else if (count >= 28 && count <= 32) { 940 sc->sc_rxfifosz = 32; 941 device_set_desc(sc->sc_dev, "16650 or compatible"); 942 } else if (count >= 56 && count <= 64) { 943 sc->sc_rxfifosz = 64; 944 device_set_desc(sc->sc_dev, "16750 or compatible"); 945 } else if (count >= 112 && count <= 128) { 946 sc->sc_rxfifosz = 128; 947 device_set_desc(sc->sc_dev, "16950 or compatible"); 948 } else if (count >= 224 && count <= 256) { 949 sc->sc_rxfifosz = 256; 950 device_set_desc(sc->sc_dev, "16x50 with 256 byte FIFO"); 951 } else { 952 sc->sc_rxfifosz = 16; 953 device_set_desc(sc->sc_dev, 954 "Non-standard ns8250 class UART with FIFOs"); 955 } 956 957 /* 958 * Force the Tx FIFO size to 16 bytes for now. We don't program the 959 * Tx trigger. Also, we assume that all data has been sent when the 960 * interrupt happens. 961 */ 962 sc->sc_txfifosz = 16; 963 964 #if 0 965 /* 966 * XXX there are some issues related to hardware flow control and 967 * it's likely that uart(4) is the cause. This basically needs more 968 * investigation, but we avoid using for hardware flow control 969 * until then. 970 */ 971 /* 16650s or higher have automatic flow control. */ 972 if (sc->sc_rxfifosz > 16) { 973 sc->sc_hwiflow = 1; 974 sc->sc_hwoflow = 1; 975 } 976 #endif 977 978 return (0); 979 } 980 981 int 982 ns8250_bus_receive(struct uart_softc *sc) 983 { 984 struct uart_bas *bas; 985 int xc; 986 uint8_t lsr; 987 988 bas = &sc->sc_bas; 989 uart_lock(sc->sc_hwmtx); 990 lsr = uart_getreg(bas, REG_LSR); 991 while (lsr & LSR_RXRDY) { 992 if (uart_rx_full(sc)) { 993 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; 994 break; 995 } 996 xc = uart_getreg(bas, REG_DATA); 997 if (lsr & LSR_FE) 998 xc |= UART_STAT_FRAMERR; 999 if (lsr & LSR_PE) 1000 xc |= UART_STAT_PARERR; 1001 uart_rx_put(sc, xc); 1002 lsr = uart_getreg(bas, REG_LSR); 1003 } 1004 /* Discard everything left in the Rx FIFO. */ 1005 while (lsr & LSR_RXRDY) { 1006 (void)uart_getreg(bas, REG_DATA); 1007 uart_barrier(bas); 1008 lsr = uart_getreg(bas, REG_LSR); 1009 } 1010 uart_unlock(sc->sc_hwmtx); 1011 return (0); 1012 } 1013 1014 int 1015 ns8250_bus_setsig(struct uart_softc *sc, int sig) 1016 { 1017 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 1018 struct uart_bas *bas; 1019 uint32_t new, old; 1020 1021 bas = &sc->sc_bas; 1022 do { 1023 old = sc->sc_hwsig; 1024 new = old; 1025 if (sig & SER_DDTR) { 1026 new = (new & ~SER_DTR) | (sig & (SER_DTR | SER_DDTR)); 1027 } 1028 if (sig & SER_DRTS) { 1029 new = (new & ~SER_RTS) | (sig & (SER_RTS | SER_DRTS)); 1030 } 1031 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 1032 uart_lock(sc->sc_hwmtx); 1033 ns8250->mcr &= ~(MCR_DTR|MCR_RTS); 1034 if (new & SER_DTR) 1035 ns8250->mcr |= MCR_DTR; 1036 if (new & SER_RTS) 1037 ns8250->mcr |= MCR_RTS; 1038 uart_setreg(bas, REG_MCR, ns8250->mcr); 1039 uart_barrier(bas); 1040 uart_unlock(sc->sc_hwmtx); 1041 return (0); 1042 } 1043 1044 int 1045 ns8250_bus_transmit(struct uart_softc *sc) 1046 { 1047 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 1048 struct uart_bas *bas; 1049 int i; 1050 1051 bas = &sc->sc_bas; 1052 uart_lock(sc->sc_hwmtx); 1053 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0) 1054 DELAY(4); 1055 for (i = 0; i < sc->sc_txdatasz; i++) { 1056 uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]); 1057 uart_barrier(bas); 1058 } 1059 if (!broken_txfifo) 1060 ns8250->ier |= IER_ETXRDY; 1061 uart_setreg(bas, REG_IER, ns8250->ier); 1062 uart_barrier(bas); 1063 if (broken_txfifo) 1064 ns8250_drain(bas, UART_DRAIN_TRANSMITTER); 1065 else 1066 sc->sc_txbusy = 1; 1067 uart_unlock(sc->sc_hwmtx); 1068 if (broken_txfifo) 1069 uart_sched_softih(sc, SER_INT_TXIDLE); 1070 return (0); 1071 } 1072 1073 void 1074 ns8250_bus_grab(struct uart_softc *sc) 1075 { 1076 struct uart_bas *bas = &sc->sc_bas; 1077 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 1078 u_char ier; 1079 1080 /* 1081 * turn off all interrupts to enter polling mode. Leave the 1082 * saved mask alone. We'll restore whatever it was in ungrab. 1083 * All pending interrupt signals are reset when IER is set to 0. 1084 */ 1085 uart_lock(sc->sc_hwmtx); 1086 ier = uart_getreg(bas, REG_IER); 1087 uart_setreg(bas, REG_IER, ier & ns8250->ier_mask); 1088 uart_barrier(bas); 1089 uart_unlock(sc->sc_hwmtx); 1090 } 1091 1092 void 1093 ns8250_bus_ungrab(struct uart_softc *sc) 1094 { 1095 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 1096 struct uart_bas *bas = &sc->sc_bas; 1097 1098 /* 1099 * Restore previous interrupt mask 1100 */ 1101 uart_lock(sc->sc_hwmtx); 1102 uart_setreg(bas, REG_IER, ns8250->ier); 1103 uart_barrier(bas); 1104 uart_unlock(sc->sc_hwmtx); 1105 } 1106