1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2012 Semihalf. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include "opt_acpi.h" 30 #include "opt_platform.h" 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/kernel.h> 35 #include <sys/bus.h> 36 37 #include <machine/bus.h> 38 #include <machine/machdep.h> 39 40 #include <dev/uart/uart.h> 41 #include <dev/uart/uart_cpu.h> 42 #ifdef FDT 43 #include <dev/uart/uart_cpu_fdt.h> 44 #include <dev/ofw/ofw_bus.h> 45 #endif 46 #include <dev/uart/uart_bus.h> 47 #include "uart_if.h" 48 49 #ifdef DEV_ACPI 50 #include <dev/uart/uart_cpu_acpi.h> 51 #include <contrib/dev/acpica/include/acpi.h> 52 #include <contrib/dev/acpica/include/accommon.h> 53 #include <contrib/dev/acpica/include/actables.h> 54 #endif 55 56 #include <sys/kdb.h> 57 58 #ifdef __aarch64__ 59 #define IS_FDT (arm64_bus_method == ARM64_BUS_FDT) 60 #elif defined(FDT) 61 #define IS_FDT 1 62 #else 63 #error Unsupported configuration 64 #endif 65 66 /* PL011 UART registers and masks*/ 67 #define UART_DR 0x00 /* Data register */ 68 #define DR_FE (1 << 8) /* Framing error */ 69 #define DR_PE (1 << 9) /* Parity error */ 70 #define DR_BE (1 << 10) /* Break error */ 71 #define DR_OE (1 << 11) /* Overrun error */ 72 73 #define UART_FR 0x06 /* Flag register */ 74 #define FR_RXFE (1 << 4) /* Receive FIFO/reg empty */ 75 #define FR_TXFF (1 << 5) /* Transmit FIFO/reg full */ 76 #define FR_RXFF (1 << 6) /* Receive FIFO/reg full */ 77 #define FR_TXFE (1 << 7) /* Transmit FIFO/reg empty */ 78 79 #define UART_IBRD 0x09 /* Integer baud rate register */ 80 #define IBRD_BDIVINT 0xffff /* Significant part of int. divisor value */ 81 82 #define UART_FBRD 0x0a /* Fractional baud rate register */ 83 #define FBRD_BDIVFRAC 0x3f /* Significant part of frac. divisor value */ 84 85 #define UART_LCR_H 0x0b /* Line control register */ 86 #define LCR_H_WLEN8 (0x3 << 5) 87 #define LCR_H_WLEN7 (0x2 << 5) 88 #define LCR_H_WLEN6 (0x1 << 5) 89 #define LCR_H_FEN (1 << 4) /* FIFO mode enable */ 90 #define LCR_H_STP2 (1 << 3) /* 2 stop frames at the end */ 91 #define LCR_H_EPS (1 << 2) /* Even parity select */ 92 #define LCR_H_PEN (1 << 1) /* Parity enable */ 93 94 #define UART_CR 0x0c /* Control register */ 95 #define CR_RXE (1 << 9) /* Receive enable */ 96 #define CR_TXE (1 << 8) /* Transmit enable */ 97 #define CR_UARTEN (1 << 0) /* UART enable */ 98 99 #define UART_IFLS 0x0d /* FIFO level select register */ 100 #define IFLS_RX_SHIFT 3 /* RX level in bits [5:3] */ 101 #define IFLS_TX_SHIFT 0 /* TX level in bits [2:0] */ 102 #define IFLS_MASK 0x07 /* RX/TX level is 3 bits */ 103 #define IFLS_LVL_1_8th 0 /* Interrupt at 1/8 full */ 104 #define IFLS_LVL_2_8th 1 /* Interrupt at 1/4 full */ 105 #define IFLS_LVL_4_8th 2 /* Interrupt at 1/2 full */ 106 #define IFLS_LVL_6_8th 3 /* Interrupt at 3/4 full */ 107 #define IFLS_LVL_7_8th 4 /* Interrupt at 7/8 full */ 108 109 #define UART_IMSC 0x0e /* Interrupt mask set/clear register */ 110 #define IMSC_MASK_ALL 0x7ff /* Mask all interrupts */ 111 112 #define UART_RIS 0x0f /* Raw interrupt status register */ 113 #define UART_RXREADY (1 << 4) /* RX buffer full */ 114 #define UART_TXEMPTY (1 << 5) /* TX buffer empty */ 115 #define RIS_RTIM (1 << 6) /* Receive timeout */ 116 #define RIS_FE (1 << 7) /* Framing error interrupt status */ 117 #define RIS_PE (1 << 8) /* Parity error interrupt status */ 118 #define RIS_BE (1 << 9) /* Break error interrupt status */ 119 #define RIS_OE (1 << 10) /* Overrun interrupt status */ 120 121 #define UART_MIS 0x10 /* Masked interrupt status register */ 122 #define UART_ICR 0x11 /* Interrupt clear register */ 123 124 #define UART_PIDREG_0 0x3f8 /* Peripheral ID register 0 */ 125 #define UART_PIDREG_1 0x3f9 /* Peripheral ID register 1 */ 126 #define UART_PIDREG_2 0x3fa /* Peripheral ID register 2 */ 127 #define UART_PIDREG_3 0x3fb /* Peripheral ID register 3 */ 128 129 /* 130 * The hardware FIFOs are 16 bytes each on rev 2 and earlier hardware, 32 bytes 131 * on rev 3 and later. We configure them to interrupt when 3/4 full/empty. For 132 * RX we set the size to the full hardware capacity so that the uart core 133 * allocates enough buffer space to hold a complete fifo full of incoming data. 134 * For TX, we need to limit the size to the capacity we know will be available 135 * when the interrupt occurs; uart_core will feed exactly that many bytes to 136 * uart_pl011_bus_transmit() which must consume them all. 137 */ 138 #define FIFO_RX_SIZE_R2 16 139 #define FIFO_TX_SIZE_R2 12 140 #define FIFO_RX_SIZE_R3 32 141 #define FIFO_TX_SIZE_R3 24 142 #define FIFO_IFLS_BITS ((IFLS_LVL_6_8th << IFLS_RX_SHIFT) | (IFLS_LVL_2_8th)) 143 144 /* 145 * FIXME: actual register size is SoC-dependent, we need to handle it 146 */ 147 #define __uart_getreg(bas, reg) \ 148 bus_space_read_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg)) 149 #define __uart_setreg(bas, reg, value) \ 150 bus_space_write_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg), value) 151 152 /* 153 * Low-level UART interface. 154 */ 155 static int uart_pl011_probe(struct uart_bas *bas); 156 static void uart_pl011_init(struct uart_bas *bas, int, int, int, int); 157 static void uart_pl011_term(struct uart_bas *bas); 158 static void uart_pl011_putc(struct uart_bas *bas, int); 159 static int uart_pl011_rxready(struct uart_bas *bas); 160 static int uart_pl011_getc(struct uart_bas *bas, struct mtx *); 161 162 static struct uart_ops uart_pl011_ops = { 163 .probe = uart_pl011_probe, 164 .init = uart_pl011_init, 165 .term = uart_pl011_term, 166 .putc = uart_pl011_putc, 167 .rxready = uart_pl011_rxready, 168 .getc = uart_pl011_getc, 169 }; 170 171 static int 172 uart_pl011_probe(struct uart_bas *bas) 173 { 174 175 return (0); 176 } 177 178 static void 179 uart_pl011_param(struct uart_bas *bas, int baudrate, int databits, int stopbits, 180 int parity) 181 { 182 uint32_t ctrl, line; 183 uint32_t baud; 184 185 /* 186 * Zero all settings to make sure 187 * UART is disabled and not configured 188 */ 189 ctrl = line = 0x0; 190 __uart_setreg(bas, UART_CR, ctrl); 191 192 /* As we know UART is disabled we may setup the line */ 193 switch (databits) { 194 case 7: 195 line |= LCR_H_WLEN7; 196 break; 197 case 6: 198 line |= LCR_H_WLEN6; 199 break; 200 case 8: 201 default: 202 line |= LCR_H_WLEN8; 203 break; 204 } 205 206 if (stopbits == 2) 207 line |= LCR_H_STP2; 208 else 209 line &= ~LCR_H_STP2; 210 211 if (parity) 212 line |= LCR_H_PEN; 213 else 214 line &= ~LCR_H_PEN; 215 line |= LCR_H_FEN; 216 217 /* Configure the rest */ 218 ctrl |= (CR_RXE | CR_TXE | CR_UARTEN); 219 220 if (bas->rclk != 0 && baudrate != 0) { 221 baud = bas->rclk * 4 / baudrate; 222 __uart_setreg(bas, UART_IBRD, ((uint32_t)(baud >> 6)) & IBRD_BDIVINT); 223 __uart_setreg(bas, UART_FBRD, (uint32_t)(baud & 0x3F) & FBRD_BDIVFRAC); 224 } 225 226 /* Add config. to line before reenabling UART */ 227 __uart_setreg(bas, UART_LCR_H, (__uart_getreg(bas, UART_LCR_H) & 228 ~0xff) | line); 229 230 /* Set rx and tx fifo levels. */ 231 __uart_setreg(bas, UART_IFLS, FIFO_IFLS_BITS); 232 233 __uart_setreg(bas, UART_CR, ctrl); 234 } 235 236 static void 237 uart_pl011_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, 238 int parity) 239 { 240 /* Mask all interrupts */ 241 __uart_setreg(bas, UART_IMSC, __uart_getreg(bas, UART_IMSC) & 242 ~IMSC_MASK_ALL); 243 244 uart_pl011_param(bas, baudrate, databits, stopbits, parity); 245 } 246 247 static void 248 uart_pl011_term(struct uart_bas *bas) 249 { 250 } 251 252 #if CHECK_EARLY_PRINTF(pl011) 253 static void 254 uart_pl011_early_putc(int c) 255 { 256 volatile uint32_t *fr = (uint32_t *)(socdev_va + UART_FR * 4); 257 volatile uint32_t *dr = (uint32_t *)(socdev_va + UART_DR * 4); 258 259 while ((*fr & FR_TXFF) != 0) 260 ; 261 *dr = c & 0xff; 262 } 263 early_putc_t *early_putc = uart_pl011_early_putc; 264 #endif /* CHECK_EARLY_PRINTF */ 265 266 static void 267 uart_pl011_putc(struct uart_bas *bas, int c) 268 { 269 270 /* Wait when TX FIFO full. Push character otherwise. */ 271 while (__uart_getreg(bas, UART_FR) & FR_TXFF) 272 ; 273 __uart_setreg(bas, UART_DR, c & 0xff); 274 } 275 276 static int 277 uart_pl011_rxready(struct uart_bas *bas) 278 { 279 280 return !(__uart_getreg(bas, UART_FR) & FR_RXFE); 281 } 282 283 static int 284 uart_pl011_getc(struct uart_bas *bas, struct mtx *hwmtx) 285 { 286 int c; 287 288 while (!uart_pl011_rxready(bas)) 289 ; 290 c = __uart_getreg(bas, UART_DR) & 0xff; 291 292 return (c); 293 } 294 295 /* 296 * High-level UART interface. 297 */ 298 struct uart_pl011_softc { 299 struct uart_softc base; 300 uint16_t imsc; /* Interrupt mask */ 301 }; 302 303 static int uart_pl011_bus_attach(struct uart_softc *); 304 static int uart_pl011_bus_detach(struct uart_softc *); 305 static int uart_pl011_bus_flush(struct uart_softc *, int); 306 static int uart_pl011_bus_getsig(struct uart_softc *); 307 static int uart_pl011_bus_ioctl(struct uart_softc *, int, intptr_t); 308 static int uart_pl011_bus_ipend(struct uart_softc *); 309 static int uart_pl011_bus_param(struct uart_softc *, int, int, int, int); 310 static int uart_pl011_bus_probe(struct uart_softc *); 311 static int uart_pl011_bus_receive(struct uart_softc *); 312 static int uart_pl011_bus_setsig(struct uart_softc *, int); 313 static int uart_pl011_bus_transmit(struct uart_softc *); 314 static void uart_pl011_bus_grab(struct uart_softc *); 315 static void uart_pl011_bus_ungrab(struct uart_softc *); 316 317 static kobj_method_t uart_pl011_methods[] = { 318 KOBJMETHOD(uart_attach, uart_pl011_bus_attach), 319 KOBJMETHOD(uart_detach, uart_pl011_bus_detach), 320 KOBJMETHOD(uart_flush, uart_pl011_bus_flush), 321 KOBJMETHOD(uart_getsig, uart_pl011_bus_getsig), 322 KOBJMETHOD(uart_ioctl, uart_pl011_bus_ioctl), 323 KOBJMETHOD(uart_ipend, uart_pl011_bus_ipend), 324 KOBJMETHOD(uart_param, uart_pl011_bus_param), 325 KOBJMETHOD(uart_probe, uart_pl011_bus_probe), 326 KOBJMETHOD(uart_receive, uart_pl011_bus_receive), 327 KOBJMETHOD(uart_setsig, uart_pl011_bus_setsig), 328 KOBJMETHOD(uart_transmit, uart_pl011_bus_transmit), 329 KOBJMETHOD(uart_grab, uart_pl011_bus_grab), 330 KOBJMETHOD(uart_ungrab, uart_pl011_bus_ungrab), 331 { 0, 0 } 332 }; 333 334 static struct uart_class uart_pl011_class = { 335 "pl011", 336 uart_pl011_methods, 337 sizeof(struct uart_pl011_softc), 338 .uc_ops = &uart_pl011_ops, 339 .uc_range = 0x48, 340 .uc_rclk = 0, 341 .uc_rshift = 2 342 }; 343 DATA_SET(uart_class_set, uart_pl011_class); 344 345 #ifdef FDT 346 static struct ofw_compat_data fdt_compat_data[] = { 347 {"arm,pl011", (uintptr_t)&uart_pl011_class}, 348 {NULL, (uintptr_t)NULL}, 349 }; 350 UART_FDT_CLASS_AND_DEVICE(fdt_compat_data); 351 #endif 352 353 #ifdef DEV_ACPI 354 static struct acpi_uart_compat_data acpi_compat_data[] = { 355 {"ARMH0011", &uart_pl011_class, ACPI_DBG2_ARM_PL011, 2, 0, 0, UART_F_IGNORE_SPCR_REGSHFT, "uart pl011"}, 356 {"ARMHB000", &uart_pl011_class, ACPI_DBG2_ARM_SBSA_GENERIC, 2, 0, 0, UART_F_IGNORE_SPCR_REGSHFT, "uart pl011"}, 357 {"ARMHB000", &uart_pl011_class, ACPI_DBG2_ARM_SBSA_32BIT, 2, 0, 0, UART_F_IGNORE_SPCR_REGSHFT, "uart pl011"}, 358 {NULL, NULL, 0, 0, 0, 0, 0, NULL}, 359 }; 360 UART_ACPI_CLASS_AND_DEVICE(acpi_compat_data); 361 #endif 362 363 static int 364 uart_pl011_bus_attach(struct uart_softc *sc) 365 { 366 struct uart_pl011_softc *psc; 367 struct uart_bas *bas; 368 369 psc = (struct uart_pl011_softc *)sc; 370 bas = &sc->sc_bas; 371 372 /* Enable interrupts */ 373 psc->imsc = (UART_RXREADY | RIS_RTIM | UART_TXEMPTY); 374 __uart_setreg(bas, UART_IMSC, psc->imsc); 375 376 /* Clear interrupts */ 377 __uart_setreg(bas, UART_ICR, IMSC_MASK_ALL); 378 379 return (0); 380 } 381 382 static int 383 uart_pl011_bus_detach(struct uart_softc *sc) 384 { 385 386 return (0); 387 } 388 389 static int 390 uart_pl011_bus_flush(struct uart_softc *sc, int what) 391 { 392 393 return (0); 394 } 395 396 static int 397 uart_pl011_bus_getsig(struct uart_softc *sc) 398 { 399 400 return (0); 401 } 402 403 static int 404 uart_pl011_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) 405 { 406 int error; 407 408 error = 0; 409 uart_lock(sc->sc_hwmtx); 410 switch (request) { 411 case UART_IOCTL_BREAK: 412 break; 413 case UART_IOCTL_BAUD: 414 *(int*)data = 115200; 415 break; 416 default: 417 error = EINVAL; 418 break; 419 } 420 uart_unlock(sc->sc_hwmtx); 421 422 return (error); 423 } 424 425 static int 426 uart_pl011_bus_ipend(struct uart_softc *sc) 427 { 428 struct uart_pl011_softc *psc; 429 struct uart_bas *bas; 430 uint32_t ints; 431 int ipend; 432 433 psc = (struct uart_pl011_softc *)sc; 434 bas = &sc->sc_bas; 435 436 uart_lock(sc->sc_hwmtx); 437 ints = __uart_getreg(bas, UART_MIS); 438 ipend = 0; 439 440 if (ints & (UART_RXREADY | RIS_RTIM)) 441 ipend |= SER_INT_RXREADY; 442 if (ints & RIS_BE) 443 ipend |= SER_INT_BREAK; 444 if (ints & RIS_OE) 445 ipend |= SER_INT_OVERRUN; 446 if (ints & UART_TXEMPTY) { 447 if (sc->sc_txbusy) 448 ipend |= SER_INT_TXIDLE; 449 450 /* Disable TX interrupt */ 451 __uart_setreg(bas, UART_IMSC, psc->imsc & ~UART_TXEMPTY); 452 } 453 454 uart_unlock(sc->sc_hwmtx); 455 456 return (ipend); 457 } 458 459 static int 460 uart_pl011_bus_param(struct uart_softc *sc, int baudrate, int databits, 461 int stopbits, int parity) 462 { 463 464 uart_lock(sc->sc_hwmtx); 465 uart_pl011_param(&sc->sc_bas, baudrate, databits, stopbits, parity); 466 uart_unlock(sc->sc_hwmtx); 467 468 return (0); 469 } 470 471 #ifdef FDT 472 static int 473 uart_pl011_bus_hwrev_fdt(struct uart_softc *sc) 474 { 475 pcell_t node; 476 uint32_t periphid; 477 478 /* 479 * The FIFO sizes vary depending on hardware; rev 2 and below have 16 480 * byte FIFOs, rev 3 and up are 32 byte. The hardware rev is in the 481 * primecell periphid register, but we get a bit of drama, as always, 482 * with the bcm2835 (rpi), which claims to be rev 3, but has 16 byte 483 * FIFOs. We check for both the old freebsd-historic and the proper 484 * bindings-defined compatible strings for bcm2835, and also check the 485 * workaround the linux drivers use for rpi3, which is to override the 486 * primecell periphid register value with a property. 487 */ 488 if (ofw_bus_is_compatible(sc->sc_dev, "brcm,bcm2835-pl011") || 489 ofw_bus_is_compatible(sc->sc_dev, "broadcom,bcm2835-uart")) { 490 return (2); 491 } else { 492 node = ofw_bus_get_node(sc->sc_dev); 493 if (OF_getencprop(node, "arm,primecell-periphid", &periphid, 494 sizeof(periphid)) > 0) { 495 return ((periphid >> 20) & 0x0f); 496 } 497 } 498 499 return (-1); 500 } 501 #endif 502 503 static int 504 uart_pl011_bus_probe(struct uart_softc *sc) 505 { 506 int hwrev; 507 508 hwrev = -1; 509 #ifdef FDT 510 if (IS_FDT) 511 hwrev = uart_pl011_bus_hwrev_fdt(sc); 512 #endif 513 if (hwrev < 0) 514 hwrev = __uart_getreg(&sc->sc_bas, UART_PIDREG_2) >> 4; 515 516 if (hwrev <= 2) { 517 sc->sc_rxfifosz = FIFO_RX_SIZE_R2; 518 sc->sc_txfifosz = FIFO_TX_SIZE_R2; 519 } else { 520 sc->sc_rxfifosz = FIFO_RX_SIZE_R3; 521 sc->sc_txfifosz = FIFO_TX_SIZE_R3; 522 } 523 524 device_set_desc(sc->sc_dev, "PrimeCell UART (PL011)"); 525 526 return (0); 527 } 528 529 static int 530 uart_pl011_bus_receive(struct uart_softc *sc) 531 { 532 struct uart_bas *bas; 533 uint32_t ints, xc; 534 int rx; 535 536 bas = &sc->sc_bas; 537 uart_lock(sc->sc_hwmtx); 538 539 for (;;) { 540 ints = __uart_getreg(bas, UART_FR); 541 if (ints & FR_RXFE) 542 break; 543 if (uart_rx_full(sc)) { 544 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; 545 break; 546 } 547 548 xc = __uart_getreg(bas, UART_DR); 549 rx = xc & 0xff; 550 551 if (xc & DR_FE) 552 rx |= UART_STAT_FRAMERR; 553 if (xc & DR_PE) 554 rx |= UART_STAT_PARERR; 555 556 uart_rx_put(sc, rx); 557 } 558 559 uart_unlock(sc->sc_hwmtx); 560 561 return (0); 562 } 563 564 static int 565 uart_pl011_bus_setsig(struct uart_softc *sc, int sig) 566 { 567 568 return (0); 569 } 570 571 static int 572 uart_pl011_bus_transmit(struct uart_softc *sc) 573 { 574 struct uart_pl011_softc *psc; 575 struct uart_bas *bas; 576 int i; 577 578 psc = (struct uart_pl011_softc *)sc; 579 bas = &sc->sc_bas; 580 uart_lock(sc->sc_hwmtx); 581 582 for (i = 0; i < sc->sc_txdatasz; i++) { 583 __uart_setreg(bas, UART_DR, sc->sc_txbuf[i]); 584 uart_barrier(bas); 585 } 586 587 /* Mark busy and enable TX interrupt */ 588 sc->sc_txbusy = 1; 589 __uart_setreg(bas, UART_IMSC, psc->imsc); 590 591 uart_unlock(sc->sc_hwmtx); 592 593 return (0); 594 } 595 596 static void 597 uart_pl011_bus_grab(struct uart_softc *sc) 598 { 599 struct uart_pl011_softc *psc; 600 struct uart_bas *bas; 601 602 psc = (struct uart_pl011_softc *)sc; 603 bas = &sc->sc_bas; 604 605 /* Disable interrupts on switch to polling */ 606 uart_lock(sc->sc_hwmtx); 607 __uart_setreg(bas, UART_IMSC, psc->imsc & ~IMSC_MASK_ALL); 608 uart_unlock(sc->sc_hwmtx); 609 } 610 611 static void 612 uart_pl011_bus_ungrab(struct uart_softc *sc) 613 { 614 struct uart_pl011_softc *psc; 615 struct uart_bas *bas; 616 617 psc = (struct uart_pl011_softc *)sc; 618 bas = &sc->sc_bas; 619 620 /* Switch to using interrupts while not grabbed */ 621 uart_lock(sc->sc_hwmtx); 622 __uart_setreg(bas, UART_IMSC, psc->imsc); 623 uart_unlock(sc->sc_hwmtx); 624 } 625