1 /* $FreeBSD$ */ 2 /*- 3 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 4 * 5 * Copyright (c) 2009 Hans Petter Selasky. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * This file contains the driver for the ATMEGA series USB OTG Controller. This 31 * driver currently only supports the DCI mode of the USB hardware. 32 */ 33 34 /* 35 * NOTE: When the chip detects BUS-reset it will also reset the 36 * endpoints, Function-address and more. 37 */ 38 39 #ifdef USB_GLOBAL_INCLUDE_FILE 40 #include USB_GLOBAL_INCLUDE_FILE 41 #else 42 #include <sys/stdint.h> 43 #include <sys/stddef.h> 44 #include <sys/param.h> 45 #include <sys/queue.h> 46 #include <sys/types.h> 47 #include <sys/systm.h> 48 #include <sys/kernel.h> 49 #include <sys/bus.h> 50 #include <sys/module.h> 51 #include <sys/lock.h> 52 #include <sys/mutex.h> 53 #include <sys/condvar.h> 54 #include <sys/sysctl.h> 55 #include <sys/sx.h> 56 #include <sys/unistd.h> 57 #include <sys/callout.h> 58 #include <sys/malloc.h> 59 #include <sys/priv.h> 60 61 #include <dev/usb/usb.h> 62 #include <dev/usb/usbdi.h> 63 64 #define USB_DEBUG_VAR atmegadci_debug 65 66 #include <dev/usb/usb_core.h> 67 #include <dev/usb/usb_debug.h> 68 #include <dev/usb/usb_busdma.h> 69 #include <dev/usb/usb_process.h> 70 #include <dev/usb/usb_transfer.h> 71 #include <dev/usb/usb_device.h> 72 #include <dev/usb/usb_hub.h> 73 #include <dev/usb/usb_util.h> 74 75 #include <dev/usb/usb_controller.h> 76 #include <dev/usb/usb_bus.h> 77 #endif /* USB_GLOBAL_INCLUDE_FILE */ 78 79 #include <dev/usb/controller/atmegadci.h> 80 81 #define ATMEGA_BUS2SC(bus) \ 82 ((struct atmegadci_softc *)(((uint8_t *)(bus)) - \ 83 ((uint8_t *)&(((struct atmegadci_softc *)0)->sc_bus)))) 84 85 #define ATMEGA_PC2SC(pc) \ 86 ATMEGA_BUS2SC(USB_DMATAG_TO_XROOT((pc)->tag_parent)->bus) 87 88 #ifdef USB_DEBUG 89 static int atmegadci_debug = 0; 90 91 static SYSCTL_NODE(_hw_usb, OID_AUTO, atmegadci, CTLFLAG_RW | CTLFLAG_MPSAFE, 0, 92 "USB ATMEGA DCI"); 93 SYSCTL_INT(_hw_usb_atmegadci, OID_AUTO, debug, CTLFLAG_RWTUN, 94 &atmegadci_debug, 0, "ATMEGA DCI debug level"); 95 #endif 96 97 #define ATMEGA_INTR_ENDPT 1 98 99 /* prototypes */ 100 101 static const struct usb_bus_methods atmegadci_bus_methods; 102 static const struct usb_pipe_methods atmegadci_device_non_isoc_methods; 103 static const struct usb_pipe_methods atmegadci_device_isoc_fs_methods; 104 105 static atmegadci_cmd_t atmegadci_setup_rx; 106 static atmegadci_cmd_t atmegadci_data_rx; 107 static atmegadci_cmd_t atmegadci_data_tx; 108 static atmegadci_cmd_t atmegadci_data_tx_sync; 109 static void atmegadci_device_done(struct usb_xfer *, usb_error_t); 110 static void atmegadci_do_poll(struct usb_bus *); 111 static void atmegadci_standard_done(struct usb_xfer *); 112 static void atmegadci_root_intr(struct atmegadci_softc *sc); 113 114 /* 115 * Here is a list of what the chip supports: 116 */ 117 static const struct usb_hw_ep_profile 118 atmegadci_ep_profile[2] = { 119 [0] = { 120 .max_in_frame_size = 64, 121 .max_out_frame_size = 64, 122 .is_simplex = 1, 123 .support_control = 1, 124 }, 125 [1] = { 126 .max_in_frame_size = 64, 127 .max_out_frame_size = 64, 128 .is_simplex = 1, 129 .support_bulk = 1, 130 .support_interrupt = 1, 131 .support_isochronous = 1, 132 .support_in = 1, 133 .support_out = 1, 134 }, 135 }; 136 137 static void 138 atmegadci_get_hw_ep_profile(struct usb_device *udev, 139 const struct usb_hw_ep_profile **ppf, uint8_t ep_addr) 140 { 141 if (ep_addr == 0) 142 *ppf = atmegadci_ep_profile; 143 else if (ep_addr < ATMEGA_EP_MAX) 144 *ppf = atmegadci_ep_profile + 1; 145 else 146 *ppf = NULL; 147 } 148 149 static void 150 atmegadci_clocks_on(struct atmegadci_softc *sc) 151 { 152 if (sc->sc_flags.clocks_off && 153 sc->sc_flags.port_powered) { 154 DPRINTFN(5, "\n"); 155 156 /* turn on clocks */ 157 (sc->sc_clocks_on) (&sc->sc_bus); 158 159 ATMEGA_WRITE_1(sc, ATMEGA_USBCON, 160 ATMEGA_USBCON_USBE | 161 ATMEGA_USBCON_OTGPADE | 162 ATMEGA_USBCON_VBUSTE); 163 164 sc->sc_flags.clocks_off = 0; 165 166 /* enable transceiver ? */ 167 } 168 } 169 170 static void 171 atmegadci_clocks_off(struct atmegadci_softc *sc) 172 { 173 if (!sc->sc_flags.clocks_off) { 174 DPRINTFN(5, "\n"); 175 176 /* disable Transceiver ? */ 177 178 ATMEGA_WRITE_1(sc, ATMEGA_USBCON, 179 ATMEGA_USBCON_USBE | 180 ATMEGA_USBCON_OTGPADE | 181 ATMEGA_USBCON_FRZCLK | 182 ATMEGA_USBCON_VBUSTE); 183 184 /* turn clocks off */ 185 (sc->sc_clocks_off) (&sc->sc_bus); 186 187 sc->sc_flags.clocks_off = 1; 188 } 189 } 190 191 static void 192 atmegadci_pull_up(struct atmegadci_softc *sc) 193 { 194 /* pullup D+, if possible */ 195 196 if (!sc->sc_flags.d_pulled_up && 197 sc->sc_flags.port_powered) { 198 sc->sc_flags.d_pulled_up = 1; 199 ATMEGA_WRITE_1(sc, ATMEGA_UDCON, 0); 200 } 201 } 202 203 static void 204 atmegadci_pull_down(struct atmegadci_softc *sc) 205 { 206 /* pulldown D+, if possible */ 207 208 if (sc->sc_flags.d_pulled_up) { 209 sc->sc_flags.d_pulled_up = 0; 210 ATMEGA_WRITE_1(sc, ATMEGA_UDCON, ATMEGA_UDCON_DETACH); 211 } 212 } 213 214 static void 215 atmegadci_wakeup_peer(struct atmegadci_softc *sc) 216 { 217 uint8_t temp; 218 219 if (!sc->sc_flags.status_suspend) { 220 return; 221 } 222 223 temp = ATMEGA_READ_1(sc, ATMEGA_UDCON); 224 ATMEGA_WRITE_1(sc, ATMEGA_UDCON, temp | ATMEGA_UDCON_RMWKUP); 225 226 /* wait 8 milliseconds */ 227 /* Wait for reset to complete. */ 228 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125); 229 230 /* hardware should have cleared RMWKUP bit */ 231 } 232 233 static void 234 atmegadci_set_address(struct atmegadci_softc *sc, uint8_t addr) 235 { 236 DPRINTFN(5, "addr=%d\n", addr); 237 238 addr |= ATMEGA_UDADDR_ADDEN; 239 240 ATMEGA_WRITE_1(sc, ATMEGA_UDADDR, addr); 241 } 242 243 static uint8_t 244 atmegadci_setup_rx(struct atmegadci_td *td) 245 { 246 struct atmegadci_softc *sc; 247 struct usb_device_request req; 248 uint16_t count; 249 uint8_t temp; 250 251 /* get pointer to softc */ 252 sc = ATMEGA_PC2SC(td->pc); 253 254 /* select endpoint number */ 255 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, td->ep_no); 256 257 /* check endpoint status */ 258 temp = ATMEGA_READ_1(sc, ATMEGA_UEINTX); 259 260 DPRINTFN(5, "UEINTX=0x%02x\n", temp); 261 262 if (!(temp & ATMEGA_UEINTX_RXSTPI)) { 263 goto not_complete; 264 } 265 /* clear did stall */ 266 td->did_stall = 0; 267 /* get the packet byte count */ 268 count = 269 (ATMEGA_READ_1(sc, ATMEGA_UEBCHX) << 8) | 270 (ATMEGA_READ_1(sc, ATMEGA_UEBCLX)); 271 272 /* mask away undefined bits */ 273 count &= 0x7FF; 274 275 /* verify data length */ 276 if (count != td->remainder) { 277 DPRINTFN(0, "Invalid SETUP packet " 278 "length, %d bytes\n", count); 279 goto not_complete; 280 } 281 if (count != sizeof(req)) { 282 DPRINTFN(0, "Unsupported SETUP packet " 283 "length, %d bytes\n", count); 284 goto not_complete; 285 } 286 /* receive data */ 287 ATMEGA_READ_MULTI_1(sc, ATMEGA_UEDATX, 288 (void *)&req, sizeof(req)); 289 290 /* copy data into real buffer */ 291 usbd_copy_in(td->pc, 0, &req, sizeof(req)); 292 293 td->offset = sizeof(req); 294 td->remainder = 0; 295 296 /* sneak peek the set address */ 297 if ((req.bmRequestType == UT_WRITE_DEVICE) && 298 (req.bRequest == UR_SET_ADDRESS)) { 299 sc->sc_dv_addr = req.wValue[0] & 0x7F; 300 /* must write address before ZLP */ 301 ATMEGA_WRITE_1(sc, ATMEGA_UDADDR, sc->sc_dv_addr); 302 } else { 303 sc->sc_dv_addr = 0xFF; 304 } 305 306 /* Clear SETUP packet interrupt and all other previous interrupts */ 307 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, 0); 308 return (0); /* complete */ 309 310 not_complete: 311 /* abort any ongoing transfer */ 312 if (!td->did_stall) { 313 DPRINTFN(5, "stalling\n"); 314 ATMEGA_WRITE_1(sc, ATMEGA_UECONX, 315 ATMEGA_UECONX_EPEN | 316 ATMEGA_UECONX_STALLRQ); 317 td->did_stall = 1; 318 } 319 if (temp & ATMEGA_UEINTX_RXSTPI) { 320 /* clear SETUP packet interrupt */ 321 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, ~ATMEGA_UEINTX_RXSTPI); 322 } 323 /* we only want to know if there is a SETUP packet */ 324 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, ATMEGA_UEIENX_RXSTPE); 325 return (1); /* not complete */ 326 } 327 328 static uint8_t 329 atmegadci_data_rx(struct atmegadci_td *td) 330 { 331 struct atmegadci_softc *sc; 332 struct usb_page_search buf_res; 333 uint16_t count; 334 uint8_t temp; 335 uint8_t to; 336 uint8_t got_short; 337 338 to = 3; /* don't loop forever! */ 339 got_short = 0; 340 341 /* get pointer to softc */ 342 sc = ATMEGA_PC2SC(td->pc); 343 344 /* select endpoint number */ 345 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, td->ep_no); 346 347 repeat: 348 /* check if any of the FIFO banks have data */ 349 /* check endpoint status */ 350 temp = ATMEGA_READ_1(sc, ATMEGA_UEINTX); 351 352 DPRINTFN(5, "temp=0x%02x rem=%u\n", temp, td->remainder); 353 354 if (temp & ATMEGA_UEINTX_RXSTPI) { 355 if (td->remainder == 0) { 356 /* 357 * We are actually complete and have 358 * received the next SETUP 359 */ 360 DPRINTFN(5, "faking complete\n"); 361 return (0); /* complete */ 362 } 363 /* 364 * USB Host Aborted the transfer. 365 */ 366 td->error = 1; 367 return (0); /* complete */ 368 } 369 /* check status */ 370 if (!(temp & (ATMEGA_UEINTX_FIFOCON | 371 ATMEGA_UEINTX_RXOUTI))) { 372 /* no data */ 373 goto not_complete; 374 } 375 /* get the packet byte count */ 376 count = 377 (ATMEGA_READ_1(sc, ATMEGA_UEBCHX) << 8) | 378 (ATMEGA_READ_1(sc, ATMEGA_UEBCLX)); 379 380 /* mask away undefined bits */ 381 count &= 0x7FF; 382 383 /* verify the packet byte count */ 384 if (count != td->max_packet_size) { 385 if (count < td->max_packet_size) { 386 /* we have a short packet */ 387 td->short_pkt = 1; 388 got_short = 1; 389 } else { 390 /* invalid USB packet */ 391 td->error = 1; 392 return (0); /* we are complete */ 393 } 394 } 395 /* verify the packet byte count */ 396 if (count > td->remainder) { 397 /* invalid USB packet */ 398 td->error = 1; 399 return (0); /* we are complete */ 400 } 401 while (count > 0) { 402 usbd_get_page(td->pc, td->offset, &buf_res); 403 404 /* get correct length */ 405 if (buf_res.length > count) { 406 buf_res.length = count; 407 } 408 /* receive data */ 409 ATMEGA_READ_MULTI_1(sc, ATMEGA_UEDATX, 410 buf_res.buffer, buf_res.length); 411 412 /* update counters */ 413 count -= buf_res.length; 414 td->offset += buf_res.length; 415 td->remainder -= buf_res.length; 416 } 417 418 /* clear OUT packet interrupt */ 419 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, ATMEGA_UEINTX_RXOUTI ^ 0xFF); 420 421 /* release FIFO bank */ 422 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, ATMEGA_UEINTX_FIFOCON ^ 0xFF); 423 424 /* check if we are complete */ 425 if ((td->remainder == 0) || got_short) { 426 if (td->short_pkt) { 427 /* we are complete */ 428 return (0); 429 } 430 /* else need to receive a zero length packet */ 431 } 432 if (--to) { 433 goto repeat; 434 } 435 not_complete: 436 /* we only want to know if there is a SETUP packet or OUT packet */ 437 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, 438 ATMEGA_UEIENX_RXSTPE | ATMEGA_UEIENX_RXOUTE); 439 return (1); /* not complete */ 440 } 441 442 static uint8_t 443 atmegadci_data_tx(struct atmegadci_td *td) 444 { 445 struct atmegadci_softc *sc; 446 struct usb_page_search buf_res; 447 uint16_t count; 448 uint8_t to; 449 uint8_t temp; 450 451 to = 3; /* don't loop forever! */ 452 453 /* get pointer to softc */ 454 sc = ATMEGA_PC2SC(td->pc); 455 456 /* select endpoint number */ 457 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, td->ep_no); 458 459 repeat: 460 461 /* check endpoint status */ 462 temp = ATMEGA_READ_1(sc, ATMEGA_UEINTX); 463 464 DPRINTFN(5, "temp=0x%02x rem=%u\n", temp, td->remainder); 465 466 if (temp & ATMEGA_UEINTX_RXSTPI) { 467 /* 468 * The current transfer was aborted 469 * by the USB Host 470 */ 471 td->error = 1; 472 return (0); /* complete */ 473 } 474 475 temp = ATMEGA_READ_1(sc, ATMEGA_UESTA0X); 476 if (temp & 3) { 477 /* cannot write any data - a bank is busy */ 478 goto not_complete; 479 } 480 481 count = td->max_packet_size; 482 if (td->remainder < count) { 483 /* we have a short packet */ 484 td->short_pkt = 1; 485 count = td->remainder; 486 } 487 while (count > 0) { 488 usbd_get_page(td->pc, td->offset, &buf_res); 489 490 /* get correct length */ 491 if (buf_res.length > count) { 492 buf_res.length = count; 493 } 494 /* transmit data */ 495 ATMEGA_WRITE_MULTI_1(sc, ATMEGA_UEDATX, 496 buf_res.buffer, buf_res.length); 497 498 /* update counters */ 499 count -= buf_res.length; 500 td->offset += buf_res.length; 501 td->remainder -= buf_res.length; 502 } 503 504 /* clear IN packet interrupt */ 505 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, 0xFF ^ ATMEGA_UEINTX_TXINI); 506 507 /* allocate FIFO bank */ 508 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, 0xFF ^ ATMEGA_UEINTX_FIFOCON); 509 510 /* check remainder */ 511 if (td->remainder == 0) { 512 if (td->short_pkt) { 513 return (0); /* complete */ 514 } 515 /* else we need to transmit a short packet */ 516 } 517 if (--to) { 518 goto repeat; 519 } 520 not_complete: 521 /* we only want to know if there is a SETUP packet or free IN packet */ 522 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, 523 ATMEGA_UEIENX_RXSTPE | ATMEGA_UEIENX_TXINE); 524 return (1); /* not complete */ 525 } 526 527 static uint8_t 528 atmegadci_data_tx_sync(struct atmegadci_td *td) 529 { 530 struct atmegadci_softc *sc; 531 uint8_t temp; 532 533 /* get pointer to softc */ 534 sc = ATMEGA_PC2SC(td->pc); 535 536 /* select endpoint number */ 537 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, td->ep_no); 538 539 /* check endpoint status */ 540 temp = ATMEGA_READ_1(sc, ATMEGA_UEINTX); 541 542 DPRINTFN(5, "temp=0x%02x\n", temp); 543 544 if (temp & ATMEGA_UEINTX_RXSTPI) { 545 DPRINTFN(5, "faking complete\n"); 546 /* Race condition */ 547 return (0); /* complete */ 548 } 549 /* 550 * The control endpoint has only got one bank, so if that bank 551 * is free the packet has been transferred! 552 */ 553 temp = ATMEGA_READ_1(sc, ATMEGA_UESTA0X); 554 if (temp & 3) { 555 /* cannot write any data - a bank is busy */ 556 goto not_complete; 557 } 558 if (sc->sc_dv_addr != 0xFF) { 559 /* set new address */ 560 atmegadci_set_address(sc, sc->sc_dv_addr); 561 } 562 return (0); /* complete */ 563 564 not_complete: 565 /* we only want to know if there is a SETUP packet or free IN packet */ 566 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, 567 ATMEGA_UEIENX_RXSTPE | ATMEGA_UEIENX_TXINE); 568 return (1); /* not complete */ 569 } 570 571 static uint8_t 572 atmegadci_xfer_do_fifo(struct usb_xfer *xfer) 573 { 574 struct atmegadci_td *td; 575 576 DPRINTFN(9, "\n"); 577 578 td = xfer->td_transfer_cache; 579 while (1) { 580 if ((td->func) (td)) { 581 /* operation in progress */ 582 break; 583 } 584 if (((void *)td) == xfer->td_transfer_last) { 585 goto done; 586 } 587 if (td->error) { 588 goto done; 589 } else if (td->remainder > 0) { 590 /* 591 * We had a short transfer. If there is no alternate 592 * next, stop processing ! 593 */ 594 if (!td->alt_next) { 595 goto done; 596 } 597 } 598 /* 599 * Fetch the next transfer descriptor and transfer 600 * some flags to the next transfer descriptor 601 */ 602 td = td->obj_next; 603 xfer->td_transfer_cache = td; 604 } 605 return (1); /* not complete */ 606 607 done: 608 /* compute all actual lengths */ 609 610 atmegadci_standard_done(xfer); 611 return (0); /* complete */ 612 } 613 614 static void 615 atmegadci_interrupt_poll(struct atmegadci_softc *sc) 616 { 617 struct usb_xfer *xfer; 618 619 repeat: 620 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 621 if (!atmegadci_xfer_do_fifo(xfer)) { 622 /* queue has been modified */ 623 goto repeat; 624 } 625 } 626 } 627 628 static void 629 atmegadci_vbus_interrupt(struct atmegadci_softc *sc, uint8_t is_on) 630 { 631 DPRINTFN(5, "vbus = %u\n", is_on); 632 633 if (is_on) { 634 if (!sc->sc_flags.status_vbus) { 635 sc->sc_flags.status_vbus = 1; 636 637 /* complete root HUB interrupt endpoint */ 638 639 atmegadci_root_intr(sc); 640 } 641 } else { 642 if (sc->sc_flags.status_vbus) { 643 sc->sc_flags.status_vbus = 0; 644 sc->sc_flags.status_bus_reset = 0; 645 sc->sc_flags.status_suspend = 0; 646 sc->sc_flags.change_suspend = 0; 647 sc->sc_flags.change_connect = 1; 648 649 /* complete root HUB interrupt endpoint */ 650 651 atmegadci_root_intr(sc); 652 } 653 } 654 } 655 656 void 657 atmegadci_interrupt(struct atmegadci_softc *sc) 658 { 659 uint8_t status; 660 661 USB_BUS_LOCK(&sc->sc_bus); 662 663 /* read interrupt status */ 664 status = ATMEGA_READ_1(sc, ATMEGA_UDINT); 665 666 /* clear all set interrupts */ 667 ATMEGA_WRITE_1(sc, ATMEGA_UDINT, (~status) & 0x7D); 668 669 DPRINTFN(14, "UDINT=0x%02x\n", status); 670 671 /* check for any bus state change interrupts */ 672 if (status & ATMEGA_UDINT_EORSTI) { 673 DPRINTFN(5, "end of reset\n"); 674 675 /* set correct state */ 676 sc->sc_flags.status_bus_reset = 1; 677 sc->sc_flags.status_suspend = 0; 678 sc->sc_flags.change_suspend = 0; 679 sc->sc_flags.change_connect = 1; 680 681 /* disable resume interrupt */ 682 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN, 683 ATMEGA_UDINT_SUSPE | 684 ATMEGA_UDINT_EORSTE); 685 686 /* complete root HUB interrupt endpoint */ 687 atmegadci_root_intr(sc); 688 } 689 /* 690 * If resume and suspend is set at the same time we interpret 691 * that like RESUME. Resume is set when there is at least 3 692 * milliseconds of inactivity on the USB BUS. 693 */ 694 if (status & ATMEGA_UDINT_WAKEUPI) { 695 DPRINTFN(5, "resume interrupt\n"); 696 697 if (sc->sc_flags.status_suspend) { 698 /* update status bits */ 699 sc->sc_flags.status_suspend = 0; 700 sc->sc_flags.change_suspend = 1; 701 702 /* disable resume interrupt */ 703 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN, 704 ATMEGA_UDINT_SUSPE | 705 ATMEGA_UDINT_EORSTE); 706 707 /* complete root HUB interrupt endpoint */ 708 atmegadci_root_intr(sc); 709 } 710 } else if (status & ATMEGA_UDINT_SUSPI) { 711 DPRINTFN(5, "suspend interrupt\n"); 712 713 if (!sc->sc_flags.status_suspend) { 714 /* update status bits */ 715 sc->sc_flags.status_suspend = 1; 716 sc->sc_flags.change_suspend = 1; 717 718 /* disable suspend interrupt */ 719 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN, 720 ATMEGA_UDINT_WAKEUPE | 721 ATMEGA_UDINT_EORSTE); 722 723 /* complete root HUB interrupt endpoint */ 724 atmegadci_root_intr(sc); 725 } 726 } 727 /* check VBUS */ 728 status = ATMEGA_READ_1(sc, ATMEGA_USBINT); 729 730 /* clear all set interrupts */ 731 ATMEGA_WRITE_1(sc, ATMEGA_USBINT, (~status) & 0x03); 732 733 if (status & ATMEGA_USBINT_VBUSTI) { 734 uint8_t temp; 735 736 DPRINTFN(5, "USBINT=0x%02x\n", status); 737 738 temp = ATMEGA_READ_1(sc, ATMEGA_USBSTA); 739 atmegadci_vbus_interrupt(sc, temp & ATMEGA_USBSTA_VBUS); 740 } 741 /* check for any endpoint interrupts */ 742 status = ATMEGA_READ_1(sc, ATMEGA_UEINT); 743 /* the hardware will clear the UEINT bits automatically */ 744 if (status) { 745 DPRINTFN(5, "real endpoint interrupt UEINT=0x%02x\n", status); 746 747 atmegadci_interrupt_poll(sc); 748 } 749 USB_BUS_UNLOCK(&sc->sc_bus); 750 } 751 752 static void 753 atmegadci_setup_standard_chain_sub(struct atmegadci_std_temp *temp) 754 { 755 struct atmegadci_td *td; 756 757 /* get current Transfer Descriptor */ 758 td = temp->td_next; 759 temp->td = td; 760 761 /* prepare for next TD */ 762 temp->td_next = td->obj_next; 763 764 /* fill out the Transfer Descriptor */ 765 td->func = temp->func; 766 td->pc = temp->pc; 767 td->offset = temp->offset; 768 td->remainder = temp->len; 769 td->error = 0; 770 td->did_stall = temp->did_stall; 771 td->short_pkt = temp->short_pkt; 772 td->alt_next = temp->setup_alt_next; 773 } 774 775 static void 776 atmegadci_setup_standard_chain(struct usb_xfer *xfer) 777 { 778 struct atmegadci_std_temp temp; 779 struct atmegadci_softc *sc; 780 struct atmegadci_td *td; 781 uint32_t x; 782 uint8_t ep_no; 783 uint8_t need_sync; 784 785 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 786 xfer->address, UE_GET_ADDR(xfer->endpointno), 787 xfer->sumlen, usbd_get_speed(xfer->xroot->udev)); 788 789 temp.max_frame_size = xfer->max_frame_size; 790 791 td = xfer->td_start[0]; 792 xfer->td_transfer_first = td; 793 xfer->td_transfer_cache = td; 794 795 /* setup temp */ 796 797 temp.pc = NULL; 798 temp.td = NULL; 799 temp.td_next = xfer->td_start[0]; 800 temp.offset = 0; 801 temp.setup_alt_next = xfer->flags_int.short_frames_ok || 802 xfer->flags_int.isochronous_xfr; 803 temp.did_stall = !xfer->flags_int.control_stall; 804 805 sc = ATMEGA_BUS2SC(xfer->xroot->bus); 806 ep_no = (xfer->endpointno & UE_ADDR); 807 808 /* check if we should prepend a setup message */ 809 810 if (xfer->flags_int.control_xfr) { 811 if (xfer->flags_int.control_hdr) { 812 temp.func = &atmegadci_setup_rx; 813 temp.len = xfer->frlengths[0]; 814 temp.pc = xfer->frbuffers + 0; 815 temp.short_pkt = temp.len ? 1 : 0; 816 /* check for last frame */ 817 if (xfer->nframes == 1) { 818 /* no STATUS stage yet, SETUP is last */ 819 if (xfer->flags_int.control_act) 820 temp.setup_alt_next = 0; 821 } 822 823 atmegadci_setup_standard_chain_sub(&temp); 824 } 825 x = 1; 826 } else { 827 x = 0; 828 } 829 830 if (x != xfer->nframes) { 831 if (xfer->endpointno & UE_DIR_IN) { 832 temp.func = &atmegadci_data_tx; 833 need_sync = 1; 834 } else { 835 temp.func = &atmegadci_data_rx; 836 need_sync = 0; 837 } 838 839 /* setup "pc" pointer */ 840 temp.pc = xfer->frbuffers + x; 841 } else { 842 need_sync = 0; 843 } 844 while (x != xfer->nframes) { 845 /* DATA0 / DATA1 message */ 846 847 temp.len = xfer->frlengths[x]; 848 849 x++; 850 851 if (x == xfer->nframes) { 852 if (xfer->flags_int.control_xfr) { 853 if (xfer->flags_int.control_act) { 854 temp.setup_alt_next = 0; 855 } 856 } else { 857 temp.setup_alt_next = 0; 858 } 859 } 860 if (temp.len == 0) { 861 /* make sure that we send an USB packet */ 862 863 temp.short_pkt = 0; 864 865 } else { 866 /* regular data transfer */ 867 868 temp.short_pkt = (xfer->flags.force_short_xfer) ? 0 : 1; 869 } 870 871 atmegadci_setup_standard_chain_sub(&temp); 872 873 if (xfer->flags_int.isochronous_xfr) { 874 temp.offset += temp.len; 875 } else { 876 /* get next Page Cache pointer */ 877 temp.pc = xfer->frbuffers + x; 878 } 879 } 880 881 if (xfer->flags_int.control_xfr) { 882 /* always setup a valid "pc" pointer for status and sync */ 883 temp.pc = xfer->frbuffers + 0; 884 temp.len = 0; 885 temp.short_pkt = 0; 886 temp.setup_alt_next = 0; 887 888 /* check if we need to sync */ 889 if (need_sync) { 890 /* we need a SYNC point after TX */ 891 temp.func = &atmegadci_data_tx_sync; 892 atmegadci_setup_standard_chain_sub(&temp); 893 } 894 895 /* check if we should append a status stage */ 896 if (!xfer->flags_int.control_act) { 897 /* 898 * Send a DATA1 message and invert the current 899 * endpoint direction. 900 */ 901 if (xfer->endpointno & UE_DIR_IN) { 902 temp.func = &atmegadci_data_rx; 903 need_sync = 0; 904 } else { 905 temp.func = &atmegadci_data_tx; 906 need_sync = 1; 907 } 908 909 atmegadci_setup_standard_chain_sub(&temp); 910 if (need_sync) { 911 /* we need a SYNC point after TX */ 912 temp.func = &atmegadci_data_tx_sync; 913 atmegadci_setup_standard_chain_sub(&temp); 914 } 915 } 916 } 917 /* must have at least one frame! */ 918 td = temp.td; 919 xfer->td_transfer_last = td; 920 } 921 922 static void 923 atmegadci_timeout(void *arg) 924 { 925 struct usb_xfer *xfer = arg; 926 927 DPRINTF("xfer=%p\n", xfer); 928 929 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 930 931 /* transfer is transferred */ 932 atmegadci_device_done(xfer, USB_ERR_TIMEOUT); 933 } 934 935 static void 936 atmegadci_start_standard_chain(struct usb_xfer *xfer) 937 { 938 DPRINTFN(9, "\n"); 939 940 /* poll one time - will turn on interrupts */ 941 if (atmegadci_xfer_do_fifo(xfer)) { 942 /* put transfer on interrupt queue */ 943 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 944 945 /* start timeout, if any */ 946 if (xfer->timeout != 0) { 947 usbd_transfer_timeout_ms(xfer, 948 &atmegadci_timeout, xfer->timeout); 949 } 950 } 951 } 952 953 static void 954 atmegadci_root_intr(struct atmegadci_softc *sc) 955 { 956 DPRINTFN(9, "\n"); 957 958 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 959 960 /* set port bit */ 961 sc->sc_hub_idata[0] = 0x02; /* we only have one port */ 962 963 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 964 sizeof(sc->sc_hub_idata)); 965 } 966 967 static usb_error_t 968 atmegadci_standard_done_sub(struct usb_xfer *xfer) 969 { 970 struct atmegadci_td *td; 971 uint32_t len; 972 uint8_t error; 973 974 DPRINTFN(9, "\n"); 975 976 td = xfer->td_transfer_cache; 977 978 do { 979 len = td->remainder; 980 981 if (xfer->aframes != xfer->nframes) { 982 /* 983 * Verify the length and subtract 984 * the remainder from "frlengths[]": 985 */ 986 if (len > xfer->frlengths[xfer->aframes]) { 987 td->error = 1; 988 } else { 989 xfer->frlengths[xfer->aframes] -= len; 990 } 991 } 992 /* Check for transfer error */ 993 if (td->error) { 994 /* the transfer is finished */ 995 error = 1; 996 td = NULL; 997 break; 998 } 999 /* Check for short transfer */ 1000 if (len > 0) { 1001 if (xfer->flags_int.short_frames_ok || 1002 xfer->flags_int.isochronous_xfr) { 1003 /* follow alt next */ 1004 if (td->alt_next) { 1005 td = td->obj_next; 1006 } else { 1007 td = NULL; 1008 } 1009 } else { 1010 /* the transfer is finished */ 1011 td = NULL; 1012 } 1013 error = 0; 1014 break; 1015 } 1016 td = td->obj_next; 1017 1018 /* this USB frame is complete */ 1019 error = 0; 1020 break; 1021 1022 } while (0); 1023 1024 /* update transfer cache */ 1025 1026 xfer->td_transfer_cache = td; 1027 1028 return (error ? 1029 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION); 1030 } 1031 1032 static void 1033 atmegadci_standard_done(struct usb_xfer *xfer) 1034 { 1035 usb_error_t err = 0; 1036 1037 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 1038 xfer, xfer->endpoint); 1039 1040 /* reset scanner */ 1041 1042 xfer->td_transfer_cache = xfer->td_transfer_first; 1043 1044 if (xfer->flags_int.control_xfr) { 1045 if (xfer->flags_int.control_hdr) { 1046 err = atmegadci_standard_done_sub(xfer); 1047 } 1048 xfer->aframes = 1; 1049 1050 if (xfer->td_transfer_cache == NULL) { 1051 goto done; 1052 } 1053 } 1054 while (xfer->aframes != xfer->nframes) { 1055 err = atmegadci_standard_done_sub(xfer); 1056 xfer->aframes++; 1057 1058 if (xfer->td_transfer_cache == NULL) { 1059 goto done; 1060 } 1061 } 1062 1063 if (xfer->flags_int.control_xfr && 1064 !xfer->flags_int.control_act) { 1065 err = atmegadci_standard_done_sub(xfer); 1066 } 1067 done: 1068 atmegadci_device_done(xfer, err); 1069 } 1070 1071 /*------------------------------------------------------------------------* 1072 * atmegadci_device_done 1073 * 1074 * NOTE: this function can be called more than one time on the 1075 * same USB transfer! 1076 *------------------------------------------------------------------------*/ 1077 static void 1078 atmegadci_device_done(struct usb_xfer *xfer, usb_error_t error) 1079 { 1080 struct atmegadci_softc *sc = ATMEGA_BUS2SC(xfer->xroot->bus); 1081 uint8_t ep_no; 1082 1083 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1084 1085 DPRINTFN(9, "xfer=%p, endpoint=%p, error=%d\n", 1086 xfer, xfer->endpoint, error); 1087 1088 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) { 1089 ep_no = (xfer->endpointno & UE_ADDR); 1090 1091 /* select endpoint number */ 1092 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, ep_no); 1093 1094 /* disable endpoint interrupt */ 1095 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, 0); 1096 1097 DPRINTFN(15, "disabled interrupts!\n"); 1098 } 1099 /* dequeue transfer and start next transfer */ 1100 usbd_transfer_done(xfer, error); 1101 } 1102 1103 static void 1104 atmegadci_xfer_stall(struct usb_xfer *xfer) 1105 { 1106 atmegadci_device_done(xfer, USB_ERR_STALLED); 1107 } 1108 1109 static void 1110 atmegadci_set_stall(struct usb_device *udev, 1111 struct usb_endpoint *ep, uint8_t *did_stall) 1112 { 1113 struct atmegadci_softc *sc; 1114 uint8_t ep_no; 1115 1116 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 1117 1118 DPRINTFN(5, "endpoint=%p\n", ep); 1119 1120 sc = ATMEGA_BUS2SC(udev->bus); 1121 /* get endpoint number */ 1122 ep_no = (ep->edesc->bEndpointAddress & UE_ADDR); 1123 /* select endpoint number */ 1124 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, ep_no); 1125 /* set stall */ 1126 ATMEGA_WRITE_1(sc, ATMEGA_UECONX, 1127 ATMEGA_UECONX_EPEN | 1128 ATMEGA_UECONX_STALLRQ); 1129 } 1130 1131 static void 1132 atmegadci_clear_stall_sub(struct atmegadci_softc *sc, uint8_t ep_no, 1133 uint8_t ep_type, uint8_t ep_dir) 1134 { 1135 uint8_t temp; 1136 1137 if (ep_type == UE_CONTROL) { 1138 /* clearing stall is not needed */ 1139 return; 1140 } 1141 /* select endpoint number */ 1142 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, ep_no); 1143 1144 /* set endpoint reset */ 1145 ATMEGA_WRITE_1(sc, ATMEGA_UERST, ATMEGA_UERST_MASK(ep_no)); 1146 1147 /* clear endpoint reset */ 1148 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 0); 1149 1150 /* set stall */ 1151 ATMEGA_WRITE_1(sc, ATMEGA_UECONX, 1152 ATMEGA_UECONX_EPEN | 1153 ATMEGA_UECONX_STALLRQ); 1154 1155 /* reset data toggle */ 1156 ATMEGA_WRITE_1(sc, ATMEGA_UECONX, 1157 ATMEGA_UECONX_EPEN | 1158 ATMEGA_UECONX_RSTDT); 1159 1160 /* clear stall */ 1161 ATMEGA_WRITE_1(sc, ATMEGA_UECONX, 1162 ATMEGA_UECONX_EPEN | 1163 ATMEGA_UECONX_STALLRQC); 1164 1165 do { 1166 if (ep_type == UE_BULK) { 1167 temp = ATMEGA_UECFG0X_EPTYPE2; 1168 } else if (ep_type == UE_INTERRUPT) { 1169 temp = ATMEGA_UECFG0X_EPTYPE3; 1170 } else { 1171 temp = ATMEGA_UECFG0X_EPTYPE1; 1172 } 1173 if (ep_dir & UE_DIR_IN) { 1174 temp |= ATMEGA_UECFG0X_EPDIR; 1175 } 1176 /* two banks, 64-bytes wMaxPacket */ 1177 ATMEGA_WRITE_1(sc, ATMEGA_UECFG0X, temp); 1178 ATMEGA_WRITE_1(sc, ATMEGA_UECFG1X, 1179 ATMEGA_UECFG1X_ALLOC | 1180 ATMEGA_UECFG1X_EPBK0 | /* one bank */ 1181 ATMEGA_UECFG1X_EPSIZE(3)); 1182 1183 temp = ATMEGA_READ_1(sc, ATMEGA_UESTA0X); 1184 if (!(temp & ATMEGA_UESTA0X_CFGOK)) { 1185 device_printf(sc->sc_bus.bdev, 1186 "Chip rejected configuration\n"); 1187 } 1188 } while (0); 1189 } 1190 1191 static void 1192 atmegadci_clear_stall(struct usb_device *udev, struct usb_endpoint *ep) 1193 { 1194 struct atmegadci_softc *sc; 1195 struct usb_endpoint_descriptor *ed; 1196 1197 DPRINTFN(5, "endpoint=%p\n", ep); 1198 1199 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 1200 1201 /* check mode */ 1202 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 1203 /* not supported */ 1204 return; 1205 } 1206 /* get softc */ 1207 sc = ATMEGA_BUS2SC(udev->bus); 1208 1209 /* get endpoint descriptor */ 1210 ed = ep->edesc; 1211 1212 /* reset endpoint */ 1213 atmegadci_clear_stall_sub(sc, 1214 (ed->bEndpointAddress & UE_ADDR), 1215 (ed->bmAttributes & UE_XFERTYPE), 1216 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT))); 1217 } 1218 1219 usb_error_t 1220 atmegadci_init(struct atmegadci_softc *sc) 1221 { 1222 uint8_t n; 1223 1224 DPRINTF("start\n"); 1225 1226 /* set up the bus structure */ 1227 sc->sc_bus.usbrev = USB_REV_1_1; 1228 sc->sc_bus.methods = &atmegadci_bus_methods; 1229 1230 USB_BUS_LOCK(&sc->sc_bus); 1231 1232 /* make sure USB is enabled */ 1233 ATMEGA_WRITE_1(sc, ATMEGA_USBCON, 1234 ATMEGA_USBCON_USBE | 1235 ATMEGA_USBCON_FRZCLK); 1236 1237 /* enable USB PAD regulator */ 1238 ATMEGA_WRITE_1(sc, ATMEGA_UHWCON, 1239 ATMEGA_UHWCON_UVREGE | 1240 ATMEGA_UHWCON_UIMOD); 1241 1242 /* the following register sets up the USB PLL, assuming 16MHz X-tal */ 1243 ATMEGA_WRITE_1(sc, 0x49 /* PLLCSR */, 0x14 | 0x02); 1244 1245 /* wait for PLL to lock */ 1246 for (n = 0; n != 20; n++) { 1247 if (ATMEGA_READ_1(sc, 0x49) & 0x01) 1248 break; 1249 /* wait a little bit for PLL to start */ 1250 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); 1251 } 1252 1253 /* make sure USB is enabled */ 1254 ATMEGA_WRITE_1(sc, ATMEGA_USBCON, 1255 ATMEGA_USBCON_USBE | 1256 ATMEGA_USBCON_OTGPADE | 1257 ATMEGA_USBCON_VBUSTE); 1258 1259 /* turn on clocks */ 1260 (sc->sc_clocks_on) (&sc->sc_bus); 1261 1262 /* make sure device is re-enumerated */ 1263 ATMEGA_WRITE_1(sc, ATMEGA_UDCON, ATMEGA_UDCON_DETACH); 1264 1265 /* wait a little for things to stabilise */ 1266 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 20); 1267 1268 /* enable interrupts */ 1269 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN, 1270 ATMEGA_UDINT_SUSPE | 1271 ATMEGA_UDINT_EORSTE); 1272 1273 /* reset all endpoints */ 1274 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 1275 (1 << ATMEGA_EP_MAX) - 1); 1276 1277 /* disable reset */ 1278 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 0); 1279 1280 /* disable all endpoints */ 1281 for (n = 0; n != ATMEGA_EP_MAX; n++) { 1282 /* select endpoint */ 1283 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, n); 1284 1285 /* disable endpoint interrupt */ 1286 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, 0); 1287 1288 /* disable endpoint */ 1289 ATMEGA_WRITE_1(sc, ATMEGA_UECONX, 0); 1290 } 1291 1292 /* turn off clocks */ 1293 1294 atmegadci_clocks_off(sc); 1295 1296 /* read initial VBUS state */ 1297 1298 n = ATMEGA_READ_1(sc, ATMEGA_USBSTA); 1299 atmegadci_vbus_interrupt(sc, n & ATMEGA_USBSTA_VBUS); 1300 1301 USB_BUS_UNLOCK(&sc->sc_bus); 1302 1303 /* catch any lost interrupts */ 1304 1305 atmegadci_do_poll(&sc->sc_bus); 1306 1307 return (0); /* success */ 1308 } 1309 1310 void 1311 atmegadci_uninit(struct atmegadci_softc *sc) 1312 { 1313 USB_BUS_LOCK(&sc->sc_bus); 1314 1315 /* turn on clocks */ 1316 (sc->sc_clocks_on) (&sc->sc_bus); 1317 1318 /* disable interrupts */ 1319 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN, 0); 1320 1321 /* reset all endpoints */ 1322 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 1323 (1 << ATMEGA_EP_MAX) - 1); 1324 1325 /* disable reset */ 1326 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 0); 1327 1328 sc->sc_flags.port_powered = 0; 1329 sc->sc_flags.status_vbus = 0; 1330 sc->sc_flags.status_bus_reset = 0; 1331 sc->sc_flags.status_suspend = 0; 1332 sc->sc_flags.change_suspend = 0; 1333 sc->sc_flags.change_connect = 1; 1334 1335 atmegadci_pull_down(sc); 1336 atmegadci_clocks_off(sc); 1337 1338 /* disable USB PAD regulator */ 1339 ATMEGA_WRITE_1(sc, ATMEGA_UHWCON, 0); 1340 1341 USB_BUS_UNLOCK(&sc->sc_bus); 1342 } 1343 1344 static void 1345 atmegadci_suspend(struct atmegadci_softc *sc) 1346 { 1347 /* TODO */ 1348 } 1349 1350 static void 1351 atmegadci_resume(struct atmegadci_softc *sc) 1352 { 1353 /* TODO */ 1354 } 1355 1356 static void 1357 atmegadci_do_poll(struct usb_bus *bus) 1358 { 1359 struct atmegadci_softc *sc = ATMEGA_BUS2SC(bus); 1360 1361 USB_BUS_LOCK(&sc->sc_bus); 1362 atmegadci_interrupt_poll(sc); 1363 USB_BUS_UNLOCK(&sc->sc_bus); 1364 } 1365 1366 /*------------------------------------------------------------------------* 1367 * atmegadci bulk support 1368 * atmegadci control support 1369 * atmegadci interrupt support 1370 *------------------------------------------------------------------------*/ 1371 static void 1372 atmegadci_device_non_isoc_open(struct usb_xfer *xfer) 1373 { 1374 return; 1375 } 1376 1377 static void 1378 atmegadci_device_non_isoc_close(struct usb_xfer *xfer) 1379 { 1380 atmegadci_device_done(xfer, USB_ERR_CANCELLED); 1381 } 1382 1383 static void 1384 atmegadci_device_non_isoc_enter(struct usb_xfer *xfer) 1385 { 1386 return; 1387 } 1388 1389 static void 1390 atmegadci_device_non_isoc_start(struct usb_xfer *xfer) 1391 { 1392 /* setup TDs */ 1393 atmegadci_setup_standard_chain(xfer); 1394 atmegadci_start_standard_chain(xfer); 1395 } 1396 1397 static const struct usb_pipe_methods atmegadci_device_non_isoc_methods = 1398 { 1399 .open = atmegadci_device_non_isoc_open, 1400 .close = atmegadci_device_non_isoc_close, 1401 .enter = atmegadci_device_non_isoc_enter, 1402 .start = atmegadci_device_non_isoc_start, 1403 }; 1404 1405 /*------------------------------------------------------------------------* 1406 * atmegadci full speed isochronous support 1407 *------------------------------------------------------------------------*/ 1408 static void 1409 atmegadci_device_isoc_fs_open(struct usb_xfer *xfer) 1410 { 1411 return; 1412 } 1413 1414 static void 1415 atmegadci_device_isoc_fs_close(struct usb_xfer *xfer) 1416 { 1417 atmegadci_device_done(xfer, USB_ERR_CANCELLED); 1418 } 1419 1420 static void 1421 atmegadci_device_isoc_fs_enter(struct usb_xfer *xfer) 1422 { 1423 struct atmegadci_softc *sc = ATMEGA_BUS2SC(xfer->xroot->bus); 1424 uint32_t nframes; 1425 1426 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 1427 xfer, xfer->endpoint->isoc_next, xfer->nframes); 1428 1429 /* get the current frame index */ 1430 1431 nframes = 1432 (ATMEGA_READ_1(sc, ATMEGA_UDFNUMH) << 8) | 1433 (ATMEGA_READ_1(sc, ATMEGA_UDFNUML)); 1434 1435 if (usbd_xfer_get_isochronous_start_frame( 1436 xfer, nframes, 0, 1, ATMEGA_FRAME_MASK, NULL)) 1437 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 1438 1439 /* setup TDs */ 1440 atmegadci_setup_standard_chain(xfer); 1441 } 1442 1443 static void 1444 atmegadci_device_isoc_fs_start(struct usb_xfer *xfer) 1445 { 1446 /* start TD chain */ 1447 atmegadci_start_standard_chain(xfer); 1448 } 1449 1450 static const struct usb_pipe_methods atmegadci_device_isoc_fs_methods = 1451 { 1452 .open = atmegadci_device_isoc_fs_open, 1453 .close = atmegadci_device_isoc_fs_close, 1454 .enter = atmegadci_device_isoc_fs_enter, 1455 .start = atmegadci_device_isoc_fs_start, 1456 }; 1457 1458 /*------------------------------------------------------------------------* 1459 * atmegadci root control support 1460 *------------------------------------------------------------------------* 1461 * Simulate a hardware HUB by handling all the necessary requests. 1462 *------------------------------------------------------------------------*/ 1463 1464 static const struct usb_device_descriptor atmegadci_devd = { 1465 .bLength = sizeof(struct usb_device_descriptor), 1466 .bDescriptorType = UDESC_DEVICE, 1467 .bcdUSB = {0x00, 0x02}, 1468 .bDeviceClass = UDCLASS_HUB, 1469 .bDeviceSubClass = UDSUBCLASS_HUB, 1470 .bDeviceProtocol = UDPROTO_FSHUB, 1471 .bMaxPacketSize = 64, 1472 .bcdDevice = {0x00, 0x01}, 1473 .iManufacturer = 1, 1474 .iProduct = 2, 1475 .bNumConfigurations = 1, 1476 }; 1477 1478 static const struct atmegadci_config_desc atmegadci_confd = { 1479 .confd = { 1480 .bLength = sizeof(struct usb_config_descriptor), 1481 .bDescriptorType = UDESC_CONFIG, 1482 .wTotalLength[0] = sizeof(atmegadci_confd), 1483 .bNumInterface = 1, 1484 .bConfigurationValue = 1, 1485 .iConfiguration = 0, 1486 .bmAttributes = UC_SELF_POWERED, 1487 .bMaxPower = 0, 1488 }, 1489 .ifcd = { 1490 .bLength = sizeof(struct usb_interface_descriptor), 1491 .bDescriptorType = UDESC_INTERFACE, 1492 .bNumEndpoints = 1, 1493 .bInterfaceClass = UICLASS_HUB, 1494 .bInterfaceSubClass = UISUBCLASS_HUB, 1495 .bInterfaceProtocol = 0, 1496 }, 1497 .endpd = { 1498 .bLength = sizeof(struct usb_endpoint_descriptor), 1499 .bDescriptorType = UDESC_ENDPOINT, 1500 .bEndpointAddress = (UE_DIR_IN | ATMEGA_INTR_ENDPT), 1501 .bmAttributes = UE_INTERRUPT, 1502 .wMaxPacketSize[0] = 8, 1503 .bInterval = 255, 1504 }, 1505 }; 1506 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) } 1507 1508 static const struct usb_hub_descriptor_min atmegadci_hubd = { 1509 .bDescLength = sizeof(atmegadci_hubd), 1510 .bDescriptorType = UDESC_HUB, 1511 .bNbrPorts = 1, 1512 HSETW(.wHubCharacteristics, (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL)), 1513 .bPwrOn2PwrGood = 50, 1514 .bHubContrCurrent = 0, 1515 .DeviceRemovable = {0}, /* port is removable */ 1516 }; 1517 1518 #define STRING_VENDOR \ 1519 "A\0T\0M\0E\0G\0A" 1520 1521 #define STRING_PRODUCT \ 1522 "D\0C\0I\0 \0R\0o\0o\0t\0 \0H\0U\0B" 1523 1524 USB_MAKE_STRING_DESC(STRING_VENDOR, atmegadci_vendor); 1525 USB_MAKE_STRING_DESC(STRING_PRODUCT, atmegadci_product); 1526 1527 static usb_error_t 1528 atmegadci_roothub_exec(struct usb_device *udev, 1529 struct usb_device_request *req, const void **pptr, uint16_t *plength) 1530 { 1531 struct atmegadci_softc *sc = ATMEGA_BUS2SC(udev->bus); 1532 const void *ptr; 1533 uint16_t len; 1534 uint16_t value; 1535 uint16_t index; 1536 uint8_t temp; 1537 usb_error_t err; 1538 1539 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1540 1541 /* buffer reset */ 1542 ptr = (const void *)&sc->sc_hub_temp; 1543 len = 0; 1544 err = 0; 1545 1546 value = UGETW(req->wValue); 1547 index = UGETW(req->wIndex); 1548 1549 /* demultiplex the control request */ 1550 1551 switch (req->bmRequestType) { 1552 case UT_READ_DEVICE: 1553 switch (req->bRequest) { 1554 case UR_GET_DESCRIPTOR: 1555 goto tr_handle_get_descriptor; 1556 case UR_GET_CONFIG: 1557 goto tr_handle_get_config; 1558 case UR_GET_STATUS: 1559 goto tr_handle_get_status; 1560 default: 1561 goto tr_stalled; 1562 } 1563 break; 1564 1565 case UT_WRITE_DEVICE: 1566 switch (req->bRequest) { 1567 case UR_SET_ADDRESS: 1568 goto tr_handle_set_address; 1569 case UR_SET_CONFIG: 1570 goto tr_handle_set_config; 1571 case UR_CLEAR_FEATURE: 1572 goto tr_valid; /* nop */ 1573 case UR_SET_DESCRIPTOR: 1574 goto tr_valid; /* nop */ 1575 case UR_SET_FEATURE: 1576 default: 1577 goto tr_stalled; 1578 } 1579 break; 1580 1581 case UT_WRITE_ENDPOINT: 1582 switch (req->bRequest) { 1583 case UR_CLEAR_FEATURE: 1584 switch (UGETW(req->wValue)) { 1585 case UF_ENDPOINT_HALT: 1586 goto tr_handle_clear_halt; 1587 case UF_DEVICE_REMOTE_WAKEUP: 1588 goto tr_handle_clear_wakeup; 1589 default: 1590 goto tr_stalled; 1591 } 1592 break; 1593 case UR_SET_FEATURE: 1594 switch (UGETW(req->wValue)) { 1595 case UF_ENDPOINT_HALT: 1596 goto tr_handle_set_halt; 1597 case UF_DEVICE_REMOTE_WAKEUP: 1598 goto tr_handle_set_wakeup; 1599 default: 1600 goto tr_stalled; 1601 } 1602 break; 1603 case UR_SYNCH_FRAME: 1604 goto tr_valid; /* nop */ 1605 default: 1606 goto tr_stalled; 1607 } 1608 break; 1609 1610 case UT_READ_ENDPOINT: 1611 switch (req->bRequest) { 1612 case UR_GET_STATUS: 1613 goto tr_handle_get_ep_status; 1614 default: 1615 goto tr_stalled; 1616 } 1617 break; 1618 1619 case UT_WRITE_INTERFACE: 1620 switch (req->bRequest) { 1621 case UR_SET_INTERFACE: 1622 goto tr_handle_set_interface; 1623 case UR_CLEAR_FEATURE: 1624 goto tr_valid; /* nop */ 1625 case UR_SET_FEATURE: 1626 default: 1627 goto tr_stalled; 1628 } 1629 break; 1630 1631 case UT_READ_INTERFACE: 1632 switch (req->bRequest) { 1633 case UR_GET_INTERFACE: 1634 goto tr_handle_get_interface; 1635 case UR_GET_STATUS: 1636 goto tr_handle_get_iface_status; 1637 default: 1638 goto tr_stalled; 1639 } 1640 break; 1641 1642 case UT_WRITE_CLASS_INTERFACE: 1643 case UT_WRITE_VENDOR_INTERFACE: 1644 /* XXX forward */ 1645 break; 1646 1647 case UT_READ_CLASS_INTERFACE: 1648 case UT_READ_VENDOR_INTERFACE: 1649 /* XXX forward */ 1650 break; 1651 1652 case UT_WRITE_CLASS_DEVICE: 1653 switch (req->bRequest) { 1654 case UR_CLEAR_FEATURE: 1655 goto tr_valid; 1656 case UR_SET_DESCRIPTOR: 1657 case UR_SET_FEATURE: 1658 break; 1659 default: 1660 goto tr_stalled; 1661 } 1662 break; 1663 1664 case UT_WRITE_CLASS_OTHER: 1665 switch (req->bRequest) { 1666 case UR_CLEAR_FEATURE: 1667 goto tr_handle_clear_port_feature; 1668 case UR_SET_FEATURE: 1669 goto tr_handle_set_port_feature; 1670 case UR_CLEAR_TT_BUFFER: 1671 case UR_RESET_TT: 1672 case UR_STOP_TT: 1673 goto tr_valid; 1674 1675 default: 1676 goto tr_stalled; 1677 } 1678 break; 1679 1680 case UT_READ_CLASS_OTHER: 1681 switch (req->bRequest) { 1682 case UR_GET_TT_STATE: 1683 goto tr_handle_get_tt_state; 1684 case UR_GET_STATUS: 1685 goto tr_handle_get_port_status; 1686 default: 1687 goto tr_stalled; 1688 } 1689 break; 1690 1691 case UT_READ_CLASS_DEVICE: 1692 switch (req->bRequest) { 1693 case UR_GET_DESCRIPTOR: 1694 goto tr_handle_get_class_descriptor; 1695 case UR_GET_STATUS: 1696 goto tr_handle_get_class_status; 1697 1698 default: 1699 goto tr_stalled; 1700 } 1701 break; 1702 default: 1703 goto tr_stalled; 1704 } 1705 goto tr_valid; 1706 1707 tr_handle_get_descriptor: 1708 switch (value >> 8) { 1709 case UDESC_DEVICE: 1710 if (value & 0xff) { 1711 goto tr_stalled; 1712 } 1713 len = sizeof(atmegadci_devd); 1714 ptr = (const void *)&atmegadci_devd; 1715 goto tr_valid; 1716 case UDESC_CONFIG: 1717 if (value & 0xff) { 1718 goto tr_stalled; 1719 } 1720 len = sizeof(atmegadci_confd); 1721 ptr = (const void *)&atmegadci_confd; 1722 goto tr_valid; 1723 case UDESC_STRING: 1724 switch (value & 0xff) { 1725 case 0: /* Language table */ 1726 len = sizeof(usb_string_lang_en); 1727 ptr = (const void *)&usb_string_lang_en; 1728 goto tr_valid; 1729 1730 case 1: /* Vendor */ 1731 len = sizeof(atmegadci_vendor); 1732 ptr = (const void *)&atmegadci_vendor; 1733 goto tr_valid; 1734 1735 case 2: /* Product */ 1736 len = sizeof(atmegadci_product); 1737 ptr = (const void *)&atmegadci_product; 1738 goto tr_valid; 1739 default: 1740 break; 1741 } 1742 break; 1743 default: 1744 goto tr_stalled; 1745 } 1746 goto tr_stalled; 1747 1748 tr_handle_get_config: 1749 len = 1; 1750 sc->sc_hub_temp.wValue[0] = sc->sc_conf; 1751 goto tr_valid; 1752 1753 tr_handle_get_status: 1754 len = 2; 1755 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED); 1756 goto tr_valid; 1757 1758 tr_handle_set_address: 1759 if (value & 0xFF00) { 1760 goto tr_stalled; 1761 } 1762 sc->sc_rt_addr = value; 1763 goto tr_valid; 1764 1765 tr_handle_set_config: 1766 if (value >= 2) { 1767 goto tr_stalled; 1768 } 1769 sc->sc_conf = value; 1770 goto tr_valid; 1771 1772 tr_handle_get_interface: 1773 len = 1; 1774 sc->sc_hub_temp.wValue[0] = 0; 1775 goto tr_valid; 1776 1777 tr_handle_get_tt_state: 1778 tr_handle_get_class_status: 1779 tr_handle_get_iface_status: 1780 tr_handle_get_ep_status: 1781 len = 2; 1782 USETW(sc->sc_hub_temp.wValue, 0); 1783 goto tr_valid; 1784 1785 tr_handle_set_halt: 1786 tr_handle_set_interface: 1787 tr_handle_set_wakeup: 1788 tr_handle_clear_wakeup: 1789 tr_handle_clear_halt: 1790 goto tr_valid; 1791 1792 tr_handle_clear_port_feature: 1793 if (index != 1) { 1794 goto tr_stalled; 1795 } 1796 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE on port %d\n", index); 1797 1798 switch (value) { 1799 case UHF_PORT_SUSPEND: 1800 atmegadci_wakeup_peer(sc); 1801 break; 1802 1803 case UHF_PORT_ENABLE: 1804 sc->sc_flags.port_enabled = 0; 1805 break; 1806 1807 case UHF_PORT_TEST: 1808 case UHF_PORT_INDICATOR: 1809 case UHF_C_PORT_ENABLE: 1810 case UHF_C_PORT_OVER_CURRENT: 1811 case UHF_C_PORT_RESET: 1812 /* nops */ 1813 break; 1814 case UHF_PORT_POWER: 1815 sc->sc_flags.port_powered = 0; 1816 atmegadci_pull_down(sc); 1817 atmegadci_clocks_off(sc); 1818 break; 1819 case UHF_C_PORT_CONNECTION: 1820 /* clear connect change flag */ 1821 sc->sc_flags.change_connect = 0; 1822 1823 if (!sc->sc_flags.status_bus_reset) { 1824 /* we are not connected */ 1825 break; 1826 } 1827 1828 /* configure the control endpoint */ 1829 1830 /* select endpoint number */ 1831 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, 0); 1832 1833 /* set endpoint reset */ 1834 ATMEGA_WRITE_1(sc, ATMEGA_UERST, ATMEGA_UERST_MASK(0)); 1835 1836 /* clear endpoint reset */ 1837 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 0); 1838 1839 /* enable and stall endpoint */ 1840 ATMEGA_WRITE_1(sc, ATMEGA_UECONX, 1841 ATMEGA_UECONX_EPEN | 1842 ATMEGA_UECONX_STALLRQ); 1843 1844 /* one bank, 64-bytes wMaxPacket */ 1845 ATMEGA_WRITE_1(sc, ATMEGA_UECFG0X, 1846 ATMEGA_UECFG0X_EPTYPE0); 1847 ATMEGA_WRITE_1(sc, ATMEGA_UECFG1X, 1848 ATMEGA_UECFG1X_ALLOC | 1849 ATMEGA_UECFG1X_EPBK0 | 1850 ATMEGA_UECFG1X_EPSIZE(3)); 1851 1852 /* check valid config */ 1853 temp = ATMEGA_READ_1(sc, ATMEGA_UESTA0X); 1854 if (!(temp & ATMEGA_UESTA0X_CFGOK)) { 1855 device_printf(sc->sc_bus.bdev, 1856 "Chip rejected EP0 configuration\n"); 1857 } 1858 break; 1859 case UHF_C_PORT_SUSPEND: 1860 sc->sc_flags.change_suspend = 0; 1861 break; 1862 default: 1863 err = USB_ERR_IOERROR; 1864 goto done; 1865 } 1866 goto tr_valid; 1867 1868 tr_handle_set_port_feature: 1869 if (index != 1) { 1870 goto tr_stalled; 1871 } 1872 DPRINTFN(9, "UR_SET_PORT_FEATURE\n"); 1873 1874 switch (value) { 1875 case UHF_PORT_ENABLE: 1876 sc->sc_flags.port_enabled = 1; 1877 break; 1878 case UHF_PORT_SUSPEND: 1879 case UHF_PORT_RESET: 1880 case UHF_PORT_TEST: 1881 case UHF_PORT_INDICATOR: 1882 /* nops */ 1883 break; 1884 case UHF_PORT_POWER: 1885 sc->sc_flags.port_powered = 1; 1886 break; 1887 default: 1888 err = USB_ERR_IOERROR; 1889 goto done; 1890 } 1891 goto tr_valid; 1892 1893 tr_handle_get_port_status: 1894 1895 DPRINTFN(9, "UR_GET_PORT_STATUS\n"); 1896 1897 if (index != 1) { 1898 goto tr_stalled; 1899 } 1900 if (sc->sc_flags.status_vbus) { 1901 atmegadci_clocks_on(sc); 1902 atmegadci_pull_up(sc); 1903 } else { 1904 atmegadci_pull_down(sc); 1905 atmegadci_clocks_off(sc); 1906 } 1907 1908 /* Select FULL-speed and Device Side Mode */ 1909 1910 value = UPS_PORT_MODE_DEVICE; 1911 1912 if (sc->sc_flags.port_powered) { 1913 value |= UPS_PORT_POWER; 1914 } 1915 if (sc->sc_flags.port_enabled) { 1916 value |= UPS_PORT_ENABLED; 1917 } 1918 if (sc->sc_flags.status_vbus && 1919 sc->sc_flags.status_bus_reset) { 1920 value |= UPS_CURRENT_CONNECT_STATUS; 1921 } 1922 if (sc->sc_flags.status_suspend) { 1923 value |= UPS_SUSPEND; 1924 } 1925 USETW(sc->sc_hub_temp.ps.wPortStatus, value); 1926 1927 value = 0; 1928 1929 if (sc->sc_flags.change_connect) { 1930 value |= UPS_C_CONNECT_STATUS; 1931 } 1932 if (sc->sc_flags.change_suspend) { 1933 value |= UPS_C_SUSPEND; 1934 } 1935 USETW(sc->sc_hub_temp.ps.wPortChange, value); 1936 len = sizeof(sc->sc_hub_temp.ps); 1937 goto tr_valid; 1938 1939 tr_handle_get_class_descriptor: 1940 if (value & 0xFF) { 1941 goto tr_stalled; 1942 } 1943 ptr = (const void *)&atmegadci_hubd; 1944 len = sizeof(atmegadci_hubd); 1945 goto tr_valid; 1946 1947 tr_stalled: 1948 err = USB_ERR_STALLED; 1949 tr_valid: 1950 done: 1951 *plength = len; 1952 *pptr = ptr; 1953 return (err); 1954 } 1955 1956 static void 1957 atmegadci_xfer_setup(struct usb_setup_params *parm) 1958 { 1959 const struct usb_hw_ep_profile *pf; 1960 struct atmegadci_softc *sc; 1961 struct usb_xfer *xfer; 1962 void *last_obj; 1963 uint32_t ntd; 1964 uint32_t n; 1965 uint8_t ep_no; 1966 1967 sc = ATMEGA_BUS2SC(parm->udev->bus); 1968 xfer = parm->curr_xfer; 1969 1970 /* 1971 * NOTE: This driver does not use any of the parameters that 1972 * are computed from the following values. Just set some 1973 * reasonable dummies: 1974 */ 1975 parm->hc_max_packet_size = 0x500; 1976 parm->hc_max_packet_count = 1; 1977 parm->hc_max_frame_size = 0x500; 1978 1979 usbd_transfer_setup_sub(parm); 1980 1981 /* 1982 * compute maximum number of TDs 1983 */ 1984 if ((xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) { 1985 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC 1 */ 1986 + 1 /* SYNC 2 */ ; 1987 } else { 1988 ntd = xfer->nframes + 1 /* SYNC */ ; 1989 } 1990 1991 /* 1992 * check if "usbd_transfer_setup_sub" set an error 1993 */ 1994 if (parm->err) 1995 return; 1996 1997 /* 1998 * allocate transfer descriptors 1999 */ 2000 last_obj = NULL; 2001 2002 /* 2003 * get profile stuff 2004 */ 2005 ep_no = xfer->endpointno & UE_ADDR; 2006 atmegadci_get_hw_ep_profile(parm->udev, &pf, ep_no); 2007 2008 if (pf == NULL) { 2009 /* should not happen */ 2010 parm->err = USB_ERR_INVAL; 2011 return; 2012 } 2013 2014 /* align data */ 2015 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1)); 2016 2017 for (n = 0; n != ntd; n++) { 2018 struct atmegadci_td *td; 2019 2020 if (parm->buf) { 2021 td = USB_ADD_BYTES(parm->buf, parm->size[0]); 2022 2023 /* init TD */ 2024 td->max_packet_size = xfer->max_packet_size; 2025 td->ep_no = ep_no; 2026 if (pf->support_multi_buffer) { 2027 td->support_multi_buffer = 1; 2028 } 2029 td->obj_next = last_obj; 2030 2031 last_obj = td; 2032 } 2033 parm->size[0] += sizeof(*td); 2034 } 2035 2036 xfer->td_start[0] = last_obj; 2037 } 2038 2039 static void 2040 atmegadci_xfer_unsetup(struct usb_xfer *xfer) 2041 { 2042 return; 2043 } 2044 2045 static void 2046 atmegadci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 2047 struct usb_endpoint *ep) 2048 { 2049 struct atmegadci_softc *sc = ATMEGA_BUS2SC(udev->bus); 2050 2051 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d,%d)\n", 2052 ep, udev->address, 2053 edesc->bEndpointAddress, udev->flags.usb_mode, 2054 sc->sc_rt_addr, udev->device_index); 2055 2056 if (udev->device_index != sc->sc_rt_addr) { 2057 if (udev->speed != USB_SPEED_FULL) { 2058 /* not supported */ 2059 return; 2060 } 2061 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_ISOCHRONOUS) 2062 ep->methods = &atmegadci_device_isoc_fs_methods; 2063 else 2064 ep->methods = &atmegadci_device_non_isoc_methods; 2065 } 2066 } 2067 2068 static void 2069 atmegadci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 2070 { 2071 struct atmegadci_softc *sc = ATMEGA_BUS2SC(bus); 2072 2073 switch (state) { 2074 case USB_HW_POWER_SUSPEND: 2075 atmegadci_suspend(sc); 2076 break; 2077 case USB_HW_POWER_SHUTDOWN: 2078 atmegadci_uninit(sc); 2079 break; 2080 case USB_HW_POWER_RESUME: 2081 atmegadci_resume(sc); 2082 break; 2083 default: 2084 break; 2085 } 2086 } 2087 2088 static const struct usb_bus_methods atmegadci_bus_methods = 2089 { 2090 .endpoint_init = &atmegadci_ep_init, 2091 .xfer_setup = &atmegadci_xfer_setup, 2092 .xfer_unsetup = &atmegadci_xfer_unsetup, 2093 .get_hw_ep_profile = &atmegadci_get_hw_ep_profile, 2094 .xfer_stall = &atmegadci_xfer_stall, 2095 .set_stall = &atmegadci_set_stall, 2096 .clear_stall = &atmegadci_clear_stall, 2097 .roothub_exec = &atmegadci_roothub_exec, 2098 .xfer_poll = &atmegadci_do_poll, 2099 .set_hw_power_sleep = &atmegadci_set_hw_power_sleep, 2100 }; 2101