1 /* $FreeBSD$ */ 2 /*- 3 * Copyright (c) 2009 Hans Petter Selasky. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 /* 28 * This file contains the driver for the ATMEGA series USB OTG Controller. This 29 * driver currently only supports the DCI mode of the USB hardware. 30 */ 31 32 /* 33 * NOTE: When the chip detects BUS-reset it will also reset the 34 * endpoints, Function-address and more. 35 */ 36 37 #ifdef USB_GLOBAL_INCLUDE_FILE 38 #include USB_GLOBAL_INCLUDE_FILE 39 #else 40 #include <sys/stdint.h> 41 #include <sys/stddef.h> 42 #include <sys/param.h> 43 #include <sys/queue.h> 44 #include <sys/types.h> 45 #include <sys/systm.h> 46 #include <sys/kernel.h> 47 #include <sys/bus.h> 48 #include <sys/module.h> 49 #include <sys/lock.h> 50 #include <sys/mutex.h> 51 #include <sys/condvar.h> 52 #include <sys/sysctl.h> 53 #include <sys/sx.h> 54 #include <sys/unistd.h> 55 #include <sys/callout.h> 56 #include <sys/malloc.h> 57 #include <sys/priv.h> 58 59 #include <dev/usb/usb.h> 60 #include <dev/usb/usbdi.h> 61 62 #define USB_DEBUG_VAR atmegadci_debug 63 64 #include <dev/usb/usb_core.h> 65 #include <dev/usb/usb_debug.h> 66 #include <dev/usb/usb_busdma.h> 67 #include <dev/usb/usb_process.h> 68 #include <dev/usb/usb_transfer.h> 69 #include <dev/usb/usb_device.h> 70 #include <dev/usb/usb_hub.h> 71 #include <dev/usb/usb_util.h> 72 73 #include <dev/usb/usb_controller.h> 74 #include <dev/usb/usb_bus.h> 75 #endif /* USB_GLOBAL_INCLUDE_FILE */ 76 77 #include <dev/usb/controller/atmegadci.h> 78 79 #define ATMEGA_BUS2SC(bus) \ 80 ((struct atmegadci_softc *)(((uint8_t *)(bus)) - \ 81 ((uint8_t *)&(((struct atmegadci_softc *)0)->sc_bus)))) 82 83 #define ATMEGA_PC2SC(pc) \ 84 ATMEGA_BUS2SC(USB_DMATAG_TO_XROOT((pc)->tag_parent)->bus) 85 86 #ifdef USB_DEBUG 87 static int atmegadci_debug = 0; 88 89 static SYSCTL_NODE(_hw_usb, OID_AUTO, atmegadci, CTLFLAG_RW, 0, 90 "USB ATMEGA DCI"); 91 SYSCTL_INT(_hw_usb_atmegadci, OID_AUTO, debug, CTLFLAG_RWTUN, 92 &atmegadci_debug, 0, "ATMEGA DCI debug level"); 93 #endif 94 95 #define ATMEGA_INTR_ENDPT 1 96 97 /* prototypes */ 98 99 static const struct usb_bus_methods atmegadci_bus_methods; 100 static const struct usb_pipe_methods atmegadci_device_non_isoc_methods; 101 static const struct usb_pipe_methods atmegadci_device_isoc_fs_methods; 102 103 static atmegadci_cmd_t atmegadci_setup_rx; 104 static atmegadci_cmd_t atmegadci_data_rx; 105 static atmegadci_cmd_t atmegadci_data_tx; 106 static atmegadci_cmd_t atmegadci_data_tx_sync; 107 static void atmegadci_device_done(struct usb_xfer *, usb_error_t); 108 static void atmegadci_do_poll(struct usb_bus *); 109 static void atmegadci_standard_done(struct usb_xfer *); 110 static void atmegadci_root_intr(struct atmegadci_softc *sc); 111 112 /* 113 * Here is a list of what the chip supports: 114 */ 115 static const struct usb_hw_ep_profile 116 atmegadci_ep_profile[2] = { 117 118 [0] = { 119 .max_in_frame_size = 64, 120 .max_out_frame_size = 64, 121 .is_simplex = 1, 122 .support_control = 1, 123 }, 124 [1] = { 125 .max_in_frame_size = 64, 126 .max_out_frame_size = 64, 127 .is_simplex = 1, 128 .support_bulk = 1, 129 .support_interrupt = 1, 130 .support_isochronous = 1, 131 .support_in = 1, 132 .support_out = 1, 133 }, 134 }; 135 136 static void 137 atmegadci_get_hw_ep_profile(struct usb_device *udev, 138 const struct usb_hw_ep_profile **ppf, uint8_t ep_addr) 139 { 140 if (ep_addr == 0) 141 *ppf = atmegadci_ep_profile; 142 else if (ep_addr < ATMEGA_EP_MAX) 143 *ppf = atmegadci_ep_profile + 1; 144 else 145 *ppf = NULL; 146 } 147 148 static void 149 atmegadci_clocks_on(struct atmegadci_softc *sc) 150 { 151 if (sc->sc_flags.clocks_off && 152 sc->sc_flags.port_powered) { 153 154 DPRINTFN(5, "\n"); 155 156 /* turn on clocks */ 157 (sc->sc_clocks_on) (&sc->sc_bus); 158 159 ATMEGA_WRITE_1(sc, ATMEGA_USBCON, 160 ATMEGA_USBCON_USBE | 161 ATMEGA_USBCON_OTGPADE | 162 ATMEGA_USBCON_VBUSTE); 163 164 sc->sc_flags.clocks_off = 0; 165 166 /* enable transceiver ? */ 167 } 168 } 169 170 static void 171 atmegadci_clocks_off(struct atmegadci_softc *sc) 172 { 173 if (!sc->sc_flags.clocks_off) { 174 175 DPRINTFN(5, "\n"); 176 177 /* disable Transceiver ? */ 178 179 ATMEGA_WRITE_1(sc, ATMEGA_USBCON, 180 ATMEGA_USBCON_USBE | 181 ATMEGA_USBCON_OTGPADE | 182 ATMEGA_USBCON_FRZCLK | 183 ATMEGA_USBCON_VBUSTE); 184 185 /* turn clocks off */ 186 (sc->sc_clocks_off) (&sc->sc_bus); 187 188 sc->sc_flags.clocks_off = 1; 189 } 190 } 191 192 static void 193 atmegadci_pull_up(struct atmegadci_softc *sc) 194 { 195 /* pullup D+, if possible */ 196 197 if (!sc->sc_flags.d_pulled_up && 198 sc->sc_flags.port_powered) { 199 sc->sc_flags.d_pulled_up = 1; 200 ATMEGA_WRITE_1(sc, ATMEGA_UDCON, 0); 201 } 202 } 203 204 static void 205 atmegadci_pull_down(struct atmegadci_softc *sc) 206 { 207 /* pulldown D+, if possible */ 208 209 if (sc->sc_flags.d_pulled_up) { 210 sc->sc_flags.d_pulled_up = 0; 211 ATMEGA_WRITE_1(sc, ATMEGA_UDCON, ATMEGA_UDCON_DETACH); 212 } 213 } 214 215 static void 216 atmegadci_wakeup_peer(struct atmegadci_softc *sc) 217 { 218 uint8_t temp; 219 220 if (!sc->sc_flags.status_suspend) { 221 return; 222 } 223 224 temp = ATMEGA_READ_1(sc, ATMEGA_UDCON); 225 ATMEGA_WRITE_1(sc, ATMEGA_UDCON, temp | ATMEGA_UDCON_RMWKUP); 226 227 /* wait 8 milliseconds */ 228 /* Wait for reset to complete. */ 229 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125); 230 231 /* hardware should have cleared RMWKUP bit */ 232 } 233 234 static void 235 atmegadci_set_address(struct atmegadci_softc *sc, uint8_t addr) 236 { 237 DPRINTFN(5, "addr=%d\n", addr); 238 239 addr |= ATMEGA_UDADDR_ADDEN; 240 241 ATMEGA_WRITE_1(sc, ATMEGA_UDADDR, addr); 242 } 243 244 static uint8_t 245 atmegadci_setup_rx(struct atmegadci_td *td) 246 { 247 struct atmegadci_softc *sc; 248 struct usb_device_request req; 249 uint16_t count; 250 uint8_t temp; 251 252 /* get pointer to softc */ 253 sc = ATMEGA_PC2SC(td->pc); 254 255 /* select endpoint number */ 256 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, td->ep_no); 257 258 /* check endpoint status */ 259 temp = ATMEGA_READ_1(sc, ATMEGA_UEINTX); 260 261 DPRINTFN(5, "UEINTX=0x%02x\n", temp); 262 263 if (!(temp & ATMEGA_UEINTX_RXSTPI)) { 264 goto not_complete; 265 } 266 /* clear did stall */ 267 td->did_stall = 0; 268 /* get the packet byte count */ 269 count = 270 (ATMEGA_READ_1(sc, ATMEGA_UEBCHX) << 8) | 271 (ATMEGA_READ_1(sc, ATMEGA_UEBCLX)); 272 273 /* mask away undefined bits */ 274 count &= 0x7FF; 275 276 /* verify data length */ 277 if (count != td->remainder) { 278 DPRINTFN(0, "Invalid SETUP packet " 279 "length, %d bytes\n", count); 280 goto not_complete; 281 } 282 if (count != sizeof(req)) { 283 DPRINTFN(0, "Unsupported SETUP packet " 284 "length, %d bytes\n", count); 285 goto not_complete; 286 } 287 /* receive data */ 288 ATMEGA_READ_MULTI_1(sc, ATMEGA_UEDATX, 289 (void *)&req, sizeof(req)); 290 291 /* copy data into real buffer */ 292 usbd_copy_in(td->pc, 0, &req, sizeof(req)); 293 294 td->offset = sizeof(req); 295 td->remainder = 0; 296 297 /* sneak peek the set address */ 298 if ((req.bmRequestType == UT_WRITE_DEVICE) && 299 (req.bRequest == UR_SET_ADDRESS)) { 300 sc->sc_dv_addr = req.wValue[0] & 0x7F; 301 /* must write address before ZLP */ 302 ATMEGA_WRITE_1(sc, ATMEGA_UDADDR, sc->sc_dv_addr); 303 } else { 304 sc->sc_dv_addr = 0xFF; 305 } 306 307 /* Clear SETUP packet interrupt and all other previous interrupts */ 308 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, 0); 309 return (0); /* complete */ 310 311 not_complete: 312 /* abort any ongoing transfer */ 313 if (!td->did_stall) { 314 DPRINTFN(5, "stalling\n"); 315 ATMEGA_WRITE_1(sc, ATMEGA_UECONX, 316 ATMEGA_UECONX_EPEN | 317 ATMEGA_UECONX_STALLRQ); 318 td->did_stall = 1; 319 } 320 if (temp & ATMEGA_UEINTX_RXSTPI) { 321 /* clear SETUP packet interrupt */ 322 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, ~ATMEGA_UEINTX_RXSTPI); 323 } 324 /* we only want to know if there is a SETUP packet */ 325 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, ATMEGA_UEIENX_RXSTPE); 326 return (1); /* not complete */ 327 } 328 329 static uint8_t 330 atmegadci_data_rx(struct atmegadci_td *td) 331 { 332 struct atmegadci_softc *sc; 333 struct usb_page_search buf_res; 334 uint16_t count; 335 uint8_t temp; 336 uint8_t to; 337 uint8_t got_short; 338 339 to = 3; /* don't loop forever! */ 340 got_short = 0; 341 342 /* get pointer to softc */ 343 sc = ATMEGA_PC2SC(td->pc); 344 345 /* select endpoint number */ 346 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, td->ep_no); 347 348 repeat: 349 /* check if any of the FIFO banks have data */ 350 /* check endpoint status */ 351 temp = ATMEGA_READ_1(sc, ATMEGA_UEINTX); 352 353 DPRINTFN(5, "temp=0x%02x rem=%u\n", temp, td->remainder); 354 355 if (temp & ATMEGA_UEINTX_RXSTPI) { 356 if (td->remainder == 0) { 357 /* 358 * We are actually complete and have 359 * received the next SETUP 360 */ 361 DPRINTFN(5, "faking complete\n"); 362 return (0); /* complete */ 363 } 364 /* 365 * USB Host Aborted the transfer. 366 */ 367 td->error = 1; 368 return (0); /* complete */ 369 } 370 /* check status */ 371 if (!(temp & (ATMEGA_UEINTX_FIFOCON | 372 ATMEGA_UEINTX_RXOUTI))) { 373 /* no data */ 374 goto not_complete; 375 } 376 /* get the packet byte count */ 377 count = 378 (ATMEGA_READ_1(sc, ATMEGA_UEBCHX) << 8) | 379 (ATMEGA_READ_1(sc, ATMEGA_UEBCLX)); 380 381 /* mask away undefined bits */ 382 count &= 0x7FF; 383 384 /* verify the packet byte count */ 385 if (count != td->max_packet_size) { 386 if (count < td->max_packet_size) { 387 /* we have a short packet */ 388 td->short_pkt = 1; 389 got_short = 1; 390 } else { 391 /* invalid USB packet */ 392 td->error = 1; 393 return (0); /* we are complete */ 394 } 395 } 396 /* verify the packet byte count */ 397 if (count > td->remainder) { 398 /* invalid USB packet */ 399 td->error = 1; 400 return (0); /* we are complete */ 401 } 402 while (count > 0) { 403 usbd_get_page(td->pc, td->offset, &buf_res); 404 405 /* get correct length */ 406 if (buf_res.length > count) { 407 buf_res.length = count; 408 } 409 /* receive data */ 410 ATMEGA_READ_MULTI_1(sc, ATMEGA_UEDATX, 411 buf_res.buffer, buf_res.length); 412 413 /* update counters */ 414 count -= buf_res.length; 415 td->offset += buf_res.length; 416 td->remainder -= buf_res.length; 417 } 418 419 /* clear OUT packet interrupt */ 420 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, ATMEGA_UEINTX_RXOUTI ^ 0xFF); 421 422 /* release FIFO bank */ 423 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, ATMEGA_UEINTX_FIFOCON ^ 0xFF); 424 425 /* check if we are complete */ 426 if ((td->remainder == 0) || got_short) { 427 if (td->short_pkt) { 428 /* we are complete */ 429 return (0); 430 } 431 /* else need to receive a zero length packet */ 432 } 433 if (--to) { 434 goto repeat; 435 } 436 not_complete: 437 /* we only want to know if there is a SETUP packet or OUT packet */ 438 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, 439 ATMEGA_UEIENX_RXSTPE | ATMEGA_UEIENX_RXOUTE); 440 return (1); /* not complete */ 441 } 442 443 static uint8_t 444 atmegadci_data_tx(struct atmegadci_td *td) 445 { 446 struct atmegadci_softc *sc; 447 struct usb_page_search buf_res; 448 uint16_t count; 449 uint8_t to; 450 uint8_t temp; 451 452 to = 3; /* don't loop forever! */ 453 454 /* get pointer to softc */ 455 sc = ATMEGA_PC2SC(td->pc); 456 457 /* select endpoint number */ 458 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, td->ep_no); 459 460 repeat: 461 462 /* check endpoint status */ 463 temp = ATMEGA_READ_1(sc, ATMEGA_UEINTX); 464 465 DPRINTFN(5, "temp=0x%02x rem=%u\n", temp, td->remainder); 466 467 if (temp & ATMEGA_UEINTX_RXSTPI) { 468 /* 469 * The current transfer was aborted 470 * by the USB Host 471 */ 472 td->error = 1; 473 return (0); /* complete */ 474 } 475 476 temp = ATMEGA_READ_1(sc, ATMEGA_UESTA0X); 477 if (temp & 3) { 478 /* cannot write any data - a bank is busy */ 479 goto not_complete; 480 } 481 482 count = td->max_packet_size; 483 if (td->remainder < count) { 484 /* we have a short packet */ 485 td->short_pkt = 1; 486 count = td->remainder; 487 } 488 while (count > 0) { 489 490 usbd_get_page(td->pc, td->offset, &buf_res); 491 492 /* get correct length */ 493 if (buf_res.length > count) { 494 buf_res.length = count; 495 } 496 /* transmit data */ 497 ATMEGA_WRITE_MULTI_1(sc, ATMEGA_UEDATX, 498 buf_res.buffer, buf_res.length); 499 500 /* update counters */ 501 count -= buf_res.length; 502 td->offset += buf_res.length; 503 td->remainder -= buf_res.length; 504 } 505 506 /* clear IN packet interrupt */ 507 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, 0xFF ^ ATMEGA_UEINTX_TXINI); 508 509 /* allocate FIFO bank */ 510 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, 0xFF ^ ATMEGA_UEINTX_FIFOCON); 511 512 /* check remainder */ 513 if (td->remainder == 0) { 514 if (td->short_pkt) { 515 return (0); /* complete */ 516 } 517 /* else we need to transmit a short packet */ 518 } 519 if (--to) { 520 goto repeat; 521 } 522 not_complete: 523 /* we only want to know if there is a SETUP packet or free IN packet */ 524 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, 525 ATMEGA_UEIENX_RXSTPE | ATMEGA_UEIENX_TXINE); 526 return (1); /* not complete */ 527 } 528 529 static uint8_t 530 atmegadci_data_tx_sync(struct atmegadci_td *td) 531 { 532 struct atmegadci_softc *sc; 533 uint8_t temp; 534 535 /* get pointer to softc */ 536 sc = ATMEGA_PC2SC(td->pc); 537 538 /* select endpoint number */ 539 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, td->ep_no); 540 541 /* check endpoint status */ 542 temp = ATMEGA_READ_1(sc, ATMEGA_UEINTX); 543 544 DPRINTFN(5, "temp=0x%02x\n", temp); 545 546 if (temp & ATMEGA_UEINTX_RXSTPI) { 547 DPRINTFN(5, "faking complete\n"); 548 /* Race condition */ 549 return (0); /* complete */ 550 } 551 /* 552 * The control endpoint has only got one bank, so if that bank 553 * is free the packet has been transferred! 554 */ 555 temp = ATMEGA_READ_1(sc, ATMEGA_UESTA0X); 556 if (temp & 3) { 557 /* cannot write any data - a bank is busy */ 558 goto not_complete; 559 } 560 if (sc->sc_dv_addr != 0xFF) { 561 /* set new address */ 562 atmegadci_set_address(sc, sc->sc_dv_addr); 563 } 564 return (0); /* complete */ 565 566 not_complete: 567 /* we only want to know if there is a SETUP packet or free IN packet */ 568 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, 569 ATMEGA_UEIENX_RXSTPE | ATMEGA_UEIENX_TXINE); 570 return (1); /* not complete */ 571 } 572 573 static uint8_t 574 atmegadci_xfer_do_fifo(struct usb_xfer *xfer) 575 { 576 struct atmegadci_td *td; 577 578 DPRINTFN(9, "\n"); 579 580 td = xfer->td_transfer_cache; 581 while (1) { 582 if ((td->func) (td)) { 583 /* operation in progress */ 584 break; 585 } 586 if (((void *)td) == xfer->td_transfer_last) { 587 goto done; 588 } 589 if (td->error) { 590 goto done; 591 } else if (td->remainder > 0) { 592 /* 593 * We had a short transfer. If there is no alternate 594 * next, stop processing ! 595 */ 596 if (!td->alt_next) { 597 goto done; 598 } 599 } 600 /* 601 * Fetch the next transfer descriptor and transfer 602 * some flags to the next transfer descriptor 603 */ 604 td = td->obj_next; 605 xfer->td_transfer_cache = td; 606 } 607 return (1); /* not complete */ 608 609 done: 610 /* compute all actual lengths */ 611 612 atmegadci_standard_done(xfer); 613 return (0); /* complete */ 614 } 615 616 static void 617 atmegadci_interrupt_poll(struct atmegadci_softc *sc) 618 { 619 struct usb_xfer *xfer; 620 621 repeat: 622 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 623 if (!atmegadci_xfer_do_fifo(xfer)) { 624 /* queue has been modified */ 625 goto repeat; 626 } 627 } 628 } 629 630 static void 631 atmegadci_vbus_interrupt(struct atmegadci_softc *sc, uint8_t is_on) 632 { 633 DPRINTFN(5, "vbus = %u\n", is_on); 634 635 if (is_on) { 636 if (!sc->sc_flags.status_vbus) { 637 sc->sc_flags.status_vbus = 1; 638 639 /* complete root HUB interrupt endpoint */ 640 641 atmegadci_root_intr(sc); 642 } 643 } else { 644 if (sc->sc_flags.status_vbus) { 645 sc->sc_flags.status_vbus = 0; 646 sc->sc_flags.status_bus_reset = 0; 647 sc->sc_flags.status_suspend = 0; 648 sc->sc_flags.change_suspend = 0; 649 sc->sc_flags.change_connect = 1; 650 651 /* complete root HUB interrupt endpoint */ 652 653 atmegadci_root_intr(sc); 654 } 655 } 656 } 657 658 void 659 atmegadci_interrupt(struct atmegadci_softc *sc) 660 { 661 uint8_t status; 662 663 USB_BUS_LOCK(&sc->sc_bus); 664 665 /* read interrupt status */ 666 status = ATMEGA_READ_1(sc, ATMEGA_UDINT); 667 668 /* clear all set interrupts */ 669 ATMEGA_WRITE_1(sc, ATMEGA_UDINT, (~status) & 0x7D); 670 671 DPRINTFN(14, "UDINT=0x%02x\n", status); 672 673 /* check for any bus state change interrupts */ 674 if (status & ATMEGA_UDINT_EORSTI) { 675 676 DPRINTFN(5, "end of reset\n"); 677 678 /* set correct state */ 679 sc->sc_flags.status_bus_reset = 1; 680 sc->sc_flags.status_suspend = 0; 681 sc->sc_flags.change_suspend = 0; 682 sc->sc_flags.change_connect = 1; 683 684 /* disable resume interrupt */ 685 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN, 686 ATMEGA_UDINT_SUSPE | 687 ATMEGA_UDINT_EORSTE); 688 689 /* complete root HUB interrupt endpoint */ 690 atmegadci_root_intr(sc); 691 } 692 /* 693 * If resume and suspend is set at the same time we interpret 694 * that like RESUME. Resume is set when there is at least 3 695 * milliseconds of inactivity on the USB BUS. 696 */ 697 if (status & ATMEGA_UDINT_WAKEUPI) { 698 699 DPRINTFN(5, "resume interrupt\n"); 700 701 if (sc->sc_flags.status_suspend) { 702 /* update status bits */ 703 sc->sc_flags.status_suspend = 0; 704 sc->sc_flags.change_suspend = 1; 705 706 /* disable resume interrupt */ 707 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN, 708 ATMEGA_UDINT_SUSPE | 709 ATMEGA_UDINT_EORSTE); 710 711 /* complete root HUB interrupt endpoint */ 712 atmegadci_root_intr(sc); 713 } 714 } else if (status & ATMEGA_UDINT_SUSPI) { 715 716 DPRINTFN(5, "suspend interrupt\n"); 717 718 if (!sc->sc_flags.status_suspend) { 719 /* update status bits */ 720 sc->sc_flags.status_suspend = 1; 721 sc->sc_flags.change_suspend = 1; 722 723 /* disable suspend interrupt */ 724 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN, 725 ATMEGA_UDINT_WAKEUPE | 726 ATMEGA_UDINT_EORSTE); 727 728 /* complete root HUB interrupt endpoint */ 729 atmegadci_root_intr(sc); 730 } 731 } 732 /* check VBUS */ 733 status = ATMEGA_READ_1(sc, ATMEGA_USBINT); 734 735 /* clear all set interrupts */ 736 ATMEGA_WRITE_1(sc, ATMEGA_USBINT, (~status) & 0x03); 737 738 if (status & ATMEGA_USBINT_VBUSTI) { 739 uint8_t temp; 740 741 DPRINTFN(5, "USBINT=0x%02x\n", status); 742 743 temp = ATMEGA_READ_1(sc, ATMEGA_USBSTA); 744 atmegadci_vbus_interrupt(sc, temp & ATMEGA_USBSTA_VBUS); 745 } 746 /* check for any endpoint interrupts */ 747 status = ATMEGA_READ_1(sc, ATMEGA_UEINT); 748 /* the hardware will clear the UEINT bits automatically */ 749 if (status) { 750 751 DPRINTFN(5, "real endpoint interrupt UEINT=0x%02x\n", status); 752 753 atmegadci_interrupt_poll(sc); 754 } 755 USB_BUS_UNLOCK(&sc->sc_bus); 756 } 757 758 static void 759 atmegadci_setup_standard_chain_sub(struct atmegadci_std_temp *temp) 760 { 761 struct atmegadci_td *td; 762 763 /* get current Transfer Descriptor */ 764 td = temp->td_next; 765 temp->td = td; 766 767 /* prepare for next TD */ 768 temp->td_next = td->obj_next; 769 770 /* fill out the Transfer Descriptor */ 771 td->func = temp->func; 772 td->pc = temp->pc; 773 td->offset = temp->offset; 774 td->remainder = temp->len; 775 td->error = 0; 776 td->did_stall = temp->did_stall; 777 td->short_pkt = temp->short_pkt; 778 td->alt_next = temp->setup_alt_next; 779 } 780 781 static void 782 atmegadci_setup_standard_chain(struct usb_xfer *xfer) 783 { 784 struct atmegadci_std_temp temp; 785 struct atmegadci_softc *sc; 786 struct atmegadci_td *td; 787 uint32_t x; 788 uint8_t ep_no; 789 uint8_t need_sync; 790 791 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 792 xfer->address, UE_GET_ADDR(xfer->endpointno), 793 xfer->sumlen, usbd_get_speed(xfer->xroot->udev)); 794 795 temp.max_frame_size = xfer->max_frame_size; 796 797 td = xfer->td_start[0]; 798 xfer->td_transfer_first = td; 799 xfer->td_transfer_cache = td; 800 801 /* setup temp */ 802 803 temp.pc = NULL; 804 temp.td = NULL; 805 temp.td_next = xfer->td_start[0]; 806 temp.offset = 0; 807 temp.setup_alt_next = xfer->flags_int.short_frames_ok || 808 xfer->flags_int.isochronous_xfr; 809 temp.did_stall = !xfer->flags_int.control_stall; 810 811 sc = ATMEGA_BUS2SC(xfer->xroot->bus); 812 ep_no = (xfer->endpointno & UE_ADDR); 813 814 /* check if we should prepend a setup message */ 815 816 if (xfer->flags_int.control_xfr) { 817 if (xfer->flags_int.control_hdr) { 818 819 temp.func = &atmegadci_setup_rx; 820 temp.len = xfer->frlengths[0]; 821 temp.pc = xfer->frbuffers + 0; 822 temp.short_pkt = temp.len ? 1 : 0; 823 /* check for last frame */ 824 if (xfer->nframes == 1) { 825 /* no STATUS stage yet, SETUP is last */ 826 if (xfer->flags_int.control_act) 827 temp.setup_alt_next = 0; 828 } 829 830 atmegadci_setup_standard_chain_sub(&temp); 831 } 832 x = 1; 833 } else { 834 x = 0; 835 } 836 837 if (x != xfer->nframes) { 838 if (xfer->endpointno & UE_DIR_IN) { 839 temp.func = &atmegadci_data_tx; 840 need_sync = 1; 841 } else { 842 temp.func = &atmegadci_data_rx; 843 need_sync = 0; 844 } 845 846 /* setup "pc" pointer */ 847 temp.pc = xfer->frbuffers + x; 848 } else { 849 need_sync = 0; 850 } 851 while (x != xfer->nframes) { 852 853 /* DATA0 / DATA1 message */ 854 855 temp.len = xfer->frlengths[x]; 856 857 x++; 858 859 if (x == xfer->nframes) { 860 if (xfer->flags_int.control_xfr) { 861 if (xfer->flags_int.control_act) { 862 temp.setup_alt_next = 0; 863 } 864 } else { 865 temp.setup_alt_next = 0; 866 } 867 } 868 if (temp.len == 0) { 869 870 /* make sure that we send an USB packet */ 871 872 temp.short_pkt = 0; 873 874 } else { 875 876 /* regular data transfer */ 877 878 temp.short_pkt = (xfer->flags.force_short_xfer) ? 0 : 1; 879 } 880 881 atmegadci_setup_standard_chain_sub(&temp); 882 883 if (xfer->flags_int.isochronous_xfr) { 884 temp.offset += temp.len; 885 } else { 886 /* get next Page Cache pointer */ 887 temp.pc = xfer->frbuffers + x; 888 } 889 } 890 891 if (xfer->flags_int.control_xfr) { 892 893 /* always setup a valid "pc" pointer for status and sync */ 894 temp.pc = xfer->frbuffers + 0; 895 temp.len = 0; 896 temp.short_pkt = 0; 897 temp.setup_alt_next = 0; 898 899 /* check if we need to sync */ 900 if (need_sync) { 901 /* we need a SYNC point after TX */ 902 temp.func = &atmegadci_data_tx_sync; 903 atmegadci_setup_standard_chain_sub(&temp); 904 } 905 906 /* check if we should append a status stage */ 907 if (!xfer->flags_int.control_act) { 908 909 /* 910 * Send a DATA1 message and invert the current 911 * endpoint direction. 912 */ 913 if (xfer->endpointno & UE_DIR_IN) { 914 temp.func = &atmegadci_data_rx; 915 need_sync = 0; 916 } else { 917 temp.func = &atmegadci_data_tx; 918 need_sync = 1; 919 } 920 921 atmegadci_setup_standard_chain_sub(&temp); 922 if (need_sync) { 923 /* we need a SYNC point after TX */ 924 temp.func = &atmegadci_data_tx_sync; 925 atmegadci_setup_standard_chain_sub(&temp); 926 } 927 } 928 } 929 /* must have at least one frame! */ 930 td = temp.td; 931 xfer->td_transfer_last = td; 932 } 933 934 static void 935 atmegadci_timeout(void *arg) 936 { 937 struct usb_xfer *xfer = arg; 938 939 DPRINTF("xfer=%p\n", xfer); 940 941 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 942 943 /* transfer is transferred */ 944 atmegadci_device_done(xfer, USB_ERR_TIMEOUT); 945 } 946 947 static void 948 atmegadci_start_standard_chain(struct usb_xfer *xfer) 949 { 950 DPRINTFN(9, "\n"); 951 952 /* poll one time - will turn on interrupts */ 953 if (atmegadci_xfer_do_fifo(xfer)) { 954 955 /* put transfer on interrupt queue */ 956 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 957 958 /* start timeout, if any */ 959 if (xfer->timeout != 0) { 960 usbd_transfer_timeout_ms(xfer, 961 &atmegadci_timeout, xfer->timeout); 962 } 963 } 964 } 965 966 static void 967 atmegadci_root_intr(struct atmegadci_softc *sc) 968 { 969 DPRINTFN(9, "\n"); 970 971 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 972 973 /* set port bit */ 974 sc->sc_hub_idata[0] = 0x02; /* we only have one port */ 975 976 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 977 sizeof(sc->sc_hub_idata)); 978 } 979 980 static usb_error_t 981 atmegadci_standard_done_sub(struct usb_xfer *xfer) 982 { 983 struct atmegadci_td *td; 984 uint32_t len; 985 uint8_t error; 986 987 DPRINTFN(9, "\n"); 988 989 td = xfer->td_transfer_cache; 990 991 do { 992 len = td->remainder; 993 994 if (xfer->aframes != xfer->nframes) { 995 /* 996 * Verify the length and subtract 997 * the remainder from "frlengths[]": 998 */ 999 if (len > xfer->frlengths[xfer->aframes]) { 1000 td->error = 1; 1001 } else { 1002 xfer->frlengths[xfer->aframes] -= len; 1003 } 1004 } 1005 /* Check for transfer error */ 1006 if (td->error) { 1007 /* the transfer is finished */ 1008 error = 1; 1009 td = NULL; 1010 break; 1011 } 1012 /* Check for short transfer */ 1013 if (len > 0) { 1014 if (xfer->flags_int.short_frames_ok || 1015 xfer->flags_int.isochronous_xfr) { 1016 /* follow alt next */ 1017 if (td->alt_next) { 1018 td = td->obj_next; 1019 } else { 1020 td = NULL; 1021 } 1022 } else { 1023 /* the transfer is finished */ 1024 td = NULL; 1025 } 1026 error = 0; 1027 break; 1028 } 1029 td = td->obj_next; 1030 1031 /* this USB frame is complete */ 1032 error = 0; 1033 break; 1034 1035 } while (0); 1036 1037 /* update transfer cache */ 1038 1039 xfer->td_transfer_cache = td; 1040 1041 return (error ? 1042 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION); 1043 } 1044 1045 static void 1046 atmegadci_standard_done(struct usb_xfer *xfer) 1047 { 1048 usb_error_t err = 0; 1049 1050 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 1051 xfer, xfer->endpoint); 1052 1053 /* reset scanner */ 1054 1055 xfer->td_transfer_cache = xfer->td_transfer_first; 1056 1057 if (xfer->flags_int.control_xfr) { 1058 1059 if (xfer->flags_int.control_hdr) { 1060 1061 err = atmegadci_standard_done_sub(xfer); 1062 } 1063 xfer->aframes = 1; 1064 1065 if (xfer->td_transfer_cache == NULL) { 1066 goto done; 1067 } 1068 } 1069 while (xfer->aframes != xfer->nframes) { 1070 1071 err = atmegadci_standard_done_sub(xfer); 1072 xfer->aframes++; 1073 1074 if (xfer->td_transfer_cache == NULL) { 1075 goto done; 1076 } 1077 } 1078 1079 if (xfer->flags_int.control_xfr && 1080 !xfer->flags_int.control_act) { 1081 1082 err = atmegadci_standard_done_sub(xfer); 1083 } 1084 done: 1085 atmegadci_device_done(xfer, err); 1086 } 1087 1088 /*------------------------------------------------------------------------* 1089 * atmegadci_device_done 1090 * 1091 * NOTE: this function can be called more than one time on the 1092 * same USB transfer! 1093 *------------------------------------------------------------------------*/ 1094 static void 1095 atmegadci_device_done(struct usb_xfer *xfer, usb_error_t error) 1096 { 1097 struct atmegadci_softc *sc = ATMEGA_BUS2SC(xfer->xroot->bus); 1098 uint8_t ep_no; 1099 1100 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1101 1102 DPRINTFN(9, "xfer=%p, endpoint=%p, error=%d\n", 1103 xfer, xfer->endpoint, error); 1104 1105 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) { 1106 ep_no = (xfer->endpointno & UE_ADDR); 1107 1108 /* select endpoint number */ 1109 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, ep_no); 1110 1111 /* disable endpoint interrupt */ 1112 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, 0); 1113 1114 DPRINTFN(15, "disabled interrupts!\n"); 1115 } 1116 /* dequeue transfer and start next transfer */ 1117 usbd_transfer_done(xfer, error); 1118 } 1119 1120 static void 1121 atmegadci_xfer_stall(struct usb_xfer *xfer) 1122 { 1123 atmegadci_device_done(xfer, USB_ERR_STALLED); 1124 } 1125 1126 static void 1127 atmegadci_set_stall(struct usb_device *udev, 1128 struct usb_endpoint *ep, uint8_t *did_stall) 1129 { 1130 struct atmegadci_softc *sc; 1131 uint8_t ep_no; 1132 1133 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 1134 1135 DPRINTFN(5, "endpoint=%p\n", ep); 1136 1137 sc = ATMEGA_BUS2SC(udev->bus); 1138 /* get endpoint number */ 1139 ep_no = (ep->edesc->bEndpointAddress & UE_ADDR); 1140 /* select endpoint number */ 1141 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, ep_no); 1142 /* set stall */ 1143 ATMEGA_WRITE_1(sc, ATMEGA_UECONX, 1144 ATMEGA_UECONX_EPEN | 1145 ATMEGA_UECONX_STALLRQ); 1146 } 1147 1148 static void 1149 atmegadci_clear_stall_sub(struct atmegadci_softc *sc, uint8_t ep_no, 1150 uint8_t ep_type, uint8_t ep_dir) 1151 { 1152 uint8_t temp; 1153 1154 if (ep_type == UE_CONTROL) { 1155 /* clearing stall is not needed */ 1156 return; 1157 } 1158 /* select endpoint number */ 1159 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, ep_no); 1160 1161 /* set endpoint reset */ 1162 ATMEGA_WRITE_1(sc, ATMEGA_UERST, ATMEGA_UERST_MASK(ep_no)); 1163 1164 /* clear endpoint reset */ 1165 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 0); 1166 1167 /* set stall */ 1168 ATMEGA_WRITE_1(sc, ATMEGA_UECONX, 1169 ATMEGA_UECONX_EPEN | 1170 ATMEGA_UECONX_STALLRQ); 1171 1172 /* reset data toggle */ 1173 ATMEGA_WRITE_1(sc, ATMEGA_UECONX, 1174 ATMEGA_UECONX_EPEN | 1175 ATMEGA_UECONX_RSTDT); 1176 1177 /* clear stall */ 1178 ATMEGA_WRITE_1(sc, ATMEGA_UECONX, 1179 ATMEGA_UECONX_EPEN | 1180 ATMEGA_UECONX_STALLRQC); 1181 1182 do { 1183 if (ep_type == UE_BULK) { 1184 temp = ATMEGA_UECFG0X_EPTYPE2; 1185 } else if (ep_type == UE_INTERRUPT) { 1186 temp = ATMEGA_UECFG0X_EPTYPE3; 1187 } else { 1188 temp = ATMEGA_UECFG0X_EPTYPE1; 1189 } 1190 if (ep_dir & UE_DIR_IN) { 1191 temp |= ATMEGA_UECFG0X_EPDIR; 1192 } 1193 /* two banks, 64-bytes wMaxPacket */ 1194 ATMEGA_WRITE_1(sc, ATMEGA_UECFG0X, temp); 1195 ATMEGA_WRITE_1(sc, ATMEGA_UECFG1X, 1196 ATMEGA_UECFG1X_ALLOC | 1197 ATMEGA_UECFG1X_EPBK0 | /* one bank */ 1198 ATMEGA_UECFG1X_EPSIZE(3)); 1199 1200 temp = ATMEGA_READ_1(sc, ATMEGA_UESTA0X); 1201 if (!(temp & ATMEGA_UESTA0X_CFGOK)) { 1202 device_printf(sc->sc_bus.bdev, 1203 "Chip rejected configuration\n"); 1204 } 1205 } while (0); 1206 } 1207 1208 static void 1209 atmegadci_clear_stall(struct usb_device *udev, struct usb_endpoint *ep) 1210 { 1211 struct atmegadci_softc *sc; 1212 struct usb_endpoint_descriptor *ed; 1213 1214 DPRINTFN(5, "endpoint=%p\n", ep); 1215 1216 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 1217 1218 /* check mode */ 1219 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 1220 /* not supported */ 1221 return; 1222 } 1223 /* get softc */ 1224 sc = ATMEGA_BUS2SC(udev->bus); 1225 1226 /* get endpoint descriptor */ 1227 ed = ep->edesc; 1228 1229 /* reset endpoint */ 1230 atmegadci_clear_stall_sub(sc, 1231 (ed->bEndpointAddress & UE_ADDR), 1232 (ed->bmAttributes & UE_XFERTYPE), 1233 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT))); 1234 } 1235 1236 usb_error_t 1237 atmegadci_init(struct atmegadci_softc *sc) 1238 { 1239 uint8_t n; 1240 1241 DPRINTF("start\n"); 1242 1243 /* set up the bus structure */ 1244 sc->sc_bus.usbrev = USB_REV_1_1; 1245 sc->sc_bus.methods = &atmegadci_bus_methods; 1246 1247 USB_BUS_LOCK(&sc->sc_bus); 1248 1249 /* make sure USB is enabled */ 1250 ATMEGA_WRITE_1(sc, ATMEGA_USBCON, 1251 ATMEGA_USBCON_USBE | 1252 ATMEGA_USBCON_FRZCLK); 1253 1254 /* enable USB PAD regulator */ 1255 ATMEGA_WRITE_1(sc, ATMEGA_UHWCON, 1256 ATMEGA_UHWCON_UVREGE | 1257 ATMEGA_UHWCON_UIMOD); 1258 1259 /* the following register sets up the USB PLL, assuming 16MHz X-tal */ 1260 ATMEGA_WRITE_1(sc, 0x49 /* PLLCSR */, 0x14 | 0x02); 1261 1262 /* wait for PLL to lock */ 1263 for (n = 0; n != 20; n++) { 1264 if (ATMEGA_READ_1(sc, 0x49) & 0x01) 1265 break; 1266 /* wait a little bit for PLL to start */ 1267 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); 1268 } 1269 1270 /* make sure USB is enabled */ 1271 ATMEGA_WRITE_1(sc, ATMEGA_USBCON, 1272 ATMEGA_USBCON_USBE | 1273 ATMEGA_USBCON_OTGPADE | 1274 ATMEGA_USBCON_VBUSTE); 1275 1276 /* turn on clocks */ 1277 (sc->sc_clocks_on) (&sc->sc_bus); 1278 1279 /* make sure device is re-enumerated */ 1280 ATMEGA_WRITE_1(sc, ATMEGA_UDCON, ATMEGA_UDCON_DETACH); 1281 1282 /* wait a little for things to stabilise */ 1283 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 20); 1284 1285 /* enable interrupts */ 1286 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN, 1287 ATMEGA_UDINT_SUSPE | 1288 ATMEGA_UDINT_EORSTE); 1289 1290 /* reset all endpoints */ 1291 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 1292 (1 << ATMEGA_EP_MAX) - 1); 1293 1294 /* disable reset */ 1295 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 0); 1296 1297 /* disable all endpoints */ 1298 for (n = 0; n != ATMEGA_EP_MAX; n++) { 1299 1300 /* select endpoint */ 1301 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, n); 1302 1303 /* disable endpoint interrupt */ 1304 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, 0); 1305 1306 /* disable endpoint */ 1307 ATMEGA_WRITE_1(sc, ATMEGA_UECONX, 0); 1308 } 1309 1310 /* turn off clocks */ 1311 1312 atmegadci_clocks_off(sc); 1313 1314 /* read initial VBUS state */ 1315 1316 n = ATMEGA_READ_1(sc, ATMEGA_USBSTA); 1317 atmegadci_vbus_interrupt(sc, n & ATMEGA_USBSTA_VBUS); 1318 1319 USB_BUS_UNLOCK(&sc->sc_bus); 1320 1321 /* catch any lost interrupts */ 1322 1323 atmegadci_do_poll(&sc->sc_bus); 1324 1325 return (0); /* success */ 1326 } 1327 1328 void 1329 atmegadci_uninit(struct atmegadci_softc *sc) 1330 { 1331 USB_BUS_LOCK(&sc->sc_bus); 1332 1333 /* turn on clocks */ 1334 (sc->sc_clocks_on) (&sc->sc_bus); 1335 1336 /* disable interrupts */ 1337 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN, 0); 1338 1339 /* reset all endpoints */ 1340 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 1341 (1 << ATMEGA_EP_MAX) - 1); 1342 1343 /* disable reset */ 1344 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 0); 1345 1346 sc->sc_flags.port_powered = 0; 1347 sc->sc_flags.status_vbus = 0; 1348 sc->sc_flags.status_bus_reset = 0; 1349 sc->sc_flags.status_suspend = 0; 1350 sc->sc_flags.change_suspend = 0; 1351 sc->sc_flags.change_connect = 1; 1352 1353 atmegadci_pull_down(sc); 1354 atmegadci_clocks_off(sc); 1355 1356 /* disable USB PAD regulator */ 1357 ATMEGA_WRITE_1(sc, ATMEGA_UHWCON, 0); 1358 1359 USB_BUS_UNLOCK(&sc->sc_bus); 1360 } 1361 1362 static void 1363 atmegadci_suspend(struct atmegadci_softc *sc) 1364 { 1365 /* TODO */ 1366 } 1367 1368 static void 1369 atmegadci_resume(struct atmegadci_softc *sc) 1370 { 1371 /* TODO */ 1372 } 1373 1374 static void 1375 atmegadci_do_poll(struct usb_bus *bus) 1376 { 1377 struct atmegadci_softc *sc = ATMEGA_BUS2SC(bus); 1378 1379 USB_BUS_LOCK(&sc->sc_bus); 1380 atmegadci_interrupt_poll(sc); 1381 USB_BUS_UNLOCK(&sc->sc_bus); 1382 } 1383 1384 /*------------------------------------------------------------------------* 1385 * atmegadci bulk support 1386 * atmegadci control support 1387 * atmegadci interrupt support 1388 *------------------------------------------------------------------------*/ 1389 static void 1390 atmegadci_device_non_isoc_open(struct usb_xfer *xfer) 1391 { 1392 return; 1393 } 1394 1395 static void 1396 atmegadci_device_non_isoc_close(struct usb_xfer *xfer) 1397 { 1398 atmegadci_device_done(xfer, USB_ERR_CANCELLED); 1399 } 1400 1401 static void 1402 atmegadci_device_non_isoc_enter(struct usb_xfer *xfer) 1403 { 1404 return; 1405 } 1406 1407 static void 1408 atmegadci_device_non_isoc_start(struct usb_xfer *xfer) 1409 { 1410 /* setup TDs */ 1411 atmegadci_setup_standard_chain(xfer); 1412 atmegadci_start_standard_chain(xfer); 1413 } 1414 1415 static const struct usb_pipe_methods atmegadci_device_non_isoc_methods = 1416 { 1417 .open = atmegadci_device_non_isoc_open, 1418 .close = atmegadci_device_non_isoc_close, 1419 .enter = atmegadci_device_non_isoc_enter, 1420 .start = atmegadci_device_non_isoc_start, 1421 }; 1422 1423 /*------------------------------------------------------------------------* 1424 * atmegadci full speed isochronous support 1425 *------------------------------------------------------------------------*/ 1426 static void 1427 atmegadci_device_isoc_fs_open(struct usb_xfer *xfer) 1428 { 1429 return; 1430 } 1431 1432 static void 1433 atmegadci_device_isoc_fs_close(struct usb_xfer *xfer) 1434 { 1435 atmegadci_device_done(xfer, USB_ERR_CANCELLED); 1436 } 1437 1438 static void 1439 atmegadci_device_isoc_fs_enter(struct usb_xfer *xfer) 1440 { 1441 struct atmegadci_softc *sc = ATMEGA_BUS2SC(xfer->xroot->bus); 1442 uint32_t temp; 1443 uint32_t nframes; 1444 1445 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 1446 xfer, xfer->endpoint->isoc_next, xfer->nframes); 1447 1448 /* get the current frame index */ 1449 1450 nframes = 1451 (ATMEGA_READ_1(sc, ATMEGA_UDFNUMH) << 8) | 1452 (ATMEGA_READ_1(sc, ATMEGA_UDFNUML)); 1453 1454 nframes &= ATMEGA_FRAME_MASK; 1455 1456 /* 1457 * check if the frame index is within the window where the frames 1458 * will be inserted 1459 */ 1460 temp = (nframes - xfer->endpoint->isoc_next) & ATMEGA_FRAME_MASK; 1461 1462 if ((xfer->endpoint->is_synced == 0) || 1463 (temp < xfer->nframes)) { 1464 /* 1465 * If there is data underflow or the pipe queue is 1466 * empty we schedule the transfer a few frames ahead 1467 * of the current frame position. Else two isochronous 1468 * transfers might overlap. 1469 */ 1470 xfer->endpoint->isoc_next = (nframes + 3) & ATMEGA_FRAME_MASK; 1471 xfer->endpoint->is_synced = 1; 1472 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 1473 } 1474 /* 1475 * compute how many milliseconds the insertion is ahead of the 1476 * current frame position: 1477 */ 1478 temp = (xfer->endpoint->isoc_next - nframes) & ATMEGA_FRAME_MASK; 1479 1480 /* 1481 * pre-compute when the isochronous transfer will be finished: 1482 */ 1483 xfer->isoc_time_complete = 1484 usb_isoc_time_expand(&sc->sc_bus, nframes) + temp + 1485 xfer->nframes; 1486 1487 /* compute frame number for next insertion */ 1488 xfer->endpoint->isoc_next += xfer->nframes; 1489 1490 /* setup TDs */ 1491 atmegadci_setup_standard_chain(xfer); 1492 } 1493 1494 static void 1495 atmegadci_device_isoc_fs_start(struct usb_xfer *xfer) 1496 { 1497 /* start TD chain */ 1498 atmegadci_start_standard_chain(xfer); 1499 } 1500 1501 static const struct usb_pipe_methods atmegadci_device_isoc_fs_methods = 1502 { 1503 .open = atmegadci_device_isoc_fs_open, 1504 .close = atmegadci_device_isoc_fs_close, 1505 .enter = atmegadci_device_isoc_fs_enter, 1506 .start = atmegadci_device_isoc_fs_start, 1507 }; 1508 1509 /*------------------------------------------------------------------------* 1510 * atmegadci root control support 1511 *------------------------------------------------------------------------* 1512 * Simulate a hardware HUB by handling all the necessary requests. 1513 *------------------------------------------------------------------------*/ 1514 1515 static const struct usb_device_descriptor atmegadci_devd = { 1516 .bLength = sizeof(struct usb_device_descriptor), 1517 .bDescriptorType = UDESC_DEVICE, 1518 .bcdUSB = {0x00, 0x02}, 1519 .bDeviceClass = UDCLASS_HUB, 1520 .bDeviceSubClass = UDSUBCLASS_HUB, 1521 .bDeviceProtocol = UDPROTO_FSHUB, 1522 .bMaxPacketSize = 64, 1523 .bcdDevice = {0x00, 0x01}, 1524 .iManufacturer = 1, 1525 .iProduct = 2, 1526 .bNumConfigurations = 1, 1527 }; 1528 1529 static const struct atmegadci_config_desc atmegadci_confd = { 1530 .confd = { 1531 .bLength = sizeof(struct usb_config_descriptor), 1532 .bDescriptorType = UDESC_CONFIG, 1533 .wTotalLength[0] = sizeof(atmegadci_confd), 1534 .bNumInterface = 1, 1535 .bConfigurationValue = 1, 1536 .iConfiguration = 0, 1537 .bmAttributes = UC_SELF_POWERED, 1538 .bMaxPower = 0, 1539 }, 1540 .ifcd = { 1541 .bLength = sizeof(struct usb_interface_descriptor), 1542 .bDescriptorType = UDESC_INTERFACE, 1543 .bNumEndpoints = 1, 1544 .bInterfaceClass = UICLASS_HUB, 1545 .bInterfaceSubClass = UISUBCLASS_HUB, 1546 .bInterfaceProtocol = 0, 1547 }, 1548 .endpd = { 1549 .bLength = sizeof(struct usb_endpoint_descriptor), 1550 .bDescriptorType = UDESC_ENDPOINT, 1551 .bEndpointAddress = (UE_DIR_IN | ATMEGA_INTR_ENDPT), 1552 .bmAttributes = UE_INTERRUPT, 1553 .wMaxPacketSize[0] = 8, 1554 .bInterval = 255, 1555 }, 1556 }; 1557 1558 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) } 1559 1560 static const struct usb_hub_descriptor_min atmegadci_hubd = { 1561 .bDescLength = sizeof(atmegadci_hubd), 1562 .bDescriptorType = UDESC_HUB, 1563 .bNbrPorts = 1, 1564 HSETW(.wHubCharacteristics, (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL)), 1565 .bPwrOn2PwrGood = 50, 1566 .bHubContrCurrent = 0, 1567 .DeviceRemovable = {0}, /* port is removable */ 1568 }; 1569 1570 #define STRING_VENDOR \ 1571 "A\0T\0M\0E\0G\0A" 1572 1573 #define STRING_PRODUCT \ 1574 "D\0C\0I\0 \0R\0o\0o\0t\0 \0H\0U\0B" 1575 1576 USB_MAKE_STRING_DESC(STRING_VENDOR, atmegadci_vendor); 1577 USB_MAKE_STRING_DESC(STRING_PRODUCT, atmegadci_product); 1578 1579 static usb_error_t 1580 atmegadci_roothub_exec(struct usb_device *udev, 1581 struct usb_device_request *req, const void **pptr, uint16_t *plength) 1582 { 1583 struct atmegadci_softc *sc = ATMEGA_BUS2SC(udev->bus); 1584 const void *ptr; 1585 uint16_t len; 1586 uint16_t value; 1587 uint16_t index; 1588 uint8_t temp; 1589 usb_error_t err; 1590 1591 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1592 1593 /* buffer reset */ 1594 ptr = (const void *)&sc->sc_hub_temp; 1595 len = 0; 1596 err = 0; 1597 1598 value = UGETW(req->wValue); 1599 index = UGETW(req->wIndex); 1600 1601 /* demultiplex the control request */ 1602 1603 switch (req->bmRequestType) { 1604 case UT_READ_DEVICE: 1605 switch (req->bRequest) { 1606 case UR_GET_DESCRIPTOR: 1607 goto tr_handle_get_descriptor; 1608 case UR_GET_CONFIG: 1609 goto tr_handle_get_config; 1610 case UR_GET_STATUS: 1611 goto tr_handle_get_status; 1612 default: 1613 goto tr_stalled; 1614 } 1615 break; 1616 1617 case UT_WRITE_DEVICE: 1618 switch (req->bRequest) { 1619 case UR_SET_ADDRESS: 1620 goto tr_handle_set_address; 1621 case UR_SET_CONFIG: 1622 goto tr_handle_set_config; 1623 case UR_CLEAR_FEATURE: 1624 goto tr_valid; /* nop */ 1625 case UR_SET_DESCRIPTOR: 1626 goto tr_valid; /* nop */ 1627 case UR_SET_FEATURE: 1628 default: 1629 goto tr_stalled; 1630 } 1631 break; 1632 1633 case UT_WRITE_ENDPOINT: 1634 switch (req->bRequest) { 1635 case UR_CLEAR_FEATURE: 1636 switch (UGETW(req->wValue)) { 1637 case UF_ENDPOINT_HALT: 1638 goto tr_handle_clear_halt; 1639 case UF_DEVICE_REMOTE_WAKEUP: 1640 goto tr_handle_clear_wakeup; 1641 default: 1642 goto tr_stalled; 1643 } 1644 break; 1645 case UR_SET_FEATURE: 1646 switch (UGETW(req->wValue)) { 1647 case UF_ENDPOINT_HALT: 1648 goto tr_handle_set_halt; 1649 case UF_DEVICE_REMOTE_WAKEUP: 1650 goto tr_handle_set_wakeup; 1651 default: 1652 goto tr_stalled; 1653 } 1654 break; 1655 case UR_SYNCH_FRAME: 1656 goto tr_valid; /* nop */ 1657 default: 1658 goto tr_stalled; 1659 } 1660 break; 1661 1662 case UT_READ_ENDPOINT: 1663 switch (req->bRequest) { 1664 case UR_GET_STATUS: 1665 goto tr_handle_get_ep_status; 1666 default: 1667 goto tr_stalled; 1668 } 1669 break; 1670 1671 case UT_WRITE_INTERFACE: 1672 switch (req->bRequest) { 1673 case UR_SET_INTERFACE: 1674 goto tr_handle_set_interface; 1675 case UR_CLEAR_FEATURE: 1676 goto tr_valid; /* nop */ 1677 case UR_SET_FEATURE: 1678 default: 1679 goto tr_stalled; 1680 } 1681 break; 1682 1683 case UT_READ_INTERFACE: 1684 switch (req->bRequest) { 1685 case UR_GET_INTERFACE: 1686 goto tr_handle_get_interface; 1687 case UR_GET_STATUS: 1688 goto tr_handle_get_iface_status; 1689 default: 1690 goto tr_stalled; 1691 } 1692 break; 1693 1694 case UT_WRITE_CLASS_INTERFACE: 1695 case UT_WRITE_VENDOR_INTERFACE: 1696 /* XXX forward */ 1697 break; 1698 1699 case UT_READ_CLASS_INTERFACE: 1700 case UT_READ_VENDOR_INTERFACE: 1701 /* XXX forward */ 1702 break; 1703 1704 case UT_WRITE_CLASS_DEVICE: 1705 switch (req->bRequest) { 1706 case UR_CLEAR_FEATURE: 1707 goto tr_valid; 1708 case UR_SET_DESCRIPTOR: 1709 case UR_SET_FEATURE: 1710 break; 1711 default: 1712 goto tr_stalled; 1713 } 1714 break; 1715 1716 case UT_WRITE_CLASS_OTHER: 1717 switch (req->bRequest) { 1718 case UR_CLEAR_FEATURE: 1719 goto tr_handle_clear_port_feature; 1720 case UR_SET_FEATURE: 1721 goto tr_handle_set_port_feature; 1722 case UR_CLEAR_TT_BUFFER: 1723 case UR_RESET_TT: 1724 case UR_STOP_TT: 1725 goto tr_valid; 1726 1727 default: 1728 goto tr_stalled; 1729 } 1730 break; 1731 1732 case UT_READ_CLASS_OTHER: 1733 switch (req->bRequest) { 1734 case UR_GET_TT_STATE: 1735 goto tr_handle_get_tt_state; 1736 case UR_GET_STATUS: 1737 goto tr_handle_get_port_status; 1738 default: 1739 goto tr_stalled; 1740 } 1741 break; 1742 1743 case UT_READ_CLASS_DEVICE: 1744 switch (req->bRequest) { 1745 case UR_GET_DESCRIPTOR: 1746 goto tr_handle_get_class_descriptor; 1747 case UR_GET_STATUS: 1748 goto tr_handle_get_class_status; 1749 1750 default: 1751 goto tr_stalled; 1752 } 1753 break; 1754 default: 1755 goto tr_stalled; 1756 } 1757 goto tr_valid; 1758 1759 tr_handle_get_descriptor: 1760 switch (value >> 8) { 1761 case UDESC_DEVICE: 1762 if (value & 0xff) { 1763 goto tr_stalled; 1764 } 1765 len = sizeof(atmegadci_devd); 1766 ptr = (const void *)&atmegadci_devd; 1767 goto tr_valid; 1768 case UDESC_CONFIG: 1769 if (value & 0xff) { 1770 goto tr_stalled; 1771 } 1772 len = sizeof(atmegadci_confd); 1773 ptr = (const void *)&atmegadci_confd; 1774 goto tr_valid; 1775 case UDESC_STRING: 1776 switch (value & 0xff) { 1777 case 0: /* Language table */ 1778 len = sizeof(usb_string_lang_en); 1779 ptr = (const void *)&usb_string_lang_en; 1780 goto tr_valid; 1781 1782 case 1: /* Vendor */ 1783 len = sizeof(atmegadci_vendor); 1784 ptr = (const void *)&atmegadci_vendor; 1785 goto tr_valid; 1786 1787 case 2: /* Product */ 1788 len = sizeof(atmegadci_product); 1789 ptr = (const void *)&atmegadci_product; 1790 goto tr_valid; 1791 default: 1792 break; 1793 } 1794 break; 1795 default: 1796 goto tr_stalled; 1797 } 1798 goto tr_stalled; 1799 1800 tr_handle_get_config: 1801 len = 1; 1802 sc->sc_hub_temp.wValue[0] = sc->sc_conf; 1803 goto tr_valid; 1804 1805 tr_handle_get_status: 1806 len = 2; 1807 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED); 1808 goto tr_valid; 1809 1810 tr_handle_set_address: 1811 if (value & 0xFF00) { 1812 goto tr_stalled; 1813 } 1814 sc->sc_rt_addr = value; 1815 goto tr_valid; 1816 1817 tr_handle_set_config: 1818 if (value >= 2) { 1819 goto tr_stalled; 1820 } 1821 sc->sc_conf = value; 1822 goto tr_valid; 1823 1824 tr_handle_get_interface: 1825 len = 1; 1826 sc->sc_hub_temp.wValue[0] = 0; 1827 goto tr_valid; 1828 1829 tr_handle_get_tt_state: 1830 tr_handle_get_class_status: 1831 tr_handle_get_iface_status: 1832 tr_handle_get_ep_status: 1833 len = 2; 1834 USETW(sc->sc_hub_temp.wValue, 0); 1835 goto tr_valid; 1836 1837 tr_handle_set_halt: 1838 tr_handle_set_interface: 1839 tr_handle_set_wakeup: 1840 tr_handle_clear_wakeup: 1841 tr_handle_clear_halt: 1842 goto tr_valid; 1843 1844 tr_handle_clear_port_feature: 1845 if (index != 1) { 1846 goto tr_stalled; 1847 } 1848 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE on port %d\n", index); 1849 1850 switch (value) { 1851 case UHF_PORT_SUSPEND: 1852 atmegadci_wakeup_peer(sc); 1853 break; 1854 1855 case UHF_PORT_ENABLE: 1856 sc->sc_flags.port_enabled = 0; 1857 break; 1858 1859 case UHF_PORT_TEST: 1860 case UHF_PORT_INDICATOR: 1861 case UHF_C_PORT_ENABLE: 1862 case UHF_C_PORT_OVER_CURRENT: 1863 case UHF_C_PORT_RESET: 1864 /* nops */ 1865 break; 1866 case UHF_PORT_POWER: 1867 sc->sc_flags.port_powered = 0; 1868 atmegadci_pull_down(sc); 1869 atmegadci_clocks_off(sc); 1870 break; 1871 case UHF_C_PORT_CONNECTION: 1872 /* clear connect change flag */ 1873 sc->sc_flags.change_connect = 0; 1874 1875 if (!sc->sc_flags.status_bus_reset) { 1876 /* we are not connected */ 1877 break; 1878 } 1879 1880 /* configure the control endpoint */ 1881 1882 /* select endpoint number */ 1883 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, 0); 1884 1885 /* set endpoint reset */ 1886 ATMEGA_WRITE_1(sc, ATMEGA_UERST, ATMEGA_UERST_MASK(0)); 1887 1888 /* clear endpoint reset */ 1889 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 0); 1890 1891 /* enable and stall endpoint */ 1892 ATMEGA_WRITE_1(sc, ATMEGA_UECONX, 1893 ATMEGA_UECONX_EPEN | 1894 ATMEGA_UECONX_STALLRQ); 1895 1896 /* one bank, 64-bytes wMaxPacket */ 1897 ATMEGA_WRITE_1(sc, ATMEGA_UECFG0X, 1898 ATMEGA_UECFG0X_EPTYPE0); 1899 ATMEGA_WRITE_1(sc, ATMEGA_UECFG1X, 1900 ATMEGA_UECFG1X_ALLOC | 1901 ATMEGA_UECFG1X_EPBK0 | 1902 ATMEGA_UECFG1X_EPSIZE(3)); 1903 1904 /* check valid config */ 1905 temp = ATMEGA_READ_1(sc, ATMEGA_UESTA0X); 1906 if (!(temp & ATMEGA_UESTA0X_CFGOK)) { 1907 device_printf(sc->sc_bus.bdev, 1908 "Chip rejected EP0 configuration\n"); 1909 } 1910 break; 1911 case UHF_C_PORT_SUSPEND: 1912 sc->sc_flags.change_suspend = 0; 1913 break; 1914 default: 1915 err = USB_ERR_IOERROR; 1916 goto done; 1917 } 1918 goto tr_valid; 1919 1920 tr_handle_set_port_feature: 1921 if (index != 1) { 1922 goto tr_stalled; 1923 } 1924 DPRINTFN(9, "UR_SET_PORT_FEATURE\n"); 1925 1926 switch (value) { 1927 case UHF_PORT_ENABLE: 1928 sc->sc_flags.port_enabled = 1; 1929 break; 1930 case UHF_PORT_SUSPEND: 1931 case UHF_PORT_RESET: 1932 case UHF_PORT_TEST: 1933 case UHF_PORT_INDICATOR: 1934 /* nops */ 1935 break; 1936 case UHF_PORT_POWER: 1937 sc->sc_flags.port_powered = 1; 1938 break; 1939 default: 1940 err = USB_ERR_IOERROR; 1941 goto done; 1942 } 1943 goto tr_valid; 1944 1945 tr_handle_get_port_status: 1946 1947 DPRINTFN(9, "UR_GET_PORT_STATUS\n"); 1948 1949 if (index != 1) { 1950 goto tr_stalled; 1951 } 1952 if (sc->sc_flags.status_vbus) { 1953 atmegadci_clocks_on(sc); 1954 atmegadci_pull_up(sc); 1955 } else { 1956 atmegadci_pull_down(sc); 1957 atmegadci_clocks_off(sc); 1958 } 1959 1960 /* Select FULL-speed and Device Side Mode */ 1961 1962 value = UPS_PORT_MODE_DEVICE; 1963 1964 if (sc->sc_flags.port_powered) { 1965 value |= UPS_PORT_POWER; 1966 } 1967 if (sc->sc_flags.port_enabled) { 1968 value |= UPS_PORT_ENABLED; 1969 } 1970 if (sc->sc_flags.status_vbus && 1971 sc->sc_flags.status_bus_reset) { 1972 value |= UPS_CURRENT_CONNECT_STATUS; 1973 } 1974 if (sc->sc_flags.status_suspend) { 1975 value |= UPS_SUSPEND; 1976 } 1977 USETW(sc->sc_hub_temp.ps.wPortStatus, value); 1978 1979 value = 0; 1980 1981 if (sc->sc_flags.change_connect) { 1982 value |= UPS_C_CONNECT_STATUS; 1983 } 1984 if (sc->sc_flags.change_suspend) { 1985 value |= UPS_C_SUSPEND; 1986 } 1987 USETW(sc->sc_hub_temp.ps.wPortChange, value); 1988 len = sizeof(sc->sc_hub_temp.ps); 1989 goto tr_valid; 1990 1991 tr_handle_get_class_descriptor: 1992 if (value & 0xFF) { 1993 goto tr_stalled; 1994 } 1995 ptr = (const void *)&atmegadci_hubd; 1996 len = sizeof(atmegadci_hubd); 1997 goto tr_valid; 1998 1999 tr_stalled: 2000 err = USB_ERR_STALLED; 2001 tr_valid: 2002 done: 2003 *plength = len; 2004 *pptr = ptr; 2005 return (err); 2006 } 2007 2008 static void 2009 atmegadci_xfer_setup(struct usb_setup_params *parm) 2010 { 2011 const struct usb_hw_ep_profile *pf; 2012 struct atmegadci_softc *sc; 2013 struct usb_xfer *xfer; 2014 void *last_obj; 2015 uint32_t ntd; 2016 uint32_t n; 2017 uint8_t ep_no; 2018 2019 sc = ATMEGA_BUS2SC(parm->udev->bus); 2020 xfer = parm->curr_xfer; 2021 2022 /* 2023 * NOTE: This driver does not use any of the parameters that 2024 * are computed from the following values. Just set some 2025 * reasonable dummies: 2026 */ 2027 parm->hc_max_packet_size = 0x500; 2028 parm->hc_max_packet_count = 1; 2029 parm->hc_max_frame_size = 0x500; 2030 2031 usbd_transfer_setup_sub(parm); 2032 2033 /* 2034 * compute maximum number of TDs 2035 */ 2036 if ((xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) { 2037 2038 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC 1 */ 2039 + 1 /* SYNC 2 */ ; 2040 } else { 2041 2042 ntd = xfer->nframes + 1 /* SYNC */ ; 2043 } 2044 2045 /* 2046 * check if "usbd_transfer_setup_sub" set an error 2047 */ 2048 if (parm->err) 2049 return; 2050 2051 /* 2052 * allocate transfer descriptors 2053 */ 2054 last_obj = NULL; 2055 2056 /* 2057 * get profile stuff 2058 */ 2059 ep_no = xfer->endpointno & UE_ADDR; 2060 atmegadci_get_hw_ep_profile(parm->udev, &pf, ep_no); 2061 2062 if (pf == NULL) { 2063 /* should not happen */ 2064 parm->err = USB_ERR_INVAL; 2065 return; 2066 } 2067 2068 /* align data */ 2069 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1)); 2070 2071 for (n = 0; n != ntd; n++) { 2072 2073 struct atmegadci_td *td; 2074 2075 if (parm->buf) { 2076 2077 td = USB_ADD_BYTES(parm->buf, parm->size[0]); 2078 2079 /* init TD */ 2080 td->max_packet_size = xfer->max_packet_size; 2081 td->ep_no = ep_no; 2082 if (pf->support_multi_buffer) { 2083 td->support_multi_buffer = 1; 2084 } 2085 td->obj_next = last_obj; 2086 2087 last_obj = td; 2088 } 2089 parm->size[0] += sizeof(*td); 2090 } 2091 2092 xfer->td_start[0] = last_obj; 2093 } 2094 2095 static void 2096 atmegadci_xfer_unsetup(struct usb_xfer *xfer) 2097 { 2098 return; 2099 } 2100 2101 static void 2102 atmegadci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 2103 struct usb_endpoint *ep) 2104 { 2105 struct atmegadci_softc *sc = ATMEGA_BUS2SC(udev->bus); 2106 2107 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d,%d)\n", 2108 ep, udev->address, 2109 edesc->bEndpointAddress, udev->flags.usb_mode, 2110 sc->sc_rt_addr, udev->device_index); 2111 2112 if (udev->device_index != sc->sc_rt_addr) { 2113 2114 if (udev->speed != USB_SPEED_FULL) { 2115 /* not supported */ 2116 return; 2117 } 2118 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_ISOCHRONOUS) 2119 ep->methods = &atmegadci_device_isoc_fs_methods; 2120 else 2121 ep->methods = &atmegadci_device_non_isoc_methods; 2122 } 2123 } 2124 2125 static void 2126 atmegadci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 2127 { 2128 struct atmegadci_softc *sc = ATMEGA_BUS2SC(bus); 2129 2130 switch (state) { 2131 case USB_HW_POWER_SUSPEND: 2132 atmegadci_suspend(sc); 2133 break; 2134 case USB_HW_POWER_SHUTDOWN: 2135 atmegadci_uninit(sc); 2136 break; 2137 case USB_HW_POWER_RESUME: 2138 atmegadci_resume(sc); 2139 break; 2140 default: 2141 break; 2142 } 2143 } 2144 2145 static const struct usb_bus_methods atmegadci_bus_methods = 2146 { 2147 .endpoint_init = &atmegadci_ep_init, 2148 .xfer_setup = &atmegadci_xfer_setup, 2149 .xfer_unsetup = &atmegadci_xfer_unsetup, 2150 .get_hw_ep_profile = &atmegadci_get_hw_ep_profile, 2151 .xfer_stall = &atmegadci_xfer_stall, 2152 .set_stall = &atmegadci_set_stall, 2153 .clear_stall = &atmegadci_clear_stall, 2154 .roothub_exec = &atmegadci_roothub_exec, 2155 .xfer_poll = &atmegadci_do_poll, 2156 .set_hw_power_sleep = &atmegadci_set_hw_power_sleep, 2157 }; 2158