1 /* $FreeBSD$ */ 2 /*- 3 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 4 * 5 * Copyright (c) 2009 Hans Petter Selasky. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * This file contains the driver for the ATMEGA series USB OTG Controller. This 31 * driver currently only supports the DCI mode of the USB hardware. 32 */ 33 34 /* 35 * NOTE: When the chip detects BUS-reset it will also reset the 36 * endpoints, Function-address and more. 37 */ 38 39 #ifdef USB_GLOBAL_INCLUDE_FILE 40 #include USB_GLOBAL_INCLUDE_FILE 41 #else 42 #include <sys/stdint.h> 43 #include <sys/stddef.h> 44 #include <sys/param.h> 45 #include <sys/queue.h> 46 #include <sys/types.h> 47 #include <sys/systm.h> 48 #include <sys/kernel.h> 49 #include <sys/bus.h> 50 #include <sys/module.h> 51 #include <sys/lock.h> 52 #include <sys/mutex.h> 53 #include <sys/condvar.h> 54 #include <sys/sysctl.h> 55 #include <sys/sx.h> 56 #include <sys/unistd.h> 57 #include <sys/callout.h> 58 #include <sys/malloc.h> 59 #include <sys/priv.h> 60 61 #include <dev/usb/usb.h> 62 #include <dev/usb/usbdi.h> 63 64 #define USB_DEBUG_VAR atmegadci_debug 65 66 #include <dev/usb/usb_core.h> 67 #include <dev/usb/usb_debug.h> 68 #include <dev/usb/usb_busdma.h> 69 #include <dev/usb/usb_process.h> 70 #include <dev/usb/usb_transfer.h> 71 #include <dev/usb/usb_device.h> 72 #include <dev/usb/usb_hub.h> 73 #include <dev/usb/usb_util.h> 74 75 #include <dev/usb/usb_controller.h> 76 #include <dev/usb/usb_bus.h> 77 #endif /* USB_GLOBAL_INCLUDE_FILE */ 78 79 #include <dev/usb/controller/atmegadci.h> 80 81 #define ATMEGA_BUS2SC(bus) \ 82 __containerof(bus, struct atmegadci_softc, sc_bus) 83 84 #define ATMEGA_PC2SC(pc) \ 85 ATMEGA_BUS2SC(USB_DMATAG_TO_XROOT((pc)->tag_parent)->bus) 86 87 #ifdef USB_DEBUG 88 static int atmegadci_debug = 0; 89 90 static SYSCTL_NODE(_hw_usb, OID_AUTO, atmegadci, CTLFLAG_RW | CTLFLAG_MPSAFE, 0, 91 "USB ATMEGA DCI"); 92 SYSCTL_INT(_hw_usb_atmegadci, OID_AUTO, debug, CTLFLAG_RWTUN, 93 &atmegadci_debug, 0, "ATMEGA DCI debug level"); 94 #endif 95 96 #define ATMEGA_INTR_ENDPT 1 97 98 /* prototypes */ 99 100 static const struct usb_bus_methods atmegadci_bus_methods; 101 static const struct usb_pipe_methods atmegadci_device_non_isoc_methods; 102 static const struct usb_pipe_methods atmegadci_device_isoc_fs_methods; 103 104 static atmegadci_cmd_t atmegadci_setup_rx; 105 static atmegadci_cmd_t atmegadci_data_rx; 106 static atmegadci_cmd_t atmegadci_data_tx; 107 static atmegadci_cmd_t atmegadci_data_tx_sync; 108 static void atmegadci_device_done(struct usb_xfer *, usb_error_t); 109 static void atmegadci_do_poll(struct usb_bus *); 110 static void atmegadci_standard_done(struct usb_xfer *); 111 static void atmegadci_root_intr(struct atmegadci_softc *sc); 112 113 /* 114 * Here is a list of what the chip supports: 115 */ 116 static const struct usb_hw_ep_profile 117 atmegadci_ep_profile[2] = { 118 [0] = { 119 .max_in_frame_size = 64, 120 .max_out_frame_size = 64, 121 .is_simplex = 1, 122 .support_control = 1, 123 }, 124 [1] = { 125 .max_in_frame_size = 64, 126 .max_out_frame_size = 64, 127 .is_simplex = 1, 128 .support_bulk = 1, 129 .support_interrupt = 1, 130 .support_isochronous = 1, 131 .support_in = 1, 132 .support_out = 1, 133 }, 134 }; 135 136 static void 137 atmegadci_get_hw_ep_profile(struct usb_device *udev, 138 const struct usb_hw_ep_profile **ppf, uint8_t ep_addr) 139 { 140 if (ep_addr == 0) 141 *ppf = atmegadci_ep_profile; 142 else if (ep_addr < ATMEGA_EP_MAX) 143 *ppf = atmegadci_ep_profile + 1; 144 else 145 *ppf = NULL; 146 } 147 148 static void 149 atmegadci_clocks_on(struct atmegadci_softc *sc) 150 { 151 if (sc->sc_flags.clocks_off && 152 sc->sc_flags.port_powered) { 153 DPRINTFN(5, "\n"); 154 155 /* turn on clocks */ 156 (sc->sc_clocks_on) (&sc->sc_bus); 157 158 ATMEGA_WRITE_1(sc, ATMEGA_USBCON, 159 ATMEGA_USBCON_USBE | 160 ATMEGA_USBCON_OTGPADE | 161 ATMEGA_USBCON_VBUSTE); 162 163 sc->sc_flags.clocks_off = 0; 164 165 /* enable transceiver ? */ 166 } 167 } 168 169 static void 170 atmegadci_clocks_off(struct atmegadci_softc *sc) 171 { 172 if (!sc->sc_flags.clocks_off) { 173 DPRINTFN(5, "\n"); 174 175 /* disable Transceiver ? */ 176 177 ATMEGA_WRITE_1(sc, ATMEGA_USBCON, 178 ATMEGA_USBCON_USBE | 179 ATMEGA_USBCON_OTGPADE | 180 ATMEGA_USBCON_FRZCLK | 181 ATMEGA_USBCON_VBUSTE); 182 183 /* turn clocks off */ 184 (sc->sc_clocks_off) (&sc->sc_bus); 185 186 sc->sc_flags.clocks_off = 1; 187 } 188 } 189 190 static void 191 atmegadci_pull_up(struct atmegadci_softc *sc) 192 { 193 /* pullup D+, if possible */ 194 195 if (!sc->sc_flags.d_pulled_up && 196 sc->sc_flags.port_powered) { 197 sc->sc_flags.d_pulled_up = 1; 198 ATMEGA_WRITE_1(sc, ATMEGA_UDCON, 0); 199 } 200 } 201 202 static void 203 atmegadci_pull_down(struct atmegadci_softc *sc) 204 { 205 /* pulldown D+, if possible */ 206 207 if (sc->sc_flags.d_pulled_up) { 208 sc->sc_flags.d_pulled_up = 0; 209 ATMEGA_WRITE_1(sc, ATMEGA_UDCON, ATMEGA_UDCON_DETACH); 210 } 211 } 212 213 static void 214 atmegadci_wakeup_peer(struct atmegadci_softc *sc) 215 { 216 uint8_t temp; 217 218 if (!sc->sc_flags.status_suspend) { 219 return; 220 } 221 222 temp = ATMEGA_READ_1(sc, ATMEGA_UDCON); 223 ATMEGA_WRITE_1(sc, ATMEGA_UDCON, temp | ATMEGA_UDCON_RMWKUP); 224 225 /* wait 8 milliseconds */ 226 /* Wait for reset to complete. */ 227 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125); 228 229 /* hardware should have cleared RMWKUP bit */ 230 } 231 232 static void 233 atmegadci_set_address(struct atmegadci_softc *sc, uint8_t addr) 234 { 235 DPRINTFN(5, "addr=%d\n", addr); 236 237 addr |= ATMEGA_UDADDR_ADDEN; 238 239 ATMEGA_WRITE_1(sc, ATMEGA_UDADDR, addr); 240 } 241 242 static uint8_t 243 atmegadci_setup_rx(struct atmegadci_td *td) 244 { 245 struct atmegadci_softc *sc; 246 struct usb_device_request req; 247 uint16_t count; 248 uint8_t temp; 249 250 /* get pointer to softc */ 251 sc = ATMEGA_PC2SC(td->pc); 252 253 /* select endpoint number */ 254 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, td->ep_no); 255 256 /* check endpoint status */ 257 temp = ATMEGA_READ_1(sc, ATMEGA_UEINTX); 258 259 DPRINTFN(5, "UEINTX=0x%02x\n", temp); 260 261 if (!(temp & ATMEGA_UEINTX_RXSTPI)) { 262 goto not_complete; 263 } 264 /* clear did stall */ 265 td->did_stall = 0; 266 /* get the packet byte count */ 267 count = 268 (ATMEGA_READ_1(sc, ATMEGA_UEBCHX) << 8) | 269 (ATMEGA_READ_1(sc, ATMEGA_UEBCLX)); 270 271 /* mask away undefined bits */ 272 count &= 0x7FF; 273 274 /* verify data length */ 275 if (count != td->remainder) { 276 DPRINTFN(0, "Invalid SETUP packet " 277 "length, %d bytes\n", count); 278 goto not_complete; 279 } 280 if (count != sizeof(req)) { 281 DPRINTFN(0, "Unsupported SETUP packet " 282 "length, %d bytes\n", count); 283 goto not_complete; 284 } 285 /* receive data */ 286 ATMEGA_READ_MULTI_1(sc, ATMEGA_UEDATX, 287 (void *)&req, sizeof(req)); 288 289 /* copy data into real buffer */ 290 usbd_copy_in(td->pc, 0, &req, sizeof(req)); 291 292 td->offset = sizeof(req); 293 td->remainder = 0; 294 295 /* sneak peek the set address */ 296 if ((req.bmRequestType == UT_WRITE_DEVICE) && 297 (req.bRequest == UR_SET_ADDRESS)) { 298 sc->sc_dv_addr = req.wValue[0] & 0x7F; 299 /* must write address before ZLP */ 300 ATMEGA_WRITE_1(sc, ATMEGA_UDADDR, sc->sc_dv_addr); 301 } else { 302 sc->sc_dv_addr = 0xFF; 303 } 304 305 /* Clear SETUP packet interrupt and all other previous interrupts */ 306 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, 0); 307 return (0); /* complete */ 308 309 not_complete: 310 /* abort any ongoing transfer */ 311 if (!td->did_stall) { 312 DPRINTFN(5, "stalling\n"); 313 ATMEGA_WRITE_1(sc, ATMEGA_UECONX, 314 ATMEGA_UECONX_EPEN | 315 ATMEGA_UECONX_STALLRQ); 316 td->did_stall = 1; 317 } 318 if (temp & ATMEGA_UEINTX_RXSTPI) { 319 /* clear SETUP packet interrupt */ 320 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, ~ATMEGA_UEINTX_RXSTPI); 321 } 322 /* we only want to know if there is a SETUP packet */ 323 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, ATMEGA_UEIENX_RXSTPE); 324 return (1); /* not complete */ 325 } 326 327 static uint8_t 328 atmegadci_data_rx(struct atmegadci_td *td) 329 { 330 struct atmegadci_softc *sc; 331 struct usb_page_search buf_res; 332 uint16_t count; 333 uint8_t temp; 334 uint8_t to; 335 uint8_t got_short; 336 337 to = 3; /* don't loop forever! */ 338 got_short = 0; 339 340 /* get pointer to softc */ 341 sc = ATMEGA_PC2SC(td->pc); 342 343 /* select endpoint number */ 344 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, td->ep_no); 345 346 repeat: 347 /* check if any of the FIFO banks have data */ 348 /* check endpoint status */ 349 temp = ATMEGA_READ_1(sc, ATMEGA_UEINTX); 350 351 DPRINTFN(5, "temp=0x%02x rem=%u\n", temp, td->remainder); 352 353 if (temp & ATMEGA_UEINTX_RXSTPI) { 354 if (td->remainder == 0) { 355 /* 356 * We are actually complete and have 357 * received the next SETUP 358 */ 359 DPRINTFN(5, "faking complete\n"); 360 return (0); /* complete */ 361 } 362 /* 363 * USB Host Aborted the transfer. 364 */ 365 td->error = 1; 366 return (0); /* complete */ 367 } 368 /* check status */ 369 if (!(temp & (ATMEGA_UEINTX_FIFOCON | 370 ATMEGA_UEINTX_RXOUTI))) { 371 /* no data */ 372 goto not_complete; 373 } 374 /* get the packet byte count */ 375 count = 376 (ATMEGA_READ_1(sc, ATMEGA_UEBCHX) << 8) | 377 (ATMEGA_READ_1(sc, ATMEGA_UEBCLX)); 378 379 /* mask away undefined bits */ 380 count &= 0x7FF; 381 382 /* verify the packet byte count */ 383 if (count != td->max_packet_size) { 384 if (count < td->max_packet_size) { 385 /* we have a short packet */ 386 td->short_pkt = 1; 387 got_short = 1; 388 } else { 389 /* invalid USB packet */ 390 td->error = 1; 391 return (0); /* we are complete */ 392 } 393 } 394 /* verify the packet byte count */ 395 if (count > td->remainder) { 396 /* invalid USB packet */ 397 td->error = 1; 398 return (0); /* we are complete */ 399 } 400 while (count > 0) { 401 usbd_get_page(td->pc, td->offset, &buf_res); 402 403 /* get correct length */ 404 if (buf_res.length > count) { 405 buf_res.length = count; 406 } 407 /* receive data */ 408 ATMEGA_READ_MULTI_1(sc, ATMEGA_UEDATX, 409 buf_res.buffer, buf_res.length); 410 411 /* update counters */ 412 count -= buf_res.length; 413 td->offset += buf_res.length; 414 td->remainder -= buf_res.length; 415 } 416 417 /* clear OUT packet interrupt */ 418 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, ATMEGA_UEINTX_RXOUTI ^ 0xFF); 419 420 /* release FIFO bank */ 421 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, ATMEGA_UEINTX_FIFOCON ^ 0xFF); 422 423 /* check if we are complete */ 424 if ((td->remainder == 0) || got_short) { 425 if (td->short_pkt) { 426 /* we are complete */ 427 return (0); 428 } 429 /* else need to receive a zero length packet */ 430 } 431 if (--to) { 432 goto repeat; 433 } 434 not_complete: 435 /* we only want to know if there is a SETUP packet or OUT packet */ 436 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, 437 ATMEGA_UEIENX_RXSTPE | ATMEGA_UEIENX_RXOUTE); 438 return (1); /* not complete */ 439 } 440 441 static uint8_t 442 atmegadci_data_tx(struct atmegadci_td *td) 443 { 444 struct atmegadci_softc *sc; 445 struct usb_page_search buf_res; 446 uint16_t count; 447 uint8_t to; 448 uint8_t temp; 449 450 to = 3; /* don't loop forever! */ 451 452 /* get pointer to softc */ 453 sc = ATMEGA_PC2SC(td->pc); 454 455 /* select endpoint number */ 456 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, td->ep_no); 457 458 repeat: 459 460 /* check endpoint status */ 461 temp = ATMEGA_READ_1(sc, ATMEGA_UEINTX); 462 463 DPRINTFN(5, "temp=0x%02x rem=%u\n", temp, td->remainder); 464 465 if (temp & ATMEGA_UEINTX_RXSTPI) { 466 /* 467 * The current transfer was aborted 468 * by the USB Host 469 */ 470 td->error = 1; 471 return (0); /* complete */ 472 } 473 474 temp = ATMEGA_READ_1(sc, ATMEGA_UESTA0X); 475 if (temp & 3) { 476 /* cannot write any data - a bank is busy */ 477 goto not_complete; 478 } 479 480 count = td->max_packet_size; 481 if (td->remainder < count) { 482 /* we have a short packet */ 483 td->short_pkt = 1; 484 count = td->remainder; 485 } 486 while (count > 0) { 487 usbd_get_page(td->pc, td->offset, &buf_res); 488 489 /* get correct length */ 490 if (buf_res.length > count) { 491 buf_res.length = count; 492 } 493 /* transmit data */ 494 ATMEGA_WRITE_MULTI_1(sc, ATMEGA_UEDATX, 495 buf_res.buffer, buf_res.length); 496 497 /* update counters */ 498 count -= buf_res.length; 499 td->offset += buf_res.length; 500 td->remainder -= buf_res.length; 501 } 502 503 /* clear IN packet interrupt */ 504 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, 0xFF ^ ATMEGA_UEINTX_TXINI); 505 506 /* allocate FIFO bank */ 507 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, 0xFF ^ ATMEGA_UEINTX_FIFOCON); 508 509 /* check remainder */ 510 if (td->remainder == 0) { 511 if (td->short_pkt) { 512 return (0); /* complete */ 513 } 514 /* else we need to transmit a short packet */ 515 } 516 if (--to) { 517 goto repeat; 518 } 519 not_complete: 520 /* we only want to know if there is a SETUP packet or free IN packet */ 521 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, 522 ATMEGA_UEIENX_RXSTPE | ATMEGA_UEIENX_TXINE); 523 return (1); /* not complete */ 524 } 525 526 static uint8_t 527 atmegadci_data_tx_sync(struct atmegadci_td *td) 528 { 529 struct atmegadci_softc *sc; 530 uint8_t temp; 531 532 /* get pointer to softc */ 533 sc = ATMEGA_PC2SC(td->pc); 534 535 /* select endpoint number */ 536 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, td->ep_no); 537 538 /* check endpoint status */ 539 temp = ATMEGA_READ_1(sc, ATMEGA_UEINTX); 540 541 DPRINTFN(5, "temp=0x%02x\n", temp); 542 543 if (temp & ATMEGA_UEINTX_RXSTPI) { 544 DPRINTFN(5, "faking complete\n"); 545 /* Race condition */ 546 return (0); /* complete */ 547 } 548 /* 549 * The control endpoint has only got one bank, so if that bank 550 * is free the packet has been transferred! 551 */ 552 temp = ATMEGA_READ_1(sc, ATMEGA_UESTA0X); 553 if (temp & 3) { 554 /* cannot write any data - a bank is busy */ 555 goto not_complete; 556 } 557 if (sc->sc_dv_addr != 0xFF) { 558 /* set new address */ 559 atmegadci_set_address(sc, sc->sc_dv_addr); 560 } 561 return (0); /* complete */ 562 563 not_complete: 564 /* we only want to know if there is a SETUP packet or free IN packet */ 565 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, 566 ATMEGA_UEIENX_RXSTPE | ATMEGA_UEIENX_TXINE); 567 return (1); /* not complete */ 568 } 569 570 static uint8_t 571 atmegadci_xfer_do_fifo(struct usb_xfer *xfer) 572 { 573 struct atmegadci_td *td; 574 575 DPRINTFN(9, "\n"); 576 577 td = xfer->td_transfer_cache; 578 while (1) { 579 if ((td->func) (td)) { 580 /* operation in progress */ 581 break; 582 } 583 if (((void *)td) == xfer->td_transfer_last) { 584 goto done; 585 } 586 if (td->error) { 587 goto done; 588 } else if (td->remainder > 0) { 589 /* 590 * We had a short transfer. If there is no alternate 591 * next, stop processing ! 592 */ 593 if (!td->alt_next) { 594 goto done; 595 } 596 } 597 /* 598 * Fetch the next transfer descriptor and transfer 599 * some flags to the next transfer descriptor 600 */ 601 td = td->obj_next; 602 xfer->td_transfer_cache = td; 603 } 604 return (1); /* not complete */ 605 606 done: 607 /* compute all actual lengths */ 608 609 atmegadci_standard_done(xfer); 610 return (0); /* complete */ 611 } 612 613 static void 614 atmegadci_interrupt_poll(struct atmegadci_softc *sc) 615 { 616 struct usb_xfer *xfer; 617 618 repeat: 619 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 620 if (!atmegadci_xfer_do_fifo(xfer)) { 621 /* queue has been modified */ 622 goto repeat; 623 } 624 } 625 } 626 627 static void 628 atmegadci_vbus_interrupt(struct atmegadci_softc *sc, uint8_t is_on) 629 { 630 DPRINTFN(5, "vbus = %u\n", is_on); 631 632 if (is_on) { 633 if (!sc->sc_flags.status_vbus) { 634 sc->sc_flags.status_vbus = 1; 635 636 /* complete root HUB interrupt endpoint */ 637 638 atmegadci_root_intr(sc); 639 } 640 } else { 641 if (sc->sc_flags.status_vbus) { 642 sc->sc_flags.status_vbus = 0; 643 sc->sc_flags.status_bus_reset = 0; 644 sc->sc_flags.status_suspend = 0; 645 sc->sc_flags.change_suspend = 0; 646 sc->sc_flags.change_connect = 1; 647 648 /* complete root HUB interrupt endpoint */ 649 650 atmegadci_root_intr(sc); 651 } 652 } 653 } 654 655 void 656 atmegadci_interrupt(struct atmegadci_softc *sc) 657 { 658 uint8_t status; 659 660 USB_BUS_LOCK(&sc->sc_bus); 661 662 /* read interrupt status */ 663 status = ATMEGA_READ_1(sc, ATMEGA_UDINT); 664 665 /* clear all set interrupts */ 666 ATMEGA_WRITE_1(sc, ATMEGA_UDINT, (~status) & 0x7D); 667 668 DPRINTFN(14, "UDINT=0x%02x\n", status); 669 670 /* check for any bus state change interrupts */ 671 if (status & ATMEGA_UDINT_EORSTI) { 672 DPRINTFN(5, "end of reset\n"); 673 674 /* set correct state */ 675 sc->sc_flags.status_bus_reset = 1; 676 sc->sc_flags.status_suspend = 0; 677 sc->sc_flags.change_suspend = 0; 678 sc->sc_flags.change_connect = 1; 679 680 /* disable resume interrupt */ 681 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN, 682 ATMEGA_UDINT_SUSPE | 683 ATMEGA_UDINT_EORSTE); 684 685 /* complete root HUB interrupt endpoint */ 686 atmegadci_root_intr(sc); 687 } 688 /* 689 * If resume and suspend is set at the same time we interpret 690 * that like RESUME. Resume is set when there is at least 3 691 * milliseconds of inactivity on the USB BUS. 692 */ 693 if (status & ATMEGA_UDINT_WAKEUPI) { 694 DPRINTFN(5, "resume interrupt\n"); 695 696 if (sc->sc_flags.status_suspend) { 697 /* update status bits */ 698 sc->sc_flags.status_suspend = 0; 699 sc->sc_flags.change_suspend = 1; 700 701 /* disable resume interrupt */ 702 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN, 703 ATMEGA_UDINT_SUSPE | 704 ATMEGA_UDINT_EORSTE); 705 706 /* complete root HUB interrupt endpoint */ 707 atmegadci_root_intr(sc); 708 } 709 } else if (status & ATMEGA_UDINT_SUSPI) { 710 DPRINTFN(5, "suspend interrupt\n"); 711 712 if (!sc->sc_flags.status_suspend) { 713 /* update status bits */ 714 sc->sc_flags.status_suspend = 1; 715 sc->sc_flags.change_suspend = 1; 716 717 /* disable suspend interrupt */ 718 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN, 719 ATMEGA_UDINT_WAKEUPE | 720 ATMEGA_UDINT_EORSTE); 721 722 /* complete root HUB interrupt endpoint */ 723 atmegadci_root_intr(sc); 724 } 725 } 726 /* check VBUS */ 727 status = ATMEGA_READ_1(sc, ATMEGA_USBINT); 728 729 /* clear all set interrupts */ 730 ATMEGA_WRITE_1(sc, ATMEGA_USBINT, (~status) & 0x03); 731 732 if (status & ATMEGA_USBINT_VBUSTI) { 733 uint8_t temp; 734 735 DPRINTFN(5, "USBINT=0x%02x\n", status); 736 737 temp = ATMEGA_READ_1(sc, ATMEGA_USBSTA); 738 atmegadci_vbus_interrupt(sc, temp & ATMEGA_USBSTA_VBUS); 739 } 740 /* check for any endpoint interrupts */ 741 status = ATMEGA_READ_1(sc, ATMEGA_UEINT); 742 /* the hardware will clear the UEINT bits automatically */ 743 if (status) { 744 DPRINTFN(5, "real endpoint interrupt UEINT=0x%02x\n", status); 745 746 atmegadci_interrupt_poll(sc); 747 } 748 USB_BUS_UNLOCK(&sc->sc_bus); 749 } 750 751 static void 752 atmegadci_setup_standard_chain_sub(struct atmegadci_std_temp *temp) 753 { 754 struct atmegadci_td *td; 755 756 /* get current Transfer Descriptor */ 757 td = temp->td_next; 758 temp->td = td; 759 760 /* prepare for next TD */ 761 temp->td_next = td->obj_next; 762 763 /* fill out the Transfer Descriptor */ 764 td->func = temp->func; 765 td->pc = temp->pc; 766 td->offset = temp->offset; 767 td->remainder = temp->len; 768 td->error = 0; 769 td->did_stall = temp->did_stall; 770 td->short_pkt = temp->short_pkt; 771 td->alt_next = temp->setup_alt_next; 772 } 773 774 static void 775 atmegadci_setup_standard_chain(struct usb_xfer *xfer) 776 { 777 struct atmegadci_std_temp temp; 778 struct atmegadci_td *td; 779 uint32_t x; 780 uint8_t need_sync; 781 782 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 783 xfer->address, UE_GET_ADDR(xfer->endpointno), 784 xfer->sumlen, usbd_get_speed(xfer->xroot->udev)); 785 786 temp.max_frame_size = xfer->max_frame_size; 787 788 td = xfer->td_start[0]; 789 xfer->td_transfer_first = td; 790 xfer->td_transfer_cache = td; 791 792 /* setup temp */ 793 794 temp.pc = NULL; 795 temp.td = NULL; 796 temp.td_next = xfer->td_start[0]; 797 temp.offset = 0; 798 temp.setup_alt_next = xfer->flags_int.short_frames_ok || 799 xfer->flags_int.isochronous_xfr; 800 temp.did_stall = !xfer->flags_int.control_stall; 801 802 /* check if we should prepend a setup message */ 803 804 if (xfer->flags_int.control_xfr) { 805 if (xfer->flags_int.control_hdr) { 806 temp.func = &atmegadci_setup_rx; 807 temp.len = xfer->frlengths[0]; 808 temp.pc = xfer->frbuffers + 0; 809 temp.short_pkt = temp.len ? 1 : 0; 810 /* check for last frame */ 811 if (xfer->nframes == 1) { 812 /* no STATUS stage yet, SETUP is last */ 813 if (xfer->flags_int.control_act) 814 temp.setup_alt_next = 0; 815 } 816 817 atmegadci_setup_standard_chain_sub(&temp); 818 } 819 x = 1; 820 } else { 821 x = 0; 822 } 823 824 if (x != xfer->nframes) { 825 if (xfer->endpointno & UE_DIR_IN) { 826 temp.func = &atmegadci_data_tx; 827 need_sync = 1; 828 } else { 829 temp.func = &atmegadci_data_rx; 830 need_sync = 0; 831 } 832 833 /* setup "pc" pointer */ 834 temp.pc = xfer->frbuffers + x; 835 } else { 836 need_sync = 0; 837 } 838 while (x != xfer->nframes) { 839 /* DATA0 / DATA1 message */ 840 841 temp.len = xfer->frlengths[x]; 842 843 x++; 844 845 if (x == xfer->nframes) { 846 if (xfer->flags_int.control_xfr) { 847 if (xfer->flags_int.control_act) { 848 temp.setup_alt_next = 0; 849 } 850 } else { 851 temp.setup_alt_next = 0; 852 } 853 } 854 if (temp.len == 0) { 855 /* make sure that we send an USB packet */ 856 857 temp.short_pkt = 0; 858 859 } else { 860 /* regular data transfer */ 861 862 temp.short_pkt = (xfer->flags.force_short_xfer) ? 0 : 1; 863 } 864 865 atmegadci_setup_standard_chain_sub(&temp); 866 867 if (xfer->flags_int.isochronous_xfr) { 868 temp.offset += temp.len; 869 } else { 870 /* get next Page Cache pointer */ 871 temp.pc = xfer->frbuffers + x; 872 } 873 } 874 875 if (xfer->flags_int.control_xfr) { 876 /* always setup a valid "pc" pointer for status and sync */ 877 temp.pc = xfer->frbuffers + 0; 878 temp.len = 0; 879 temp.short_pkt = 0; 880 temp.setup_alt_next = 0; 881 882 /* check if we need to sync */ 883 if (need_sync) { 884 /* we need a SYNC point after TX */ 885 temp.func = &atmegadci_data_tx_sync; 886 atmegadci_setup_standard_chain_sub(&temp); 887 } 888 889 /* check if we should append a status stage */ 890 if (!xfer->flags_int.control_act) { 891 /* 892 * Send a DATA1 message and invert the current 893 * endpoint direction. 894 */ 895 if (xfer->endpointno & UE_DIR_IN) { 896 temp.func = &atmegadci_data_rx; 897 need_sync = 0; 898 } else { 899 temp.func = &atmegadci_data_tx; 900 need_sync = 1; 901 } 902 903 atmegadci_setup_standard_chain_sub(&temp); 904 if (need_sync) { 905 /* we need a SYNC point after TX */ 906 temp.func = &atmegadci_data_tx_sync; 907 atmegadci_setup_standard_chain_sub(&temp); 908 } 909 } 910 } 911 /* must have at least one frame! */ 912 td = temp.td; 913 xfer->td_transfer_last = td; 914 } 915 916 static void 917 atmegadci_timeout(void *arg) 918 { 919 struct usb_xfer *xfer = arg; 920 921 DPRINTF("xfer=%p\n", xfer); 922 923 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 924 925 /* transfer is transferred */ 926 atmegadci_device_done(xfer, USB_ERR_TIMEOUT); 927 } 928 929 static void 930 atmegadci_start_standard_chain(struct usb_xfer *xfer) 931 { 932 DPRINTFN(9, "\n"); 933 934 /* poll one time - will turn on interrupts */ 935 if (atmegadci_xfer_do_fifo(xfer)) { 936 /* put transfer on interrupt queue */ 937 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 938 939 /* start timeout, if any */ 940 if (xfer->timeout != 0) { 941 usbd_transfer_timeout_ms(xfer, 942 &atmegadci_timeout, xfer->timeout); 943 } 944 } 945 } 946 947 static void 948 atmegadci_root_intr(struct atmegadci_softc *sc) 949 { 950 DPRINTFN(9, "\n"); 951 952 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 953 954 /* set port bit */ 955 sc->sc_hub_idata[0] = 0x02; /* we only have one port */ 956 957 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 958 sizeof(sc->sc_hub_idata)); 959 } 960 961 static usb_error_t 962 atmegadci_standard_done_sub(struct usb_xfer *xfer) 963 { 964 struct atmegadci_td *td; 965 uint32_t len; 966 uint8_t error; 967 968 DPRINTFN(9, "\n"); 969 970 td = xfer->td_transfer_cache; 971 972 do { 973 len = td->remainder; 974 975 if (xfer->aframes != xfer->nframes) { 976 /* 977 * Verify the length and subtract 978 * the remainder from "frlengths[]": 979 */ 980 if (len > xfer->frlengths[xfer->aframes]) { 981 td->error = 1; 982 } else { 983 xfer->frlengths[xfer->aframes] -= len; 984 } 985 } 986 /* Check for transfer error */ 987 if (td->error) { 988 /* the transfer is finished */ 989 error = 1; 990 td = NULL; 991 break; 992 } 993 /* Check for short transfer */ 994 if (len > 0) { 995 if (xfer->flags_int.short_frames_ok || 996 xfer->flags_int.isochronous_xfr) { 997 /* follow alt next */ 998 if (td->alt_next) { 999 td = td->obj_next; 1000 } else { 1001 td = NULL; 1002 } 1003 } else { 1004 /* the transfer is finished */ 1005 td = NULL; 1006 } 1007 error = 0; 1008 break; 1009 } 1010 td = td->obj_next; 1011 1012 /* this USB frame is complete */ 1013 error = 0; 1014 break; 1015 1016 } while (0); 1017 1018 /* update transfer cache */ 1019 1020 xfer->td_transfer_cache = td; 1021 1022 return (error ? 1023 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION); 1024 } 1025 1026 static void 1027 atmegadci_standard_done(struct usb_xfer *xfer) 1028 { 1029 usb_error_t err = 0; 1030 1031 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 1032 xfer, xfer->endpoint); 1033 1034 /* reset scanner */ 1035 1036 xfer->td_transfer_cache = xfer->td_transfer_first; 1037 1038 if (xfer->flags_int.control_xfr) { 1039 if (xfer->flags_int.control_hdr) { 1040 err = atmegadci_standard_done_sub(xfer); 1041 } 1042 xfer->aframes = 1; 1043 1044 if (xfer->td_transfer_cache == NULL) { 1045 goto done; 1046 } 1047 } 1048 while (xfer->aframes != xfer->nframes) { 1049 err = atmegadci_standard_done_sub(xfer); 1050 xfer->aframes++; 1051 1052 if (xfer->td_transfer_cache == NULL) { 1053 goto done; 1054 } 1055 } 1056 1057 if (xfer->flags_int.control_xfr && 1058 !xfer->flags_int.control_act) { 1059 err = atmegadci_standard_done_sub(xfer); 1060 } 1061 done: 1062 atmegadci_device_done(xfer, err); 1063 } 1064 1065 /*------------------------------------------------------------------------* 1066 * atmegadci_device_done 1067 * 1068 * NOTE: this function can be called more than one time on the 1069 * same USB transfer! 1070 *------------------------------------------------------------------------*/ 1071 static void 1072 atmegadci_device_done(struct usb_xfer *xfer, usb_error_t error) 1073 { 1074 struct atmegadci_softc *sc = ATMEGA_BUS2SC(xfer->xroot->bus); 1075 uint8_t ep_no; 1076 1077 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1078 1079 DPRINTFN(9, "xfer=%p, endpoint=%p, error=%d\n", 1080 xfer, xfer->endpoint, error); 1081 1082 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) { 1083 ep_no = (xfer->endpointno & UE_ADDR); 1084 1085 /* select endpoint number */ 1086 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, ep_no); 1087 1088 /* disable endpoint interrupt */ 1089 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, 0); 1090 1091 DPRINTFN(15, "disabled interrupts!\n"); 1092 } 1093 /* dequeue transfer and start next transfer */ 1094 usbd_transfer_done(xfer, error); 1095 } 1096 1097 static void 1098 atmegadci_xfer_stall(struct usb_xfer *xfer) 1099 { 1100 atmegadci_device_done(xfer, USB_ERR_STALLED); 1101 } 1102 1103 static void 1104 atmegadci_set_stall(struct usb_device *udev, 1105 struct usb_endpoint *ep, uint8_t *did_stall) 1106 { 1107 struct atmegadci_softc *sc; 1108 uint8_t ep_no; 1109 1110 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 1111 1112 DPRINTFN(5, "endpoint=%p\n", ep); 1113 1114 sc = ATMEGA_BUS2SC(udev->bus); 1115 /* get endpoint number */ 1116 ep_no = (ep->edesc->bEndpointAddress & UE_ADDR); 1117 /* select endpoint number */ 1118 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, ep_no); 1119 /* set stall */ 1120 ATMEGA_WRITE_1(sc, ATMEGA_UECONX, 1121 ATMEGA_UECONX_EPEN | 1122 ATMEGA_UECONX_STALLRQ); 1123 } 1124 1125 static void 1126 atmegadci_clear_stall_sub(struct atmegadci_softc *sc, uint8_t ep_no, 1127 uint8_t ep_type, uint8_t ep_dir) 1128 { 1129 uint8_t temp; 1130 1131 if (ep_type == UE_CONTROL) { 1132 /* clearing stall is not needed */ 1133 return; 1134 } 1135 /* select endpoint number */ 1136 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, ep_no); 1137 1138 /* set endpoint reset */ 1139 ATMEGA_WRITE_1(sc, ATMEGA_UERST, ATMEGA_UERST_MASK(ep_no)); 1140 1141 /* clear endpoint reset */ 1142 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 0); 1143 1144 /* set stall */ 1145 ATMEGA_WRITE_1(sc, ATMEGA_UECONX, 1146 ATMEGA_UECONX_EPEN | 1147 ATMEGA_UECONX_STALLRQ); 1148 1149 /* reset data toggle */ 1150 ATMEGA_WRITE_1(sc, ATMEGA_UECONX, 1151 ATMEGA_UECONX_EPEN | 1152 ATMEGA_UECONX_RSTDT); 1153 1154 /* clear stall */ 1155 ATMEGA_WRITE_1(sc, ATMEGA_UECONX, 1156 ATMEGA_UECONX_EPEN | 1157 ATMEGA_UECONX_STALLRQC); 1158 1159 do { 1160 if (ep_type == UE_BULK) { 1161 temp = ATMEGA_UECFG0X_EPTYPE2; 1162 } else if (ep_type == UE_INTERRUPT) { 1163 temp = ATMEGA_UECFG0X_EPTYPE3; 1164 } else { 1165 temp = ATMEGA_UECFG0X_EPTYPE1; 1166 } 1167 if (ep_dir & UE_DIR_IN) { 1168 temp |= ATMEGA_UECFG0X_EPDIR; 1169 } 1170 /* two banks, 64-bytes wMaxPacket */ 1171 ATMEGA_WRITE_1(sc, ATMEGA_UECFG0X, temp); 1172 ATMEGA_WRITE_1(sc, ATMEGA_UECFG1X, 1173 ATMEGA_UECFG1X_ALLOC | 1174 ATMEGA_UECFG1X_EPBK0 | /* one bank */ 1175 ATMEGA_UECFG1X_EPSIZE(3)); 1176 1177 temp = ATMEGA_READ_1(sc, ATMEGA_UESTA0X); 1178 if (!(temp & ATMEGA_UESTA0X_CFGOK)) { 1179 device_printf(sc->sc_bus.bdev, 1180 "Chip rejected configuration\n"); 1181 } 1182 } while (0); 1183 } 1184 1185 static void 1186 atmegadci_clear_stall(struct usb_device *udev, struct usb_endpoint *ep) 1187 { 1188 struct atmegadci_softc *sc; 1189 struct usb_endpoint_descriptor *ed; 1190 1191 DPRINTFN(5, "endpoint=%p\n", ep); 1192 1193 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 1194 1195 /* check mode */ 1196 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 1197 /* not supported */ 1198 return; 1199 } 1200 /* get softc */ 1201 sc = ATMEGA_BUS2SC(udev->bus); 1202 1203 /* get endpoint descriptor */ 1204 ed = ep->edesc; 1205 1206 /* reset endpoint */ 1207 atmegadci_clear_stall_sub(sc, 1208 (ed->bEndpointAddress & UE_ADDR), 1209 (ed->bmAttributes & UE_XFERTYPE), 1210 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT))); 1211 } 1212 1213 usb_error_t 1214 atmegadci_init(struct atmegadci_softc *sc) 1215 { 1216 uint8_t n; 1217 1218 DPRINTF("start\n"); 1219 1220 /* set up the bus structure */ 1221 sc->sc_bus.usbrev = USB_REV_1_1; 1222 sc->sc_bus.methods = &atmegadci_bus_methods; 1223 1224 USB_BUS_LOCK(&sc->sc_bus); 1225 1226 /* make sure USB is enabled */ 1227 ATMEGA_WRITE_1(sc, ATMEGA_USBCON, 1228 ATMEGA_USBCON_USBE | 1229 ATMEGA_USBCON_FRZCLK); 1230 1231 /* enable USB PAD regulator */ 1232 ATMEGA_WRITE_1(sc, ATMEGA_UHWCON, 1233 ATMEGA_UHWCON_UVREGE | 1234 ATMEGA_UHWCON_UIMOD); 1235 1236 /* the following register sets up the USB PLL, assuming 16MHz X-tal */ 1237 ATMEGA_WRITE_1(sc, 0x49 /* PLLCSR */, 0x14 | 0x02); 1238 1239 /* wait for PLL to lock */ 1240 for (n = 0; n != 20; n++) { 1241 if (ATMEGA_READ_1(sc, 0x49) & 0x01) 1242 break; 1243 /* wait a little bit for PLL to start */ 1244 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); 1245 } 1246 1247 /* make sure USB is enabled */ 1248 ATMEGA_WRITE_1(sc, ATMEGA_USBCON, 1249 ATMEGA_USBCON_USBE | 1250 ATMEGA_USBCON_OTGPADE | 1251 ATMEGA_USBCON_VBUSTE); 1252 1253 /* turn on clocks */ 1254 (sc->sc_clocks_on) (&sc->sc_bus); 1255 1256 /* make sure device is re-enumerated */ 1257 ATMEGA_WRITE_1(sc, ATMEGA_UDCON, ATMEGA_UDCON_DETACH); 1258 1259 /* wait a little for things to stabilise */ 1260 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 20); 1261 1262 /* enable interrupts */ 1263 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN, 1264 ATMEGA_UDINT_SUSPE | 1265 ATMEGA_UDINT_EORSTE); 1266 1267 /* reset all endpoints */ 1268 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 1269 (1 << ATMEGA_EP_MAX) - 1); 1270 1271 /* disable reset */ 1272 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 0); 1273 1274 /* disable all endpoints */ 1275 for (n = 0; n != ATMEGA_EP_MAX; n++) { 1276 /* select endpoint */ 1277 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, n); 1278 1279 /* disable endpoint interrupt */ 1280 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, 0); 1281 1282 /* disable endpoint */ 1283 ATMEGA_WRITE_1(sc, ATMEGA_UECONX, 0); 1284 } 1285 1286 /* turn off clocks */ 1287 1288 atmegadci_clocks_off(sc); 1289 1290 /* read initial VBUS state */ 1291 1292 n = ATMEGA_READ_1(sc, ATMEGA_USBSTA); 1293 atmegadci_vbus_interrupt(sc, n & ATMEGA_USBSTA_VBUS); 1294 1295 USB_BUS_UNLOCK(&sc->sc_bus); 1296 1297 /* catch any lost interrupts */ 1298 1299 atmegadci_do_poll(&sc->sc_bus); 1300 1301 return (0); /* success */ 1302 } 1303 1304 void 1305 atmegadci_uninit(struct atmegadci_softc *sc) 1306 { 1307 USB_BUS_LOCK(&sc->sc_bus); 1308 1309 /* turn on clocks */ 1310 (sc->sc_clocks_on) (&sc->sc_bus); 1311 1312 /* disable interrupts */ 1313 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN, 0); 1314 1315 /* reset all endpoints */ 1316 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 1317 (1 << ATMEGA_EP_MAX) - 1); 1318 1319 /* disable reset */ 1320 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 0); 1321 1322 sc->sc_flags.port_powered = 0; 1323 sc->sc_flags.status_vbus = 0; 1324 sc->sc_flags.status_bus_reset = 0; 1325 sc->sc_flags.status_suspend = 0; 1326 sc->sc_flags.change_suspend = 0; 1327 sc->sc_flags.change_connect = 1; 1328 1329 atmegadci_pull_down(sc); 1330 atmegadci_clocks_off(sc); 1331 1332 /* disable USB PAD regulator */ 1333 ATMEGA_WRITE_1(sc, ATMEGA_UHWCON, 0); 1334 1335 USB_BUS_UNLOCK(&sc->sc_bus); 1336 } 1337 1338 static void 1339 atmegadci_suspend(struct atmegadci_softc *sc) 1340 { 1341 /* TODO */ 1342 } 1343 1344 static void 1345 atmegadci_resume(struct atmegadci_softc *sc) 1346 { 1347 /* TODO */ 1348 } 1349 1350 static void 1351 atmegadci_do_poll(struct usb_bus *bus) 1352 { 1353 struct atmegadci_softc *sc = ATMEGA_BUS2SC(bus); 1354 1355 USB_BUS_LOCK(&sc->sc_bus); 1356 atmegadci_interrupt_poll(sc); 1357 USB_BUS_UNLOCK(&sc->sc_bus); 1358 } 1359 1360 /*------------------------------------------------------------------------* 1361 * atmegadci bulk support 1362 * atmegadci control support 1363 * atmegadci interrupt support 1364 *------------------------------------------------------------------------*/ 1365 static void 1366 atmegadci_device_non_isoc_open(struct usb_xfer *xfer) 1367 { 1368 return; 1369 } 1370 1371 static void 1372 atmegadci_device_non_isoc_close(struct usb_xfer *xfer) 1373 { 1374 atmegadci_device_done(xfer, USB_ERR_CANCELLED); 1375 } 1376 1377 static void 1378 atmegadci_device_non_isoc_enter(struct usb_xfer *xfer) 1379 { 1380 return; 1381 } 1382 1383 static void 1384 atmegadci_device_non_isoc_start(struct usb_xfer *xfer) 1385 { 1386 /* setup TDs */ 1387 atmegadci_setup_standard_chain(xfer); 1388 atmegadci_start_standard_chain(xfer); 1389 } 1390 1391 static const struct usb_pipe_methods atmegadci_device_non_isoc_methods = 1392 { 1393 .open = atmegadci_device_non_isoc_open, 1394 .close = atmegadci_device_non_isoc_close, 1395 .enter = atmegadci_device_non_isoc_enter, 1396 .start = atmegadci_device_non_isoc_start, 1397 }; 1398 1399 /*------------------------------------------------------------------------* 1400 * atmegadci full speed isochronous support 1401 *------------------------------------------------------------------------*/ 1402 static void 1403 atmegadci_device_isoc_fs_open(struct usb_xfer *xfer) 1404 { 1405 return; 1406 } 1407 1408 static void 1409 atmegadci_device_isoc_fs_close(struct usb_xfer *xfer) 1410 { 1411 atmegadci_device_done(xfer, USB_ERR_CANCELLED); 1412 } 1413 1414 static void 1415 atmegadci_device_isoc_fs_enter(struct usb_xfer *xfer) 1416 { 1417 struct atmegadci_softc *sc = ATMEGA_BUS2SC(xfer->xroot->bus); 1418 uint32_t nframes; 1419 1420 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 1421 xfer, xfer->endpoint->isoc_next, xfer->nframes); 1422 1423 /* get the current frame index */ 1424 1425 nframes = 1426 (ATMEGA_READ_1(sc, ATMEGA_UDFNUMH) << 8) | 1427 (ATMEGA_READ_1(sc, ATMEGA_UDFNUML)); 1428 1429 if (usbd_xfer_get_isochronous_start_frame( 1430 xfer, nframes, 0, 1, ATMEGA_FRAME_MASK, NULL)) 1431 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 1432 1433 /* setup TDs */ 1434 atmegadci_setup_standard_chain(xfer); 1435 } 1436 1437 static void 1438 atmegadci_device_isoc_fs_start(struct usb_xfer *xfer) 1439 { 1440 /* start TD chain */ 1441 atmegadci_start_standard_chain(xfer); 1442 } 1443 1444 static const struct usb_pipe_methods atmegadci_device_isoc_fs_methods = 1445 { 1446 .open = atmegadci_device_isoc_fs_open, 1447 .close = atmegadci_device_isoc_fs_close, 1448 .enter = atmegadci_device_isoc_fs_enter, 1449 .start = atmegadci_device_isoc_fs_start, 1450 }; 1451 1452 /*------------------------------------------------------------------------* 1453 * atmegadci root control support 1454 *------------------------------------------------------------------------* 1455 * Simulate a hardware HUB by handling all the necessary requests. 1456 *------------------------------------------------------------------------*/ 1457 1458 static const struct usb_device_descriptor atmegadci_devd = { 1459 .bLength = sizeof(struct usb_device_descriptor), 1460 .bDescriptorType = UDESC_DEVICE, 1461 .bcdUSB = {0x00, 0x02}, 1462 .bDeviceClass = UDCLASS_HUB, 1463 .bDeviceSubClass = UDSUBCLASS_HUB, 1464 .bDeviceProtocol = UDPROTO_FSHUB, 1465 .bMaxPacketSize = 64, 1466 .bcdDevice = {0x00, 0x01}, 1467 .iManufacturer = 1, 1468 .iProduct = 2, 1469 .bNumConfigurations = 1, 1470 }; 1471 1472 static const struct atmegadci_config_desc atmegadci_confd = { 1473 .confd = { 1474 .bLength = sizeof(struct usb_config_descriptor), 1475 .bDescriptorType = UDESC_CONFIG, 1476 .wTotalLength[0] = sizeof(atmegadci_confd), 1477 .bNumInterface = 1, 1478 .bConfigurationValue = 1, 1479 .iConfiguration = 0, 1480 .bmAttributes = UC_SELF_POWERED, 1481 .bMaxPower = 0, 1482 }, 1483 .ifcd = { 1484 .bLength = sizeof(struct usb_interface_descriptor), 1485 .bDescriptorType = UDESC_INTERFACE, 1486 .bNumEndpoints = 1, 1487 .bInterfaceClass = UICLASS_HUB, 1488 .bInterfaceSubClass = UISUBCLASS_HUB, 1489 .bInterfaceProtocol = 0, 1490 }, 1491 .endpd = { 1492 .bLength = sizeof(struct usb_endpoint_descriptor), 1493 .bDescriptorType = UDESC_ENDPOINT, 1494 .bEndpointAddress = (UE_DIR_IN | ATMEGA_INTR_ENDPT), 1495 .bmAttributes = UE_INTERRUPT, 1496 .wMaxPacketSize[0] = 8, 1497 .bInterval = 255, 1498 }, 1499 }; 1500 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) } 1501 1502 static const struct usb_hub_descriptor_min atmegadci_hubd = { 1503 .bDescLength = sizeof(atmegadci_hubd), 1504 .bDescriptorType = UDESC_HUB, 1505 .bNbrPorts = 1, 1506 HSETW(.wHubCharacteristics, (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL)), 1507 .bPwrOn2PwrGood = 50, 1508 .bHubContrCurrent = 0, 1509 .DeviceRemovable = {0}, /* port is removable */ 1510 }; 1511 1512 #define STRING_VENDOR \ 1513 "A\0T\0M\0E\0G\0A" 1514 1515 #define STRING_PRODUCT \ 1516 "D\0C\0I\0 \0R\0o\0o\0t\0 \0H\0U\0B" 1517 1518 USB_MAKE_STRING_DESC(STRING_VENDOR, atmegadci_vendor); 1519 USB_MAKE_STRING_DESC(STRING_PRODUCT, atmegadci_product); 1520 1521 static usb_error_t 1522 atmegadci_roothub_exec(struct usb_device *udev, 1523 struct usb_device_request *req, const void **pptr, uint16_t *plength) 1524 { 1525 struct atmegadci_softc *sc = ATMEGA_BUS2SC(udev->bus); 1526 const void *ptr; 1527 uint16_t len; 1528 uint16_t value; 1529 uint16_t index; 1530 uint8_t temp; 1531 usb_error_t err; 1532 1533 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1534 1535 /* buffer reset */ 1536 ptr = (const void *)&sc->sc_hub_temp; 1537 len = 0; 1538 err = 0; 1539 1540 value = UGETW(req->wValue); 1541 index = UGETW(req->wIndex); 1542 1543 /* demultiplex the control request */ 1544 1545 switch (req->bmRequestType) { 1546 case UT_READ_DEVICE: 1547 switch (req->bRequest) { 1548 case UR_GET_DESCRIPTOR: 1549 goto tr_handle_get_descriptor; 1550 case UR_GET_CONFIG: 1551 goto tr_handle_get_config; 1552 case UR_GET_STATUS: 1553 goto tr_handle_get_status; 1554 default: 1555 goto tr_stalled; 1556 } 1557 break; 1558 1559 case UT_WRITE_DEVICE: 1560 switch (req->bRequest) { 1561 case UR_SET_ADDRESS: 1562 goto tr_handle_set_address; 1563 case UR_SET_CONFIG: 1564 goto tr_handle_set_config; 1565 case UR_CLEAR_FEATURE: 1566 goto tr_valid; /* nop */ 1567 case UR_SET_DESCRIPTOR: 1568 goto tr_valid; /* nop */ 1569 case UR_SET_FEATURE: 1570 default: 1571 goto tr_stalled; 1572 } 1573 break; 1574 1575 case UT_WRITE_ENDPOINT: 1576 switch (req->bRequest) { 1577 case UR_CLEAR_FEATURE: 1578 switch (UGETW(req->wValue)) { 1579 case UF_ENDPOINT_HALT: 1580 goto tr_handle_clear_halt; 1581 case UF_DEVICE_REMOTE_WAKEUP: 1582 goto tr_handle_clear_wakeup; 1583 default: 1584 goto tr_stalled; 1585 } 1586 break; 1587 case UR_SET_FEATURE: 1588 switch (UGETW(req->wValue)) { 1589 case UF_ENDPOINT_HALT: 1590 goto tr_handle_set_halt; 1591 case UF_DEVICE_REMOTE_WAKEUP: 1592 goto tr_handle_set_wakeup; 1593 default: 1594 goto tr_stalled; 1595 } 1596 break; 1597 case UR_SYNCH_FRAME: 1598 goto tr_valid; /* nop */ 1599 default: 1600 goto tr_stalled; 1601 } 1602 break; 1603 1604 case UT_READ_ENDPOINT: 1605 switch (req->bRequest) { 1606 case UR_GET_STATUS: 1607 goto tr_handle_get_ep_status; 1608 default: 1609 goto tr_stalled; 1610 } 1611 break; 1612 1613 case UT_WRITE_INTERFACE: 1614 switch (req->bRequest) { 1615 case UR_SET_INTERFACE: 1616 goto tr_handle_set_interface; 1617 case UR_CLEAR_FEATURE: 1618 goto tr_valid; /* nop */ 1619 case UR_SET_FEATURE: 1620 default: 1621 goto tr_stalled; 1622 } 1623 break; 1624 1625 case UT_READ_INTERFACE: 1626 switch (req->bRequest) { 1627 case UR_GET_INTERFACE: 1628 goto tr_handle_get_interface; 1629 case UR_GET_STATUS: 1630 goto tr_handle_get_iface_status; 1631 default: 1632 goto tr_stalled; 1633 } 1634 break; 1635 1636 case UT_WRITE_CLASS_INTERFACE: 1637 case UT_WRITE_VENDOR_INTERFACE: 1638 /* XXX forward */ 1639 break; 1640 1641 case UT_READ_CLASS_INTERFACE: 1642 case UT_READ_VENDOR_INTERFACE: 1643 /* XXX forward */ 1644 break; 1645 1646 case UT_WRITE_CLASS_DEVICE: 1647 switch (req->bRequest) { 1648 case UR_CLEAR_FEATURE: 1649 goto tr_valid; 1650 case UR_SET_DESCRIPTOR: 1651 case UR_SET_FEATURE: 1652 break; 1653 default: 1654 goto tr_stalled; 1655 } 1656 break; 1657 1658 case UT_WRITE_CLASS_OTHER: 1659 switch (req->bRequest) { 1660 case UR_CLEAR_FEATURE: 1661 goto tr_handle_clear_port_feature; 1662 case UR_SET_FEATURE: 1663 goto tr_handle_set_port_feature; 1664 case UR_CLEAR_TT_BUFFER: 1665 case UR_RESET_TT: 1666 case UR_STOP_TT: 1667 goto tr_valid; 1668 1669 default: 1670 goto tr_stalled; 1671 } 1672 break; 1673 1674 case UT_READ_CLASS_OTHER: 1675 switch (req->bRequest) { 1676 case UR_GET_TT_STATE: 1677 goto tr_handle_get_tt_state; 1678 case UR_GET_STATUS: 1679 goto tr_handle_get_port_status; 1680 default: 1681 goto tr_stalled; 1682 } 1683 break; 1684 1685 case UT_READ_CLASS_DEVICE: 1686 switch (req->bRequest) { 1687 case UR_GET_DESCRIPTOR: 1688 goto tr_handle_get_class_descriptor; 1689 case UR_GET_STATUS: 1690 goto tr_handle_get_class_status; 1691 1692 default: 1693 goto tr_stalled; 1694 } 1695 break; 1696 default: 1697 goto tr_stalled; 1698 } 1699 goto tr_valid; 1700 1701 tr_handle_get_descriptor: 1702 switch (value >> 8) { 1703 case UDESC_DEVICE: 1704 if (value & 0xff) { 1705 goto tr_stalled; 1706 } 1707 len = sizeof(atmegadci_devd); 1708 ptr = (const void *)&atmegadci_devd; 1709 goto tr_valid; 1710 case UDESC_CONFIG: 1711 if (value & 0xff) { 1712 goto tr_stalled; 1713 } 1714 len = sizeof(atmegadci_confd); 1715 ptr = (const void *)&atmegadci_confd; 1716 goto tr_valid; 1717 case UDESC_STRING: 1718 switch (value & 0xff) { 1719 case 0: /* Language table */ 1720 len = sizeof(usb_string_lang_en); 1721 ptr = (const void *)&usb_string_lang_en; 1722 goto tr_valid; 1723 1724 case 1: /* Vendor */ 1725 len = sizeof(atmegadci_vendor); 1726 ptr = (const void *)&atmegadci_vendor; 1727 goto tr_valid; 1728 1729 case 2: /* Product */ 1730 len = sizeof(atmegadci_product); 1731 ptr = (const void *)&atmegadci_product; 1732 goto tr_valid; 1733 default: 1734 break; 1735 } 1736 break; 1737 default: 1738 goto tr_stalled; 1739 } 1740 goto tr_stalled; 1741 1742 tr_handle_get_config: 1743 len = 1; 1744 sc->sc_hub_temp.wValue[0] = sc->sc_conf; 1745 goto tr_valid; 1746 1747 tr_handle_get_status: 1748 len = 2; 1749 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED); 1750 goto tr_valid; 1751 1752 tr_handle_set_address: 1753 if (value & 0xFF00) { 1754 goto tr_stalled; 1755 } 1756 sc->sc_rt_addr = value; 1757 goto tr_valid; 1758 1759 tr_handle_set_config: 1760 if (value >= 2) { 1761 goto tr_stalled; 1762 } 1763 sc->sc_conf = value; 1764 goto tr_valid; 1765 1766 tr_handle_get_interface: 1767 len = 1; 1768 sc->sc_hub_temp.wValue[0] = 0; 1769 goto tr_valid; 1770 1771 tr_handle_get_tt_state: 1772 tr_handle_get_class_status: 1773 tr_handle_get_iface_status: 1774 tr_handle_get_ep_status: 1775 len = 2; 1776 USETW(sc->sc_hub_temp.wValue, 0); 1777 goto tr_valid; 1778 1779 tr_handle_set_halt: 1780 tr_handle_set_interface: 1781 tr_handle_set_wakeup: 1782 tr_handle_clear_wakeup: 1783 tr_handle_clear_halt: 1784 goto tr_valid; 1785 1786 tr_handle_clear_port_feature: 1787 if (index != 1) { 1788 goto tr_stalled; 1789 } 1790 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE on port %d\n", index); 1791 1792 switch (value) { 1793 case UHF_PORT_SUSPEND: 1794 atmegadci_wakeup_peer(sc); 1795 break; 1796 1797 case UHF_PORT_ENABLE: 1798 sc->sc_flags.port_enabled = 0; 1799 break; 1800 1801 case UHF_PORT_TEST: 1802 case UHF_PORT_INDICATOR: 1803 case UHF_C_PORT_ENABLE: 1804 case UHF_C_PORT_OVER_CURRENT: 1805 case UHF_C_PORT_RESET: 1806 /* nops */ 1807 break; 1808 case UHF_PORT_POWER: 1809 sc->sc_flags.port_powered = 0; 1810 atmegadci_pull_down(sc); 1811 atmegadci_clocks_off(sc); 1812 break; 1813 case UHF_C_PORT_CONNECTION: 1814 /* clear connect change flag */ 1815 sc->sc_flags.change_connect = 0; 1816 1817 if (!sc->sc_flags.status_bus_reset) { 1818 /* we are not connected */ 1819 break; 1820 } 1821 1822 /* configure the control endpoint */ 1823 1824 /* select endpoint number */ 1825 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, 0); 1826 1827 /* set endpoint reset */ 1828 ATMEGA_WRITE_1(sc, ATMEGA_UERST, ATMEGA_UERST_MASK(0)); 1829 1830 /* clear endpoint reset */ 1831 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 0); 1832 1833 /* enable and stall endpoint */ 1834 ATMEGA_WRITE_1(sc, ATMEGA_UECONX, 1835 ATMEGA_UECONX_EPEN | 1836 ATMEGA_UECONX_STALLRQ); 1837 1838 /* one bank, 64-bytes wMaxPacket */ 1839 ATMEGA_WRITE_1(sc, ATMEGA_UECFG0X, 1840 ATMEGA_UECFG0X_EPTYPE0); 1841 ATMEGA_WRITE_1(sc, ATMEGA_UECFG1X, 1842 ATMEGA_UECFG1X_ALLOC | 1843 ATMEGA_UECFG1X_EPBK0 | 1844 ATMEGA_UECFG1X_EPSIZE(3)); 1845 1846 /* check valid config */ 1847 temp = ATMEGA_READ_1(sc, ATMEGA_UESTA0X); 1848 if (!(temp & ATMEGA_UESTA0X_CFGOK)) { 1849 device_printf(sc->sc_bus.bdev, 1850 "Chip rejected EP0 configuration\n"); 1851 } 1852 break; 1853 case UHF_C_PORT_SUSPEND: 1854 sc->sc_flags.change_suspend = 0; 1855 break; 1856 default: 1857 err = USB_ERR_IOERROR; 1858 goto done; 1859 } 1860 goto tr_valid; 1861 1862 tr_handle_set_port_feature: 1863 if (index != 1) { 1864 goto tr_stalled; 1865 } 1866 DPRINTFN(9, "UR_SET_PORT_FEATURE\n"); 1867 1868 switch (value) { 1869 case UHF_PORT_ENABLE: 1870 sc->sc_flags.port_enabled = 1; 1871 break; 1872 case UHF_PORT_SUSPEND: 1873 case UHF_PORT_RESET: 1874 case UHF_PORT_TEST: 1875 case UHF_PORT_INDICATOR: 1876 /* nops */ 1877 break; 1878 case UHF_PORT_POWER: 1879 sc->sc_flags.port_powered = 1; 1880 break; 1881 default: 1882 err = USB_ERR_IOERROR; 1883 goto done; 1884 } 1885 goto tr_valid; 1886 1887 tr_handle_get_port_status: 1888 1889 DPRINTFN(9, "UR_GET_PORT_STATUS\n"); 1890 1891 if (index != 1) { 1892 goto tr_stalled; 1893 } 1894 if (sc->sc_flags.status_vbus) { 1895 atmegadci_clocks_on(sc); 1896 atmegadci_pull_up(sc); 1897 } else { 1898 atmegadci_pull_down(sc); 1899 atmegadci_clocks_off(sc); 1900 } 1901 1902 /* Select FULL-speed and Device Side Mode */ 1903 1904 value = UPS_PORT_MODE_DEVICE; 1905 1906 if (sc->sc_flags.port_powered) { 1907 value |= UPS_PORT_POWER; 1908 } 1909 if (sc->sc_flags.port_enabled) { 1910 value |= UPS_PORT_ENABLED; 1911 } 1912 if (sc->sc_flags.status_vbus && 1913 sc->sc_flags.status_bus_reset) { 1914 value |= UPS_CURRENT_CONNECT_STATUS; 1915 } 1916 if (sc->sc_flags.status_suspend) { 1917 value |= UPS_SUSPEND; 1918 } 1919 USETW(sc->sc_hub_temp.ps.wPortStatus, value); 1920 1921 value = 0; 1922 1923 if (sc->sc_flags.change_connect) { 1924 value |= UPS_C_CONNECT_STATUS; 1925 } 1926 if (sc->sc_flags.change_suspend) { 1927 value |= UPS_C_SUSPEND; 1928 } 1929 USETW(sc->sc_hub_temp.ps.wPortChange, value); 1930 len = sizeof(sc->sc_hub_temp.ps); 1931 goto tr_valid; 1932 1933 tr_handle_get_class_descriptor: 1934 if (value & 0xFF) { 1935 goto tr_stalled; 1936 } 1937 ptr = (const void *)&atmegadci_hubd; 1938 len = sizeof(atmegadci_hubd); 1939 goto tr_valid; 1940 1941 tr_stalled: 1942 err = USB_ERR_STALLED; 1943 tr_valid: 1944 done: 1945 *plength = len; 1946 *pptr = ptr; 1947 return (err); 1948 } 1949 1950 static void 1951 atmegadci_xfer_setup(struct usb_setup_params *parm) 1952 { 1953 const struct usb_hw_ep_profile *pf; 1954 struct usb_xfer *xfer; 1955 void *last_obj; 1956 uint32_t ntd; 1957 uint32_t n; 1958 uint8_t ep_no; 1959 1960 xfer = parm->curr_xfer; 1961 1962 /* 1963 * NOTE: This driver does not use any of the parameters that 1964 * are computed from the following values. Just set some 1965 * reasonable dummies: 1966 */ 1967 parm->hc_max_packet_size = 0x500; 1968 parm->hc_max_packet_count = 1; 1969 parm->hc_max_frame_size = 0x500; 1970 1971 usbd_transfer_setup_sub(parm); 1972 1973 /* 1974 * compute maximum number of TDs 1975 */ 1976 if ((xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) { 1977 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC 1 */ 1978 + 1 /* SYNC 2 */ ; 1979 } else { 1980 ntd = xfer->nframes + 1 /* SYNC */ ; 1981 } 1982 1983 /* 1984 * check if "usbd_transfer_setup_sub" set an error 1985 */ 1986 if (parm->err) 1987 return; 1988 1989 /* 1990 * allocate transfer descriptors 1991 */ 1992 last_obj = NULL; 1993 1994 /* 1995 * get profile stuff 1996 */ 1997 ep_no = xfer->endpointno & UE_ADDR; 1998 atmegadci_get_hw_ep_profile(parm->udev, &pf, ep_no); 1999 2000 if (pf == NULL) { 2001 /* should not happen */ 2002 parm->err = USB_ERR_INVAL; 2003 return; 2004 } 2005 2006 /* align data */ 2007 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1)); 2008 2009 for (n = 0; n != ntd; n++) { 2010 struct atmegadci_td *td; 2011 2012 if (parm->buf) { 2013 td = USB_ADD_BYTES(parm->buf, parm->size[0]); 2014 2015 /* init TD */ 2016 td->max_packet_size = xfer->max_packet_size; 2017 td->ep_no = ep_no; 2018 if (pf->support_multi_buffer) { 2019 td->support_multi_buffer = 1; 2020 } 2021 td->obj_next = last_obj; 2022 2023 last_obj = td; 2024 } 2025 parm->size[0] += sizeof(*td); 2026 } 2027 2028 xfer->td_start[0] = last_obj; 2029 } 2030 2031 static void 2032 atmegadci_xfer_unsetup(struct usb_xfer *xfer) 2033 { 2034 return; 2035 } 2036 2037 static void 2038 atmegadci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 2039 struct usb_endpoint *ep) 2040 { 2041 struct atmegadci_softc *sc = ATMEGA_BUS2SC(udev->bus); 2042 2043 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d,%d)\n", 2044 ep, udev->address, 2045 edesc->bEndpointAddress, udev->flags.usb_mode, 2046 sc->sc_rt_addr, udev->device_index); 2047 2048 if (udev->device_index != sc->sc_rt_addr) { 2049 if (udev->speed != USB_SPEED_FULL) { 2050 /* not supported */ 2051 return; 2052 } 2053 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_ISOCHRONOUS) 2054 ep->methods = &atmegadci_device_isoc_fs_methods; 2055 else 2056 ep->methods = &atmegadci_device_non_isoc_methods; 2057 } 2058 } 2059 2060 static void 2061 atmegadci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 2062 { 2063 struct atmegadci_softc *sc = ATMEGA_BUS2SC(bus); 2064 2065 switch (state) { 2066 case USB_HW_POWER_SUSPEND: 2067 atmegadci_suspend(sc); 2068 break; 2069 case USB_HW_POWER_SHUTDOWN: 2070 atmegadci_uninit(sc); 2071 break; 2072 case USB_HW_POWER_RESUME: 2073 atmegadci_resume(sc); 2074 break; 2075 default: 2076 break; 2077 } 2078 } 2079 2080 static const struct usb_bus_methods atmegadci_bus_methods = 2081 { 2082 .endpoint_init = &atmegadci_ep_init, 2083 .xfer_setup = &atmegadci_xfer_setup, 2084 .xfer_unsetup = &atmegadci_xfer_unsetup, 2085 .get_hw_ep_profile = &atmegadci_get_hw_ep_profile, 2086 .xfer_stall = &atmegadci_xfer_stall, 2087 .set_stall = &atmegadci_set_stall, 2088 .clear_stall = &atmegadci_clear_stall, 2089 .roothub_exec = &atmegadci_roothub_exec, 2090 .xfer_poll = &atmegadci_do_poll, 2091 .set_hw_power_sleep = &atmegadci_set_hw_power_sleep, 2092 }; 2093