1 /* $FreeBSD$ */ 2 /*- 3 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 4 * 5 * Copyright (c) 2009 Hans Petter Selasky. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * This file contains the driver for the AVR32 series USB Device 31 * Controller 32 */ 33 34 /* 35 * NOTE: When the chip detects BUS-reset it will also reset the 36 * endpoints, Function-address and more. 37 */ 38 #ifdef USB_GLOBAL_INCLUDE_FILE 39 #include USB_GLOBAL_INCLUDE_FILE 40 #else 41 #include <sys/stdint.h> 42 #include <sys/stddef.h> 43 #include <sys/param.h> 44 #include <sys/queue.h> 45 #include <sys/types.h> 46 #include <sys/systm.h> 47 #include <sys/kernel.h> 48 #include <sys/bus.h> 49 #include <sys/module.h> 50 #include <sys/lock.h> 51 #include <sys/mutex.h> 52 #include <sys/condvar.h> 53 #include <sys/sysctl.h> 54 #include <sys/sx.h> 55 #include <sys/unistd.h> 56 #include <sys/callout.h> 57 #include <sys/malloc.h> 58 #include <sys/priv.h> 59 60 #include <dev/usb/usb.h> 61 #include <dev/usb/usbdi.h> 62 63 #define USB_DEBUG_VAR avr32dci_debug 64 65 #include <dev/usb/usb_core.h> 66 #include <dev/usb/usb_debug.h> 67 #include <dev/usb/usb_busdma.h> 68 #include <dev/usb/usb_process.h> 69 #include <dev/usb/usb_transfer.h> 70 #include <dev/usb/usb_device.h> 71 #include <dev/usb/usb_hub.h> 72 #include <dev/usb/usb_util.h> 73 74 #include <dev/usb/usb_controller.h> 75 #include <dev/usb/usb_bus.h> 76 #endif /* USB_GLOBAL_INCLUDE_FILE */ 77 78 #include <dev/usb/controller/avr32dci.h> 79 80 #define AVR32_BUS2SC(bus) \ 81 ((struct avr32dci_softc *)(((uint8_t *)(bus)) - \ 82 ((uint8_t *)&(((struct avr32dci_softc *)0)->sc_bus)))) 83 84 #define AVR32_PC2SC(pc) \ 85 AVR32_BUS2SC(USB_DMATAG_TO_XROOT((pc)->tag_parent)->bus) 86 87 #ifdef USB_DEBUG 88 static int avr32dci_debug = 0; 89 90 static SYSCTL_NODE(_hw_usb, OID_AUTO, avr32dci, 91 CTLFLAG_RW | CTLFLAG_MPSAFE, 0, 92 "USB AVR32 DCI"); 93 SYSCTL_INT(_hw_usb_avr32dci, OID_AUTO, debug, CTLFLAG_RWTUN, 94 &avr32dci_debug, 0, "AVR32 DCI debug level"); 95 #endif 96 97 #define AVR32_INTR_ENDPT 1 98 99 /* prototypes */ 100 101 static const struct usb_bus_methods avr32dci_bus_methods; 102 static const struct usb_pipe_methods avr32dci_device_non_isoc_methods; 103 static const struct usb_pipe_methods avr32dci_device_isoc_fs_methods; 104 105 static avr32dci_cmd_t avr32dci_setup_rx; 106 static avr32dci_cmd_t avr32dci_data_rx; 107 static avr32dci_cmd_t avr32dci_data_tx; 108 static avr32dci_cmd_t avr32dci_data_tx_sync; 109 static void avr32dci_device_done(struct usb_xfer *, usb_error_t); 110 static void avr32dci_do_poll(struct usb_bus *); 111 static void avr32dci_standard_done(struct usb_xfer *); 112 static void avr32dci_root_intr(struct avr32dci_softc *sc); 113 114 /* 115 * Here is a list of what the chip supports: 116 */ 117 static const struct usb_hw_ep_profile 118 avr32dci_ep_profile[4] = { 119 120 [0] = { 121 .max_in_frame_size = 64, 122 .max_out_frame_size = 64, 123 .is_simplex = 1, 124 .support_control = 1, 125 }, 126 127 [1] = { 128 .max_in_frame_size = 512, 129 .max_out_frame_size = 512, 130 .is_simplex = 1, 131 .support_bulk = 1, 132 .support_interrupt = 1, 133 .support_isochronous = 1, 134 .support_in = 1, 135 .support_out = 1, 136 }, 137 138 [2] = { 139 .max_in_frame_size = 64, 140 .max_out_frame_size = 64, 141 .is_simplex = 1, 142 .support_bulk = 1, 143 .support_interrupt = 1, 144 .support_in = 1, 145 .support_out = 1, 146 }, 147 148 [3] = { 149 .max_in_frame_size = 1024, 150 .max_out_frame_size = 1024, 151 .is_simplex = 1, 152 .support_bulk = 1, 153 .support_interrupt = 1, 154 .support_isochronous = 1, 155 .support_in = 1, 156 .support_out = 1, 157 }, 158 }; 159 160 static void 161 avr32dci_get_hw_ep_profile(struct usb_device *udev, 162 const struct usb_hw_ep_profile **ppf, uint8_t ep_addr) 163 { 164 if (ep_addr == 0) 165 *ppf = avr32dci_ep_profile; 166 else if (ep_addr < 3) 167 *ppf = avr32dci_ep_profile + 1; 168 else if (ep_addr < 5) 169 *ppf = avr32dci_ep_profile + 2; 170 else if (ep_addr < 7) 171 *ppf = avr32dci_ep_profile + 3; 172 else 173 *ppf = NULL; 174 } 175 176 static void 177 avr32dci_mod_ctrl(struct avr32dci_softc *sc, uint32_t set, uint32_t clear) 178 { 179 uint32_t temp; 180 181 temp = AVR32_READ_4(sc, AVR32_CTRL); 182 temp |= set; 183 temp &= ~clear; 184 AVR32_WRITE_4(sc, AVR32_CTRL, temp); 185 } 186 187 static void 188 avr32dci_mod_ien(struct avr32dci_softc *sc, uint32_t set, uint32_t clear) 189 { 190 uint32_t temp; 191 192 temp = AVR32_READ_4(sc, AVR32_IEN); 193 temp |= set; 194 temp &= ~clear; 195 AVR32_WRITE_4(sc, AVR32_IEN, temp); 196 } 197 198 static void 199 avr32dci_clocks_on(struct avr32dci_softc *sc) 200 { 201 if (sc->sc_flags.clocks_off && 202 sc->sc_flags.port_powered) { 203 204 DPRINTFN(5, "\n"); 205 206 /* turn on clocks */ 207 (sc->sc_clocks_on) (&sc->sc_bus); 208 209 avr32dci_mod_ctrl(sc, AVR32_CTRL_DEV_EN_USBA, 0); 210 211 sc->sc_flags.clocks_off = 0; 212 } 213 } 214 215 static void 216 avr32dci_clocks_off(struct avr32dci_softc *sc) 217 { 218 if (!sc->sc_flags.clocks_off) { 219 220 DPRINTFN(5, "\n"); 221 222 avr32dci_mod_ctrl(sc, 0, AVR32_CTRL_DEV_EN_USBA); 223 224 /* turn clocks off */ 225 (sc->sc_clocks_off) (&sc->sc_bus); 226 227 sc->sc_flags.clocks_off = 1; 228 } 229 } 230 231 static void 232 avr32dci_pull_up(struct avr32dci_softc *sc) 233 { 234 /* pullup D+, if possible */ 235 236 if (!sc->sc_flags.d_pulled_up && 237 sc->sc_flags.port_powered) { 238 sc->sc_flags.d_pulled_up = 1; 239 avr32dci_mod_ctrl(sc, 0, AVR32_CTRL_DEV_DETACH); 240 } 241 } 242 243 static void 244 avr32dci_pull_down(struct avr32dci_softc *sc) 245 { 246 /* pulldown D+, if possible */ 247 248 if (sc->sc_flags.d_pulled_up) { 249 sc->sc_flags.d_pulled_up = 0; 250 avr32dci_mod_ctrl(sc, AVR32_CTRL_DEV_DETACH, 0); 251 } 252 } 253 254 static void 255 avr32dci_wakeup_peer(struct avr32dci_softc *sc) 256 { 257 if (!sc->sc_flags.status_suspend) { 258 return; 259 } 260 avr32dci_mod_ctrl(sc, AVR32_CTRL_DEV_REWAKEUP, 0); 261 262 /* wait 8 milliseconds */ 263 /* Wait for reset to complete. */ 264 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125); 265 266 /* hardware should have cleared RMWKUP bit */ 267 } 268 269 static void 270 avr32dci_set_address(struct avr32dci_softc *sc, uint8_t addr) 271 { 272 DPRINTFN(5, "addr=%d\n", addr); 273 274 avr32dci_mod_ctrl(sc, AVR32_CTRL_DEV_FADDR_EN | addr, 0); 275 } 276 277 static uint8_t 278 avr32dci_setup_rx(struct avr32dci_td *td) 279 { 280 struct avr32dci_softc *sc; 281 struct usb_device_request req; 282 uint16_t count; 283 uint32_t temp; 284 285 /* get pointer to softc */ 286 sc = AVR32_PC2SC(td->pc); 287 288 /* check endpoint status */ 289 temp = AVR32_READ_4(sc, AVR32_EPTSTA(td->ep_no)); 290 291 DPRINTFN(5, "EPTSTA(%u)=0x%08x\n", td->ep_no, temp); 292 293 if (!(temp & AVR32_EPTSTA_RX_SETUP)) { 294 goto not_complete; 295 } 296 /* clear did stall */ 297 td->did_stall = 0; 298 /* get the packet byte count */ 299 count = AVR32_EPTSTA_BYTE_COUNT(temp); 300 301 /* verify data length */ 302 if (count != td->remainder) { 303 DPRINTFN(0, "Invalid SETUP packet " 304 "length, %d bytes\n", count); 305 goto not_complete; 306 } 307 if (count != sizeof(req)) { 308 DPRINTFN(0, "Unsupported SETUP packet " 309 "length, %d bytes\n", count); 310 goto not_complete; 311 } 312 /* receive data */ 313 memcpy(&req, sc->physdata, sizeof(req)); 314 315 /* copy data into real buffer */ 316 usbd_copy_in(td->pc, 0, &req, sizeof(req)); 317 318 td->offset = sizeof(req); 319 td->remainder = 0; 320 321 /* sneak peek the set address */ 322 if ((req.bmRequestType == UT_WRITE_DEVICE) && 323 (req.bRequest == UR_SET_ADDRESS)) { 324 sc->sc_dv_addr = req.wValue[0] & 0x7F; 325 /* must write address before ZLP */ 326 avr32dci_mod_ctrl(sc, 0, AVR32_CTRL_DEV_FADDR_EN | 327 AVR32_CTRL_DEV_ADDR); 328 avr32dci_mod_ctrl(sc, sc->sc_dv_addr, 0); 329 } else { 330 sc->sc_dv_addr = 0xFF; 331 } 332 333 /* clear SETUP packet interrupt */ 334 AVR32_WRITE_4(sc, AVR32_EPTCLRSTA(td->ep_no), AVR32_EPTSTA_RX_SETUP); 335 return (0); /* complete */ 336 337 not_complete: 338 if (temp & AVR32_EPTSTA_RX_SETUP) { 339 /* clear SETUP packet interrupt */ 340 AVR32_WRITE_4(sc, AVR32_EPTCLRSTA(td->ep_no), AVR32_EPTSTA_RX_SETUP); 341 } 342 /* abort any ongoing transfer */ 343 if (!td->did_stall) { 344 DPRINTFN(5, "stalling\n"); 345 AVR32_WRITE_4(sc, AVR32_EPTSETSTA(td->ep_no), 346 AVR32_EPTSTA_FRCESTALL); 347 td->did_stall = 1; 348 } 349 return (1); /* not complete */ 350 } 351 352 static uint8_t 353 avr32dci_data_rx(struct avr32dci_td *td) 354 { 355 struct avr32dci_softc *sc; 356 struct usb_page_search buf_res; 357 uint16_t count; 358 uint32_t temp; 359 uint8_t to; 360 uint8_t got_short; 361 362 to = 4; /* don't loop forever! */ 363 got_short = 0; 364 365 /* get pointer to softc */ 366 sc = AVR32_PC2SC(td->pc); 367 368 repeat: 369 /* check if any of the FIFO banks have data */ 370 /* check endpoint status */ 371 temp = AVR32_READ_4(sc, AVR32_EPTSTA(td->ep_no)); 372 373 DPRINTFN(5, "EPTSTA(%u)=0x%08x\n", td->ep_no, temp); 374 375 if (temp & AVR32_EPTSTA_RX_SETUP) { 376 if (td->remainder == 0) { 377 /* 378 * We are actually complete and have 379 * received the next SETUP 380 */ 381 DPRINTFN(5, "faking complete\n"); 382 return (0); /* complete */ 383 } 384 /* 385 * USB Host Aborted the transfer. 386 */ 387 td->error = 1; 388 return (0); /* complete */ 389 } 390 /* check status */ 391 if (!(temp & AVR32_EPTSTA_RX_BK_RDY)) { 392 /* no data */ 393 goto not_complete; 394 } 395 /* get the packet byte count */ 396 count = AVR32_EPTSTA_BYTE_COUNT(temp); 397 398 /* verify the packet byte count */ 399 if (count != td->max_packet_size) { 400 if (count < td->max_packet_size) { 401 /* we have a short packet */ 402 td->short_pkt = 1; 403 got_short = 1; 404 } else { 405 /* invalid USB packet */ 406 td->error = 1; 407 return (0); /* we are complete */ 408 } 409 } 410 /* verify the packet byte count */ 411 if (count > td->remainder) { 412 /* invalid USB packet */ 413 td->error = 1; 414 return (0); /* we are complete */ 415 } 416 while (count > 0) { 417 usbd_get_page(td->pc, td->offset, &buf_res); 418 419 /* get correct length */ 420 if (buf_res.length > count) { 421 buf_res.length = count; 422 } 423 /* receive data */ 424 memcpy(buf_res.buffer, sc->physdata + 425 (AVR32_EPTSTA_CURRENT_BANK(temp) << td->bank_shift) + 426 (td->ep_no << 16) + (td->offset % td->max_packet_size), buf_res.length); 427 /* update counters */ 428 count -= buf_res.length; 429 td->offset += buf_res.length; 430 td->remainder -= buf_res.length; 431 } 432 433 /* clear OUT packet interrupt */ 434 AVR32_WRITE_4(sc, AVR32_EPTCLRSTA(td->ep_no), AVR32_EPTSTA_RX_BK_RDY); 435 436 /* check if we are complete */ 437 if ((td->remainder == 0) || got_short) { 438 if (td->short_pkt) { 439 /* we are complete */ 440 return (0); 441 } 442 /* else need to receive a zero length packet */ 443 } 444 if (--to) { 445 goto repeat; 446 } 447 not_complete: 448 return (1); /* not complete */ 449 } 450 451 static uint8_t 452 avr32dci_data_tx(struct avr32dci_td *td) 453 { 454 struct avr32dci_softc *sc; 455 struct usb_page_search buf_res; 456 uint16_t count; 457 uint8_t to; 458 uint32_t temp; 459 460 to = 4; /* don't loop forever! */ 461 462 /* get pointer to softc */ 463 sc = AVR32_PC2SC(td->pc); 464 465 repeat: 466 467 /* check endpoint status */ 468 temp = AVR32_READ_4(sc, AVR32_EPTSTA(td->ep_no)); 469 470 DPRINTFN(5, "EPTSTA(%u)=0x%08x\n", td->ep_no, temp); 471 472 if (temp & AVR32_EPTSTA_RX_SETUP) { 473 /* 474 * The current transfer was aborted 475 * by the USB Host 476 */ 477 td->error = 1; 478 return (0); /* complete */ 479 } 480 if (temp & AVR32_EPTSTA_TX_PK_RDY) { 481 /* cannot write any data - all banks are busy */ 482 goto not_complete; 483 } 484 count = td->max_packet_size; 485 if (td->remainder < count) { 486 /* we have a short packet */ 487 td->short_pkt = 1; 488 count = td->remainder; 489 } 490 while (count > 0) { 491 492 usbd_get_page(td->pc, td->offset, &buf_res); 493 494 /* get correct length */ 495 if (buf_res.length > count) { 496 buf_res.length = count; 497 } 498 /* transmit data */ 499 memcpy(sc->physdata + 500 (AVR32_EPTSTA_CURRENT_BANK(temp) << td->bank_shift) + 501 (td->ep_no << 16) + (td->offset % td->max_packet_size), 502 buf_res.buffer, buf_res.length); 503 /* update counters */ 504 count -= buf_res.length; 505 td->offset += buf_res.length; 506 td->remainder -= buf_res.length; 507 } 508 509 /* allocate FIFO bank */ 510 AVR32_WRITE_4(sc, AVR32_EPTCTL(td->ep_no), AVR32_EPTCTL_TX_PK_RDY); 511 512 /* check remainder */ 513 if (td->remainder == 0) { 514 if (td->short_pkt) { 515 return (0); /* complete */ 516 } 517 /* else we need to transmit a short packet */ 518 } 519 if (--to) { 520 goto repeat; 521 } 522 not_complete: 523 return (1); /* not complete */ 524 } 525 526 static uint8_t 527 avr32dci_data_tx_sync(struct avr32dci_td *td) 528 { 529 struct avr32dci_softc *sc; 530 uint32_t temp; 531 532 /* get pointer to softc */ 533 sc = AVR32_PC2SC(td->pc); 534 535 /* check endpoint status */ 536 temp = AVR32_READ_4(sc, AVR32_EPTSTA(td->ep_no)); 537 538 DPRINTFN(5, "EPTSTA(%u)=0x%08x\n", td->ep_no, temp); 539 540 if (temp & AVR32_EPTSTA_RX_SETUP) { 541 DPRINTFN(5, "faking complete\n"); 542 /* Race condition */ 543 return (0); /* complete */ 544 } 545 /* 546 * The control endpoint has only got one bank, so if that bank 547 * is free the packet has been transferred! 548 */ 549 if (AVR32_EPTSTA_BUSY_BANK_STA(temp) != 0) { 550 /* cannot write any data - a bank is busy */ 551 goto not_complete; 552 } 553 if (sc->sc_dv_addr != 0xFF) { 554 /* set new address */ 555 avr32dci_set_address(sc, sc->sc_dv_addr); 556 } 557 return (0); /* complete */ 558 559 not_complete: 560 return (1); /* not complete */ 561 } 562 563 static uint8_t 564 avr32dci_xfer_do_fifo(struct usb_xfer *xfer) 565 { 566 struct avr32dci_td *td; 567 568 DPRINTFN(9, "\n"); 569 570 td = xfer->td_transfer_cache; 571 while (1) { 572 if ((td->func) (td)) { 573 /* operation in progress */ 574 break; 575 } 576 if (((void *)td) == xfer->td_transfer_last) { 577 goto done; 578 } 579 if (td->error) { 580 goto done; 581 } else if (td->remainder > 0) { 582 /* 583 * We had a short transfer. If there is no alternate 584 * next, stop processing ! 585 */ 586 if (!td->alt_next) { 587 goto done; 588 } 589 } 590 /* 591 * Fetch the next transfer descriptor and transfer 592 * some flags to the next transfer descriptor 593 */ 594 td = td->obj_next; 595 xfer->td_transfer_cache = td; 596 } 597 return (1); /* not complete */ 598 599 done: 600 /* compute all actual lengths */ 601 602 avr32dci_standard_done(xfer); 603 return (0); /* complete */ 604 } 605 606 static void 607 avr32dci_interrupt_poll(struct avr32dci_softc *sc) 608 { 609 struct usb_xfer *xfer; 610 611 repeat: 612 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 613 if (!avr32dci_xfer_do_fifo(xfer)) { 614 /* queue has been modified */ 615 goto repeat; 616 } 617 } 618 } 619 620 void 621 avr32dci_vbus_interrupt(struct avr32dci_softc *sc, uint8_t is_on) 622 { 623 DPRINTFN(5, "vbus = %u\n", is_on); 624 625 if (is_on) { 626 if (!sc->sc_flags.status_vbus) { 627 sc->sc_flags.status_vbus = 1; 628 629 /* complete root HUB interrupt endpoint */ 630 631 avr32dci_root_intr(sc); 632 } 633 } else { 634 if (sc->sc_flags.status_vbus) { 635 sc->sc_flags.status_vbus = 0; 636 sc->sc_flags.status_bus_reset = 0; 637 sc->sc_flags.status_suspend = 0; 638 sc->sc_flags.change_suspend = 0; 639 sc->sc_flags.change_connect = 1; 640 641 /* complete root HUB interrupt endpoint */ 642 643 avr32dci_root_intr(sc); 644 } 645 } 646 } 647 648 void 649 avr32dci_interrupt(struct avr32dci_softc *sc) 650 { 651 uint32_t status; 652 653 USB_BUS_LOCK(&sc->sc_bus); 654 655 /* read interrupt status */ 656 status = AVR32_READ_4(sc, AVR32_INTSTA); 657 658 /* clear all set interrupts */ 659 AVR32_WRITE_4(sc, AVR32_CLRINT, status); 660 661 DPRINTFN(14, "INTSTA=0x%08x\n", status); 662 663 /* check for any bus state change interrupts */ 664 if (status & AVR32_INT_ENDRESET) { 665 666 DPRINTFN(5, "end of reset\n"); 667 668 /* set correct state */ 669 sc->sc_flags.status_bus_reset = 1; 670 sc->sc_flags.status_suspend = 0; 671 sc->sc_flags.change_suspend = 0; 672 sc->sc_flags.change_connect = 1; 673 674 /* disable resume interrupt */ 675 avr32dci_mod_ien(sc, AVR32_INT_DET_SUSPD | 676 AVR32_INT_ENDRESET, AVR32_INT_WAKE_UP); 677 678 /* complete root HUB interrupt endpoint */ 679 avr32dci_root_intr(sc); 680 } 681 /* 682 * If resume and suspend is set at the same time we interpret 683 * that like RESUME. Resume is set when there is at least 3 684 * milliseconds of inactivity on the USB BUS. 685 */ 686 if (status & AVR32_INT_WAKE_UP) { 687 688 DPRINTFN(5, "resume interrupt\n"); 689 690 if (sc->sc_flags.status_suspend) { 691 /* update status bits */ 692 sc->sc_flags.status_suspend = 0; 693 sc->sc_flags.change_suspend = 1; 694 695 /* disable resume interrupt */ 696 avr32dci_mod_ien(sc, AVR32_INT_DET_SUSPD | 697 AVR32_INT_ENDRESET, AVR32_INT_WAKE_UP); 698 699 /* complete root HUB interrupt endpoint */ 700 avr32dci_root_intr(sc); 701 } 702 } else if (status & AVR32_INT_DET_SUSPD) { 703 704 DPRINTFN(5, "suspend interrupt\n"); 705 706 if (!sc->sc_flags.status_suspend) { 707 /* update status bits */ 708 sc->sc_flags.status_suspend = 1; 709 sc->sc_flags.change_suspend = 1; 710 711 /* disable suspend interrupt */ 712 avr32dci_mod_ien(sc, AVR32_INT_WAKE_UP | 713 AVR32_INT_ENDRESET, AVR32_INT_DET_SUSPD); 714 715 /* complete root HUB interrupt endpoint */ 716 avr32dci_root_intr(sc); 717 } 718 } 719 /* check for any endpoint interrupts */ 720 if (status & -AVR32_INT_EPT_INT(0)) { 721 722 DPRINTFN(5, "real endpoint interrupt\n"); 723 724 avr32dci_interrupt_poll(sc); 725 } 726 USB_BUS_UNLOCK(&sc->sc_bus); 727 } 728 729 static void 730 avr32dci_setup_standard_chain_sub(struct avr32dci_std_temp *temp) 731 { 732 struct avr32dci_td *td; 733 734 /* get current Transfer Descriptor */ 735 td = temp->td_next; 736 temp->td = td; 737 738 /* prepare for next TD */ 739 temp->td_next = td->obj_next; 740 741 /* fill out the Transfer Descriptor */ 742 td->func = temp->func; 743 td->pc = temp->pc; 744 td->offset = temp->offset; 745 td->remainder = temp->len; 746 td->error = 0; 747 td->did_stall = temp->did_stall; 748 td->short_pkt = temp->short_pkt; 749 td->alt_next = temp->setup_alt_next; 750 } 751 752 static void 753 avr32dci_setup_standard_chain(struct usb_xfer *xfer) 754 { 755 struct avr32dci_std_temp temp; 756 struct avr32dci_softc *sc; 757 struct avr32dci_td *td; 758 uint32_t x; 759 uint8_t ep_no; 760 uint8_t need_sync; 761 762 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 763 xfer->address, UE_GET_ADDR(xfer->endpointno), 764 xfer->sumlen, usbd_get_speed(xfer->xroot->udev)); 765 766 temp.max_frame_size = xfer->max_frame_size; 767 768 td = xfer->td_start[0]; 769 xfer->td_transfer_first = td; 770 xfer->td_transfer_cache = td; 771 772 /* setup temp */ 773 774 temp.pc = NULL; 775 temp.td = NULL; 776 temp.td_next = xfer->td_start[0]; 777 temp.offset = 0; 778 temp.setup_alt_next = xfer->flags_int.short_frames_ok || 779 xfer->flags_int.isochronous_xfr; 780 temp.did_stall = !xfer->flags_int.control_stall; 781 782 sc = AVR32_BUS2SC(xfer->xroot->bus); 783 ep_no = (xfer->endpointno & UE_ADDR); 784 785 /* check if we should prepend a setup message */ 786 787 if (xfer->flags_int.control_xfr) { 788 if (xfer->flags_int.control_hdr) { 789 790 temp.func = &avr32dci_setup_rx; 791 temp.len = xfer->frlengths[0]; 792 temp.pc = xfer->frbuffers + 0; 793 temp.short_pkt = temp.len ? 1 : 0; 794 /* check for last frame */ 795 if (xfer->nframes == 1) { 796 /* no STATUS stage yet, SETUP is last */ 797 if (xfer->flags_int.control_act) 798 temp.setup_alt_next = 0; 799 } 800 avr32dci_setup_standard_chain_sub(&temp); 801 } 802 x = 1; 803 } else { 804 x = 0; 805 } 806 807 if (x != xfer->nframes) { 808 if (xfer->endpointno & UE_DIR_IN) { 809 temp.func = &avr32dci_data_tx; 810 need_sync = 1; 811 } else { 812 temp.func = &avr32dci_data_rx; 813 need_sync = 0; 814 } 815 816 /* setup "pc" pointer */ 817 temp.pc = xfer->frbuffers + x; 818 } else { 819 need_sync = 0; 820 } 821 while (x != xfer->nframes) { 822 823 /* DATA0 / DATA1 message */ 824 825 temp.len = xfer->frlengths[x]; 826 827 x++; 828 829 if (x == xfer->nframes) { 830 if (xfer->flags_int.control_xfr) { 831 if (xfer->flags_int.control_act) { 832 temp.setup_alt_next = 0; 833 } 834 } else { 835 temp.setup_alt_next = 0; 836 } 837 } 838 if (temp.len == 0) { 839 840 /* make sure that we send an USB packet */ 841 842 temp.short_pkt = 0; 843 844 } else { 845 846 /* regular data transfer */ 847 848 temp.short_pkt = (xfer->flags.force_short_xfer) ? 0 : 1; 849 } 850 851 avr32dci_setup_standard_chain_sub(&temp); 852 853 if (xfer->flags_int.isochronous_xfr) { 854 temp.offset += temp.len; 855 } else { 856 /* get next Page Cache pointer */ 857 temp.pc = xfer->frbuffers + x; 858 } 859 } 860 861 if (xfer->flags_int.control_xfr) { 862 863 /* always setup a valid "pc" pointer for status and sync */ 864 temp.pc = xfer->frbuffers + 0; 865 temp.len = 0; 866 temp.short_pkt = 0; 867 temp.setup_alt_next = 0; 868 869 /* check if we need to sync */ 870 if (need_sync) { 871 /* we need a SYNC point after TX */ 872 temp.func = &avr32dci_data_tx_sync; 873 avr32dci_setup_standard_chain_sub(&temp); 874 } 875 /* check if we should append a status stage */ 876 if (!xfer->flags_int.control_act) { 877 878 /* 879 * Send a DATA1 message and invert the current 880 * endpoint direction. 881 */ 882 if (xfer->endpointno & UE_DIR_IN) { 883 temp.func = &avr32dci_data_rx; 884 need_sync = 0; 885 } else { 886 temp.func = &avr32dci_data_tx; 887 need_sync = 1; 888 } 889 890 avr32dci_setup_standard_chain_sub(&temp); 891 if (need_sync) { 892 /* we need a SYNC point after TX */ 893 temp.func = &avr32dci_data_tx_sync; 894 avr32dci_setup_standard_chain_sub(&temp); 895 } 896 } 897 } 898 /* must have at least one frame! */ 899 td = temp.td; 900 xfer->td_transfer_last = td; 901 } 902 903 static void 904 avr32dci_timeout(void *arg) 905 { 906 struct usb_xfer *xfer = arg; 907 908 DPRINTF("xfer=%p\n", xfer); 909 910 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 911 912 /* transfer is transferred */ 913 avr32dci_device_done(xfer, USB_ERR_TIMEOUT); 914 } 915 916 static void 917 avr32dci_start_standard_chain(struct usb_xfer *xfer) 918 { 919 DPRINTFN(9, "\n"); 920 921 /* poll one time - will turn on interrupts */ 922 if (avr32dci_xfer_do_fifo(xfer)) { 923 uint8_t ep_no = xfer->endpointno & UE_ADDR; 924 struct avr32dci_softc *sc = AVR32_BUS2SC(xfer->xroot->bus); 925 926 avr32dci_mod_ien(sc, AVR32_INT_EPT_INT(ep_no), 0); 927 928 /* put transfer on interrupt queue */ 929 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 930 931 /* start timeout, if any */ 932 if (xfer->timeout != 0) { 933 usbd_transfer_timeout_ms(xfer, 934 &avr32dci_timeout, xfer->timeout); 935 } 936 } 937 } 938 939 static void 940 avr32dci_root_intr(struct avr32dci_softc *sc) 941 { 942 DPRINTFN(9, "\n"); 943 944 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 945 946 /* set port bit */ 947 sc->sc_hub_idata[0] = 0x02; /* we only have one port */ 948 949 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 950 sizeof(sc->sc_hub_idata)); 951 } 952 953 static usb_error_t 954 avr32dci_standard_done_sub(struct usb_xfer *xfer) 955 { 956 struct avr32dci_td *td; 957 uint32_t len; 958 uint8_t error; 959 960 DPRINTFN(9, "\n"); 961 962 td = xfer->td_transfer_cache; 963 964 do { 965 len = td->remainder; 966 967 if (xfer->aframes != xfer->nframes) { 968 /* 969 * Verify the length and subtract 970 * the remainder from "frlengths[]": 971 */ 972 if (len > xfer->frlengths[xfer->aframes]) { 973 td->error = 1; 974 } else { 975 xfer->frlengths[xfer->aframes] -= len; 976 } 977 } 978 /* Check for transfer error */ 979 if (td->error) { 980 /* the transfer is finished */ 981 error = 1; 982 td = NULL; 983 break; 984 } 985 /* Check for short transfer */ 986 if (len > 0) { 987 if (xfer->flags_int.short_frames_ok || 988 xfer->flags_int.isochronous_xfr) { 989 /* follow alt next */ 990 if (td->alt_next) { 991 td = td->obj_next; 992 } else { 993 td = NULL; 994 } 995 } else { 996 /* the transfer is finished */ 997 td = NULL; 998 } 999 error = 0; 1000 break; 1001 } 1002 td = td->obj_next; 1003 1004 /* this USB frame is complete */ 1005 error = 0; 1006 break; 1007 1008 } while (0); 1009 1010 /* update transfer cache */ 1011 1012 xfer->td_transfer_cache = td; 1013 1014 return (error ? 1015 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION); 1016 } 1017 1018 static void 1019 avr32dci_standard_done(struct usb_xfer *xfer) 1020 { 1021 usb_error_t err = 0; 1022 1023 DPRINTFN(13, "xfer=%p pipe=%p transfer done\n", 1024 xfer, xfer->endpoint); 1025 1026 /* reset scanner */ 1027 1028 xfer->td_transfer_cache = xfer->td_transfer_first; 1029 1030 if (xfer->flags_int.control_xfr) { 1031 1032 if (xfer->flags_int.control_hdr) { 1033 1034 err = avr32dci_standard_done_sub(xfer); 1035 } 1036 xfer->aframes = 1; 1037 1038 if (xfer->td_transfer_cache == NULL) { 1039 goto done; 1040 } 1041 } 1042 while (xfer->aframes != xfer->nframes) { 1043 1044 err = avr32dci_standard_done_sub(xfer); 1045 xfer->aframes++; 1046 1047 if (xfer->td_transfer_cache == NULL) { 1048 goto done; 1049 } 1050 } 1051 1052 if (xfer->flags_int.control_xfr && 1053 !xfer->flags_int.control_act) { 1054 1055 err = avr32dci_standard_done_sub(xfer); 1056 } 1057 done: 1058 avr32dci_device_done(xfer, err); 1059 } 1060 1061 /*------------------------------------------------------------------------* 1062 * avr32dci_device_done 1063 * 1064 * NOTE: this function can be called more than one time on the 1065 * same USB transfer! 1066 *------------------------------------------------------------------------*/ 1067 static void 1068 avr32dci_device_done(struct usb_xfer *xfer, usb_error_t error) 1069 { 1070 struct avr32dci_softc *sc = AVR32_BUS2SC(xfer->xroot->bus); 1071 uint8_t ep_no; 1072 1073 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1074 1075 DPRINTFN(9, "xfer=%p, pipe=%p, error=%d\n", 1076 xfer, xfer->endpoint, error); 1077 1078 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) { 1079 ep_no = (xfer->endpointno & UE_ADDR); 1080 1081 /* disable endpoint interrupt */ 1082 avr32dci_mod_ien(sc, 0, AVR32_INT_EPT_INT(ep_no)); 1083 1084 DPRINTFN(15, "disabled interrupts!\n"); 1085 } 1086 /* dequeue transfer and start next transfer */ 1087 usbd_transfer_done(xfer, error); 1088 } 1089 1090 static void 1091 avr32dci_xfer_stall(struct usb_xfer *xfer) 1092 { 1093 avr32dci_device_done(xfer, USB_ERR_STALLED); 1094 } 1095 1096 static void 1097 avr32dci_set_stall(struct usb_device *udev, 1098 struct usb_endpoint *pipe, uint8_t *did_stall) 1099 { 1100 struct avr32dci_softc *sc; 1101 uint8_t ep_no; 1102 1103 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 1104 1105 DPRINTFN(5, "pipe=%p\n", pipe); 1106 1107 sc = AVR32_BUS2SC(udev->bus); 1108 /* get endpoint number */ 1109 ep_no = (pipe->edesc->bEndpointAddress & UE_ADDR); 1110 /* set stall */ 1111 AVR32_WRITE_4(sc, AVR32_EPTSETSTA(ep_no), AVR32_EPTSTA_FRCESTALL); 1112 } 1113 1114 static void 1115 avr32dci_clear_stall_sub(struct avr32dci_softc *sc, uint8_t ep_no, 1116 uint8_t ep_type, uint8_t ep_dir) 1117 { 1118 const struct usb_hw_ep_profile *pf; 1119 uint32_t temp; 1120 uint32_t epsize; 1121 uint8_t n; 1122 1123 if (ep_type == UE_CONTROL) { 1124 /* clearing stall is not needed */ 1125 return; 1126 } 1127 /* set endpoint reset */ 1128 AVR32_WRITE_4(sc, AVR32_EPTRST, AVR32_EPTRST_MASK(ep_no)); 1129 1130 /* set stall */ 1131 AVR32_WRITE_4(sc, AVR32_EPTSETSTA(ep_no), AVR32_EPTSTA_FRCESTALL); 1132 1133 /* reset data toggle */ 1134 AVR32_WRITE_4(sc, AVR32_EPTCLRSTA(ep_no), AVR32_EPTSTA_TOGGLESQ); 1135 1136 /* clear stall */ 1137 AVR32_WRITE_4(sc, AVR32_EPTCLRSTA(ep_no), AVR32_EPTSTA_FRCESTALL); 1138 1139 if (ep_type == UE_BULK) { 1140 temp = AVR32_EPTCFG_TYPE_BULK; 1141 } else if (ep_type == UE_INTERRUPT) { 1142 temp = AVR32_EPTCFG_TYPE_INTR; 1143 } else { 1144 temp = AVR32_EPTCFG_TYPE_ISOC | 1145 AVR32_EPTCFG_NB_TRANS(1); 1146 } 1147 if (ep_dir & UE_DIR_IN) { 1148 temp |= AVR32_EPTCFG_EPDIR_IN; 1149 } 1150 avr32dci_get_hw_ep_profile(NULL, &pf, ep_no); 1151 1152 /* compute endpoint size (use maximum) */ 1153 epsize = pf->max_in_frame_size | pf->max_out_frame_size; 1154 n = 0; 1155 while ((epsize /= 2)) 1156 n++; 1157 temp |= AVR32_EPTCFG_EPSIZE(n); 1158 1159 /* use the maximum number of banks supported */ 1160 if (ep_no < 1) 1161 temp |= AVR32_EPTCFG_NBANK(1); 1162 else if (ep_no < 3) 1163 temp |= AVR32_EPTCFG_NBANK(2); 1164 else 1165 temp |= AVR32_EPTCFG_NBANK(3); 1166 1167 AVR32_WRITE_4(sc, AVR32_EPTCFG(ep_no), temp); 1168 1169 temp = AVR32_READ_4(sc, AVR32_EPTCFG(ep_no)); 1170 1171 if (!(temp & AVR32_EPTCFG_EPT_MAPD)) { 1172 device_printf(sc->sc_bus.bdev, "Chip rejected configuration\n"); 1173 } else { 1174 AVR32_WRITE_4(sc, AVR32_EPTCTLENB(ep_no), 1175 AVR32_EPTCTL_EPT_ENABL); 1176 } 1177 } 1178 1179 static void 1180 avr32dci_clear_stall(struct usb_device *udev, struct usb_endpoint *pipe) 1181 { 1182 struct avr32dci_softc *sc; 1183 struct usb_endpoint_descriptor *ed; 1184 1185 DPRINTFN(5, "pipe=%p\n", pipe); 1186 1187 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 1188 1189 /* check mode */ 1190 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 1191 /* not supported */ 1192 return; 1193 } 1194 /* get softc */ 1195 sc = AVR32_BUS2SC(udev->bus); 1196 1197 /* get endpoint descriptor */ 1198 ed = pipe->edesc; 1199 1200 /* reset endpoint */ 1201 avr32dci_clear_stall_sub(sc, 1202 (ed->bEndpointAddress & UE_ADDR), 1203 (ed->bmAttributes & UE_XFERTYPE), 1204 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT))); 1205 } 1206 1207 usb_error_t 1208 avr32dci_init(struct avr32dci_softc *sc) 1209 { 1210 uint8_t n; 1211 1212 DPRINTF("start\n"); 1213 1214 /* set up the bus structure */ 1215 sc->sc_bus.usbrev = USB_REV_1_1; 1216 sc->sc_bus.methods = &avr32dci_bus_methods; 1217 1218 USB_BUS_LOCK(&sc->sc_bus); 1219 1220 /* make sure USB is enabled */ 1221 avr32dci_mod_ctrl(sc, AVR32_CTRL_DEV_EN_USBA, 0); 1222 1223 /* turn on clocks */ 1224 (sc->sc_clocks_on) (&sc->sc_bus); 1225 1226 /* make sure device is re-enumerated */ 1227 avr32dci_mod_ctrl(sc, AVR32_CTRL_DEV_DETACH, 0); 1228 1229 /* wait a little for things to stabilise */ 1230 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 20); 1231 1232 /* disable interrupts */ 1233 avr32dci_mod_ien(sc, 0, 0xFFFFFFFF); 1234 1235 /* enable interrupts */ 1236 avr32dci_mod_ien(sc, AVR32_INT_DET_SUSPD | 1237 AVR32_INT_ENDRESET, 0); 1238 1239 /* reset all endpoints */ 1240 AVR32_WRITE_4(sc, AVR32_EPTRST, (1 << AVR32_EP_MAX) - 1); 1241 1242 /* disable all endpoints */ 1243 for (n = 0; n != AVR32_EP_MAX; n++) { 1244 /* disable endpoint */ 1245 AVR32_WRITE_4(sc, AVR32_EPTCTLDIS(n), AVR32_EPTCTL_EPT_ENABL); 1246 } 1247 1248 /* turn off clocks */ 1249 1250 avr32dci_clocks_off(sc); 1251 1252 USB_BUS_UNLOCK(&sc->sc_bus); 1253 1254 /* catch any lost interrupts */ 1255 1256 avr32dci_do_poll(&sc->sc_bus); 1257 1258 return (0); /* success */ 1259 } 1260 1261 void 1262 avr32dci_uninit(struct avr32dci_softc *sc) 1263 { 1264 uint8_t n; 1265 1266 USB_BUS_LOCK(&sc->sc_bus); 1267 1268 /* turn on clocks */ 1269 (sc->sc_clocks_on) (&sc->sc_bus); 1270 1271 /* disable interrupts */ 1272 avr32dci_mod_ien(sc, 0, 0xFFFFFFFF); 1273 1274 /* reset all endpoints */ 1275 AVR32_WRITE_4(sc, AVR32_EPTRST, (1 << AVR32_EP_MAX) - 1); 1276 1277 /* disable all endpoints */ 1278 for (n = 0; n != AVR32_EP_MAX; n++) { 1279 /* disable endpoint */ 1280 AVR32_WRITE_4(sc, AVR32_EPTCTLDIS(n), AVR32_EPTCTL_EPT_ENABL); 1281 } 1282 1283 sc->sc_flags.port_powered = 0; 1284 sc->sc_flags.status_vbus = 0; 1285 sc->sc_flags.status_bus_reset = 0; 1286 sc->sc_flags.status_suspend = 0; 1287 sc->sc_flags.change_suspend = 0; 1288 sc->sc_flags.change_connect = 1; 1289 1290 avr32dci_pull_down(sc); 1291 avr32dci_clocks_off(sc); 1292 1293 USB_BUS_UNLOCK(&sc->sc_bus); 1294 } 1295 1296 static void 1297 avr32dci_suspend(struct avr32dci_softc *sc) 1298 { 1299 /* TODO */ 1300 } 1301 1302 static void 1303 avr32dci_resume(struct avr32dci_softc *sc) 1304 { 1305 /* TODO */ 1306 } 1307 1308 static void 1309 avr32dci_do_poll(struct usb_bus *bus) 1310 { 1311 struct avr32dci_softc *sc = AVR32_BUS2SC(bus); 1312 1313 USB_BUS_LOCK(&sc->sc_bus); 1314 avr32dci_interrupt_poll(sc); 1315 USB_BUS_UNLOCK(&sc->sc_bus); 1316 } 1317 1318 /*------------------------------------------------------------------------* 1319 * avr32dci bulk support 1320 * avr32dci control support 1321 * avr32dci interrupt support 1322 *------------------------------------------------------------------------*/ 1323 static void 1324 avr32dci_device_non_isoc_open(struct usb_xfer *xfer) 1325 { 1326 return; 1327 } 1328 1329 static void 1330 avr32dci_device_non_isoc_close(struct usb_xfer *xfer) 1331 { 1332 avr32dci_device_done(xfer, USB_ERR_CANCELLED); 1333 } 1334 1335 static void 1336 avr32dci_device_non_isoc_enter(struct usb_xfer *xfer) 1337 { 1338 return; 1339 } 1340 1341 static void 1342 avr32dci_device_non_isoc_start(struct usb_xfer *xfer) 1343 { 1344 /* setup TDs */ 1345 avr32dci_setup_standard_chain(xfer); 1346 avr32dci_start_standard_chain(xfer); 1347 } 1348 1349 static const struct usb_pipe_methods avr32dci_device_non_isoc_methods = 1350 { 1351 .open = avr32dci_device_non_isoc_open, 1352 .close = avr32dci_device_non_isoc_close, 1353 .enter = avr32dci_device_non_isoc_enter, 1354 .start = avr32dci_device_non_isoc_start, 1355 }; 1356 1357 /*------------------------------------------------------------------------* 1358 * avr32dci full speed isochronous support 1359 *------------------------------------------------------------------------*/ 1360 static void 1361 avr32dci_device_isoc_fs_open(struct usb_xfer *xfer) 1362 { 1363 return; 1364 } 1365 1366 static void 1367 avr32dci_device_isoc_fs_close(struct usb_xfer *xfer) 1368 { 1369 avr32dci_device_done(xfer, USB_ERR_CANCELLED); 1370 } 1371 1372 static void 1373 avr32dci_device_isoc_fs_enter(struct usb_xfer *xfer) 1374 { 1375 struct avr32dci_softc *sc = AVR32_BUS2SC(xfer->xroot->bus); 1376 uint32_t temp; 1377 uint32_t nframes; 1378 uint8_t ep_no; 1379 1380 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 1381 xfer, xfer->endpoint->isoc_next, xfer->nframes); 1382 1383 /* get the current frame index */ 1384 ep_no = xfer->endpointno & UE_ADDR; 1385 nframes = (AVR32_READ_4(sc, AVR32_FNUM) / 8); 1386 1387 nframes &= AVR32_FRAME_MASK; 1388 1389 /* 1390 * check if the frame index is within the window where the frames 1391 * will be inserted 1392 */ 1393 temp = (nframes - xfer->endpoint->isoc_next) & AVR32_FRAME_MASK; 1394 1395 if ((xfer->endpoint->is_synced == 0) || 1396 (temp < xfer->nframes)) { 1397 /* 1398 * If there is data underflow or the pipe queue is 1399 * empty we schedule the transfer a few frames ahead 1400 * of the current frame position. Else two isochronous 1401 * transfers might overlap. 1402 */ 1403 xfer->endpoint->isoc_next = (nframes + 3) & AVR32_FRAME_MASK; 1404 xfer->endpoint->is_synced = 1; 1405 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 1406 } 1407 /* 1408 * compute how many milliseconds the insertion is ahead of the 1409 * current frame position: 1410 */ 1411 temp = (xfer->endpoint->isoc_next - nframes) & AVR32_FRAME_MASK; 1412 1413 /* 1414 * pre-compute when the isochronous transfer will be finished: 1415 */ 1416 xfer->isoc_time_complete = 1417 usb_isoc_time_expand(&sc->sc_bus, nframes) + temp + 1418 xfer->nframes; 1419 1420 /* compute frame number for next insertion */ 1421 xfer->endpoint->isoc_next += xfer->nframes; 1422 1423 /* setup TDs */ 1424 avr32dci_setup_standard_chain(xfer); 1425 } 1426 1427 static void 1428 avr32dci_device_isoc_fs_start(struct usb_xfer *xfer) 1429 { 1430 /* start TD chain */ 1431 avr32dci_start_standard_chain(xfer); 1432 } 1433 1434 static const struct usb_pipe_methods avr32dci_device_isoc_fs_methods = 1435 { 1436 .open = avr32dci_device_isoc_fs_open, 1437 .close = avr32dci_device_isoc_fs_close, 1438 .enter = avr32dci_device_isoc_fs_enter, 1439 .start = avr32dci_device_isoc_fs_start, 1440 }; 1441 1442 /*------------------------------------------------------------------------* 1443 * avr32dci root control support 1444 *------------------------------------------------------------------------* 1445 * Simulate a hardware HUB by handling all the necessary requests. 1446 *------------------------------------------------------------------------*/ 1447 1448 static const struct usb_device_descriptor avr32dci_devd = { 1449 .bLength = sizeof(struct usb_device_descriptor), 1450 .bDescriptorType = UDESC_DEVICE, 1451 .bcdUSB = {0x00, 0x02}, 1452 .bDeviceClass = UDCLASS_HUB, 1453 .bDeviceSubClass = UDSUBCLASS_HUB, 1454 .bDeviceProtocol = UDPROTO_HSHUBSTT, 1455 .bMaxPacketSize = 64, 1456 .bcdDevice = {0x00, 0x01}, 1457 .iManufacturer = 1, 1458 .iProduct = 2, 1459 .bNumConfigurations = 1, 1460 }; 1461 1462 static const struct usb_device_qualifier avr32dci_odevd = { 1463 .bLength = sizeof(struct usb_device_qualifier), 1464 .bDescriptorType = UDESC_DEVICE_QUALIFIER, 1465 .bcdUSB = {0x00, 0x02}, 1466 .bDeviceClass = UDCLASS_HUB, 1467 .bDeviceSubClass = UDSUBCLASS_HUB, 1468 .bDeviceProtocol = UDPROTO_FSHUB, 1469 .bMaxPacketSize0 = 0, 1470 .bNumConfigurations = 0, 1471 }; 1472 1473 static const struct avr32dci_config_desc avr32dci_confd = { 1474 .confd = { 1475 .bLength = sizeof(struct usb_config_descriptor), 1476 .bDescriptorType = UDESC_CONFIG, 1477 .wTotalLength[0] = sizeof(avr32dci_confd), 1478 .bNumInterface = 1, 1479 .bConfigurationValue = 1, 1480 .iConfiguration = 0, 1481 .bmAttributes = UC_SELF_POWERED, 1482 .bMaxPower = 0, 1483 }, 1484 .ifcd = { 1485 .bLength = sizeof(struct usb_interface_descriptor), 1486 .bDescriptorType = UDESC_INTERFACE, 1487 .bNumEndpoints = 1, 1488 .bInterfaceClass = UICLASS_HUB, 1489 .bInterfaceSubClass = UISUBCLASS_HUB, 1490 .bInterfaceProtocol = 0, 1491 }, 1492 .endpd = { 1493 .bLength = sizeof(struct usb_endpoint_descriptor), 1494 .bDescriptorType = UDESC_ENDPOINT, 1495 .bEndpointAddress = (UE_DIR_IN | AVR32_INTR_ENDPT), 1496 .bmAttributes = UE_INTERRUPT, 1497 .wMaxPacketSize[0] = 8, 1498 .bInterval = 255, 1499 }, 1500 }; 1501 1502 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) } 1503 1504 static const struct usb_hub_descriptor_min avr32dci_hubd = { 1505 .bDescLength = sizeof(avr32dci_hubd), 1506 .bDescriptorType = UDESC_HUB, 1507 .bNbrPorts = 1, 1508 HSETW(.wHubCharacteristics, (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL)), 1509 .bPwrOn2PwrGood = 50, 1510 .bHubContrCurrent = 0, 1511 .DeviceRemovable = {0}, /* port is removable */ 1512 }; 1513 1514 #define STRING_VENDOR \ 1515 "A\0V\0R\0003\0002" 1516 1517 #define STRING_PRODUCT \ 1518 "D\0C\0I\0 \0R\0o\0o\0t\0 \0H\0U\0B" 1519 1520 USB_MAKE_STRING_DESC(STRING_VENDOR, avr32dci_vendor); 1521 USB_MAKE_STRING_DESC(STRING_PRODUCT, avr32dci_product); 1522 1523 static usb_error_t 1524 avr32dci_roothub_exec(struct usb_device *udev, 1525 struct usb_device_request *req, const void **pptr, uint16_t *plength) 1526 { 1527 struct avr32dci_softc *sc = AVR32_BUS2SC(udev->bus); 1528 const void *ptr; 1529 uint16_t len; 1530 uint16_t value; 1531 uint16_t index; 1532 uint32_t temp; 1533 usb_error_t err; 1534 1535 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1536 1537 /* buffer reset */ 1538 ptr = (const void *)&sc->sc_hub_temp; 1539 len = 0; 1540 err = 0; 1541 1542 value = UGETW(req->wValue); 1543 index = UGETW(req->wIndex); 1544 1545 /* demultiplex the control request */ 1546 1547 switch (req->bmRequestType) { 1548 case UT_READ_DEVICE: 1549 switch (req->bRequest) { 1550 case UR_GET_DESCRIPTOR: 1551 goto tr_handle_get_descriptor; 1552 case UR_GET_CONFIG: 1553 goto tr_handle_get_config; 1554 case UR_GET_STATUS: 1555 goto tr_handle_get_status; 1556 default: 1557 goto tr_stalled; 1558 } 1559 break; 1560 1561 case UT_WRITE_DEVICE: 1562 switch (req->bRequest) { 1563 case UR_SET_ADDRESS: 1564 goto tr_handle_set_address; 1565 case UR_SET_CONFIG: 1566 goto tr_handle_set_config; 1567 case UR_CLEAR_FEATURE: 1568 goto tr_valid; /* nop */ 1569 case UR_SET_DESCRIPTOR: 1570 goto tr_valid; /* nop */ 1571 case UR_SET_FEATURE: 1572 default: 1573 goto tr_stalled; 1574 } 1575 break; 1576 1577 case UT_WRITE_ENDPOINT: 1578 switch (req->bRequest) { 1579 case UR_CLEAR_FEATURE: 1580 switch (UGETW(req->wValue)) { 1581 case UF_ENDPOINT_HALT: 1582 goto tr_handle_clear_halt; 1583 case UF_DEVICE_REMOTE_WAKEUP: 1584 goto tr_handle_clear_wakeup; 1585 default: 1586 goto tr_stalled; 1587 } 1588 break; 1589 case UR_SET_FEATURE: 1590 switch (UGETW(req->wValue)) { 1591 case UF_ENDPOINT_HALT: 1592 goto tr_handle_set_halt; 1593 case UF_DEVICE_REMOTE_WAKEUP: 1594 goto tr_handle_set_wakeup; 1595 default: 1596 goto tr_stalled; 1597 } 1598 break; 1599 case UR_SYNCH_FRAME: 1600 goto tr_valid; /* nop */ 1601 default: 1602 goto tr_stalled; 1603 } 1604 break; 1605 1606 case UT_READ_ENDPOINT: 1607 switch (req->bRequest) { 1608 case UR_GET_STATUS: 1609 goto tr_handle_get_ep_status; 1610 default: 1611 goto tr_stalled; 1612 } 1613 break; 1614 1615 case UT_WRITE_INTERFACE: 1616 switch (req->bRequest) { 1617 case UR_SET_INTERFACE: 1618 goto tr_handle_set_interface; 1619 case UR_CLEAR_FEATURE: 1620 goto tr_valid; /* nop */ 1621 case UR_SET_FEATURE: 1622 default: 1623 goto tr_stalled; 1624 } 1625 break; 1626 1627 case UT_READ_INTERFACE: 1628 switch (req->bRequest) { 1629 case UR_GET_INTERFACE: 1630 goto tr_handle_get_interface; 1631 case UR_GET_STATUS: 1632 goto tr_handle_get_iface_status; 1633 default: 1634 goto tr_stalled; 1635 } 1636 break; 1637 1638 case UT_WRITE_CLASS_INTERFACE: 1639 case UT_WRITE_VENDOR_INTERFACE: 1640 /* XXX forward */ 1641 break; 1642 1643 case UT_READ_CLASS_INTERFACE: 1644 case UT_READ_VENDOR_INTERFACE: 1645 /* XXX forward */ 1646 break; 1647 1648 case UT_WRITE_CLASS_DEVICE: 1649 switch (req->bRequest) { 1650 case UR_CLEAR_FEATURE: 1651 goto tr_valid; 1652 case UR_SET_DESCRIPTOR: 1653 case UR_SET_FEATURE: 1654 break; 1655 default: 1656 goto tr_stalled; 1657 } 1658 break; 1659 1660 case UT_WRITE_CLASS_OTHER: 1661 switch (req->bRequest) { 1662 case UR_CLEAR_FEATURE: 1663 goto tr_handle_clear_port_feature; 1664 case UR_SET_FEATURE: 1665 goto tr_handle_set_port_feature; 1666 case UR_CLEAR_TT_BUFFER: 1667 case UR_RESET_TT: 1668 case UR_STOP_TT: 1669 goto tr_valid; 1670 1671 default: 1672 goto tr_stalled; 1673 } 1674 break; 1675 1676 case UT_READ_CLASS_OTHER: 1677 switch (req->bRequest) { 1678 case UR_GET_TT_STATE: 1679 goto tr_handle_get_tt_state; 1680 case UR_GET_STATUS: 1681 goto tr_handle_get_port_status; 1682 default: 1683 goto tr_stalled; 1684 } 1685 break; 1686 1687 case UT_READ_CLASS_DEVICE: 1688 switch (req->bRequest) { 1689 case UR_GET_DESCRIPTOR: 1690 goto tr_handle_get_class_descriptor; 1691 case UR_GET_STATUS: 1692 goto tr_handle_get_class_status; 1693 1694 default: 1695 goto tr_stalled; 1696 } 1697 break; 1698 default: 1699 goto tr_stalled; 1700 } 1701 goto tr_valid; 1702 1703 tr_handle_get_descriptor: 1704 switch (value >> 8) { 1705 case UDESC_DEVICE: 1706 if (value & 0xff) { 1707 goto tr_stalled; 1708 } 1709 len = sizeof(avr32dci_devd); 1710 ptr = (const void *)&avr32dci_devd; 1711 goto tr_valid; 1712 case UDESC_CONFIG: 1713 if (value & 0xff) { 1714 goto tr_stalled; 1715 } 1716 len = sizeof(avr32dci_confd); 1717 ptr = (const void *)&avr32dci_confd; 1718 goto tr_valid; 1719 case UDESC_STRING: 1720 switch (value & 0xff) { 1721 case 0: /* Language table */ 1722 len = sizeof(usb_string_lang_en); 1723 ptr = (const void *)&usb_string_lang_en; 1724 goto tr_valid; 1725 1726 case 1: /* Vendor */ 1727 len = sizeof(avr32dci_vendor); 1728 ptr = (const void *)&avr32dci_vendor; 1729 goto tr_valid; 1730 1731 case 2: /* Product */ 1732 len = sizeof(avr32dci_product); 1733 ptr = (const void *)&avr32dci_product; 1734 goto tr_valid; 1735 default: 1736 break; 1737 } 1738 break; 1739 default: 1740 goto tr_stalled; 1741 } 1742 goto tr_stalled; 1743 1744 tr_handle_get_config: 1745 len = 1; 1746 sc->sc_hub_temp.wValue[0] = sc->sc_conf; 1747 goto tr_valid; 1748 1749 tr_handle_get_status: 1750 len = 2; 1751 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED); 1752 goto tr_valid; 1753 1754 tr_handle_set_address: 1755 if (value & 0xFF00) { 1756 goto tr_stalled; 1757 } 1758 sc->sc_rt_addr = value; 1759 goto tr_valid; 1760 1761 tr_handle_set_config: 1762 if (value >= 2) { 1763 goto tr_stalled; 1764 } 1765 sc->sc_conf = value; 1766 goto tr_valid; 1767 1768 tr_handle_get_interface: 1769 len = 1; 1770 sc->sc_hub_temp.wValue[0] = 0; 1771 goto tr_valid; 1772 1773 tr_handle_get_tt_state: 1774 tr_handle_get_class_status: 1775 tr_handle_get_iface_status: 1776 tr_handle_get_ep_status: 1777 len = 2; 1778 USETW(sc->sc_hub_temp.wValue, 0); 1779 goto tr_valid; 1780 1781 tr_handle_set_halt: 1782 tr_handle_set_interface: 1783 tr_handle_set_wakeup: 1784 tr_handle_clear_wakeup: 1785 tr_handle_clear_halt: 1786 goto tr_valid; 1787 1788 tr_handle_clear_port_feature: 1789 if (index != 1) { 1790 goto tr_stalled; 1791 } 1792 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE on port %d\n", index); 1793 1794 switch (value) { 1795 case UHF_PORT_SUSPEND: 1796 avr32dci_wakeup_peer(sc); 1797 break; 1798 1799 case UHF_PORT_ENABLE: 1800 sc->sc_flags.port_enabled = 0; 1801 break; 1802 1803 case UHF_PORT_TEST: 1804 case UHF_PORT_INDICATOR: 1805 case UHF_C_PORT_ENABLE: 1806 case UHF_C_PORT_OVER_CURRENT: 1807 case UHF_C_PORT_RESET: 1808 /* nops */ 1809 break; 1810 case UHF_PORT_POWER: 1811 sc->sc_flags.port_powered = 0; 1812 avr32dci_pull_down(sc); 1813 avr32dci_clocks_off(sc); 1814 break; 1815 case UHF_C_PORT_CONNECTION: 1816 /* clear connect change flag */ 1817 sc->sc_flags.change_connect = 0; 1818 1819 if (!sc->sc_flags.status_bus_reset) { 1820 /* we are not connected */ 1821 break; 1822 } 1823 /* configure the control endpoint */ 1824 /* set endpoint reset */ 1825 AVR32_WRITE_4(sc, AVR32_EPTRST, AVR32_EPTRST_MASK(0)); 1826 1827 /* set stall */ 1828 AVR32_WRITE_4(sc, AVR32_EPTSETSTA(0), AVR32_EPTSTA_FRCESTALL); 1829 1830 /* reset data toggle */ 1831 AVR32_WRITE_4(sc, AVR32_EPTCLRSTA(0), AVR32_EPTSTA_TOGGLESQ); 1832 1833 /* clear stall */ 1834 AVR32_WRITE_4(sc, AVR32_EPTCLRSTA(0), AVR32_EPTSTA_FRCESTALL); 1835 1836 /* configure */ 1837 AVR32_WRITE_4(sc, AVR32_EPTCFG(0), AVR32_EPTCFG_TYPE_CTRL | 1838 AVR32_EPTCFG_NBANK(1) | AVR32_EPTCFG_EPSIZE(6)); 1839 1840 temp = AVR32_READ_4(sc, AVR32_EPTCFG(0)); 1841 1842 if (!(temp & AVR32_EPTCFG_EPT_MAPD)) { 1843 device_printf(sc->sc_bus.bdev, 1844 "Chip rejected configuration\n"); 1845 } else { 1846 AVR32_WRITE_4(sc, AVR32_EPTCTLENB(0), 1847 AVR32_EPTCTL_EPT_ENABL); 1848 } 1849 break; 1850 case UHF_C_PORT_SUSPEND: 1851 sc->sc_flags.change_suspend = 0; 1852 break; 1853 default: 1854 err = USB_ERR_IOERROR; 1855 goto done; 1856 } 1857 goto tr_valid; 1858 1859 tr_handle_set_port_feature: 1860 if (index != 1) { 1861 goto tr_stalled; 1862 } 1863 DPRINTFN(9, "UR_SET_PORT_FEATURE\n"); 1864 1865 switch (value) { 1866 case UHF_PORT_ENABLE: 1867 sc->sc_flags.port_enabled = 1; 1868 break; 1869 case UHF_PORT_SUSPEND: 1870 case UHF_PORT_RESET: 1871 case UHF_PORT_TEST: 1872 case UHF_PORT_INDICATOR: 1873 /* nops */ 1874 break; 1875 case UHF_PORT_POWER: 1876 sc->sc_flags.port_powered = 1; 1877 break; 1878 default: 1879 err = USB_ERR_IOERROR; 1880 goto done; 1881 } 1882 goto tr_valid; 1883 1884 tr_handle_get_port_status: 1885 1886 DPRINTFN(9, "UR_GET_PORT_STATUS\n"); 1887 1888 if (index != 1) { 1889 goto tr_stalled; 1890 } 1891 if (sc->sc_flags.status_vbus) { 1892 avr32dci_clocks_on(sc); 1893 avr32dci_pull_up(sc); 1894 } else { 1895 avr32dci_pull_down(sc); 1896 avr32dci_clocks_off(sc); 1897 } 1898 1899 /* Select Device Side Mode */ 1900 1901 value = UPS_PORT_MODE_DEVICE; 1902 1903 /* Check for High Speed */ 1904 if (AVR32_READ_4(sc, AVR32_INTSTA) & AVR32_INT_SPEED) 1905 value |= UPS_HIGH_SPEED; 1906 1907 if (sc->sc_flags.port_powered) { 1908 value |= UPS_PORT_POWER; 1909 } 1910 if (sc->sc_flags.port_enabled) { 1911 value |= UPS_PORT_ENABLED; 1912 } 1913 if (sc->sc_flags.status_vbus && 1914 sc->sc_flags.status_bus_reset) { 1915 value |= UPS_CURRENT_CONNECT_STATUS; 1916 } 1917 if (sc->sc_flags.status_suspend) { 1918 value |= UPS_SUSPEND; 1919 } 1920 USETW(sc->sc_hub_temp.ps.wPortStatus, value); 1921 1922 value = 0; 1923 1924 if (sc->sc_flags.change_connect) { 1925 value |= UPS_C_CONNECT_STATUS; 1926 } 1927 if (sc->sc_flags.change_suspend) { 1928 value |= UPS_C_SUSPEND; 1929 } 1930 USETW(sc->sc_hub_temp.ps.wPortChange, value); 1931 len = sizeof(sc->sc_hub_temp.ps); 1932 goto tr_valid; 1933 1934 tr_handle_get_class_descriptor: 1935 if (value & 0xFF) { 1936 goto tr_stalled; 1937 } 1938 ptr = (const void *)&avr32dci_hubd; 1939 len = sizeof(avr32dci_hubd); 1940 goto tr_valid; 1941 1942 tr_stalled: 1943 err = USB_ERR_STALLED; 1944 tr_valid: 1945 done: 1946 *plength = len; 1947 *pptr = ptr; 1948 return (err); 1949 } 1950 1951 static void 1952 avr32dci_xfer_setup(struct usb_setup_params *parm) 1953 { 1954 const struct usb_hw_ep_profile *pf; 1955 struct avr32dci_softc *sc; 1956 struct usb_xfer *xfer; 1957 void *last_obj; 1958 uint32_t ntd; 1959 uint32_t n; 1960 uint8_t ep_no; 1961 1962 sc = AVR32_BUS2SC(parm->udev->bus); 1963 xfer = parm->curr_xfer; 1964 1965 /* 1966 * NOTE: This driver does not use any of the parameters that 1967 * are computed from the following values. Just set some 1968 * reasonable dummies: 1969 */ 1970 parm->hc_max_packet_size = 0x400; 1971 parm->hc_max_packet_count = 1; 1972 parm->hc_max_frame_size = 0x400; 1973 1974 usbd_transfer_setup_sub(parm); 1975 1976 /* 1977 * compute maximum number of TDs 1978 */ 1979 if ((xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) { 1980 1981 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC 1 */ 1982 + 1 /* SYNC 2 */ ; 1983 } else { 1984 1985 ntd = xfer->nframes + 1 /* SYNC */ ; 1986 } 1987 1988 /* 1989 * check if "usbd_transfer_setup_sub" set an error 1990 */ 1991 if (parm->err) 1992 return; 1993 1994 /* 1995 * allocate transfer descriptors 1996 */ 1997 last_obj = NULL; 1998 1999 /* 2000 * get profile stuff 2001 */ 2002 ep_no = xfer->endpointno & UE_ADDR; 2003 avr32dci_get_hw_ep_profile(parm->udev, &pf, ep_no); 2004 2005 if (pf == NULL) { 2006 /* should not happen */ 2007 parm->err = USB_ERR_INVAL; 2008 return; 2009 } 2010 /* align data */ 2011 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1)); 2012 2013 for (n = 0; n != ntd; n++) { 2014 2015 struct avr32dci_td *td; 2016 2017 if (parm->buf) { 2018 uint32_t temp; 2019 2020 td = USB_ADD_BYTES(parm->buf, parm->size[0]); 2021 2022 /* init TD */ 2023 td->max_packet_size = xfer->max_packet_size; 2024 td->ep_no = ep_no; 2025 temp = pf->max_in_frame_size | pf->max_out_frame_size; 2026 td->bank_shift = 0; 2027 while ((temp /= 2)) 2028 td->bank_shift++; 2029 if (pf->support_multi_buffer) { 2030 td->support_multi_buffer = 1; 2031 } 2032 td->obj_next = last_obj; 2033 2034 last_obj = td; 2035 } 2036 parm->size[0] += sizeof(*td); 2037 } 2038 2039 xfer->td_start[0] = last_obj; 2040 } 2041 2042 static void 2043 avr32dci_xfer_unsetup(struct usb_xfer *xfer) 2044 { 2045 return; 2046 } 2047 2048 static void 2049 avr32dci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 2050 struct usb_endpoint *pipe) 2051 { 2052 struct avr32dci_softc *sc = AVR32_BUS2SC(udev->bus); 2053 2054 DPRINTFN(2, "pipe=%p, addr=%d, endpt=%d, mode=%d (%d,%d)\n", 2055 pipe, udev->address, 2056 edesc->bEndpointAddress, udev->flags.usb_mode, 2057 sc->sc_rt_addr, udev->device_index); 2058 2059 if (udev->device_index != sc->sc_rt_addr) { 2060 2061 if ((udev->speed != USB_SPEED_FULL) && 2062 (udev->speed != USB_SPEED_HIGH)) { 2063 /* not supported */ 2064 return; 2065 } 2066 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_ISOCHRONOUS) 2067 pipe->methods = &avr32dci_device_isoc_fs_methods; 2068 else 2069 pipe->methods = &avr32dci_device_non_isoc_methods; 2070 } 2071 } 2072 2073 static void 2074 avr32dci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 2075 { 2076 struct avr32dci_softc *sc = AVR32_BUS2SC(bus); 2077 2078 switch (state) { 2079 case USB_HW_POWER_SUSPEND: 2080 avr32dci_suspend(sc); 2081 break; 2082 case USB_HW_POWER_SHUTDOWN: 2083 avr32dci_uninit(sc); 2084 break; 2085 case USB_HW_POWER_RESUME: 2086 avr32dci_resume(sc); 2087 break; 2088 default: 2089 break; 2090 } 2091 } 2092 2093 static const struct usb_bus_methods avr32dci_bus_methods = 2094 { 2095 .endpoint_init = &avr32dci_ep_init, 2096 .xfer_setup = &avr32dci_xfer_setup, 2097 .xfer_unsetup = &avr32dci_xfer_unsetup, 2098 .get_hw_ep_profile = &avr32dci_get_hw_ep_profile, 2099 .xfer_stall = &avr32dci_xfer_stall, 2100 .set_stall = &avr32dci_set_stall, 2101 .clear_stall = &avr32dci_clear_stall, 2102 .roothub_exec = &avr32dci_roothub_exec, 2103 .xfer_poll = &avr32dci_do_poll, 2104 .set_hw_power_sleep = &avr32dci_set_hw_power_sleep, 2105 }; 2106