1 /* $FreeBSD$ */ 2 /*- 3 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved. 4 * Copyright (c) 2004 The NetBSD Foundation, Inc. All rights reserved. 5 * Copyright (c) 2004 Lennart Augustsson. All rights reserved. 6 * Copyright (c) 2004 Charles M. Hannum. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* 31 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 32 * 33 * The EHCI 0.96 spec can be found at 34 * http://developer.intel.com/technology/usb/download/ehci-r096.pdf 35 * The EHCI 1.0 spec can be found at 36 * http://developer.intel.com/technology/usb/download/ehci-r10.pdf 37 * and the USB 2.0 spec at 38 * http://www.usb.org/developers/docs/usb_20.zip 39 * 40 */ 41 42 /* 43 * TODO: 44 * 1) command failures are not recovered correctly 45 */ 46 47 #ifdef USB_GLOBAL_INCLUDE_FILE 48 #include USB_GLOBAL_INCLUDE_FILE 49 #else 50 #include <sys/stdint.h> 51 #include <sys/stddef.h> 52 #include <sys/param.h> 53 #include <sys/queue.h> 54 #include <sys/types.h> 55 #include <sys/systm.h> 56 #include <sys/kernel.h> 57 #include <sys/bus.h> 58 #include <sys/module.h> 59 #include <sys/lock.h> 60 #include <sys/mutex.h> 61 #include <sys/condvar.h> 62 #include <sys/sysctl.h> 63 #include <sys/sx.h> 64 #include <sys/unistd.h> 65 #include <sys/callout.h> 66 #include <sys/malloc.h> 67 #include <sys/priv.h> 68 69 #include <dev/usb/usb.h> 70 #include <dev/usb/usbdi.h> 71 72 #define USB_DEBUG_VAR ehcidebug 73 74 #include <dev/usb/usb_core.h> 75 #include <dev/usb/usb_debug.h> 76 #include <dev/usb/usb_busdma.h> 77 #include <dev/usb/usb_process.h> 78 #include <dev/usb/usb_transfer.h> 79 #include <dev/usb/usb_device.h> 80 #include <dev/usb/usb_hub.h> 81 #include <dev/usb/usb_util.h> 82 83 #include <dev/usb/usb_controller.h> 84 #include <dev/usb/usb_bus.h> 85 #endif /* USB_GLOBAL_INCLUDE_FILE */ 86 87 #include <dev/usb/controller/ehci.h> 88 #include <dev/usb/controller/ehcireg.h> 89 90 #define EHCI_BUS2SC(bus) \ 91 ((ehci_softc_t *)(((uint8_t *)(bus)) - \ 92 ((uint8_t *)&(((ehci_softc_t *)0)->sc_bus)))) 93 94 #ifdef USB_DEBUG 95 static int ehcidebug = 0; 96 static int ehcinohighspeed = 0; 97 static int ehciiaadbug = 0; 98 static int ehcilostintrbug = 0; 99 100 static SYSCTL_NODE(_hw_usb, OID_AUTO, ehci, CTLFLAG_RW, 0, "USB ehci"); 101 SYSCTL_INT(_hw_usb_ehci, OID_AUTO, debug, CTLFLAG_RWTUN, 102 &ehcidebug, 0, "Debug level"); 103 SYSCTL_INT(_hw_usb_ehci, OID_AUTO, no_hs, CTLFLAG_RWTUN, 104 &ehcinohighspeed, 0, "Disable High Speed USB"); 105 SYSCTL_INT(_hw_usb_ehci, OID_AUTO, iaadbug, CTLFLAG_RWTUN, 106 &ehciiaadbug, 0, "Enable doorbell bug workaround"); 107 SYSCTL_INT(_hw_usb_ehci, OID_AUTO, lostintrbug, CTLFLAG_RWTUN, 108 &ehcilostintrbug, 0, "Enable lost interrupt bug workaround"); 109 110 static void ehci_dump_regs(ehci_softc_t *sc); 111 static void ehci_dump_sqh(ehci_softc_t *sc, ehci_qh_t *sqh); 112 113 #endif 114 115 #define EHCI_INTR_ENDPT 1 116 117 static const struct usb_bus_methods ehci_bus_methods; 118 static const struct usb_pipe_methods ehci_device_bulk_methods; 119 static const struct usb_pipe_methods ehci_device_ctrl_methods; 120 static const struct usb_pipe_methods ehci_device_intr_methods; 121 static const struct usb_pipe_methods ehci_device_isoc_fs_methods; 122 static const struct usb_pipe_methods ehci_device_isoc_hs_methods; 123 124 static void ehci_do_poll(struct usb_bus *); 125 static void ehci_device_done(struct usb_xfer *, usb_error_t); 126 static uint8_t ehci_check_transfer(struct usb_xfer *); 127 static void ehci_timeout(void *); 128 static void ehci_poll_timeout(void *); 129 130 static void ehci_root_intr(ehci_softc_t *sc); 131 132 struct ehci_std_temp { 133 ehci_softc_t *sc; 134 struct usb_page_cache *pc; 135 ehci_qtd_t *td; 136 ehci_qtd_t *td_next; 137 uint32_t average; 138 uint32_t qtd_status; 139 uint32_t len; 140 uint16_t max_frame_size; 141 uint8_t shortpkt; 142 uint8_t auto_data_toggle; 143 uint8_t setup_alt_next; 144 uint8_t last_frame; 145 }; 146 147 void 148 ehci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb) 149 { 150 ehci_softc_t *sc = EHCI_BUS2SC(bus); 151 uint32_t i; 152 153 cb(bus, &sc->sc_hw.pframes_pc, &sc->sc_hw.pframes_pg, 154 sizeof(uint32_t) * EHCI_FRAMELIST_COUNT, EHCI_FRAMELIST_ALIGN); 155 156 cb(bus, &sc->sc_hw.terminate_pc, &sc->sc_hw.terminate_pg, 157 sizeof(struct ehci_qh_sub), EHCI_QH_ALIGN); 158 159 cb(bus, &sc->sc_hw.async_start_pc, &sc->sc_hw.async_start_pg, 160 sizeof(ehci_qh_t), EHCI_QH_ALIGN); 161 162 for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 163 cb(bus, sc->sc_hw.intr_start_pc + i, 164 sc->sc_hw.intr_start_pg + i, 165 sizeof(ehci_qh_t), EHCI_QH_ALIGN); 166 } 167 168 for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 169 cb(bus, sc->sc_hw.isoc_hs_start_pc + i, 170 sc->sc_hw.isoc_hs_start_pg + i, 171 sizeof(ehci_itd_t), EHCI_ITD_ALIGN); 172 } 173 174 for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 175 cb(bus, sc->sc_hw.isoc_fs_start_pc + i, 176 sc->sc_hw.isoc_fs_start_pg + i, 177 sizeof(ehci_sitd_t), EHCI_SITD_ALIGN); 178 } 179 } 180 181 usb_error_t 182 ehci_reset(ehci_softc_t *sc) 183 { 184 uint32_t hcr; 185 int i; 186 187 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 188 for (i = 0; i < 100; i++) { 189 usb_pause_mtx(NULL, hz / 128); 190 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 191 if (!hcr) { 192 if (sc->sc_flags & (EHCI_SCFLG_SETMODE | EHCI_SCFLG_BIGEMMIO)) { 193 /* 194 * Force USBMODE as requested. Controllers 195 * may have multiple operating modes. 196 */ 197 uint32_t usbmode = EOREAD4(sc, EHCI_USBMODE); 198 if (sc->sc_flags & EHCI_SCFLG_SETMODE) { 199 usbmode = (usbmode &~ EHCI_UM_CM) | EHCI_UM_CM_HOST; 200 device_printf(sc->sc_bus.bdev, 201 "set host controller mode\n"); 202 } 203 if (sc->sc_flags & EHCI_SCFLG_BIGEMMIO) { 204 usbmode = (usbmode &~ EHCI_UM_ES) | EHCI_UM_ES_BE; 205 device_printf(sc->sc_bus.bdev, 206 "set big-endian mode\n"); 207 } 208 EOWRITE4(sc, EHCI_USBMODE, usbmode); 209 } 210 return (0); 211 } 212 } 213 device_printf(sc->sc_bus.bdev, "reset timeout\n"); 214 return (USB_ERR_IOERROR); 215 } 216 217 static usb_error_t 218 ehci_hcreset(ehci_softc_t *sc) 219 { 220 uint32_t hcr; 221 int i; 222 223 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 224 for (i = 0; i < 100; i++) { 225 usb_pause_mtx(NULL, hz / 128); 226 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 227 if (hcr) 228 break; 229 } 230 if (!hcr) 231 /* 232 * Fall through and try reset anyway even though 233 * Table 2-9 in the EHCI spec says this will result 234 * in undefined behavior. 235 */ 236 device_printf(sc->sc_bus.bdev, "stop timeout\n"); 237 238 return (ehci_reset(sc)); 239 } 240 241 static int 242 ehci_init_sub(struct ehci_softc *sc) 243 { 244 struct usb_page_search buf_res; 245 uint32_t cparams; 246 uint32_t hcr; 247 uint8_t i; 248 249 cparams = EREAD4(sc, EHCI_HCCPARAMS); 250 251 DPRINTF("cparams=0x%x\n", cparams); 252 253 if (EHCI_HCC_64BIT(cparams)) { 254 DPRINTF("HCC uses 64-bit structures\n"); 255 256 /* MUST clear segment register if 64 bit capable */ 257 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 258 } 259 260 usbd_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res); 261 EOWRITE4(sc, EHCI_PERIODICLISTBASE, buf_res.physaddr); 262 263 usbd_get_page(&sc->sc_hw.async_start_pc, 0, &buf_res); 264 EOWRITE4(sc, EHCI_ASYNCLISTADDR, buf_res.physaddr | EHCI_LINK_QH); 265 266 /* enable interrupts */ 267 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 268 269 /* turn on controller */ 270 EOWRITE4(sc, EHCI_USBCMD, 271 EHCI_CMD_ITC_1 | /* 1 microframes interrupt delay */ 272 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 273 EHCI_CMD_ASE | 274 EHCI_CMD_PSE | 275 EHCI_CMD_RS); 276 277 /* Take over port ownership */ 278 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 279 280 for (i = 0; i < 100; i++) { 281 usb_pause_mtx(NULL, hz / 128); 282 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 283 if (!hcr) { 284 break; 285 } 286 } 287 if (hcr) { 288 device_printf(sc->sc_bus.bdev, "run timeout\n"); 289 return (USB_ERR_IOERROR); 290 } 291 return (USB_ERR_NORMAL_COMPLETION); 292 } 293 294 usb_error_t 295 ehci_init(ehci_softc_t *sc) 296 { 297 struct usb_page_search buf_res; 298 uint32_t version; 299 uint32_t sparams; 300 uint16_t i; 301 uint16_t x; 302 uint16_t y; 303 uint16_t bit; 304 usb_error_t err = 0; 305 306 DPRINTF("start\n"); 307 308 usb_callout_init_mtx(&sc->sc_tmo_pcd, &sc->sc_bus.bus_mtx, 0); 309 usb_callout_init_mtx(&sc->sc_tmo_poll, &sc->sc_bus.bus_mtx, 0); 310 311 sc->sc_offs = EHCI_CAPLENGTH(EREAD4(sc, EHCI_CAPLEN_HCIVERSION)); 312 313 #ifdef USB_DEBUG 314 if (ehciiaadbug) 315 sc->sc_flags |= EHCI_SCFLG_IAADBUG; 316 if (ehcilostintrbug) 317 sc->sc_flags |= EHCI_SCFLG_LOSTINTRBUG; 318 if (ehcidebug > 2) { 319 ehci_dump_regs(sc); 320 } 321 #endif 322 323 version = EHCI_HCIVERSION(EREAD4(sc, EHCI_CAPLEN_HCIVERSION)); 324 device_printf(sc->sc_bus.bdev, "EHCI version %x.%x\n", 325 version >> 8, version & 0xff); 326 327 sparams = EREAD4(sc, EHCI_HCSPARAMS); 328 DPRINTF("sparams=0x%x\n", sparams); 329 330 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 331 sc->sc_bus.usbrev = USB_REV_2_0; 332 333 if (!(sc->sc_flags & EHCI_SCFLG_DONTRESET)) { 334 /* Reset the controller */ 335 DPRINTF("%s: resetting\n", 336 device_get_nameunit(sc->sc_bus.bdev)); 337 338 err = ehci_hcreset(sc); 339 if (err) { 340 device_printf(sc->sc_bus.bdev, "reset timeout\n"); 341 return (err); 342 } 343 } 344 345 /* 346 * use current frame-list-size selection 0: 1024*4 bytes 1: 512*4 347 * bytes 2: 256*4 bytes 3: unknown 348 */ 349 if (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD)) == 3) { 350 device_printf(sc->sc_bus.bdev, "invalid frame-list-size\n"); 351 return (USB_ERR_IOERROR); 352 } 353 /* set up the bus struct */ 354 sc->sc_bus.methods = &ehci_bus_methods; 355 356 sc->sc_eintrs = EHCI_NORMAL_INTRS; 357 358 if (1) { 359 struct ehci_qh_sub *qh; 360 361 usbd_get_page(&sc->sc_hw.terminate_pc, 0, &buf_res); 362 363 qh = buf_res.buffer; 364 365 sc->sc_terminate_self = htohc32(sc, buf_res.physaddr); 366 367 /* init terminate TD */ 368 qh->qtd_next = 369 htohc32(sc, EHCI_LINK_TERMINATE); 370 qh->qtd_altnext = 371 htohc32(sc, EHCI_LINK_TERMINATE); 372 qh->qtd_status = 373 htohc32(sc, EHCI_QTD_HALTED); 374 } 375 376 for (i = 0; i < EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 377 ehci_qh_t *qh; 378 379 usbd_get_page(sc->sc_hw.intr_start_pc + i, 0, &buf_res); 380 381 qh = buf_res.buffer; 382 383 /* initialize page cache pointer */ 384 385 qh->page_cache = sc->sc_hw.intr_start_pc + i; 386 387 /* store a pointer to queue head */ 388 389 sc->sc_intr_p_last[i] = qh; 390 391 qh->qh_self = 392 htohc32(sc, buf_res.physaddr) | 393 htohc32(sc, EHCI_LINK_QH); 394 395 qh->qh_endp = 396 htohc32(sc, EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 397 qh->qh_endphub = 398 htohc32(sc, EHCI_QH_SET_MULT(1)); 399 qh->qh_curqtd = 0; 400 401 qh->qh_qtd.qtd_next = 402 htohc32(sc, EHCI_LINK_TERMINATE); 403 qh->qh_qtd.qtd_altnext = 404 htohc32(sc, EHCI_LINK_TERMINATE); 405 qh->qh_qtd.qtd_status = 406 htohc32(sc, EHCI_QTD_HALTED); 407 } 408 409 /* 410 * the QHs are arranged to give poll intervals that are 411 * powers of 2 times 1ms 412 */ 413 bit = EHCI_VIRTUAL_FRAMELIST_COUNT / 2; 414 while (bit) { 415 x = bit; 416 while (x & bit) { 417 ehci_qh_t *qh_x; 418 ehci_qh_t *qh_y; 419 420 y = (x ^ bit) | (bit / 2); 421 422 qh_x = sc->sc_intr_p_last[x]; 423 qh_y = sc->sc_intr_p_last[y]; 424 425 /* 426 * the next QH has half the poll interval 427 */ 428 qh_x->qh_link = qh_y->qh_self; 429 430 x++; 431 } 432 bit >>= 1; 433 } 434 435 if (1) { 436 ehci_qh_t *qh; 437 438 qh = sc->sc_intr_p_last[0]; 439 440 /* the last (1ms) QH terminates */ 441 qh->qh_link = htohc32(sc, EHCI_LINK_TERMINATE); 442 } 443 for (i = 0; i < EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 444 ehci_sitd_t *sitd; 445 ehci_itd_t *itd; 446 447 usbd_get_page(sc->sc_hw.isoc_fs_start_pc + i, 0, &buf_res); 448 449 sitd = buf_res.buffer; 450 451 /* initialize page cache pointer */ 452 453 sitd->page_cache = sc->sc_hw.isoc_fs_start_pc + i; 454 455 /* store a pointer to the transfer descriptor */ 456 457 sc->sc_isoc_fs_p_last[i] = sitd; 458 459 /* initialize full speed isochronous */ 460 461 sitd->sitd_self = 462 htohc32(sc, buf_res.physaddr) | 463 htohc32(sc, EHCI_LINK_SITD); 464 465 sitd->sitd_back = 466 htohc32(sc, EHCI_LINK_TERMINATE); 467 468 sitd->sitd_next = 469 sc->sc_intr_p_last[i | (EHCI_VIRTUAL_FRAMELIST_COUNT / 2)]->qh_self; 470 471 472 usbd_get_page(sc->sc_hw.isoc_hs_start_pc + i, 0, &buf_res); 473 474 itd = buf_res.buffer; 475 476 /* initialize page cache pointer */ 477 478 itd->page_cache = sc->sc_hw.isoc_hs_start_pc + i; 479 480 /* store a pointer to the transfer descriptor */ 481 482 sc->sc_isoc_hs_p_last[i] = itd; 483 484 /* initialize high speed isochronous */ 485 486 itd->itd_self = 487 htohc32(sc, buf_res.physaddr) | 488 htohc32(sc, EHCI_LINK_ITD); 489 490 itd->itd_next = 491 sitd->sitd_self; 492 } 493 494 usbd_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res); 495 496 if (1) { 497 uint32_t *pframes; 498 499 pframes = buf_res.buffer; 500 501 /* 502 * execution order: 503 * pframes -> high speed isochronous -> 504 * full speed isochronous -> interrupt QH's 505 */ 506 for (i = 0; i < EHCI_FRAMELIST_COUNT; i++) { 507 pframes[i] = sc->sc_isoc_hs_p_last 508 [i & (EHCI_VIRTUAL_FRAMELIST_COUNT - 1)]->itd_self; 509 } 510 } 511 usbd_get_page(&sc->sc_hw.async_start_pc, 0, &buf_res); 512 513 if (1) { 514 515 ehci_qh_t *qh; 516 517 qh = buf_res.buffer; 518 519 /* initialize page cache pointer */ 520 521 qh->page_cache = &sc->sc_hw.async_start_pc; 522 523 /* store a pointer to the queue head */ 524 525 sc->sc_async_p_last = qh; 526 527 /* init dummy QH that starts the async list */ 528 529 qh->qh_self = 530 htohc32(sc, buf_res.physaddr) | 531 htohc32(sc, EHCI_LINK_QH); 532 533 /* fill the QH */ 534 qh->qh_endp = 535 htohc32(sc, EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 536 qh->qh_endphub = htohc32(sc, EHCI_QH_SET_MULT(1)); 537 qh->qh_link = qh->qh_self; 538 qh->qh_curqtd = 0; 539 540 /* fill the overlay qTD */ 541 qh->qh_qtd.qtd_next = htohc32(sc, EHCI_LINK_TERMINATE); 542 qh->qh_qtd.qtd_altnext = htohc32(sc, EHCI_LINK_TERMINATE); 543 qh->qh_qtd.qtd_status = htohc32(sc, EHCI_QTD_HALTED); 544 } 545 /* flush all cache into memory */ 546 547 usb_bus_mem_flush_all(&sc->sc_bus, &ehci_iterate_hw_softc); 548 549 #ifdef USB_DEBUG 550 if (ehcidebug) { 551 ehci_dump_sqh(sc, sc->sc_async_p_last); 552 } 553 #endif 554 555 /* finial setup */ 556 err = ehci_init_sub(sc); 557 558 if (!err) { 559 /* catch any lost interrupts */ 560 ehci_do_poll(&sc->sc_bus); 561 } 562 return (err); 563 } 564 565 /* 566 * shut down the controller when the system is going down 567 */ 568 void 569 ehci_detach(ehci_softc_t *sc) 570 { 571 USB_BUS_LOCK(&sc->sc_bus); 572 573 usb_callout_stop(&sc->sc_tmo_pcd); 574 usb_callout_stop(&sc->sc_tmo_poll); 575 576 EOWRITE4(sc, EHCI_USBINTR, 0); 577 USB_BUS_UNLOCK(&sc->sc_bus); 578 579 if (ehci_hcreset(sc)) { 580 DPRINTF("reset failed!\n"); 581 } 582 583 /* XXX let stray task complete */ 584 usb_pause_mtx(NULL, hz / 20); 585 586 usb_callout_drain(&sc->sc_tmo_pcd); 587 usb_callout_drain(&sc->sc_tmo_poll); 588 } 589 590 static void 591 ehci_suspend(ehci_softc_t *sc) 592 { 593 DPRINTF("stopping the HC\n"); 594 595 /* reset HC */ 596 ehci_hcreset(sc); 597 } 598 599 static void 600 ehci_resume(ehci_softc_t *sc) 601 { 602 /* reset HC */ 603 ehci_hcreset(sc); 604 605 /* setup HC */ 606 ehci_init_sub(sc); 607 608 /* catch any lost interrupts */ 609 ehci_do_poll(&sc->sc_bus); 610 } 611 612 #ifdef USB_DEBUG 613 static void 614 ehci_dump_regs(ehci_softc_t *sc) 615 { 616 uint32_t i; 617 618 i = EOREAD4(sc, EHCI_USBCMD); 619 printf("cmd=0x%08x\n", i); 620 621 if (i & EHCI_CMD_ITC_1) 622 printf(" EHCI_CMD_ITC_1\n"); 623 if (i & EHCI_CMD_ITC_2) 624 printf(" EHCI_CMD_ITC_2\n"); 625 if (i & EHCI_CMD_ITC_4) 626 printf(" EHCI_CMD_ITC_4\n"); 627 if (i & EHCI_CMD_ITC_8) 628 printf(" EHCI_CMD_ITC_8\n"); 629 if (i & EHCI_CMD_ITC_16) 630 printf(" EHCI_CMD_ITC_16\n"); 631 if (i & EHCI_CMD_ITC_32) 632 printf(" EHCI_CMD_ITC_32\n"); 633 if (i & EHCI_CMD_ITC_64) 634 printf(" EHCI_CMD_ITC_64\n"); 635 if (i & EHCI_CMD_ASPME) 636 printf(" EHCI_CMD_ASPME\n"); 637 if (i & EHCI_CMD_ASPMC) 638 printf(" EHCI_CMD_ASPMC\n"); 639 if (i & EHCI_CMD_LHCR) 640 printf(" EHCI_CMD_LHCR\n"); 641 if (i & EHCI_CMD_IAAD) 642 printf(" EHCI_CMD_IAAD\n"); 643 if (i & EHCI_CMD_ASE) 644 printf(" EHCI_CMD_ASE\n"); 645 if (i & EHCI_CMD_PSE) 646 printf(" EHCI_CMD_PSE\n"); 647 if (i & EHCI_CMD_FLS_M) 648 printf(" EHCI_CMD_FLS_M\n"); 649 if (i & EHCI_CMD_HCRESET) 650 printf(" EHCI_CMD_HCRESET\n"); 651 if (i & EHCI_CMD_RS) 652 printf(" EHCI_CMD_RS\n"); 653 654 i = EOREAD4(sc, EHCI_USBSTS); 655 656 printf("sts=0x%08x\n", i); 657 658 if (i & EHCI_STS_ASS) 659 printf(" EHCI_STS_ASS\n"); 660 if (i & EHCI_STS_PSS) 661 printf(" EHCI_STS_PSS\n"); 662 if (i & EHCI_STS_REC) 663 printf(" EHCI_STS_REC\n"); 664 if (i & EHCI_STS_HCH) 665 printf(" EHCI_STS_HCH\n"); 666 if (i & EHCI_STS_IAA) 667 printf(" EHCI_STS_IAA\n"); 668 if (i & EHCI_STS_HSE) 669 printf(" EHCI_STS_HSE\n"); 670 if (i & EHCI_STS_FLR) 671 printf(" EHCI_STS_FLR\n"); 672 if (i & EHCI_STS_PCD) 673 printf(" EHCI_STS_PCD\n"); 674 if (i & EHCI_STS_ERRINT) 675 printf(" EHCI_STS_ERRINT\n"); 676 if (i & EHCI_STS_INT) 677 printf(" EHCI_STS_INT\n"); 678 679 printf("ien=0x%08x\n", 680 EOREAD4(sc, EHCI_USBINTR)); 681 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 682 EOREAD4(sc, EHCI_FRINDEX), 683 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 684 EOREAD4(sc, EHCI_PERIODICLISTBASE), 685 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 686 for (i = 1; i <= sc->sc_noport; i++) { 687 printf("port %d status=0x%08x\n", i, 688 EOREAD4(sc, EHCI_PORTSC(i))); 689 } 690 } 691 692 static void 693 ehci_dump_link(ehci_softc_t *sc, uint32_t link, int type) 694 { 695 link = hc32toh(sc, link); 696 printf("0x%08x", link); 697 if (link & EHCI_LINK_TERMINATE) 698 printf("<T>"); 699 else { 700 printf("<"); 701 if (type) { 702 switch (EHCI_LINK_TYPE(link)) { 703 case EHCI_LINK_ITD: 704 printf("ITD"); 705 break; 706 case EHCI_LINK_QH: 707 printf("QH"); 708 break; 709 case EHCI_LINK_SITD: 710 printf("SITD"); 711 break; 712 case EHCI_LINK_FSTN: 713 printf("FSTN"); 714 break; 715 } 716 } 717 printf(">"); 718 } 719 } 720 721 static void 722 ehci_dump_qtd(ehci_softc_t *sc, ehci_qtd_t *qtd) 723 { 724 uint32_t s; 725 726 printf(" next="); 727 ehci_dump_link(sc, qtd->qtd_next, 0); 728 printf(" altnext="); 729 ehci_dump_link(sc, qtd->qtd_altnext, 0); 730 printf("\n"); 731 s = hc32toh(sc, qtd->qtd_status); 732 printf(" status=0x%08x: toggle=%d bytes=0x%x ioc=%d c_page=0x%x\n", 733 s, EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_BYTES(s), 734 EHCI_QTD_GET_IOC(s), EHCI_QTD_GET_C_PAGE(s)); 735 printf(" cerr=%d pid=%d stat=%s%s%s%s%s%s%s%s\n", 736 EHCI_QTD_GET_CERR(s), EHCI_QTD_GET_PID(s), 737 (s & EHCI_QTD_ACTIVE) ? "ACTIVE" : "NOT_ACTIVE", 738 (s & EHCI_QTD_HALTED) ? "-HALTED" : "", 739 (s & EHCI_QTD_BUFERR) ? "-BUFERR" : "", 740 (s & EHCI_QTD_BABBLE) ? "-BABBLE" : "", 741 (s & EHCI_QTD_XACTERR) ? "-XACTERR" : "", 742 (s & EHCI_QTD_MISSEDMICRO) ? "-MISSED" : "", 743 (s & EHCI_QTD_SPLITXSTATE) ? "-SPLIT" : "", 744 (s & EHCI_QTD_PINGSTATE) ? "-PING" : ""); 745 746 for (s = 0; s < 5; s++) { 747 printf(" buffer[%d]=0x%08x\n", s, 748 hc32toh(sc, qtd->qtd_buffer[s])); 749 } 750 for (s = 0; s < 5; s++) { 751 printf(" buffer_hi[%d]=0x%08x\n", s, 752 hc32toh(sc, qtd->qtd_buffer_hi[s])); 753 } 754 } 755 756 static uint8_t 757 ehci_dump_sqtd(ehci_softc_t *sc, ehci_qtd_t *sqtd) 758 { 759 uint8_t temp; 760 761 usb_pc_cpu_invalidate(sqtd->page_cache); 762 printf("QTD(%p) at 0x%08x:\n", sqtd, hc32toh(sc, sqtd->qtd_self)); 763 ehci_dump_qtd(sc, sqtd); 764 temp = (sqtd->qtd_next & htohc32(sc, EHCI_LINK_TERMINATE)) ? 1 : 0; 765 return (temp); 766 } 767 768 static void 769 ehci_dump_sqtds(ehci_softc_t *sc, ehci_qtd_t *sqtd) 770 { 771 uint16_t i; 772 uint8_t stop; 773 774 stop = 0; 775 for (i = 0; sqtd && (i < 20) && !stop; sqtd = sqtd->obj_next, i++) { 776 stop = ehci_dump_sqtd(sc, sqtd); 777 } 778 if (sqtd) { 779 printf("dump aborted, too many TDs\n"); 780 } 781 } 782 783 static void 784 ehci_dump_sqh(ehci_softc_t *sc, ehci_qh_t *qh) 785 { 786 uint32_t endp; 787 uint32_t endphub; 788 789 usb_pc_cpu_invalidate(qh->page_cache); 790 printf("QH(%p) at 0x%08x:\n", qh, hc32toh(sc, qh->qh_self) & ~0x1F); 791 printf(" link="); 792 ehci_dump_link(sc, qh->qh_link, 1); 793 printf("\n"); 794 endp = hc32toh(sc, qh->qh_endp); 795 printf(" endp=0x%08x\n", endp); 796 printf(" addr=0x%02x inact=%d endpt=%d eps=%d dtc=%d hrecl=%d\n", 797 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 798 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp), 799 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp)); 800 printf(" mpl=0x%x ctl=%d nrl=%d\n", 801 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_CTL(endp), 802 EHCI_QH_GET_NRL(endp)); 803 endphub = hc32toh(sc, qh->qh_endphub); 804 printf(" endphub=0x%08x\n", endphub); 805 printf(" smask=0x%02x cmask=0x%02x huba=0x%02x port=%d mult=%d\n", 806 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 807 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 808 EHCI_QH_GET_MULT(endphub)); 809 printf(" curqtd="); 810 ehci_dump_link(sc, qh->qh_curqtd, 0); 811 printf("\n"); 812 printf("Overlay qTD:\n"); 813 ehci_dump_qtd(sc, (void *)&qh->qh_qtd); 814 } 815 816 static void 817 ehci_dump_sitd(ehci_softc_t *sc, ehci_sitd_t *sitd) 818 { 819 usb_pc_cpu_invalidate(sitd->page_cache); 820 printf("SITD(%p) at 0x%08x\n", sitd, hc32toh(sc, sitd->sitd_self) & ~0x1F); 821 printf(" next=0x%08x\n", hc32toh(sc, sitd->sitd_next)); 822 printf(" portaddr=0x%08x dir=%s addr=%d endpt=0x%x port=0x%x huba=0x%x\n", 823 hc32toh(sc, sitd->sitd_portaddr), 824 (sitd->sitd_portaddr & htohc32(sc, EHCI_SITD_SET_DIR_IN)) 825 ? "in" : "out", 826 EHCI_SITD_GET_ADDR(hc32toh(sc, sitd->sitd_portaddr)), 827 EHCI_SITD_GET_ENDPT(hc32toh(sc, sitd->sitd_portaddr)), 828 EHCI_SITD_GET_PORT(hc32toh(sc, sitd->sitd_portaddr)), 829 EHCI_SITD_GET_HUBA(hc32toh(sc, sitd->sitd_portaddr))); 830 printf(" mask=0x%08x\n", hc32toh(sc, sitd->sitd_mask)); 831 printf(" status=0x%08x <%s> len=0x%x\n", hc32toh(sc, sitd->sitd_status), 832 (sitd->sitd_status & htohc32(sc, EHCI_SITD_ACTIVE)) ? "ACTIVE" : "", 833 EHCI_SITD_GET_LEN(hc32toh(sc, sitd->sitd_status))); 834 printf(" back=0x%08x, bp=0x%08x,0x%08x,0x%08x,0x%08x\n", 835 hc32toh(sc, sitd->sitd_back), 836 hc32toh(sc, sitd->sitd_bp[0]), 837 hc32toh(sc, sitd->sitd_bp[1]), 838 hc32toh(sc, sitd->sitd_bp_hi[0]), 839 hc32toh(sc, sitd->sitd_bp_hi[1])); 840 } 841 842 static void 843 ehci_dump_itd(ehci_softc_t *sc, ehci_itd_t *itd) 844 { 845 usb_pc_cpu_invalidate(itd->page_cache); 846 printf("ITD(%p) at 0x%08x\n", itd, hc32toh(sc, itd->itd_self) & ~0x1F); 847 printf(" next=0x%08x\n", hc32toh(sc, itd->itd_next)); 848 printf(" status[0]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[0]), 849 (itd->itd_status[0] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 850 printf(" status[1]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[1]), 851 (itd->itd_status[1] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 852 printf(" status[2]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[2]), 853 (itd->itd_status[2] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 854 printf(" status[3]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[3]), 855 (itd->itd_status[3] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 856 printf(" status[4]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[4]), 857 (itd->itd_status[4] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 858 printf(" status[5]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[5]), 859 (itd->itd_status[5] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 860 printf(" status[6]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[6]), 861 (itd->itd_status[6] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 862 printf(" status[7]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[7]), 863 (itd->itd_status[7] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 864 printf(" bp[0]=0x%08x\n", hc32toh(sc, itd->itd_bp[0])); 865 printf(" addr=0x%02x; endpt=0x%01x\n", 866 EHCI_ITD_GET_ADDR(hc32toh(sc, itd->itd_bp[0])), 867 EHCI_ITD_GET_ENDPT(hc32toh(sc, itd->itd_bp[0]))); 868 printf(" bp[1]=0x%08x\n", hc32toh(sc, itd->itd_bp[1])); 869 printf(" dir=%s; mpl=0x%02x\n", 870 (hc32toh(sc, itd->itd_bp[1]) & EHCI_ITD_SET_DIR_IN) ? "in" : "out", 871 EHCI_ITD_GET_MPL(hc32toh(sc, itd->itd_bp[1]))); 872 printf(" bp[2..6]=0x%08x,0x%08x,0x%08x,0x%08x,0x%08x\n", 873 hc32toh(sc, itd->itd_bp[2]), 874 hc32toh(sc, itd->itd_bp[3]), 875 hc32toh(sc, itd->itd_bp[4]), 876 hc32toh(sc, itd->itd_bp[5]), 877 hc32toh(sc, itd->itd_bp[6])); 878 printf(" bp_hi=0x%08x,0x%08x,0x%08x,0x%08x,\n" 879 " 0x%08x,0x%08x,0x%08x\n", 880 hc32toh(sc, itd->itd_bp_hi[0]), 881 hc32toh(sc, itd->itd_bp_hi[1]), 882 hc32toh(sc, itd->itd_bp_hi[2]), 883 hc32toh(sc, itd->itd_bp_hi[3]), 884 hc32toh(sc, itd->itd_bp_hi[4]), 885 hc32toh(sc, itd->itd_bp_hi[5]), 886 hc32toh(sc, itd->itd_bp_hi[6])); 887 } 888 889 static void 890 ehci_dump_isoc(ehci_softc_t *sc) 891 { 892 ehci_itd_t *itd; 893 ehci_sitd_t *sitd; 894 uint16_t max = 1000; 895 uint16_t pos; 896 897 pos = (EOREAD4(sc, EHCI_FRINDEX) / 8) & 898 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 899 900 printf("%s: isochronous dump from frame 0x%03x:\n", 901 __FUNCTION__, pos); 902 903 itd = sc->sc_isoc_hs_p_last[pos]; 904 sitd = sc->sc_isoc_fs_p_last[pos]; 905 906 while (itd && max && max--) { 907 ehci_dump_itd(sc, itd); 908 itd = itd->prev; 909 } 910 911 while (sitd && max && max--) { 912 ehci_dump_sitd(sc, sitd); 913 sitd = sitd->prev; 914 } 915 } 916 917 #endif 918 919 static void 920 ehci_transfer_intr_enqueue(struct usb_xfer *xfer) 921 { 922 /* check for early completion */ 923 if (ehci_check_transfer(xfer)) { 924 return; 925 } 926 /* put transfer on interrupt queue */ 927 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 928 929 /* start timeout, if any */ 930 if (xfer->timeout != 0) { 931 usbd_transfer_timeout_ms(xfer, &ehci_timeout, xfer->timeout); 932 } 933 } 934 935 #define EHCI_APPEND_FS_TD(std,last) (last) = _ehci_append_fs_td(std,last) 936 static ehci_sitd_t * 937 _ehci_append_fs_td(ehci_sitd_t *std, ehci_sitd_t *last) 938 { 939 DPRINTFN(11, "%p to %p\n", std, last); 940 941 /* (sc->sc_bus.mtx) must be locked */ 942 943 std->next = last->next; 944 std->sitd_next = last->sitd_next; 945 946 std->prev = last; 947 948 usb_pc_cpu_flush(std->page_cache); 949 950 /* 951 * the last->next->prev is never followed: std->next->prev = std; 952 */ 953 last->next = std; 954 last->sitd_next = std->sitd_self; 955 956 usb_pc_cpu_flush(last->page_cache); 957 958 return (std); 959 } 960 961 #define EHCI_APPEND_HS_TD(std,last) (last) = _ehci_append_hs_td(std,last) 962 static ehci_itd_t * 963 _ehci_append_hs_td(ehci_itd_t *std, ehci_itd_t *last) 964 { 965 DPRINTFN(11, "%p to %p\n", std, last); 966 967 /* (sc->sc_bus.mtx) must be locked */ 968 969 std->next = last->next; 970 std->itd_next = last->itd_next; 971 972 std->prev = last; 973 974 usb_pc_cpu_flush(std->page_cache); 975 976 /* 977 * the last->next->prev is never followed: std->next->prev = std; 978 */ 979 last->next = std; 980 last->itd_next = std->itd_self; 981 982 usb_pc_cpu_flush(last->page_cache); 983 984 return (std); 985 } 986 987 #define EHCI_APPEND_QH(sqh,last) (last) = _ehci_append_qh(sqh,last) 988 static ehci_qh_t * 989 _ehci_append_qh(ehci_qh_t *sqh, ehci_qh_t *last) 990 { 991 DPRINTFN(11, "%p to %p\n", sqh, last); 992 993 if (sqh->prev != NULL) { 994 /* should not happen */ 995 DPRINTFN(0, "QH already linked!\n"); 996 return (last); 997 } 998 /* (sc->sc_bus.mtx) must be locked */ 999 1000 sqh->next = last->next; 1001 sqh->qh_link = last->qh_link; 1002 1003 sqh->prev = last; 1004 1005 usb_pc_cpu_flush(sqh->page_cache); 1006 1007 /* 1008 * the last->next->prev is never followed: sqh->next->prev = sqh; 1009 */ 1010 1011 last->next = sqh; 1012 last->qh_link = sqh->qh_self; 1013 1014 usb_pc_cpu_flush(last->page_cache); 1015 1016 return (sqh); 1017 } 1018 1019 #define EHCI_REMOVE_FS_TD(std,last) (last) = _ehci_remove_fs_td(std,last) 1020 static ehci_sitd_t * 1021 _ehci_remove_fs_td(ehci_sitd_t *std, ehci_sitd_t *last) 1022 { 1023 DPRINTFN(11, "%p from %p\n", std, last); 1024 1025 /* (sc->sc_bus.mtx) must be locked */ 1026 1027 std->prev->next = std->next; 1028 std->prev->sitd_next = std->sitd_next; 1029 1030 usb_pc_cpu_flush(std->prev->page_cache); 1031 1032 if (std->next) { 1033 std->next->prev = std->prev; 1034 usb_pc_cpu_flush(std->next->page_cache); 1035 } 1036 return ((last == std) ? std->prev : last); 1037 } 1038 1039 #define EHCI_REMOVE_HS_TD(std,last) (last) = _ehci_remove_hs_td(std,last) 1040 static ehci_itd_t * 1041 _ehci_remove_hs_td(ehci_itd_t *std, ehci_itd_t *last) 1042 { 1043 DPRINTFN(11, "%p from %p\n", std, last); 1044 1045 /* (sc->sc_bus.mtx) must be locked */ 1046 1047 std->prev->next = std->next; 1048 std->prev->itd_next = std->itd_next; 1049 1050 usb_pc_cpu_flush(std->prev->page_cache); 1051 1052 if (std->next) { 1053 std->next->prev = std->prev; 1054 usb_pc_cpu_flush(std->next->page_cache); 1055 } 1056 return ((last == std) ? std->prev : last); 1057 } 1058 1059 #define EHCI_REMOVE_QH(sqh,last) (last) = _ehci_remove_qh(sqh,last) 1060 static ehci_qh_t * 1061 _ehci_remove_qh(ehci_qh_t *sqh, ehci_qh_t *last) 1062 { 1063 DPRINTFN(11, "%p from %p\n", sqh, last); 1064 1065 /* (sc->sc_bus.mtx) must be locked */ 1066 1067 /* only remove if not removed from a queue */ 1068 if (sqh->prev) { 1069 1070 sqh->prev->next = sqh->next; 1071 sqh->prev->qh_link = sqh->qh_link; 1072 1073 usb_pc_cpu_flush(sqh->prev->page_cache); 1074 1075 if (sqh->next) { 1076 sqh->next->prev = sqh->prev; 1077 usb_pc_cpu_flush(sqh->next->page_cache); 1078 } 1079 last = ((last == sqh) ? sqh->prev : last); 1080 1081 sqh->prev = 0; 1082 1083 usb_pc_cpu_flush(sqh->page_cache); 1084 } 1085 return (last); 1086 } 1087 1088 static void 1089 ehci_data_toggle_update(struct usb_xfer *xfer, uint16_t actlen, uint16_t xlen) 1090 { 1091 uint16_t rem; 1092 uint8_t dt; 1093 1094 /* count number of full packets */ 1095 dt = (actlen / xfer->max_packet_size) & 1; 1096 1097 /* compute remainder */ 1098 rem = actlen % xfer->max_packet_size; 1099 1100 if (rem > 0) 1101 dt ^= 1; /* short packet at the end */ 1102 else if (actlen != xlen) 1103 dt ^= 1; /* zero length packet at the end */ 1104 else if (xlen == 0) 1105 dt ^= 1; /* zero length transfer */ 1106 1107 xfer->endpoint->toggle_next ^= dt; 1108 } 1109 1110 static usb_error_t 1111 ehci_non_isoc_done_sub(struct usb_xfer *xfer) 1112 { 1113 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 1114 ehci_qtd_t *td; 1115 ehci_qtd_t *td_alt_next; 1116 uint32_t status; 1117 uint16_t len; 1118 1119 td = xfer->td_transfer_cache; 1120 td_alt_next = td->alt_next; 1121 1122 if (xfer->aframes != xfer->nframes) { 1123 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0); 1124 } 1125 while (1) { 1126 1127 usb_pc_cpu_invalidate(td->page_cache); 1128 status = hc32toh(sc, td->qtd_status); 1129 1130 len = EHCI_QTD_GET_BYTES(status); 1131 1132 /* 1133 * Verify the status length and 1134 * add the length to "frlengths[]": 1135 */ 1136 if (len > td->len) { 1137 /* should not happen */ 1138 DPRINTF("Invalid status length, " 1139 "0x%04x/0x%04x bytes\n", len, td->len); 1140 status |= EHCI_QTD_HALTED; 1141 } else if (xfer->aframes != xfer->nframes) { 1142 xfer->frlengths[xfer->aframes] += td->len - len; 1143 /* manually update data toggle */ 1144 ehci_data_toggle_update(xfer, td->len - len, td->len); 1145 } 1146 1147 /* Check for last transfer */ 1148 if (((void *)td) == xfer->td_transfer_last) { 1149 td = NULL; 1150 break; 1151 } 1152 /* Check for transfer error */ 1153 if (status & EHCI_QTD_HALTED) { 1154 /* the transfer is finished */ 1155 td = NULL; 1156 break; 1157 } 1158 /* Check for short transfer */ 1159 if (len > 0) { 1160 if (xfer->flags_int.short_frames_ok) { 1161 /* follow alt next */ 1162 td = td->alt_next; 1163 } else { 1164 /* the transfer is finished */ 1165 td = NULL; 1166 } 1167 break; 1168 } 1169 td = td->obj_next; 1170 1171 if (td->alt_next != td_alt_next) { 1172 /* this USB frame is complete */ 1173 break; 1174 } 1175 } 1176 1177 /* update transfer cache */ 1178 1179 xfer->td_transfer_cache = td; 1180 1181 #ifdef USB_DEBUG 1182 if (status & EHCI_QTD_STATERRS) { 1183 DPRINTFN(11, "error, addr=%d, endpt=0x%02x, frame=0x%02x" 1184 "status=%s%s%s%s%s%s%s%s\n", 1185 xfer->address, xfer->endpointno, xfer->aframes, 1186 (status & EHCI_QTD_ACTIVE) ? "[ACTIVE]" : "[NOT_ACTIVE]", 1187 (status & EHCI_QTD_HALTED) ? "[HALTED]" : "", 1188 (status & EHCI_QTD_BUFERR) ? "[BUFERR]" : "", 1189 (status & EHCI_QTD_BABBLE) ? "[BABBLE]" : "", 1190 (status & EHCI_QTD_XACTERR) ? "[XACTERR]" : "", 1191 (status & EHCI_QTD_MISSEDMICRO) ? "[MISSED]" : "", 1192 (status & EHCI_QTD_SPLITXSTATE) ? "[SPLIT]" : "", 1193 (status & EHCI_QTD_PINGSTATE) ? "[PING]" : ""); 1194 } 1195 #endif 1196 if (status & EHCI_QTD_HALTED) { 1197 if ((xfer->xroot->udev->parent_hs_hub != NULL) || 1198 (xfer->xroot->udev->address != 0)) { 1199 /* try to separate I/O errors from STALL */ 1200 if (EHCI_QTD_GET_CERR(status) == 0) 1201 return (USB_ERR_IOERROR); 1202 } 1203 return (USB_ERR_STALLED); 1204 } 1205 return (USB_ERR_NORMAL_COMPLETION); 1206 } 1207 1208 static void 1209 ehci_non_isoc_done(struct usb_xfer *xfer) 1210 { 1211 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 1212 ehci_qh_t *qh; 1213 uint32_t status; 1214 usb_error_t err = 0; 1215 1216 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 1217 xfer, xfer->endpoint); 1218 1219 #ifdef USB_DEBUG 1220 if (ehcidebug > 10) { 1221 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 1222 1223 ehci_dump_sqtds(sc, xfer->td_transfer_first); 1224 } 1225 #endif 1226 1227 /* extract data toggle directly from the QH's overlay area */ 1228 1229 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1230 1231 usb_pc_cpu_invalidate(qh->page_cache); 1232 1233 status = hc32toh(sc, qh->qh_qtd.qtd_status); 1234 1235 /* reset scanner */ 1236 1237 xfer->td_transfer_cache = xfer->td_transfer_first; 1238 1239 if (xfer->flags_int.control_xfr) { 1240 1241 if (xfer->flags_int.control_hdr) { 1242 1243 err = ehci_non_isoc_done_sub(xfer); 1244 } 1245 xfer->aframes = 1; 1246 1247 if (xfer->td_transfer_cache == NULL) { 1248 goto done; 1249 } 1250 } 1251 while (xfer->aframes != xfer->nframes) { 1252 1253 err = ehci_non_isoc_done_sub(xfer); 1254 xfer->aframes++; 1255 1256 if (xfer->td_transfer_cache == NULL) { 1257 goto done; 1258 } 1259 } 1260 1261 if (xfer->flags_int.control_xfr && 1262 !xfer->flags_int.control_act) { 1263 1264 err = ehci_non_isoc_done_sub(xfer); 1265 } 1266 done: 1267 ehci_device_done(xfer, err); 1268 } 1269 1270 /*------------------------------------------------------------------------* 1271 * ehci_check_transfer 1272 * 1273 * Return values: 1274 * 0: USB transfer is not finished 1275 * Else: USB transfer is finished 1276 *------------------------------------------------------------------------*/ 1277 static uint8_t 1278 ehci_check_transfer(struct usb_xfer *xfer) 1279 { 1280 const struct usb_pipe_methods *methods = xfer->endpoint->methods; 1281 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 1282 1283 uint32_t status; 1284 1285 DPRINTFN(13, "xfer=%p checking transfer\n", xfer); 1286 1287 if (methods == &ehci_device_isoc_fs_methods) { 1288 ehci_sitd_t *td; 1289 1290 /* isochronous full speed transfer */ 1291 1292 td = xfer->td_transfer_last; 1293 usb_pc_cpu_invalidate(td->page_cache); 1294 status = hc32toh(sc, td->sitd_status); 1295 1296 /* also check if first is complete */ 1297 1298 td = xfer->td_transfer_first; 1299 usb_pc_cpu_invalidate(td->page_cache); 1300 status |= hc32toh(sc, td->sitd_status); 1301 1302 if (!(status & EHCI_SITD_ACTIVE)) { 1303 ehci_device_done(xfer, USB_ERR_NORMAL_COMPLETION); 1304 goto transferred; 1305 } 1306 } else if (methods == &ehci_device_isoc_hs_methods) { 1307 ehci_itd_t *td; 1308 1309 /* isochronous high speed transfer */ 1310 1311 /* check last transfer */ 1312 td = xfer->td_transfer_last; 1313 usb_pc_cpu_invalidate(td->page_cache); 1314 status = td->itd_status[0]; 1315 status |= td->itd_status[1]; 1316 status |= td->itd_status[2]; 1317 status |= td->itd_status[3]; 1318 status |= td->itd_status[4]; 1319 status |= td->itd_status[5]; 1320 status |= td->itd_status[6]; 1321 status |= td->itd_status[7]; 1322 1323 /* also check first transfer */ 1324 td = xfer->td_transfer_first; 1325 usb_pc_cpu_invalidate(td->page_cache); 1326 status |= td->itd_status[0]; 1327 status |= td->itd_status[1]; 1328 status |= td->itd_status[2]; 1329 status |= td->itd_status[3]; 1330 status |= td->itd_status[4]; 1331 status |= td->itd_status[5]; 1332 status |= td->itd_status[6]; 1333 status |= td->itd_status[7]; 1334 1335 /* if no transactions are active we continue */ 1336 if (!(status & htohc32(sc, EHCI_ITD_ACTIVE))) { 1337 ehci_device_done(xfer, USB_ERR_NORMAL_COMPLETION); 1338 goto transferred; 1339 } 1340 } else { 1341 ehci_qtd_t *td; 1342 ehci_qh_t *qh; 1343 1344 /* non-isochronous transfer */ 1345 1346 /* 1347 * check whether there is an error somewhere in the middle, 1348 * or whether there was a short packet (SPD and not ACTIVE) 1349 */ 1350 td = xfer->td_transfer_cache; 1351 1352 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1353 1354 usb_pc_cpu_invalidate(qh->page_cache); 1355 1356 status = hc32toh(sc, qh->qh_qtd.qtd_status); 1357 if (status & EHCI_QTD_ACTIVE) { 1358 /* transfer is pending */ 1359 goto done; 1360 } 1361 1362 while (1) { 1363 usb_pc_cpu_invalidate(td->page_cache); 1364 status = hc32toh(sc, td->qtd_status); 1365 1366 /* 1367 * Check if there is an active TD which 1368 * indicates that the transfer isn't done. 1369 */ 1370 if (status & EHCI_QTD_ACTIVE) { 1371 /* update cache */ 1372 xfer->td_transfer_cache = td; 1373 goto done; 1374 } 1375 /* 1376 * last transfer descriptor makes the transfer done 1377 */ 1378 if (((void *)td) == xfer->td_transfer_last) { 1379 break; 1380 } 1381 /* 1382 * any kind of error makes the transfer done 1383 */ 1384 if (status & EHCI_QTD_HALTED) { 1385 break; 1386 } 1387 /* 1388 * if there is no alternate next transfer, a short 1389 * packet also makes the transfer done 1390 */ 1391 if (EHCI_QTD_GET_BYTES(status)) { 1392 if (xfer->flags_int.short_frames_ok) { 1393 /* follow alt next */ 1394 if (td->alt_next) { 1395 td = td->alt_next; 1396 continue; 1397 } 1398 } 1399 /* transfer is done */ 1400 break; 1401 } 1402 td = td->obj_next; 1403 } 1404 ehci_non_isoc_done(xfer); 1405 goto transferred; 1406 } 1407 1408 done: 1409 DPRINTFN(13, "xfer=%p is still active\n", xfer); 1410 return (0); 1411 1412 transferred: 1413 return (1); 1414 } 1415 1416 static void 1417 ehci_pcd_enable(ehci_softc_t *sc) 1418 { 1419 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1420 1421 sc->sc_eintrs |= EHCI_STS_PCD; 1422 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1423 1424 /* acknowledge any PCD interrupt */ 1425 EOWRITE4(sc, EHCI_USBSTS, EHCI_STS_PCD); 1426 1427 ehci_root_intr(sc); 1428 } 1429 1430 static void 1431 ehci_interrupt_poll(ehci_softc_t *sc) 1432 { 1433 struct usb_xfer *xfer; 1434 1435 repeat: 1436 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 1437 /* 1438 * check if transfer is transferred 1439 */ 1440 if (ehci_check_transfer(xfer)) { 1441 /* queue has been modified */ 1442 goto repeat; 1443 } 1444 } 1445 } 1446 1447 /* 1448 * Some EHCI chips from VIA / ATI seem to trigger interrupts before 1449 * writing back the qTD status, or miss signalling occasionally under 1450 * heavy load. If the host machine is too fast, we can miss 1451 * transaction completion - when we scan the active list the 1452 * transaction still seems to be active. This generally exhibits 1453 * itself as a umass stall that never recovers. 1454 * 1455 * We work around this behaviour by setting up this callback after any 1456 * softintr that completes with transactions still pending, giving us 1457 * another chance to check for completion after the writeback has 1458 * taken place. 1459 */ 1460 static void 1461 ehci_poll_timeout(void *arg) 1462 { 1463 ehci_softc_t *sc = arg; 1464 1465 DPRINTFN(3, "\n"); 1466 ehci_interrupt_poll(sc); 1467 } 1468 1469 /*------------------------------------------------------------------------* 1470 * ehci_interrupt - EHCI interrupt handler 1471 * 1472 * NOTE: Do not access "sc->sc_bus.bdev" inside the interrupt handler, 1473 * hence the interrupt handler will be setup before "sc->sc_bus.bdev" 1474 * is present ! 1475 *------------------------------------------------------------------------*/ 1476 void 1477 ehci_interrupt(ehci_softc_t *sc) 1478 { 1479 uint32_t status; 1480 1481 USB_BUS_LOCK(&sc->sc_bus); 1482 1483 DPRINTFN(16, "real interrupt\n"); 1484 1485 #ifdef USB_DEBUG 1486 if (ehcidebug > 15) { 1487 ehci_dump_regs(sc); 1488 } 1489 #endif 1490 1491 status = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1492 if (status == 0) { 1493 /* the interrupt was not for us */ 1494 goto done; 1495 } 1496 if (!(status & sc->sc_eintrs)) { 1497 goto done; 1498 } 1499 EOWRITE4(sc, EHCI_USBSTS, status); /* acknowledge */ 1500 1501 status &= sc->sc_eintrs; 1502 1503 if (status & EHCI_STS_HSE) { 1504 printf("%s: unrecoverable error, " 1505 "controller halted\n", __FUNCTION__); 1506 #ifdef USB_DEBUG 1507 ehci_dump_regs(sc); 1508 ehci_dump_isoc(sc); 1509 #endif 1510 } 1511 if (status & EHCI_STS_PCD) { 1512 /* 1513 * Disable PCD interrupt for now, because it will be 1514 * on until the port has been reset. 1515 */ 1516 sc->sc_eintrs &= ~EHCI_STS_PCD; 1517 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1518 1519 ehci_root_intr(sc); 1520 1521 /* do not allow RHSC interrupts > 1 per second */ 1522 usb_callout_reset(&sc->sc_tmo_pcd, hz, 1523 (void *)&ehci_pcd_enable, sc); 1524 } 1525 status &= ~(EHCI_STS_INT | EHCI_STS_ERRINT | EHCI_STS_PCD | EHCI_STS_IAA); 1526 1527 if (status != 0) { 1528 /* block unprocessed interrupts */ 1529 sc->sc_eintrs &= ~status; 1530 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1531 printf("%s: blocking interrupts 0x%x\n", __FUNCTION__, status); 1532 } 1533 /* poll all the USB transfers */ 1534 ehci_interrupt_poll(sc); 1535 1536 if (sc->sc_flags & EHCI_SCFLG_LOSTINTRBUG) { 1537 usb_callout_reset(&sc->sc_tmo_poll, hz / 128, 1538 (void *)&ehci_poll_timeout, sc); 1539 } 1540 1541 done: 1542 USB_BUS_UNLOCK(&sc->sc_bus); 1543 } 1544 1545 /* 1546 * called when a request does not complete 1547 */ 1548 static void 1549 ehci_timeout(void *arg) 1550 { 1551 struct usb_xfer *xfer = arg; 1552 1553 DPRINTF("xfer=%p\n", xfer); 1554 1555 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1556 1557 /* transfer is transferred */ 1558 ehci_device_done(xfer, USB_ERR_TIMEOUT); 1559 } 1560 1561 static void 1562 ehci_do_poll(struct usb_bus *bus) 1563 { 1564 ehci_softc_t *sc = EHCI_BUS2SC(bus); 1565 1566 USB_BUS_LOCK(&sc->sc_bus); 1567 ehci_interrupt_poll(sc); 1568 USB_BUS_UNLOCK(&sc->sc_bus); 1569 } 1570 1571 static void 1572 ehci_setup_standard_chain_sub(struct ehci_std_temp *temp) 1573 { 1574 struct usb_page_search buf_res; 1575 ehci_qtd_t *td; 1576 ehci_qtd_t *td_next; 1577 ehci_qtd_t *td_alt_next; 1578 uint32_t buf_offset; 1579 uint32_t average; 1580 uint32_t len_old; 1581 uint32_t terminate; 1582 uint32_t qtd_altnext; 1583 uint8_t shortpkt_old; 1584 uint8_t precompute; 1585 1586 terminate = temp->sc->sc_terminate_self; 1587 qtd_altnext = temp->sc->sc_terminate_self; 1588 td_alt_next = NULL; 1589 buf_offset = 0; 1590 shortpkt_old = temp->shortpkt; 1591 len_old = temp->len; 1592 precompute = 1; 1593 1594 restart: 1595 1596 td = temp->td; 1597 td_next = temp->td_next; 1598 1599 while (1) { 1600 1601 if (temp->len == 0) { 1602 1603 if (temp->shortpkt) { 1604 break; 1605 } 1606 /* send a Zero Length Packet, ZLP, last */ 1607 1608 temp->shortpkt = 1; 1609 average = 0; 1610 1611 } else { 1612 1613 average = temp->average; 1614 1615 if (temp->len < average) { 1616 if (temp->len % temp->max_frame_size) { 1617 temp->shortpkt = 1; 1618 } 1619 average = temp->len; 1620 } 1621 } 1622 1623 if (td_next == NULL) { 1624 panic("%s: out of EHCI transfer descriptors!", __FUNCTION__); 1625 } 1626 /* get next TD */ 1627 1628 td = td_next; 1629 td_next = td->obj_next; 1630 1631 /* check if we are pre-computing */ 1632 1633 if (precompute) { 1634 1635 /* update remaining length */ 1636 1637 temp->len -= average; 1638 1639 continue; 1640 } 1641 /* fill out current TD */ 1642 1643 td->qtd_status = 1644 temp->qtd_status | 1645 htohc32(temp->sc, EHCI_QTD_IOC | 1646 EHCI_QTD_SET_BYTES(average)); 1647 1648 if (average == 0) { 1649 1650 if (temp->auto_data_toggle == 0) { 1651 1652 /* update data toggle, ZLP case */ 1653 1654 temp->qtd_status ^= 1655 htohc32(temp->sc, EHCI_QTD_TOGGLE_MASK); 1656 } 1657 td->len = 0; 1658 1659 /* properly reset reserved fields */ 1660 td->qtd_buffer[0] = 0; 1661 td->qtd_buffer[1] = 0; 1662 td->qtd_buffer[2] = 0; 1663 td->qtd_buffer[3] = 0; 1664 td->qtd_buffer[4] = 0; 1665 td->qtd_buffer_hi[0] = 0; 1666 td->qtd_buffer_hi[1] = 0; 1667 td->qtd_buffer_hi[2] = 0; 1668 td->qtd_buffer_hi[3] = 0; 1669 td->qtd_buffer_hi[4] = 0; 1670 } else { 1671 1672 uint8_t x; 1673 1674 if (temp->auto_data_toggle == 0) { 1675 1676 /* update data toggle */ 1677 1678 if (((average + temp->max_frame_size - 1) / 1679 temp->max_frame_size) & 1) { 1680 temp->qtd_status ^= 1681 htohc32(temp->sc, EHCI_QTD_TOGGLE_MASK); 1682 } 1683 } 1684 td->len = average; 1685 1686 /* update remaining length */ 1687 1688 temp->len -= average; 1689 1690 /* fill out buffer pointers */ 1691 1692 usbd_get_page(temp->pc, buf_offset, &buf_res); 1693 td->qtd_buffer[0] = 1694 htohc32(temp->sc, buf_res.physaddr); 1695 td->qtd_buffer_hi[0] = 0; 1696 1697 x = 1; 1698 1699 while (average > EHCI_PAGE_SIZE) { 1700 average -= EHCI_PAGE_SIZE; 1701 buf_offset += EHCI_PAGE_SIZE; 1702 usbd_get_page(temp->pc, buf_offset, &buf_res); 1703 td->qtd_buffer[x] = 1704 htohc32(temp->sc, 1705 buf_res.physaddr & (~0xFFF)); 1706 td->qtd_buffer_hi[x] = 0; 1707 x++; 1708 } 1709 1710 /* 1711 * NOTE: The "average" variable is never zero after 1712 * exiting the loop above ! 1713 * 1714 * NOTE: We have to subtract one from the offset to 1715 * ensure that we are computing the physical address 1716 * of a valid page ! 1717 */ 1718 buf_offset += average; 1719 usbd_get_page(temp->pc, buf_offset - 1, &buf_res); 1720 td->qtd_buffer[x] = 1721 htohc32(temp->sc, 1722 buf_res.physaddr & (~0xFFF)); 1723 td->qtd_buffer_hi[x] = 0; 1724 1725 /* properly reset reserved fields */ 1726 while (++x < EHCI_QTD_NBUFFERS) { 1727 td->qtd_buffer[x] = 0; 1728 td->qtd_buffer_hi[x] = 0; 1729 } 1730 } 1731 1732 if (td_next) { 1733 /* link the current TD with the next one */ 1734 td->qtd_next = td_next->qtd_self; 1735 } 1736 td->qtd_altnext = qtd_altnext; 1737 td->alt_next = td_alt_next; 1738 1739 usb_pc_cpu_flush(td->page_cache); 1740 } 1741 1742 if (precompute) { 1743 precompute = 0; 1744 1745 /* setup alt next pointer, if any */ 1746 if (temp->last_frame) { 1747 td_alt_next = NULL; 1748 qtd_altnext = terminate; 1749 } else { 1750 /* we use this field internally */ 1751 td_alt_next = td_next; 1752 if (temp->setup_alt_next) { 1753 qtd_altnext = td_next->qtd_self; 1754 } else { 1755 qtd_altnext = terminate; 1756 } 1757 } 1758 1759 /* restore */ 1760 temp->shortpkt = shortpkt_old; 1761 temp->len = len_old; 1762 goto restart; 1763 } 1764 temp->td = td; 1765 temp->td_next = td_next; 1766 } 1767 1768 static void 1769 ehci_setup_standard_chain(struct usb_xfer *xfer, ehci_qh_t **qh_last) 1770 { 1771 struct ehci_std_temp temp; 1772 const struct usb_pipe_methods *methods; 1773 ehci_qh_t *qh; 1774 ehci_qtd_t *td; 1775 uint32_t qh_endp; 1776 uint32_t qh_endphub; 1777 uint32_t x; 1778 1779 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 1780 xfer->address, UE_GET_ADDR(xfer->endpointno), 1781 xfer->sumlen, usbd_get_speed(xfer->xroot->udev)); 1782 1783 temp.average = xfer->max_hc_frame_size; 1784 temp.max_frame_size = xfer->max_frame_size; 1785 temp.sc = EHCI_BUS2SC(xfer->xroot->bus); 1786 1787 /* toggle the DMA set we are using */ 1788 xfer->flags_int.curr_dma_set ^= 1; 1789 1790 /* get next DMA set */ 1791 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 1792 1793 xfer->td_transfer_first = td; 1794 xfer->td_transfer_cache = td; 1795 1796 temp.td = NULL; 1797 temp.td_next = td; 1798 temp.qtd_status = 0; 1799 temp.last_frame = 0; 1800 temp.setup_alt_next = xfer->flags_int.short_frames_ok; 1801 1802 if (xfer->flags_int.control_xfr) { 1803 if (xfer->endpoint->toggle_next) { 1804 /* DATA1 is next */ 1805 temp.qtd_status |= 1806 htohc32(temp.sc, EHCI_QTD_SET_TOGGLE(1)); 1807 } 1808 temp.auto_data_toggle = 0; 1809 } else { 1810 temp.auto_data_toggle = 1; 1811 } 1812 1813 if ((xfer->xroot->udev->parent_hs_hub != NULL) || 1814 (xfer->xroot->udev->address != 0)) { 1815 /* max 3 retries */ 1816 temp.qtd_status |= 1817 htohc32(temp.sc, EHCI_QTD_SET_CERR(3)); 1818 } 1819 /* check if we should prepend a setup message */ 1820 1821 if (xfer->flags_int.control_xfr) { 1822 if (xfer->flags_int.control_hdr) { 1823 1824 xfer->endpoint->toggle_next = 0; 1825 1826 temp.qtd_status &= 1827 htohc32(temp.sc, EHCI_QTD_SET_CERR(3)); 1828 temp.qtd_status |= htohc32(temp.sc, 1829 EHCI_QTD_ACTIVE | 1830 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 1831 EHCI_QTD_SET_TOGGLE(0)); 1832 1833 temp.len = xfer->frlengths[0]; 1834 temp.pc = xfer->frbuffers + 0; 1835 temp.shortpkt = temp.len ? 1 : 0; 1836 /* check for last frame */ 1837 if (xfer->nframes == 1) { 1838 /* no STATUS stage yet, SETUP is last */ 1839 if (xfer->flags_int.control_act) { 1840 temp.last_frame = 1; 1841 temp.setup_alt_next = 0; 1842 } 1843 } 1844 ehci_setup_standard_chain_sub(&temp); 1845 } 1846 x = 1; 1847 } else { 1848 x = 0; 1849 } 1850 1851 while (x != xfer->nframes) { 1852 1853 /* DATA0 / DATA1 message */ 1854 1855 temp.len = xfer->frlengths[x]; 1856 temp.pc = xfer->frbuffers + x; 1857 1858 x++; 1859 1860 if (x == xfer->nframes) { 1861 if (xfer->flags_int.control_xfr) { 1862 /* no STATUS stage yet, DATA is last */ 1863 if (xfer->flags_int.control_act) { 1864 temp.last_frame = 1; 1865 temp.setup_alt_next = 0; 1866 } 1867 } else { 1868 temp.last_frame = 1; 1869 temp.setup_alt_next = 0; 1870 } 1871 } 1872 /* keep previous data toggle and error count */ 1873 1874 temp.qtd_status &= 1875 htohc32(temp.sc, EHCI_QTD_SET_CERR(3) | 1876 EHCI_QTD_SET_TOGGLE(1)); 1877 1878 if (temp.len == 0) { 1879 1880 /* make sure that we send an USB packet */ 1881 1882 temp.shortpkt = 0; 1883 1884 } else { 1885 1886 /* regular data transfer */ 1887 1888 temp.shortpkt = (xfer->flags.force_short_xfer) ? 0 : 1; 1889 } 1890 1891 /* set endpoint direction */ 1892 1893 temp.qtd_status |= 1894 (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) ? 1895 htohc32(temp.sc, EHCI_QTD_ACTIVE | 1896 EHCI_QTD_SET_PID(EHCI_QTD_PID_IN)) : 1897 htohc32(temp.sc, EHCI_QTD_ACTIVE | 1898 EHCI_QTD_SET_PID(EHCI_QTD_PID_OUT)); 1899 1900 ehci_setup_standard_chain_sub(&temp); 1901 } 1902 1903 /* check if we should append a status stage */ 1904 1905 if (xfer->flags_int.control_xfr && 1906 !xfer->flags_int.control_act) { 1907 1908 /* 1909 * Send a DATA1 message and invert the current endpoint 1910 * direction. 1911 */ 1912 1913 temp.qtd_status &= htohc32(temp.sc, EHCI_QTD_SET_CERR(3) | 1914 EHCI_QTD_SET_TOGGLE(1)); 1915 temp.qtd_status |= 1916 (UE_GET_DIR(xfer->endpointno) == UE_DIR_OUT) ? 1917 htohc32(temp.sc, EHCI_QTD_ACTIVE | 1918 EHCI_QTD_SET_PID(EHCI_QTD_PID_IN) | 1919 EHCI_QTD_SET_TOGGLE(1)) : 1920 htohc32(temp.sc, EHCI_QTD_ACTIVE | 1921 EHCI_QTD_SET_PID(EHCI_QTD_PID_OUT) | 1922 EHCI_QTD_SET_TOGGLE(1)); 1923 1924 temp.len = 0; 1925 temp.pc = NULL; 1926 temp.shortpkt = 0; 1927 temp.last_frame = 1; 1928 temp.setup_alt_next = 0; 1929 1930 ehci_setup_standard_chain_sub(&temp); 1931 } 1932 td = temp.td; 1933 1934 /* the last TD terminates the transfer: */ 1935 td->qtd_next = htohc32(temp.sc, EHCI_LINK_TERMINATE); 1936 td->qtd_altnext = htohc32(temp.sc, EHCI_LINK_TERMINATE); 1937 1938 usb_pc_cpu_flush(td->page_cache); 1939 1940 /* must have at least one frame! */ 1941 1942 xfer->td_transfer_last = td; 1943 1944 #ifdef USB_DEBUG 1945 if (ehcidebug > 8) { 1946 DPRINTF("nexttog=%d; data before transfer:\n", 1947 xfer->endpoint->toggle_next); 1948 ehci_dump_sqtds(temp.sc, 1949 xfer->td_transfer_first); 1950 } 1951 #endif 1952 1953 methods = xfer->endpoint->methods; 1954 1955 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1956 1957 /* the "qh_link" field is filled when the QH is added */ 1958 1959 qh_endp = 1960 (EHCI_QH_SET_ADDR(xfer->address) | 1961 EHCI_QH_SET_ENDPT(UE_GET_ADDR(xfer->endpointno)) | 1962 EHCI_QH_SET_MPL(xfer->max_packet_size)); 1963 1964 if (usbd_get_speed(xfer->xroot->udev) == USB_SPEED_HIGH) { 1965 qh_endp |= EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH); 1966 if (methods != &ehci_device_intr_methods) 1967 qh_endp |= EHCI_QH_SET_NRL(8); 1968 } else { 1969 1970 if (usbd_get_speed(xfer->xroot->udev) == USB_SPEED_FULL) { 1971 qh_endp |= EHCI_QH_SET_EPS(EHCI_QH_SPEED_FULL); 1972 } else { 1973 qh_endp |= EHCI_QH_SET_EPS(EHCI_QH_SPEED_LOW); 1974 } 1975 1976 if (methods == &ehci_device_ctrl_methods) { 1977 qh_endp |= EHCI_QH_CTL; 1978 } 1979 if (methods != &ehci_device_intr_methods) { 1980 /* Only try one time per microframe! */ 1981 qh_endp |= EHCI_QH_SET_NRL(1); 1982 } 1983 } 1984 1985 if (temp.auto_data_toggle == 0) { 1986 /* software computes the data toggle */ 1987 qh_endp |= EHCI_QH_DTC; 1988 } 1989 1990 qh->qh_endp = htohc32(temp.sc, qh_endp); 1991 1992 qh_endphub = 1993 (EHCI_QH_SET_MULT(xfer->max_packet_count & 3) | 1994 EHCI_QH_SET_CMASK(xfer->endpoint->usb_cmask) | 1995 EHCI_QH_SET_SMASK(xfer->endpoint->usb_smask) | 1996 EHCI_QH_SET_HUBA(xfer->xroot->udev->hs_hub_addr) | 1997 EHCI_QH_SET_PORT(xfer->xroot->udev->hs_port_no)); 1998 1999 qh->qh_endphub = htohc32(temp.sc, qh_endphub); 2000 qh->qh_curqtd = 0; 2001 2002 /* fill the overlay qTD */ 2003 2004 if (temp.auto_data_toggle && xfer->endpoint->toggle_next) { 2005 /* DATA1 is next */ 2006 qh->qh_qtd.qtd_status = htohc32(temp.sc, EHCI_QTD_SET_TOGGLE(1)); 2007 } else { 2008 qh->qh_qtd.qtd_status = 0; 2009 } 2010 2011 td = xfer->td_transfer_first; 2012 2013 qh->qh_qtd.qtd_next = td->qtd_self; 2014 qh->qh_qtd.qtd_altnext = 2015 htohc32(temp.sc, EHCI_LINK_TERMINATE); 2016 2017 /* properly reset reserved fields */ 2018 qh->qh_qtd.qtd_buffer[0] = 0; 2019 qh->qh_qtd.qtd_buffer[1] = 0; 2020 qh->qh_qtd.qtd_buffer[2] = 0; 2021 qh->qh_qtd.qtd_buffer[3] = 0; 2022 qh->qh_qtd.qtd_buffer[4] = 0; 2023 qh->qh_qtd.qtd_buffer_hi[0] = 0; 2024 qh->qh_qtd.qtd_buffer_hi[1] = 0; 2025 qh->qh_qtd.qtd_buffer_hi[2] = 0; 2026 qh->qh_qtd.qtd_buffer_hi[3] = 0; 2027 qh->qh_qtd.qtd_buffer_hi[4] = 0; 2028 2029 usb_pc_cpu_flush(qh->page_cache); 2030 2031 if (xfer->xroot->udev->flags.self_suspended == 0) { 2032 EHCI_APPEND_QH(qh, *qh_last); 2033 } 2034 } 2035 2036 static void 2037 ehci_root_intr(ehci_softc_t *sc) 2038 { 2039 uint16_t i; 2040 uint16_t m; 2041 2042 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2043 2044 /* clear any old interrupt data */ 2045 memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata)); 2046 2047 /* set bits */ 2048 m = (sc->sc_noport + 1); 2049 if (m > (8 * sizeof(sc->sc_hub_idata))) { 2050 m = (8 * sizeof(sc->sc_hub_idata)); 2051 } 2052 for (i = 1; i < m; i++) { 2053 /* pick out CHANGE bits from the status register */ 2054 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) { 2055 sc->sc_hub_idata[i / 8] |= 1 << (i % 8); 2056 DPRINTF("port %d changed\n", i); 2057 } 2058 } 2059 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 2060 sizeof(sc->sc_hub_idata)); 2061 } 2062 2063 static void 2064 ehci_isoc_fs_done(ehci_softc_t *sc, struct usb_xfer *xfer) 2065 { 2066 uint32_t nframes = xfer->nframes; 2067 uint32_t status; 2068 uint32_t *plen = xfer->frlengths; 2069 uint16_t len = 0; 2070 ehci_sitd_t *td = xfer->td_transfer_first; 2071 ehci_sitd_t **pp_last = &sc->sc_isoc_fs_p_last[xfer->qh_pos]; 2072 2073 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 2074 xfer, xfer->endpoint); 2075 2076 while (nframes--) { 2077 if (td == NULL) { 2078 panic("%s:%d: out of TD's\n", 2079 __FUNCTION__, __LINE__); 2080 } 2081 if (pp_last >= &sc->sc_isoc_fs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) { 2082 pp_last = &sc->sc_isoc_fs_p_last[0]; 2083 } 2084 #ifdef USB_DEBUG 2085 if (ehcidebug > 15) { 2086 DPRINTF("isoc FS-TD\n"); 2087 ehci_dump_sitd(sc, td); 2088 } 2089 #endif 2090 usb_pc_cpu_invalidate(td->page_cache); 2091 status = hc32toh(sc, td->sitd_status); 2092 2093 len = EHCI_SITD_GET_LEN(status); 2094 2095 DPRINTFN(2, "status=0x%08x, rem=%u\n", status, len); 2096 2097 if (*plen >= len) { 2098 len = *plen - len; 2099 } else { 2100 len = 0; 2101 } 2102 2103 *plen = len; 2104 2105 /* remove FS-TD from schedule */ 2106 EHCI_REMOVE_FS_TD(td, *pp_last); 2107 2108 pp_last++; 2109 plen++; 2110 td = td->obj_next; 2111 } 2112 2113 xfer->aframes = xfer->nframes; 2114 } 2115 2116 static void 2117 ehci_isoc_hs_done(ehci_softc_t *sc, struct usb_xfer *xfer) 2118 { 2119 uint32_t nframes = xfer->nframes; 2120 uint32_t status; 2121 uint32_t *plen = xfer->frlengths; 2122 uint16_t len = 0; 2123 uint8_t td_no = 0; 2124 ehci_itd_t *td = xfer->td_transfer_first; 2125 ehci_itd_t **pp_last = &sc->sc_isoc_hs_p_last[xfer->qh_pos]; 2126 2127 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 2128 xfer, xfer->endpoint); 2129 2130 while (nframes) { 2131 if (td == NULL) { 2132 panic("%s:%d: out of TD's\n", 2133 __FUNCTION__, __LINE__); 2134 } 2135 if (pp_last >= &sc->sc_isoc_hs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) { 2136 pp_last = &sc->sc_isoc_hs_p_last[0]; 2137 } 2138 #ifdef USB_DEBUG 2139 if (ehcidebug > 15) { 2140 DPRINTF("isoc HS-TD\n"); 2141 ehci_dump_itd(sc, td); 2142 } 2143 #endif 2144 2145 usb_pc_cpu_invalidate(td->page_cache); 2146 status = hc32toh(sc, td->itd_status[td_no]); 2147 2148 len = EHCI_ITD_GET_LEN(status); 2149 2150 DPRINTFN(2, "status=0x%08x, len=%u\n", status, len); 2151 2152 if (xfer->endpoint->usb_smask & (1 << td_no)) { 2153 2154 if (*plen >= len) { 2155 /* 2156 * The length is valid. NOTE: The 2157 * complete length is written back 2158 * into the status field, and not the 2159 * remainder like with other transfer 2160 * descriptor types. 2161 */ 2162 } else { 2163 /* Invalid length - truncate */ 2164 len = 0; 2165 } 2166 2167 *plen = len; 2168 plen++; 2169 nframes--; 2170 } 2171 2172 td_no++; 2173 2174 if ((td_no == 8) || (nframes == 0)) { 2175 /* remove HS-TD from schedule */ 2176 EHCI_REMOVE_HS_TD(td, *pp_last); 2177 pp_last++; 2178 2179 td_no = 0; 2180 td = td->obj_next; 2181 } 2182 } 2183 xfer->aframes = xfer->nframes; 2184 } 2185 2186 /* NOTE: "done" can be run two times in a row, 2187 * from close and from interrupt 2188 */ 2189 static void 2190 ehci_device_done(struct usb_xfer *xfer, usb_error_t error) 2191 { 2192 const struct usb_pipe_methods *methods = xfer->endpoint->methods; 2193 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2194 2195 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2196 2197 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n", 2198 xfer, xfer->endpoint, error); 2199 2200 if ((methods == &ehci_device_bulk_methods) || 2201 (methods == &ehci_device_ctrl_methods)) { 2202 #ifdef USB_DEBUG 2203 if (ehcidebug > 8) { 2204 DPRINTF("nexttog=%d; data after transfer:\n", 2205 xfer->endpoint->toggle_next); 2206 ehci_dump_sqtds(sc, 2207 xfer->td_transfer_first); 2208 } 2209 #endif 2210 2211 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 2212 sc->sc_async_p_last); 2213 } 2214 if (methods == &ehci_device_intr_methods) { 2215 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 2216 sc->sc_intr_p_last[xfer->qh_pos]); 2217 } 2218 /* 2219 * Only finish isochronous transfers once which will update 2220 * "xfer->frlengths". 2221 */ 2222 if (xfer->td_transfer_first && 2223 xfer->td_transfer_last) { 2224 if (methods == &ehci_device_isoc_fs_methods) { 2225 ehci_isoc_fs_done(sc, xfer); 2226 } 2227 if (methods == &ehci_device_isoc_hs_methods) { 2228 ehci_isoc_hs_done(sc, xfer); 2229 } 2230 xfer->td_transfer_first = NULL; 2231 xfer->td_transfer_last = NULL; 2232 } 2233 /* dequeue transfer and start next transfer */ 2234 usbd_transfer_done(xfer, error); 2235 } 2236 2237 /*------------------------------------------------------------------------* 2238 * ehci bulk support 2239 *------------------------------------------------------------------------*/ 2240 static void 2241 ehci_device_bulk_open(struct usb_xfer *xfer) 2242 { 2243 return; 2244 } 2245 2246 static void 2247 ehci_device_bulk_close(struct usb_xfer *xfer) 2248 { 2249 ehci_device_done(xfer, USB_ERR_CANCELLED); 2250 } 2251 2252 static void 2253 ehci_device_bulk_enter(struct usb_xfer *xfer) 2254 { 2255 return; 2256 } 2257 2258 static void 2259 ehci_doorbell_async(struct ehci_softc *sc) 2260 { 2261 uint32_t temp; 2262 2263 /* 2264 * XXX Performance quirk: Some Host Controllers have a too low 2265 * interrupt rate. Issue an IAAD to stimulate the Host 2266 * Controller after queueing the BULK transfer. 2267 * 2268 * XXX Force the host controller to refresh any QH caches. 2269 */ 2270 temp = EOREAD4(sc, EHCI_USBCMD); 2271 if (!(temp & EHCI_CMD_IAAD)) 2272 EOWRITE4(sc, EHCI_USBCMD, temp | EHCI_CMD_IAAD); 2273 } 2274 2275 static void 2276 ehci_device_bulk_start(struct usb_xfer *xfer) 2277 { 2278 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2279 2280 /* setup TD's and QH */ 2281 ehci_setup_standard_chain(xfer, &sc->sc_async_p_last); 2282 2283 /* put transfer on interrupt queue */ 2284 ehci_transfer_intr_enqueue(xfer); 2285 2286 /* 2287 * XXX Certain nVidia chipsets choke when using the IAAD 2288 * feature too frequently. 2289 */ 2290 if (sc->sc_flags & EHCI_SCFLG_IAADBUG) 2291 return; 2292 2293 ehci_doorbell_async(sc); 2294 } 2295 2296 static const struct usb_pipe_methods ehci_device_bulk_methods = 2297 { 2298 .open = ehci_device_bulk_open, 2299 .close = ehci_device_bulk_close, 2300 .enter = ehci_device_bulk_enter, 2301 .start = ehci_device_bulk_start, 2302 }; 2303 2304 /*------------------------------------------------------------------------* 2305 * ehci control support 2306 *------------------------------------------------------------------------*/ 2307 static void 2308 ehci_device_ctrl_open(struct usb_xfer *xfer) 2309 { 2310 return; 2311 } 2312 2313 static void 2314 ehci_device_ctrl_close(struct usb_xfer *xfer) 2315 { 2316 ehci_device_done(xfer, USB_ERR_CANCELLED); 2317 } 2318 2319 static void 2320 ehci_device_ctrl_enter(struct usb_xfer *xfer) 2321 { 2322 return; 2323 } 2324 2325 static void 2326 ehci_device_ctrl_start(struct usb_xfer *xfer) 2327 { 2328 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2329 2330 /* setup TD's and QH */ 2331 ehci_setup_standard_chain(xfer, &sc->sc_async_p_last); 2332 2333 /* put transfer on interrupt queue */ 2334 ehci_transfer_intr_enqueue(xfer); 2335 } 2336 2337 static const struct usb_pipe_methods ehci_device_ctrl_methods = 2338 { 2339 .open = ehci_device_ctrl_open, 2340 .close = ehci_device_ctrl_close, 2341 .enter = ehci_device_ctrl_enter, 2342 .start = ehci_device_ctrl_start, 2343 }; 2344 2345 /*------------------------------------------------------------------------* 2346 * ehci interrupt support 2347 *------------------------------------------------------------------------*/ 2348 static void 2349 ehci_device_intr_open(struct usb_xfer *xfer) 2350 { 2351 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2352 uint16_t best; 2353 uint16_t bit; 2354 uint16_t x; 2355 2356 usb_hs_bandwidth_alloc(xfer); 2357 2358 /* 2359 * Find the best QH position corresponding to the given interval: 2360 */ 2361 2362 best = 0; 2363 bit = EHCI_VIRTUAL_FRAMELIST_COUNT / 2; 2364 while (bit) { 2365 if (xfer->interval >= bit) { 2366 x = bit; 2367 best = bit; 2368 while (x & bit) { 2369 if (sc->sc_intr_stat[x] < 2370 sc->sc_intr_stat[best]) { 2371 best = x; 2372 } 2373 x++; 2374 } 2375 break; 2376 } 2377 bit >>= 1; 2378 } 2379 2380 sc->sc_intr_stat[best]++; 2381 xfer->qh_pos = best; 2382 2383 DPRINTFN(3, "best=%d interval=%d\n", 2384 best, xfer->interval); 2385 } 2386 2387 static void 2388 ehci_device_intr_close(struct usb_xfer *xfer) 2389 { 2390 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2391 2392 sc->sc_intr_stat[xfer->qh_pos]--; 2393 2394 ehci_device_done(xfer, USB_ERR_CANCELLED); 2395 2396 /* bandwidth must be freed after device done */ 2397 usb_hs_bandwidth_free(xfer); 2398 } 2399 2400 static void 2401 ehci_device_intr_enter(struct usb_xfer *xfer) 2402 { 2403 return; 2404 } 2405 2406 static void 2407 ehci_device_intr_start(struct usb_xfer *xfer) 2408 { 2409 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2410 2411 /* setup TD's and QH */ 2412 ehci_setup_standard_chain(xfer, &sc->sc_intr_p_last[xfer->qh_pos]); 2413 2414 /* put transfer on interrupt queue */ 2415 ehci_transfer_intr_enqueue(xfer); 2416 } 2417 2418 static const struct usb_pipe_methods ehci_device_intr_methods = 2419 { 2420 .open = ehci_device_intr_open, 2421 .close = ehci_device_intr_close, 2422 .enter = ehci_device_intr_enter, 2423 .start = ehci_device_intr_start, 2424 }; 2425 2426 /*------------------------------------------------------------------------* 2427 * ehci full speed isochronous support 2428 *------------------------------------------------------------------------*/ 2429 static void 2430 ehci_device_isoc_fs_open(struct usb_xfer *xfer) 2431 { 2432 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2433 ehci_sitd_t *td; 2434 uint32_t sitd_portaddr; 2435 uint8_t ds; 2436 2437 sitd_portaddr = 2438 EHCI_SITD_SET_ADDR(xfer->address) | 2439 EHCI_SITD_SET_ENDPT(UE_GET_ADDR(xfer->endpointno)) | 2440 EHCI_SITD_SET_HUBA(xfer->xroot->udev->hs_hub_addr) | 2441 EHCI_SITD_SET_PORT(xfer->xroot->udev->hs_port_no); 2442 2443 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) 2444 sitd_portaddr |= EHCI_SITD_SET_DIR_IN; 2445 2446 sitd_portaddr = htohc32(sc, sitd_portaddr); 2447 2448 /* initialize all TD's */ 2449 2450 for (ds = 0; ds != 2; ds++) { 2451 2452 for (td = xfer->td_start[ds]; td; td = td->obj_next) { 2453 2454 td->sitd_portaddr = sitd_portaddr; 2455 2456 /* 2457 * TODO: make some kind of automatic 2458 * SMASK/CMASK selection based on micro-frame 2459 * usage 2460 * 2461 * micro-frame usage (8 microframes per 1ms) 2462 */ 2463 td->sitd_back = htohc32(sc, EHCI_LINK_TERMINATE); 2464 2465 usb_pc_cpu_flush(td->page_cache); 2466 } 2467 } 2468 } 2469 2470 static void 2471 ehci_device_isoc_fs_close(struct usb_xfer *xfer) 2472 { 2473 ehci_device_done(xfer, USB_ERR_CANCELLED); 2474 } 2475 2476 static void 2477 ehci_device_isoc_fs_enter(struct usb_xfer *xfer) 2478 { 2479 struct usb_page_search buf_res; 2480 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2481 ehci_sitd_t *td; 2482 ehci_sitd_t *td_last = NULL; 2483 ehci_sitd_t **pp_last; 2484 uint32_t *plen; 2485 uint32_t buf_offset; 2486 uint32_t nframes; 2487 uint32_t temp; 2488 uint32_t sitd_mask; 2489 uint16_t tlen; 2490 uint8_t sa; 2491 uint8_t sb; 2492 2493 #ifdef USB_DEBUG 2494 uint8_t once = 1; 2495 2496 #endif 2497 2498 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 2499 xfer, xfer->endpoint->isoc_next, xfer->nframes); 2500 2501 /* get the current frame index */ 2502 2503 nframes = EOREAD4(sc, EHCI_FRINDEX) / 8; 2504 2505 /* 2506 * check if the frame index is within the window where the frames 2507 * will be inserted 2508 */ 2509 buf_offset = (nframes - xfer->endpoint->isoc_next) & 2510 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2511 2512 if ((xfer->endpoint->is_synced == 0) || 2513 (buf_offset < xfer->nframes)) { 2514 /* 2515 * If there is data underflow or the pipe queue is empty we 2516 * schedule the transfer a few frames ahead of the current 2517 * frame position. Else two isochronous transfers might 2518 * overlap. 2519 */ 2520 xfer->endpoint->isoc_next = (nframes + 3) & 2521 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2522 xfer->endpoint->is_synced = 1; 2523 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 2524 } 2525 /* 2526 * compute how many milliseconds the insertion is ahead of the 2527 * current frame position: 2528 */ 2529 buf_offset = (xfer->endpoint->isoc_next - nframes) & 2530 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2531 2532 /* 2533 * pre-compute when the isochronous transfer will be finished: 2534 */ 2535 xfer->isoc_time_complete = 2536 usb_isoc_time_expand(&sc->sc_bus, nframes) + 2537 buf_offset + xfer->nframes; 2538 2539 /* get the real number of frames */ 2540 2541 nframes = xfer->nframes; 2542 2543 buf_offset = 0; 2544 2545 plen = xfer->frlengths; 2546 2547 /* toggle the DMA set we are using */ 2548 xfer->flags_int.curr_dma_set ^= 1; 2549 2550 /* get next DMA set */ 2551 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 2552 xfer->td_transfer_first = td; 2553 2554 pp_last = &sc->sc_isoc_fs_p_last[xfer->endpoint->isoc_next]; 2555 2556 /* store starting position */ 2557 2558 xfer->qh_pos = xfer->endpoint->isoc_next; 2559 2560 while (nframes--) { 2561 if (td == NULL) { 2562 panic("%s:%d: out of TD's\n", 2563 __FUNCTION__, __LINE__); 2564 } 2565 if (pp_last >= &sc->sc_isoc_fs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) 2566 pp_last = &sc->sc_isoc_fs_p_last[0]; 2567 2568 /* reuse sitd_portaddr and sitd_back from last transfer */ 2569 2570 if (*plen > xfer->max_frame_size) { 2571 #ifdef USB_DEBUG 2572 if (once) { 2573 once = 0; 2574 printf("%s: frame length(%d) exceeds %d " 2575 "bytes (frame truncated)\n", 2576 __FUNCTION__, *plen, 2577 xfer->max_frame_size); 2578 } 2579 #endif 2580 *plen = xfer->max_frame_size; 2581 } 2582 2583 /* allocate a slot */ 2584 2585 sa = usbd_fs_isoc_schedule_alloc_slot(xfer, 2586 xfer->isoc_time_complete - nframes - 1); 2587 2588 if (sa == 255) { 2589 /* 2590 * Schedule is FULL, set length to zero: 2591 */ 2592 2593 *plen = 0; 2594 sa = USB_FS_ISOC_UFRAME_MAX - 1; 2595 } 2596 if (*plen) { 2597 /* 2598 * only call "usbd_get_page()" when we have a 2599 * non-zero length 2600 */ 2601 usbd_get_page(xfer->frbuffers, buf_offset, &buf_res); 2602 td->sitd_bp[0] = htohc32(sc, buf_res.physaddr); 2603 buf_offset += *plen; 2604 /* 2605 * NOTE: We need to subtract one from the offset so 2606 * that we are on a valid page! 2607 */ 2608 usbd_get_page(xfer->frbuffers, buf_offset - 1, 2609 &buf_res); 2610 temp = buf_res.physaddr & ~0xFFF; 2611 } else { 2612 td->sitd_bp[0] = 0; 2613 temp = 0; 2614 } 2615 2616 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_OUT) { 2617 tlen = *plen; 2618 if (tlen <= 188) { 2619 temp |= 1; /* T-count = 1, TP = ALL */ 2620 tlen = 1; 2621 } else { 2622 tlen += 187; 2623 tlen /= 188; 2624 temp |= tlen; /* T-count = [1..6] */ 2625 temp |= 8; /* TP = Begin */ 2626 } 2627 2628 tlen += sa; 2629 2630 if (tlen >= 8) { 2631 sb = 0; 2632 } else { 2633 sb = (1 << tlen); 2634 } 2635 2636 sa = (1 << sa); 2637 sa = (sb - sa) & 0x3F; 2638 sb = 0; 2639 } else { 2640 sb = (-(4 << sa)) & 0xFE; 2641 sa = (1 << sa) & 0x3F; 2642 } 2643 2644 sitd_mask = (EHCI_SITD_SET_SMASK(sa) | 2645 EHCI_SITD_SET_CMASK(sb)); 2646 2647 td->sitd_bp[1] = htohc32(sc, temp); 2648 2649 td->sitd_mask = htohc32(sc, sitd_mask); 2650 2651 if (nframes == 0) { 2652 td->sitd_status = htohc32(sc, 2653 EHCI_SITD_IOC | 2654 EHCI_SITD_ACTIVE | 2655 EHCI_SITD_SET_LEN(*plen)); 2656 } else { 2657 td->sitd_status = htohc32(sc, 2658 EHCI_SITD_ACTIVE | 2659 EHCI_SITD_SET_LEN(*plen)); 2660 } 2661 usb_pc_cpu_flush(td->page_cache); 2662 2663 #ifdef USB_DEBUG 2664 if (ehcidebug > 15) { 2665 DPRINTF("FS-TD %d\n", nframes); 2666 ehci_dump_sitd(sc, td); 2667 } 2668 #endif 2669 /* insert TD into schedule */ 2670 EHCI_APPEND_FS_TD(td, *pp_last); 2671 pp_last++; 2672 2673 plen++; 2674 td_last = td; 2675 td = td->obj_next; 2676 } 2677 2678 xfer->td_transfer_last = td_last; 2679 2680 /* update isoc_next */ 2681 xfer->endpoint->isoc_next = (pp_last - &sc->sc_isoc_fs_p_last[0]) & 2682 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2683 2684 /* 2685 * We don't allow cancelling of the SPLIT transaction USB FULL 2686 * speed transfer, because it disturbs the bandwidth 2687 * computation algorithm. 2688 */ 2689 xfer->flags_int.can_cancel_immed = 0; 2690 } 2691 2692 static void 2693 ehci_device_isoc_fs_start(struct usb_xfer *xfer) 2694 { 2695 /* 2696 * We don't allow cancelling of the SPLIT transaction USB FULL 2697 * speed transfer, because it disturbs the bandwidth 2698 * computation algorithm. 2699 */ 2700 xfer->flags_int.can_cancel_immed = 0; 2701 2702 /* set a default timeout */ 2703 if (xfer->timeout == 0) 2704 xfer->timeout = 500; /* ms */ 2705 2706 /* put transfer on interrupt queue */ 2707 ehci_transfer_intr_enqueue(xfer); 2708 } 2709 2710 static const struct usb_pipe_methods ehci_device_isoc_fs_methods = 2711 { 2712 .open = ehci_device_isoc_fs_open, 2713 .close = ehci_device_isoc_fs_close, 2714 .enter = ehci_device_isoc_fs_enter, 2715 .start = ehci_device_isoc_fs_start, 2716 }; 2717 2718 /*------------------------------------------------------------------------* 2719 * ehci high speed isochronous support 2720 *------------------------------------------------------------------------*/ 2721 static void 2722 ehci_device_isoc_hs_open(struct usb_xfer *xfer) 2723 { 2724 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2725 ehci_itd_t *td; 2726 uint32_t temp; 2727 uint8_t ds; 2728 2729 usb_hs_bandwidth_alloc(xfer); 2730 2731 /* initialize all TD's */ 2732 2733 for (ds = 0; ds != 2; ds++) { 2734 2735 for (td = xfer->td_start[ds]; td; td = td->obj_next) { 2736 2737 /* set TD inactive */ 2738 td->itd_status[0] = 0; 2739 td->itd_status[1] = 0; 2740 td->itd_status[2] = 0; 2741 td->itd_status[3] = 0; 2742 td->itd_status[4] = 0; 2743 td->itd_status[5] = 0; 2744 td->itd_status[6] = 0; 2745 td->itd_status[7] = 0; 2746 2747 /* set endpoint and address */ 2748 td->itd_bp[0] = htohc32(sc, 2749 EHCI_ITD_SET_ADDR(xfer->address) | 2750 EHCI_ITD_SET_ENDPT(UE_GET_ADDR(xfer->endpointno))); 2751 2752 temp = 2753 EHCI_ITD_SET_MPL(xfer->max_packet_size & 0x7FF); 2754 2755 /* set direction */ 2756 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) { 2757 temp |= EHCI_ITD_SET_DIR_IN; 2758 } 2759 /* set maximum packet size */ 2760 td->itd_bp[1] = htohc32(sc, temp); 2761 2762 /* set transfer multiplier */ 2763 td->itd_bp[2] = htohc32(sc, xfer->max_packet_count & 3); 2764 2765 usb_pc_cpu_flush(td->page_cache); 2766 } 2767 } 2768 } 2769 2770 static void 2771 ehci_device_isoc_hs_close(struct usb_xfer *xfer) 2772 { 2773 ehci_device_done(xfer, USB_ERR_CANCELLED); 2774 2775 /* bandwidth must be freed after device done */ 2776 usb_hs_bandwidth_free(xfer); 2777 } 2778 2779 static void 2780 ehci_device_isoc_hs_enter(struct usb_xfer *xfer) 2781 { 2782 struct usb_page_search buf_res; 2783 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2784 ehci_itd_t *td; 2785 ehci_itd_t *td_last = NULL; 2786 ehci_itd_t **pp_last; 2787 bus_size_t page_addr; 2788 uint32_t *plen; 2789 uint32_t status; 2790 uint32_t buf_offset; 2791 uint32_t nframes; 2792 uint32_t itd_offset[8 + 1]; 2793 uint8_t x; 2794 uint8_t td_no; 2795 uint8_t page_no; 2796 uint8_t shift = usbd_xfer_get_fps_shift(xfer); 2797 2798 #ifdef USB_DEBUG 2799 uint8_t once = 1; 2800 2801 #endif 2802 2803 DPRINTFN(6, "xfer=%p next=%d nframes=%d shift=%d\n", 2804 xfer, xfer->endpoint->isoc_next, xfer->nframes, (int)shift); 2805 2806 /* get the current frame index */ 2807 2808 nframes = EOREAD4(sc, EHCI_FRINDEX) / 8; 2809 2810 /* 2811 * check if the frame index is within the window where the frames 2812 * will be inserted 2813 */ 2814 buf_offset = (nframes - xfer->endpoint->isoc_next) & 2815 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2816 2817 if ((xfer->endpoint->is_synced == 0) || 2818 (buf_offset < (((xfer->nframes << shift) + 7) / 8))) { 2819 /* 2820 * If there is data underflow or the pipe queue is empty we 2821 * schedule the transfer a few frames ahead of the current 2822 * frame position. Else two isochronous transfers might 2823 * overlap. 2824 */ 2825 xfer->endpoint->isoc_next = (nframes + 3) & 2826 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2827 xfer->endpoint->is_synced = 1; 2828 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 2829 } 2830 /* 2831 * compute how many milliseconds the insertion is ahead of the 2832 * current frame position: 2833 */ 2834 buf_offset = (xfer->endpoint->isoc_next - nframes) & 2835 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2836 2837 /* 2838 * pre-compute when the isochronous transfer will be finished: 2839 */ 2840 xfer->isoc_time_complete = 2841 usb_isoc_time_expand(&sc->sc_bus, nframes) + buf_offset + 2842 (((xfer->nframes << shift) + 7) / 8); 2843 2844 /* get the real number of frames */ 2845 2846 nframes = xfer->nframes; 2847 2848 buf_offset = 0; 2849 td_no = 0; 2850 2851 plen = xfer->frlengths; 2852 2853 /* toggle the DMA set we are using */ 2854 xfer->flags_int.curr_dma_set ^= 1; 2855 2856 /* get next DMA set */ 2857 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 2858 xfer->td_transfer_first = td; 2859 2860 pp_last = &sc->sc_isoc_hs_p_last[xfer->endpoint->isoc_next]; 2861 2862 /* store starting position */ 2863 2864 xfer->qh_pos = xfer->endpoint->isoc_next; 2865 2866 while (nframes) { 2867 if (td == NULL) { 2868 panic("%s:%d: out of TD's\n", 2869 __FUNCTION__, __LINE__); 2870 } 2871 if (pp_last >= &sc->sc_isoc_hs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) { 2872 pp_last = &sc->sc_isoc_hs_p_last[0]; 2873 } 2874 /* range check */ 2875 if (*plen > xfer->max_frame_size) { 2876 #ifdef USB_DEBUG 2877 if (once) { 2878 once = 0; 2879 printf("%s: frame length(%d) exceeds %d bytes " 2880 "(frame truncated)\n", 2881 __FUNCTION__, *plen, xfer->max_frame_size); 2882 } 2883 #endif 2884 *plen = xfer->max_frame_size; 2885 } 2886 2887 if (xfer->endpoint->usb_smask & (1 << td_no)) { 2888 status = (EHCI_ITD_SET_LEN(*plen) | 2889 EHCI_ITD_ACTIVE | 2890 EHCI_ITD_SET_PG(0)); 2891 td->itd_status[td_no] = htohc32(sc, status); 2892 itd_offset[td_no] = buf_offset; 2893 buf_offset += *plen; 2894 plen++; 2895 nframes --; 2896 } else { 2897 td->itd_status[td_no] = 0; /* not active */ 2898 itd_offset[td_no] = buf_offset; 2899 } 2900 2901 td_no++; 2902 2903 if ((td_no == 8) || (nframes == 0)) { 2904 2905 /* the rest of the transfers are not active, if any */ 2906 for (x = td_no; x != 8; x++) { 2907 td->itd_status[x] = 0; /* not active */ 2908 } 2909 2910 /* check if there is any data to be transferred */ 2911 if (itd_offset[0] != buf_offset) { 2912 page_no = 0; 2913 itd_offset[td_no] = buf_offset; 2914 2915 /* get first page offset */ 2916 usbd_get_page(xfer->frbuffers, itd_offset[0], &buf_res); 2917 /* get page address */ 2918 page_addr = buf_res.physaddr & ~0xFFF; 2919 /* update page address */ 2920 td->itd_bp[0] &= htohc32(sc, 0xFFF); 2921 td->itd_bp[0] |= htohc32(sc, page_addr); 2922 2923 for (x = 0; x != td_no; x++) { 2924 /* set page number and page offset */ 2925 status = (EHCI_ITD_SET_PG(page_no) | 2926 (buf_res.physaddr & 0xFFF)); 2927 td->itd_status[x] |= htohc32(sc, status); 2928 2929 /* get next page offset */ 2930 if (itd_offset[x + 1] == buf_offset) { 2931 /* 2932 * We subtract one so that 2933 * we don't go off the last 2934 * page! 2935 */ 2936 usbd_get_page(xfer->frbuffers, buf_offset - 1, &buf_res); 2937 } else { 2938 usbd_get_page(xfer->frbuffers, itd_offset[x + 1], &buf_res); 2939 } 2940 2941 /* check if we need a new page */ 2942 if ((buf_res.physaddr ^ page_addr) & ~0xFFF) { 2943 /* new page needed */ 2944 page_addr = buf_res.physaddr & ~0xFFF; 2945 if (page_no == 6) { 2946 panic("%s: too many pages\n", __FUNCTION__); 2947 } 2948 page_no++; 2949 /* update page address */ 2950 td->itd_bp[page_no] &= htohc32(sc, 0xFFF); 2951 td->itd_bp[page_no] |= htohc32(sc, page_addr); 2952 } 2953 } 2954 } 2955 /* set IOC bit if we are complete */ 2956 if (nframes == 0) { 2957 td->itd_status[td_no - 1] |= htohc32(sc, EHCI_ITD_IOC); 2958 } 2959 usb_pc_cpu_flush(td->page_cache); 2960 #ifdef USB_DEBUG 2961 if (ehcidebug > 15) { 2962 DPRINTF("HS-TD %d\n", nframes); 2963 ehci_dump_itd(sc, td); 2964 } 2965 #endif 2966 /* insert TD into schedule */ 2967 EHCI_APPEND_HS_TD(td, *pp_last); 2968 pp_last++; 2969 2970 td_no = 0; 2971 td_last = td; 2972 td = td->obj_next; 2973 } 2974 } 2975 2976 xfer->td_transfer_last = td_last; 2977 2978 /* update isoc_next */ 2979 xfer->endpoint->isoc_next = (pp_last - &sc->sc_isoc_hs_p_last[0]) & 2980 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2981 } 2982 2983 static void 2984 ehci_device_isoc_hs_start(struct usb_xfer *xfer) 2985 { 2986 /* put transfer on interrupt queue */ 2987 ehci_transfer_intr_enqueue(xfer); 2988 } 2989 2990 static const struct usb_pipe_methods ehci_device_isoc_hs_methods = 2991 { 2992 .open = ehci_device_isoc_hs_open, 2993 .close = ehci_device_isoc_hs_close, 2994 .enter = ehci_device_isoc_hs_enter, 2995 .start = ehci_device_isoc_hs_start, 2996 }; 2997 2998 /*------------------------------------------------------------------------* 2999 * ehci root control support 3000 *------------------------------------------------------------------------* 3001 * Simulate a hardware hub by handling all the necessary requests. 3002 *------------------------------------------------------------------------*/ 3003 3004 static const 3005 struct usb_device_descriptor ehci_devd = 3006 { 3007 sizeof(struct usb_device_descriptor), 3008 UDESC_DEVICE, /* type */ 3009 {0x00, 0x02}, /* USB version */ 3010 UDCLASS_HUB, /* class */ 3011 UDSUBCLASS_HUB, /* subclass */ 3012 UDPROTO_HSHUBSTT, /* protocol */ 3013 64, /* max packet */ 3014 {0}, {0}, {0x00, 0x01}, /* device id */ 3015 1, 2, 0, /* string indicies */ 3016 1 /* # of configurations */ 3017 }; 3018 3019 static const 3020 struct usb_device_qualifier ehci_odevd = 3021 { 3022 sizeof(struct usb_device_qualifier), 3023 UDESC_DEVICE_QUALIFIER, /* type */ 3024 {0x00, 0x02}, /* USB version */ 3025 UDCLASS_HUB, /* class */ 3026 UDSUBCLASS_HUB, /* subclass */ 3027 UDPROTO_FSHUB, /* protocol */ 3028 0, /* max packet */ 3029 0, /* # of configurations */ 3030 0 3031 }; 3032 3033 static const struct ehci_config_desc ehci_confd = { 3034 .confd = { 3035 .bLength = sizeof(struct usb_config_descriptor), 3036 .bDescriptorType = UDESC_CONFIG, 3037 .wTotalLength[0] = sizeof(ehci_confd), 3038 .bNumInterface = 1, 3039 .bConfigurationValue = 1, 3040 .iConfiguration = 0, 3041 .bmAttributes = UC_SELF_POWERED, 3042 .bMaxPower = 0 /* max power */ 3043 }, 3044 .ifcd = { 3045 .bLength = sizeof(struct usb_interface_descriptor), 3046 .bDescriptorType = UDESC_INTERFACE, 3047 .bNumEndpoints = 1, 3048 .bInterfaceClass = UICLASS_HUB, 3049 .bInterfaceSubClass = UISUBCLASS_HUB, 3050 .bInterfaceProtocol = 0, 3051 }, 3052 .endpd = { 3053 .bLength = sizeof(struct usb_endpoint_descriptor), 3054 .bDescriptorType = UDESC_ENDPOINT, 3055 .bEndpointAddress = UE_DIR_IN | EHCI_INTR_ENDPT, 3056 .bmAttributes = UE_INTERRUPT, 3057 .wMaxPacketSize[0] = 8, /* max packet (63 ports) */ 3058 .bInterval = 255, 3059 }, 3060 }; 3061 3062 static const 3063 struct usb_hub_descriptor ehci_hubd = 3064 { 3065 .bDescLength = 0, /* dynamic length */ 3066 .bDescriptorType = UDESC_HUB, 3067 }; 3068 3069 static void 3070 ehci_disown(ehci_softc_t *sc, uint16_t index, uint8_t lowspeed) 3071 { 3072 uint32_t port; 3073 uint32_t v; 3074 3075 DPRINTF("index=%d lowspeed=%d\n", index, lowspeed); 3076 3077 port = EHCI_PORTSC(index); 3078 v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR; 3079 EOWRITE4(sc, port, v | EHCI_PS_PO); 3080 } 3081 3082 static usb_error_t 3083 ehci_roothub_exec(struct usb_device *udev, 3084 struct usb_device_request *req, const void **pptr, uint16_t *plength) 3085 { 3086 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus); 3087 const char *str_ptr; 3088 const void *ptr; 3089 uint32_t port; 3090 uint32_t v; 3091 uint16_t len; 3092 uint16_t i; 3093 uint16_t value; 3094 uint16_t index; 3095 usb_error_t err; 3096 3097 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 3098 3099 /* buffer reset */ 3100 ptr = (const void *)&sc->sc_hub_desc; 3101 len = 0; 3102 err = 0; 3103 3104 value = UGETW(req->wValue); 3105 index = UGETW(req->wIndex); 3106 3107 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x " 3108 "wValue=0x%04x wIndex=0x%04x\n", 3109 req->bmRequestType, req->bRequest, 3110 UGETW(req->wLength), value, index); 3111 3112 #define C(x,y) ((x) | ((y) << 8)) 3113 switch (C(req->bRequest, req->bmRequestType)) { 3114 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 3115 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 3116 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 3117 /* 3118 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 3119 * for the integrated root hub. 3120 */ 3121 break; 3122 case C(UR_GET_CONFIG, UT_READ_DEVICE): 3123 len = 1; 3124 sc->sc_hub_desc.temp[0] = sc->sc_conf; 3125 break; 3126 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3127 switch (value >> 8) { 3128 case UDESC_DEVICE: 3129 if ((value & 0xff) != 0) { 3130 err = USB_ERR_IOERROR; 3131 goto done; 3132 } 3133 len = sizeof(ehci_devd); 3134 ptr = (const void *)&ehci_devd; 3135 break; 3136 /* 3137 * We can't really operate at another speed, 3138 * but the specification says we need this 3139 * descriptor: 3140 */ 3141 case UDESC_DEVICE_QUALIFIER: 3142 if ((value & 0xff) != 0) { 3143 err = USB_ERR_IOERROR; 3144 goto done; 3145 } 3146 len = sizeof(ehci_odevd); 3147 ptr = (const void *)&ehci_odevd; 3148 break; 3149 3150 case UDESC_CONFIG: 3151 if ((value & 0xff) != 0) { 3152 err = USB_ERR_IOERROR; 3153 goto done; 3154 } 3155 len = sizeof(ehci_confd); 3156 ptr = (const void *)&ehci_confd; 3157 break; 3158 3159 case UDESC_STRING: 3160 switch (value & 0xff) { 3161 case 0: /* Language table */ 3162 str_ptr = "\001"; 3163 break; 3164 3165 case 1: /* Vendor */ 3166 str_ptr = sc->sc_vendor; 3167 break; 3168 3169 case 2: /* Product */ 3170 str_ptr = "EHCI root HUB"; 3171 break; 3172 3173 default: 3174 str_ptr = ""; 3175 break; 3176 } 3177 3178 len = usb_make_str_desc( 3179 sc->sc_hub_desc.temp, 3180 sizeof(sc->sc_hub_desc.temp), 3181 str_ptr); 3182 break; 3183 default: 3184 err = USB_ERR_IOERROR; 3185 goto done; 3186 } 3187 break; 3188 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 3189 len = 1; 3190 sc->sc_hub_desc.temp[0] = 0; 3191 break; 3192 case C(UR_GET_STATUS, UT_READ_DEVICE): 3193 len = 2; 3194 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED); 3195 break; 3196 case C(UR_GET_STATUS, UT_READ_INTERFACE): 3197 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 3198 len = 2; 3199 USETW(sc->sc_hub_desc.stat.wStatus, 0); 3200 break; 3201 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 3202 if (value >= EHCI_MAX_DEVICES) { 3203 err = USB_ERR_IOERROR; 3204 goto done; 3205 } 3206 sc->sc_addr = value; 3207 break; 3208 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 3209 if ((value != 0) && (value != 1)) { 3210 err = USB_ERR_IOERROR; 3211 goto done; 3212 } 3213 sc->sc_conf = value; 3214 break; 3215 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 3216 break; 3217 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 3218 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 3219 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 3220 err = USB_ERR_IOERROR; 3221 goto done; 3222 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 3223 break; 3224 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 3225 break; 3226 /* Hub requests */ 3227 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3228 break; 3229 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3230 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n"); 3231 3232 if ((index < 1) || 3233 (index > sc->sc_noport)) { 3234 err = USB_ERR_IOERROR; 3235 goto done; 3236 } 3237 port = EHCI_PORTSC(index); 3238 v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR; 3239 switch (value) { 3240 case UHF_PORT_ENABLE: 3241 EOWRITE4(sc, port, v & ~EHCI_PS_PE); 3242 break; 3243 case UHF_PORT_SUSPEND: 3244 if ((v & EHCI_PS_SUSP) && (!(v & EHCI_PS_FPR))) { 3245 3246 /* 3247 * waking up a High Speed device is rather 3248 * complicated if 3249 */ 3250 EOWRITE4(sc, port, v | EHCI_PS_FPR); 3251 } 3252 /* wait 20ms for resume sequence to complete */ 3253 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50); 3254 3255 EOWRITE4(sc, port, v & ~(EHCI_PS_SUSP | 3256 EHCI_PS_FPR | (3 << 10) /* High Speed */ )); 3257 3258 /* 4ms settle time */ 3259 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250); 3260 break; 3261 case UHF_PORT_POWER: 3262 EOWRITE4(sc, port, v & ~EHCI_PS_PP); 3263 break; 3264 case UHF_PORT_TEST: 3265 DPRINTFN(3, "clear port test " 3266 "%d\n", index); 3267 break; 3268 case UHF_PORT_INDICATOR: 3269 DPRINTFN(3, "clear port ind " 3270 "%d\n", index); 3271 EOWRITE4(sc, port, v & ~EHCI_PS_PIC); 3272 break; 3273 case UHF_C_PORT_CONNECTION: 3274 EOWRITE4(sc, port, v | EHCI_PS_CSC); 3275 break; 3276 case UHF_C_PORT_ENABLE: 3277 EOWRITE4(sc, port, v | EHCI_PS_PEC); 3278 break; 3279 case UHF_C_PORT_SUSPEND: 3280 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 3281 break; 3282 case UHF_C_PORT_OVER_CURRENT: 3283 EOWRITE4(sc, port, v | EHCI_PS_OCC); 3284 break; 3285 case UHF_C_PORT_RESET: 3286 sc->sc_isreset = 0; 3287 break; 3288 default: 3289 err = USB_ERR_IOERROR; 3290 goto done; 3291 } 3292 break; 3293 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3294 if ((value & 0xff) != 0) { 3295 err = USB_ERR_IOERROR; 3296 goto done; 3297 } 3298 v = EREAD4(sc, EHCI_HCSPARAMS); 3299 3300 sc->sc_hub_desc.hubd = ehci_hubd; 3301 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport; 3302 3303 if (EHCI_HCS_PPC(v)) 3304 i = UHD_PWR_INDIVIDUAL; 3305 else 3306 i = UHD_PWR_NO_SWITCH; 3307 3308 if (EHCI_HCS_P_INDICATOR(v)) 3309 i |= UHD_PORT_IND; 3310 3311 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, i); 3312 /* XXX can't find out? */ 3313 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 200; 3314 /* XXX don't know if ports are removable or not */ 3315 sc->sc_hub_desc.hubd.bDescLength = 3316 8 + ((sc->sc_noport + 7) / 8); 3317 len = sc->sc_hub_desc.hubd.bDescLength; 3318 break; 3319 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3320 len = 16; 3321 memset(sc->sc_hub_desc.temp, 0, 16); 3322 break; 3323 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3324 DPRINTFN(9, "get port status i=%d\n", 3325 index); 3326 if ((index < 1) || 3327 (index > sc->sc_noport)) { 3328 err = USB_ERR_IOERROR; 3329 goto done; 3330 } 3331 v = EOREAD4(sc, EHCI_PORTSC(index)); 3332 DPRINTFN(9, "port status=0x%04x\n", v); 3333 if (sc->sc_flags & (EHCI_SCFLG_FORCESPEED | EHCI_SCFLG_TT)) { 3334 if ((v & 0xc000000) == 0x8000000) 3335 i = UPS_HIGH_SPEED; 3336 else if ((v & 0xc000000) == 0x4000000) 3337 i = UPS_LOW_SPEED; 3338 else 3339 i = 0; 3340 } else { 3341 i = UPS_HIGH_SPEED; 3342 } 3343 if (v & EHCI_PS_CS) 3344 i |= UPS_CURRENT_CONNECT_STATUS; 3345 if (v & EHCI_PS_PE) 3346 i |= UPS_PORT_ENABLED; 3347 if ((v & EHCI_PS_SUSP) && !(v & EHCI_PS_FPR)) 3348 i |= UPS_SUSPEND; 3349 if (v & EHCI_PS_OCA) 3350 i |= UPS_OVERCURRENT_INDICATOR; 3351 if (v & EHCI_PS_PR) 3352 i |= UPS_RESET; 3353 if (v & EHCI_PS_PP) 3354 i |= UPS_PORT_POWER; 3355 USETW(sc->sc_hub_desc.ps.wPortStatus, i); 3356 i = 0; 3357 if (v & EHCI_PS_CSC) 3358 i |= UPS_C_CONNECT_STATUS; 3359 if (v & EHCI_PS_PEC) 3360 i |= UPS_C_PORT_ENABLED; 3361 if (v & EHCI_PS_OCC) 3362 i |= UPS_C_OVERCURRENT_INDICATOR; 3363 if (v & EHCI_PS_FPR) 3364 i |= UPS_C_SUSPEND; 3365 if (sc->sc_isreset) 3366 i |= UPS_C_PORT_RESET; 3367 USETW(sc->sc_hub_desc.ps.wPortChange, i); 3368 len = sizeof(sc->sc_hub_desc.ps); 3369 break; 3370 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3371 err = USB_ERR_IOERROR; 3372 goto done; 3373 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3374 break; 3375 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 3376 if ((index < 1) || 3377 (index > sc->sc_noport)) { 3378 err = USB_ERR_IOERROR; 3379 goto done; 3380 } 3381 port = EHCI_PORTSC(index); 3382 v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR; 3383 switch (value) { 3384 case UHF_PORT_ENABLE: 3385 EOWRITE4(sc, port, v | EHCI_PS_PE); 3386 break; 3387 case UHF_PORT_SUSPEND: 3388 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 3389 break; 3390 case UHF_PORT_RESET: 3391 DPRINTFN(6, "reset port %d\n", index); 3392 #ifdef USB_DEBUG 3393 if (ehcinohighspeed) { 3394 /* 3395 * Connect USB device to companion 3396 * controller. 3397 */ 3398 ehci_disown(sc, index, 1); 3399 break; 3400 } 3401 #endif 3402 if (EHCI_PS_IS_LOWSPEED(v) && 3403 (sc->sc_flags & EHCI_SCFLG_TT) == 0) { 3404 /* Low speed device, give up ownership. */ 3405 ehci_disown(sc, index, 1); 3406 break; 3407 } 3408 /* Start reset sequence. */ 3409 v &= ~(EHCI_PS_PE | EHCI_PS_PR); 3410 EOWRITE4(sc, port, v | EHCI_PS_PR); 3411 3412 /* Wait for reset to complete. */ 3413 usb_pause_mtx(&sc->sc_bus.bus_mtx, 3414 USB_MS_TO_TICKS(usb_port_root_reset_delay)); 3415 3416 /* Terminate reset sequence. */ 3417 if (!(sc->sc_flags & EHCI_SCFLG_NORESTERM)) 3418 EOWRITE4(sc, port, v); 3419 3420 /* Wait for HC to complete reset. */ 3421 usb_pause_mtx(&sc->sc_bus.bus_mtx, 3422 USB_MS_TO_TICKS(EHCI_PORT_RESET_COMPLETE)); 3423 3424 v = EOREAD4(sc, port); 3425 DPRINTF("ehci after reset, status=0x%08x\n", v); 3426 if (v & EHCI_PS_PR) { 3427 device_printf(sc->sc_bus.bdev, 3428 "port reset timeout\n"); 3429 err = USB_ERR_TIMEOUT; 3430 goto done; 3431 } 3432 if (!(v & EHCI_PS_PE) && 3433 (sc->sc_flags & EHCI_SCFLG_TT) == 0) { 3434 /* Not a high speed device, give up ownership.*/ 3435 ehci_disown(sc, index, 0); 3436 break; 3437 } 3438 sc->sc_isreset = 1; 3439 DPRINTF("ehci port %d reset, status = 0x%08x\n", 3440 index, v); 3441 break; 3442 3443 case UHF_PORT_POWER: 3444 DPRINTFN(3, "set port power %d\n", index); 3445 EOWRITE4(sc, port, v | EHCI_PS_PP); 3446 break; 3447 3448 case UHF_PORT_TEST: 3449 DPRINTFN(3, "set port test %d\n", index); 3450 break; 3451 3452 case UHF_PORT_INDICATOR: 3453 DPRINTFN(3, "set port ind %d\n", index); 3454 EOWRITE4(sc, port, v | EHCI_PS_PIC); 3455 break; 3456 3457 default: 3458 err = USB_ERR_IOERROR; 3459 goto done; 3460 } 3461 break; 3462 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 3463 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 3464 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 3465 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 3466 break; 3467 default: 3468 err = USB_ERR_IOERROR; 3469 goto done; 3470 } 3471 done: 3472 *plength = len; 3473 *pptr = ptr; 3474 return (err); 3475 } 3476 3477 static void 3478 ehci_xfer_setup(struct usb_setup_params *parm) 3479 { 3480 struct usb_page_search page_info; 3481 struct usb_page_cache *pc; 3482 ehci_softc_t *sc; 3483 struct usb_xfer *xfer; 3484 void *last_obj; 3485 uint32_t nqtd; 3486 uint32_t nqh; 3487 uint32_t nsitd; 3488 uint32_t nitd; 3489 uint32_t n; 3490 3491 sc = EHCI_BUS2SC(parm->udev->bus); 3492 xfer = parm->curr_xfer; 3493 3494 nqtd = 0; 3495 nqh = 0; 3496 nsitd = 0; 3497 nitd = 0; 3498 3499 /* 3500 * compute maximum number of some structures 3501 */ 3502 if (parm->methods == &ehci_device_ctrl_methods) { 3503 3504 /* 3505 * The proof for the "nqtd" formula is illustrated like 3506 * this: 3507 * 3508 * +------------------------------------+ 3509 * | | 3510 * | |remainder -> | 3511 * | +-----+---+ | 3512 * | | xxx | x | frm 0 | 3513 * | +-----+---++ | 3514 * | | xxx | xx | frm 1 | 3515 * | +-----+----+ | 3516 * | ... | 3517 * +------------------------------------+ 3518 * 3519 * "xxx" means a completely full USB transfer descriptor 3520 * 3521 * "x" and "xx" means a short USB packet 3522 * 3523 * For the remainder of an USB transfer modulo 3524 * "max_data_length" we need two USB transfer descriptors. 3525 * One to transfer the remaining data and one to finalise 3526 * with a zero length packet in case the "force_short_xfer" 3527 * flag is set. We only need two USB transfer descriptors in 3528 * the case where the transfer length of the first one is a 3529 * factor of "max_frame_size". The rest of the needed USB 3530 * transfer descriptors is given by the buffer size divided 3531 * by the maximum data payload. 3532 */ 3533 parm->hc_max_packet_size = 0x400; 3534 parm->hc_max_packet_count = 1; 3535 parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX; 3536 xfer->flags_int.bdma_enable = 1; 3537 3538 usbd_transfer_setup_sub(parm); 3539 3540 nqh = 1; 3541 nqtd = ((2 * xfer->nframes) + 1 /* STATUS */ 3542 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3543 3544 } else if (parm->methods == &ehci_device_bulk_methods) { 3545 3546 parm->hc_max_packet_size = 0x400; 3547 parm->hc_max_packet_count = 1; 3548 parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX; 3549 xfer->flags_int.bdma_enable = 1; 3550 3551 usbd_transfer_setup_sub(parm); 3552 3553 nqh = 1; 3554 nqtd = ((2 * xfer->nframes) 3555 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3556 3557 } else if (parm->methods == &ehci_device_intr_methods) { 3558 3559 if (parm->speed == USB_SPEED_HIGH) { 3560 parm->hc_max_packet_size = 0x400; 3561 parm->hc_max_packet_count = 3; 3562 } else if (parm->speed == USB_SPEED_FULL) { 3563 parm->hc_max_packet_size = USB_FS_BYTES_PER_HS_UFRAME; 3564 parm->hc_max_packet_count = 1; 3565 } else { 3566 parm->hc_max_packet_size = USB_FS_BYTES_PER_HS_UFRAME / 8; 3567 parm->hc_max_packet_count = 1; 3568 } 3569 3570 parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX; 3571 xfer->flags_int.bdma_enable = 1; 3572 3573 usbd_transfer_setup_sub(parm); 3574 3575 nqh = 1; 3576 nqtd = ((2 * xfer->nframes) 3577 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3578 3579 } else if (parm->methods == &ehci_device_isoc_fs_methods) { 3580 3581 parm->hc_max_packet_size = 0x3FF; 3582 parm->hc_max_packet_count = 1; 3583 parm->hc_max_frame_size = 0x3FF; 3584 xfer->flags_int.bdma_enable = 1; 3585 3586 usbd_transfer_setup_sub(parm); 3587 3588 nsitd = xfer->nframes; 3589 3590 } else if (parm->methods == &ehci_device_isoc_hs_methods) { 3591 3592 parm->hc_max_packet_size = 0x400; 3593 parm->hc_max_packet_count = 3; 3594 parm->hc_max_frame_size = 0xC00; 3595 xfer->flags_int.bdma_enable = 1; 3596 3597 usbd_transfer_setup_sub(parm); 3598 3599 nitd = ((xfer->nframes + 7) / 8) << 3600 usbd_xfer_get_fps_shift(xfer); 3601 3602 } else { 3603 3604 parm->hc_max_packet_size = 0x400; 3605 parm->hc_max_packet_count = 1; 3606 parm->hc_max_frame_size = 0x400; 3607 3608 usbd_transfer_setup_sub(parm); 3609 } 3610 3611 alloc_dma_set: 3612 3613 if (parm->err) { 3614 return; 3615 } 3616 /* 3617 * Allocate queue heads and transfer descriptors 3618 */ 3619 last_obj = NULL; 3620 3621 if (usbd_transfer_setup_sub_malloc( 3622 parm, &pc, sizeof(ehci_itd_t), 3623 EHCI_ITD_ALIGN, nitd)) { 3624 parm->err = USB_ERR_NOMEM; 3625 return; 3626 } 3627 if (parm->buf) { 3628 for (n = 0; n != nitd; n++) { 3629 ehci_itd_t *td; 3630 3631 usbd_get_page(pc + n, 0, &page_info); 3632 3633 td = page_info.buffer; 3634 3635 /* init TD */ 3636 td->itd_self = htohc32(sc, page_info.physaddr | EHCI_LINK_ITD); 3637 td->obj_next = last_obj; 3638 td->page_cache = pc + n; 3639 3640 last_obj = td; 3641 3642 usb_pc_cpu_flush(pc + n); 3643 } 3644 } 3645 if (usbd_transfer_setup_sub_malloc( 3646 parm, &pc, sizeof(ehci_sitd_t), 3647 EHCI_SITD_ALIGN, nsitd)) { 3648 parm->err = USB_ERR_NOMEM; 3649 return; 3650 } 3651 if (parm->buf) { 3652 for (n = 0; n != nsitd; n++) { 3653 ehci_sitd_t *td; 3654 3655 usbd_get_page(pc + n, 0, &page_info); 3656 3657 td = page_info.buffer; 3658 3659 /* init TD */ 3660 td->sitd_self = htohc32(sc, page_info.physaddr | EHCI_LINK_SITD); 3661 td->obj_next = last_obj; 3662 td->page_cache = pc + n; 3663 3664 last_obj = td; 3665 3666 usb_pc_cpu_flush(pc + n); 3667 } 3668 } 3669 if (usbd_transfer_setup_sub_malloc( 3670 parm, &pc, sizeof(ehci_qtd_t), 3671 EHCI_QTD_ALIGN, nqtd)) { 3672 parm->err = USB_ERR_NOMEM; 3673 return; 3674 } 3675 if (parm->buf) { 3676 for (n = 0; n != nqtd; n++) { 3677 ehci_qtd_t *qtd; 3678 3679 usbd_get_page(pc + n, 0, &page_info); 3680 3681 qtd = page_info.buffer; 3682 3683 /* init TD */ 3684 qtd->qtd_self = htohc32(sc, page_info.physaddr); 3685 qtd->obj_next = last_obj; 3686 qtd->page_cache = pc + n; 3687 3688 last_obj = qtd; 3689 3690 usb_pc_cpu_flush(pc + n); 3691 } 3692 } 3693 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj; 3694 3695 last_obj = NULL; 3696 3697 if (usbd_transfer_setup_sub_malloc( 3698 parm, &pc, sizeof(ehci_qh_t), 3699 EHCI_QH_ALIGN, nqh)) { 3700 parm->err = USB_ERR_NOMEM; 3701 return; 3702 } 3703 if (parm->buf) { 3704 for (n = 0; n != nqh; n++) { 3705 ehci_qh_t *qh; 3706 3707 usbd_get_page(pc + n, 0, &page_info); 3708 3709 qh = page_info.buffer; 3710 3711 /* init QH */ 3712 qh->qh_self = htohc32(sc, page_info.physaddr | EHCI_LINK_QH); 3713 qh->obj_next = last_obj; 3714 qh->page_cache = pc + n; 3715 3716 last_obj = qh; 3717 3718 usb_pc_cpu_flush(pc + n); 3719 } 3720 } 3721 xfer->qh_start[xfer->flags_int.curr_dma_set] = last_obj; 3722 3723 if (!xfer->flags_int.curr_dma_set) { 3724 xfer->flags_int.curr_dma_set = 1; 3725 goto alloc_dma_set; 3726 } 3727 } 3728 3729 static void 3730 ehci_xfer_unsetup(struct usb_xfer *xfer) 3731 { 3732 return; 3733 } 3734 3735 static void 3736 ehci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 3737 struct usb_endpoint *ep) 3738 { 3739 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus); 3740 3741 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d)\n", 3742 ep, udev->address, 3743 edesc->bEndpointAddress, udev->flags.usb_mode, 3744 sc->sc_addr); 3745 3746 if (udev->device_index != sc->sc_addr) { 3747 3748 if ((udev->speed != USB_SPEED_HIGH) && 3749 ((udev->hs_hub_addr == 0) || 3750 (udev->hs_port_no == 0) || 3751 (udev->parent_hs_hub == NULL) || 3752 (udev->parent_hs_hub->hub == NULL))) { 3753 /* We need a transaction translator */ 3754 goto done; 3755 } 3756 switch (edesc->bmAttributes & UE_XFERTYPE) { 3757 case UE_CONTROL: 3758 ep->methods = &ehci_device_ctrl_methods; 3759 break; 3760 case UE_INTERRUPT: 3761 ep->methods = &ehci_device_intr_methods; 3762 break; 3763 case UE_ISOCHRONOUS: 3764 if (udev->speed == USB_SPEED_HIGH) { 3765 ep->methods = &ehci_device_isoc_hs_methods; 3766 } else if (udev->speed == USB_SPEED_FULL) { 3767 ep->methods = &ehci_device_isoc_fs_methods; 3768 } 3769 break; 3770 case UE_BULK: 3771 ep->methods = &ehci_device_bulk_methods; 3772 break; 3773 default: 3774 /* do nothing */ 3775 break; 3776 } 3777 } 3778 done: 3779 return; 3780 } 3781 3782 static void 3783 ehci_get_dma_delay(struct usb_device *udev, uint32_t *pus) 3784 { 3785 /* 3786 * Wait until the hardware has finished any possible use of 3787 * the transfer descriptor(s) and QH 3788 */ 3789 *pus = (1125); /* microseconds */ 3790 } 3791 3792 static void 3793 ehci_device_resume(struct usb_device *udev) 3794 { 3795 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus); 3796 struct usb_xfer *xfer; 3797 const struct usb_pipe_methods *methods; 3798 3799 DPRINTF("\n"); 3800 3801 USB_BUS_LOCK(udev->bus); 3802 3803 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3804 3805 if (xfer->xroot->udev == udev) { 3806 3807 methods = xfer->endpoint->methods; 3808 3809 if ((methods == &ehci_device_bulk_methods) || 3810 (methods == &ehci_device_ctrl_methods)) { 3811 EHCI_APPEND_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 3812 sc->sc_async_p_last); 3813 } 3814 if (methods == &ehci_device_intr_methods) { 3815 EHCI_APPEND_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 3816 sc->sc_intr_p_last[xfer->qh_pos]); 3817 } 3818 } 3819 } 3820 3821 USB_BUS_UNLOCK(udev->bus); 3822 3823 return; 3824 } 3825 3826 static void 3827 ehci_device_suspend(struct usb_device *udev) 3828 { 3829 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus); 3830 struct usb_xfer *xfer; 3831 const struct usb_pipe_methods *methods; 3832 3833 DPRINTF("\n"); 3834 3835 USB_BUS_LOCK(udev->bus); 3836 3837 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3838 3839 if (xfer->xroot->udev == udev) { 3840 3841 methods = xfer->endpoint->methods; 3842 3843 if ((methods == &ehci_device_bulk_methods) || 3844 (methods == &ehci_device_ctrl_methods)) { 3845 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 3846 sc->sc_async_p_last); 3847 } 3848 if (methods == &ehci_device_intr_methods) { 3849 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 3850 sc->sc_intr_p_last[xfer->qh_pos]); 3851 } 3852 } 3853 } 3854 3855 USB_BUS_UNLOCK(udev->bus); 3856 } 3857 3858 static void 3859 ehci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 3860 { 3861 struct ehci_softc *sc = EHCI_BUS2SC(bus); 3862 3863 switch (state) { 3864 case USB_HW_POWER_SUSPEND: 3865 case USB_HW_POWER_SHUTDOWN: 3866 ehci_suspend(sc); 3867 break; 3868 case USB_HW_POWER_RESUME: 3869 ehci_resume(sc); 3870 break; 3871 default: 3872 break; 3873 } 3874 } 3875 3876 static void 3877 ehci_set_hw_power(struct usb_bus *bus) 3878 { 3879 ehci_softc_t *sc = EHCI_BUS2SC(bus); 3880 uint32_t temp; 3881 uint32_t flags; 3882 3883 DPRINTF("\n"); 3884 3885 USB_BUS_LOCK(bus); 3886 3887 flags = bus->hw_power_state; 3888 3889 temp = EOREAD4(sc, EHCI_USBCMD); 3890 3891 temp &= ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 3892 3893 if (flags & (USB_HW_POWER_CONTROL | 3894 USB_HW_POWER_BULK)) { 3895 DPRINTF("Async is active\n"); 3896 temp |= EHCI_CMD_ASE; 3897 } 3898 if (flags & (USB_HW_POWER_INTERRUPT | 3899 USB_HW_POWER_ISOC)) { 3900 DPRINTF("Periodic is active\n"); 3901 temp |= EHCI_CMD_PSE; 3902 } 3903 EOWRITE4(sc, EHCI_USBCMD, temp); 3904 3905 USB_BUS_UNLOCK(bus); 3906 3907 return; 3908 } 3909 3910 static void 3911 ehci_start_dma_delay_second(struct usb_xfer *xfer) 3912 { 3913 struct ehci_softc *sc = EHCI_BUS2SC(xfer->xroot->bus); 3914 3915 DPRINTF("\n"); 3916 3917 /* trigger doorbell */ 3918 ehci_doorbell_async(sc); 3919 3920 /* give the doorbell 4ms */ 3921 usbd_transfer_timeout_ms(xfer, 3922 (void (*)(void *))&usb_dma_delay_done_cb, 4); 3923 } 3924 3925 /* 3926 * Ring the doorbell twice before freeing any DMA descriptors. Some host 3927 * controllers apparently cache the QH descriptors and need a message 3928 * that the cache needs to be discarded. 3929 */ 3930 static void 3931 ehci_start_dma_delay(struct usb_xfer *xfer) 3932 { 3933 struct ehci_softc *sc = EHCI_BUS2SC(xfer->xroot->bus); 3934 3935 DPRINTF("\n"); 3936 3937 /* trigger doorbell */ 3938 ehci_doorbell_async(sc); 3939 3940 /* give the doorbell 4ms */ 3941 usbd_transfer_timeout_ms(xfer, 3942 (void (*)(void *))&ehci_start_dma_delay_second, 4); 3943 } 3944 3945 static const struct usb_bus_methods ehci_bus_methods = 3946 { 3947 .endpoint_init = ehci_ep_init, 3948 .xfer_setup = ehci_xfer_setup, 3949 .xfer_unsetup = ehci_xfer_unsetup, 3950 .get_dma_delay = ehci_get_dma_delay, 3951 .device_resume = ehci_device_resume, 3952 .device_suspend = ehci_device_suspend, 3953 .set_hw_power = ehci_set_hw_power, 3954 .set_hw_power_sleep = ehci_set_hw_power_sleep, 3955 .roothub_exec = ehci_roothub_exec, 3956 .xfer_poll = ehci_do_poll, 3957 .start_dma_delay = ehci_start_dma_delay, 3958 }; 3959