1 /* $FreeBSD$ */ 2 /*- 3 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 4 * 5 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved. 6 * Copyright (c) 2004 The NetBSD Foundation, Inc. All rights reserved. 7 * Copyright (c) 2004 Lennart Augustsson. All rights reserved. 8 * Copyright (c) 2004 Charles M. Hannum. All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32 /* 33 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 34 * 35 * The EHCI 0.96 spec can be found at 36 * http://developer.intel.com/technology/usb/download/ehci-r096.pdf 37 * The EHCI 1.0 spec can be found at 38 * http://developer.intel.com/technology/usb/download/ehci-r10.pdf 39 * and the USB 2.0 spec at 40 * http://www.usb.org/developers/docs/usb_20.zip 41 * 42 */ 43 44 /* 45 * TODO: 46 * 1) command failures are not recovered correctly 47 */ 48 49 #ifdef USB_GLOBAL_INCLUDE_FILE 50 #include USB_GLOBAL_INCLUDE_FILE 51 #else 52 #include <sys/stdint.h> 53 #include <sys/stddef.h> 54 #include <sys/param.h> 55 #include <sys/queue.h> 56 #include <sys/types.h> 57 #include <sys/systm.h> 58 #include <sys/kernel.h> 59 #include <sys/bus.h> 60 #include <sys/module.h> 61 #include <sys/lock.h> 62 #include <sys/mutex.h> 63 #include <sys/condvar.h> 64 #include <sys/sysctl.h> 65 #include <sys/sx.h> 66 #include <sys/unistd.h> 67 #include <sys/callout.h> 68 #include <sys/malloc.h> 69 #include <sys/priv.h> 70 71 #include <dev/usb/usb.h> 72 #include <dev/usb/usbdi.h> 73 74 #define USB_DEBUG_VAR ehcidebug 75 76 #include <dev/usb/usb_core.h> 77 #include <dev/usb/usb_debug.h> 78 #include <dev/usb/usb_busdma.h> 79 #include <dev/usb/usb_process.h> 80 #include <dev/usb/usb_transfer.h> 81 #include <dev/usb/usb_device.h> 82 #include <dev/usb/usb_hub.h> 83 #include <dev/usb/usb_util.h> 84 85 #include <dev/usb/usb_controller.h> 86 #include <dev/usb/usb_bus.h> 87 #endif /* USB_GLOBAL_INCLUDE_FILE */ 88 89 #include <dev/usb/controller/ehci.h> 90 #include <dev/usb/controller/ehcireg.h> 91 92 #define EHCI_BUS2SC(bus) \ 93 ((ehci_softc_t *)(((uint8_t *)(bus)) - \ 94 ((uint8_t *)&(((ehci_softc_t *)0)->sc_bus)))) 95 96 #ifdef USB_DEBUG 97 static int ehcidebug = 0; 98 static int ehcinohighspeed = 0; 99 static int ehciiaadbug = 0; 100 static int ehcilostintrbug = 0; 101 102 static SYSCTL_NODE(_hw_usb, OID_AUTO, ehci, CTLFLAG_RW | CTLFLAG_MPSAFE, 0, 103 "USB ehci"); 104 SYSCTL_INT(_hw_usb_ehci, OID_AUTO, debug, CTLFLAG_RWTUN, 105 &ehcidebug, 0, "Debug level"); 106 SYSCTL_INT(_hw_usb_ehci, OID_AUTO, no_hs, CTLFLAG_RWTUN, 107 &ehcinohighspeed, 0, "Disable High Speed USB"); 108 SYSCTL_INT(_hw_usb_ehci, OID_AUTO, iaadbug, CTLFLAG_RWTUN, 109 &ehciiaadbug, 0, "Enable doorbell bug workaround"); 110 SYSCTL_INT(_hw_usb_ehci, OID_AUTO, lostintrbug, CTLFLAG_RWTUN, 111 &ehcilostintrbug, 0, "Enable lost interrupt bug workaround"); 112 113 static void ehci_dump_regs(ehci_softc_t *sc); 114 static void ehci_dump_sqh(ehci_softc_t *sc, ehci_qh_t *sqh); 115 116 #endif 117 118 #define EHCI_INTR_ENDPT 1 119 120 static const struct usb_bus_methods ehci_bus_methods; 121 static const struct usb_pipe_methods ehci_device_bulk_methods; 122 static const struct usb_pipe_methods ehci_device_ctrl_methods; 123 static const struct usb_pipe_methods ehci_device_intr_methods; 124 static const struct usb_pipe_methods ehci_device_isoc_fs_methods; 125 static const struct usb_pipe_methods ehci_device_isoc_hs_methods; 126 127 static void ehci_do_poll(struct usb_bus *); 128 static void ehci_device_done(struct usb_xfer *, usb_error_t); 129 static uint8_t ehci_check_transfer(struct usb_xfer *); 130 static void ehci_timeout(void *); 131 static void ehci_poll_timeout(void *); 132 133 static void ehci_root_intr(ehci_softc_t *sc); 134 135 struct ehci_std_temp { 136 ehci_softc_t *sc; 137 struct usb_page_cache *pc; 138 ehci_qtd_t *td; 139 ehci_qtd_t *td_next; 140 uint32_t average; 141 uint32_t qtd_status; 142 uint32_t len; 143 uint16_t max_frame_size; 144 uint8_t shortpkt; 145 uint8_t auto_data_toggle; 146 uint8_t setup_alt_next; 147 uint8_t last_frame; 148 }; 149 150 void 151 ehci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb) 152 { 153 ehci_softc_t *sc = EHCI_BUS2SC(bus); 154 uint32_t i; 155 156 cb(bus, &sc->sc_hw.pframes_pc, &sc->sc_hw.pframes_pg, 157 sizeof(uint32_t) * EHCI_FRAMELIST_COUNT, EHCI_FRAMELIST_ALIGN); 158 159 cb(bus, &sc->sc_hw.terminate_pc, &sc->sc_hw.terminate_pg, 160 sizeof(struct ehci_qh_sub), EHCI_QH_ALIGN); 161 162 cb(bus, &sc->sc_hw.async_start_pc, &sc->sc_hw.async_start_pg, 163 sizeof(ehci_qh_t), EHCI_QH_ALIGN); 164 165 for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 166 cb(bus, sc->sc_hw.intr_start_pc + i, 167 sc->sc_hw.intr_start_pg + i, 168 sizeof(ehci_qh_t), EHCI_QH_ALIGN); 169 } 170 171 for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 172 cb(bus, sc->sc_hw.isoc_hs_start_pc + i, 173 sc->sc_hw.isoc_hs_start_pg + i, 174 sizeof(ehci_itd_t), EHCI_ITD_ALIGN); 175 } 176 177 for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 178 cb(bus, sc->sc_hw.isoc_fs_start_pc + i, 179 sc->sc_hw.isoc_fs_start_pg + i, 180 sizeof(ehci_sitd_t), EHCI_SITD_ALIGN); 181 } 182 } 183 184 usb_error_t 185 ehci_reset(ehci_softc_t *sc) 186 { 187 uint32_t hcr; 188 int i; 189 190 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 191 for (i = 0; i < 100; i++) { 192 usb_pause_mtx(NULL, hz / 128); 193 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 194 if (!hcr) { 195 if (sc->sc_vendor_post_reset != NULL) 196 sc->sc_vendor_post_reset(sc); 197 return (0); 198 } 199 } 200 device_printf(sc->sc_bus.bdev, "reset timeout\n"); 201 return (USB_ERR_IOERROR); 202 } 203 204 static usb_error_t 205 ehci_hcreset(ehci_softc_t *sc) 206 { 207 uint32_t hcr; 208 int i; 209 210 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 211 for (i = 0; i < 100; i++) { 212 usb_pause_mtx(NULL, hz / 128); 213 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 214 if (hcr) 215 break; 216 } 217 if (!hcr) 218 /* 219 * Fall through and try reset anyway even though 220 * Table 2-9 in the EHCI spec says this will result 221 * in undefined behavior. 222 */ 223 device_printf(sc->sc_bus.bdev, "stop timeout\n"); 224 225 return (ehci_reset(sc)); 226 } 227 228 static int 229 ehci_init_sub(struct ehci_softc *sc) 230 { 231 struct usb_page_search buf_res; 232 uint32_t cparams; 233 uint32_t hcr; 234 uint8_t i; 235 236 cparams = EREAD4(sc, EHCI_HCCPARAMS); 237 238 DPRINTF("cparams=0x%x\n", cparams); 239 240 if (EHCI_HCC_64BIT(cparams)) { 241 DPRINTF("HCC uses 64-bit structures\n"); 242 243 /* MUST clear segment register if 64 bit capable */ 244 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 245 } 246 247 usbd_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res); 248 EOWRITE4(sc, EHCI_PERIODICLISTBASE, buf_res.physaddr); 249 250 usbd_get_page(&sc->sc_hw.async_start_pc, 0, &buf_res); 251 EOWRITE4(sc, EHCI_ASYNCLISTADDR, buf_res.physaddr | EHCI_LINK_QH); 252 253 /* enable interrupts */ 254 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 255 256 /* turn on controller */ 257 EOWRITE4(sc, EHCI_USBCMD, 258 EHCI_CMD_ITC_1 | /* 1 microframes interrupt delay */ 259 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 260 EHCI_CMD_ASE | 261 EHCI_CMD_PSE | 262 EHCI_CMD_RS); 263 264 /* Take over port ownership */ 265 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 266 267 for (i = 0; i < 100; i++) { 268 usb_pause_mtx(NULL, hz / 128); 269 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 270 if (!hcr) { 271 break; 272 } 273 } 274 if (hcr) { 275 device_printf(sc->sc_bus.bdev, "run timeout\n"); 276 return (USB_ERR_IOERROR); 277 } 278 return (USB_ERR_NORMAL_COMPLETION); 279 } 280 281 usb_error_t 282 ehci_init(ehci_softc_t *sc) 283 { 284 struct usb_page_search buf_res; 285 uint32_t version; 286 uint32_t sparams; 287 uint16_t i; 288 uint16_t x; 289 uint16_t y; 290 uint16_t bit; 291 usb_error_t err = 0; 292 293 DPRINTF("start\n"); 294 295 usb_callout_init_mtx(&sc->sc_tmo_pcd, &sc->sc_bus.bus_mtx, 0); 296 usb_callout_init_mtx(&sc->sc_tmo_poll, &sc->sc_bus.bus_mtx, 0); 297 298 sc->sc_offs = EHCI_CAPLENGTH(EREAD4(sc, EHCI_CAPLEN_HCIVERSION)); 299 300 #ifdef USB_DEBUG 301 if (ehciiaadbug) 302 sc->sc_flags |= EHCI_SCFLG_IAADBUG; 303 if (ehcilostintrbug) 304 sc->sc_flags |= EHCI_SCFLG_LOSTINTRBUG; 305 if (ehcidebug > 2) { 306 ehci_dump_regs(sc); 307 } 308 #endif 309 310 version = EHCI_HCIVERSION(EREAD4(sc, EHCI_CAPLEN_HCIVERSION)); 311 device_printf(sc->sc_bus.bdev, "EHCI version %x.%x\n", 312 version >> 8, version & 0xff); 313 314 sparams = EREAD4(sc, EHCI_HCSPARAMS); 315 DPRINTF("sparams=0x%x\n", sparams); 316 317 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 318 sc->sc_bus.usbrev = USB_REV_2_0; 319 320 if (!(sc->sc_flags & EHCI_SCFLG_DONTRESET)) { 321 /* Reset the controller */ 322 DPRINTF("%s: resetting\n", 323 device_get_nameunit(sc->sc_bus.bdev)); 324 325 err = ehci_hcreset(sc); 326 if (err) { 327 device_printf(sc->sc_bus.bdev, "reset timeout\n"); 328 return (err); 329 } 330 } 331 332 /* 333 * use current frame-list-size selection 0: 1024*4 bytes 1: 512*4 334 * bytes 2: 256*4 bytes 3: unknown 335 */ 336 if (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD)) == 3) { 337 device_printf(sc->sc_bus.bdev, "invalid frame-list-size\n"); 338 return (USB_ERR_IOERROR); 339 } 340 /* set up the bus struct */ 341 sc->sc_bus.methods = &ehci_bus_methods; 342 343 sc->sc_eintrs = EHCI_NORMAL_INTRS; 344 345 if (1) { 346 struct ehci_qh_sub *qh; 347 348 usbd_get_page(&sc->sc_hw.terminate_pc, 0, &buf_res); 349 350 qh = buf_res.buffer; 351 352 sc->sc_terminate_self = htohc32(sc, buf_res.physaddr); 353 354 /* init terminate TD */ 355 qh->qtd_next = 356 htohc32(sc, EHCI_LINK_TERMINATE); 357 qh->qtd_altnext = 358 htohc32(sc, EHCI_LINK_TERMINATE); 359 qh->qtd_status = 360 htohc32(sc, EHCI_QTD_HALTED); 361 } 362 363 for (i = 0; i < EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 364 ehci_qh_t *qh; 365 366 usbd_get_page(sc->sc_hw.intr_start_pc + i, 0, &buf_res); 367 368 qh = buf_res.buffer; 369 370 /* initialize page cache pointer */ 371 372 qh->page_cache = sc->sc_hw.intr_start_pc + i; 373 374 /* store a pointer to queue head */ 375 376 sc->sc_intr_p_last[i] = qh; 377 378 qh->qh_self = 379 htohc32(sc, buf_res.physaddr) | 380 htohc32(sc, EHCI_LINK_QH); 381 382 qh->qh_endp = 383 htohc32(sc, EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 384 qh->qh_endphub = 385 htohc32(sc, EHCI_QH_SET_MULT(1)); 386 qh->qh_curqtd = 0; 387 388 qh->qh_qtd.qtd_next = 389 htohc32(sc, EHCI_LINK_TERMINATE); 390 qh->qh_qtd.qtd_altnext = 391 htohc32(sc, EHCI_LINK_TERMINATE); 392 qh->qh_qtd.qtd_status = 393 htohc32(sc, EHCI_QTD_HALTED); 394 } 395 396 /* 397 * the QHs are arranged to give poll intervals that are 398 * powers of 2 times 1ms 399 */ 400 bit = EHCI_VIRTUAL_FRAMELIST_COUNT / 2; 401 while (bit) { 402 x = bit; 403 while (x & bit) { 404 ehci_qh_t *qh_x; 405 ehci_qh_t *qh_y; 406 407 y = (x ^ bit) | (bit / 2); 408 409 qh_x = sc->sc_intr_p_last[x]; 410 qh_y = sc->sc_intr_p_last[y]; 411 412 /* 413 * the next QH has half the poll interval 414 */ 415 qh_x->qh_link = qh_y->qh_self; 416 417 x++; 418 } 419 bit >>= 1; 420 } 421 422 if (1) { 423 ehci_qh_t *qh; 424 425 qh = sc->sc_intr_p_last[0]; 426 427 /* the last (1ms) QH terminates */ 428 qh->qh_link = htohc32(sc, EHCI_LINK_TERMINATE); 429 } 430 for (i = 0; i < EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 431 ehci_sitd_t *sitd; 432 ehci_itd_t *itd; 433 434 usbd_get_page(sc->sc_hw.isoc_fs_start_pc + i, 0, &buf_res); 435 436 sitd = buf_res.buffer; 437 438 /* initialize page cache pointer */ 439 440 sitd->page_cache = sc->sc_hw.isoc_fs_start_pc + i; 441 442 /* store a pointer to the transfer descriptor */ 443 444 sc->sc_isoc_fs_p_last[i] = sitd; 445 446 /* initialize full speed isochronous */ 447 448 sitd->sitd_self = 449 htohc32(sc, buf_res.physaddr) | 450 htohc32(sc, EHCI_LINK_SITD); 451 452 sitd->sitd_back = 453 htohc32(sc, EHCI_LINK_TERMINATE); 454 455 sitd->sitd_next = 456 sc->sc_intr_p_last[i | (EHCI_VIRTUAL_FRAMELIST_COUNT / 2)]->qh_self; 457 458 459 usbd_get_page(sc->sc_hw.isoc_hs_start_pc + i, 0, &buf_res); 460 461 itd = buf_res.buffer; 462 463 /* initialize page cache pointer */ 464 465 itd->page_cache = sc->sc_hw.isoc_hs_start_pc + i; 466 467 /* store a pointer to the transfer descriptor */ 468 469 sc->sc_isoc_hs_p_last[i] = itd; 470 471 /* initialize high speed isochronous */ 472 473 itd->itd_self = 474 htohc32(sc, buf_res.physaddr) | 475 htohc32(sc, EHCI_LINK_ITD); 476 477 itd->itd_next = 478 sitd->sitd_self; 479 } 480 481 usbd_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res); 482 483 if (1) { 484 uint32_t *pframes; 485 486 pframes = buf_res.buffer; 487 488 /* 489 * execution order: 490 * pframes -> high speed isochronous -> 491 * full speed isochronous -> interrupt QH's 492 */ 493 for (i = 0; i < EHCI_FRAMELIST_COUNT; i++) { 494 pframes[i] = sc->sc_isoc_hs_p_last 495 [i & (EHCI_VIRTUAL_FRAMELIST_COUNT - 1)]->itd_self; 496 } 497 } 498 usbd_get_page(&sc->sc_hw.async_start_pc, 0, &buf_res); 499 500 if (1) { 501 502 ehci_qh_t *qh; 503 504 qh = buf_res.buffer; 505 506 /* initialize page cache pointer */ 507 508 qh->page_cache = &sc->sc_hw.async_start_pc; 509 510 /* store a pointer to the queue head */ 511 512 sc->sc_async_p_last = qh; 513 514 /* init dummy QH that starts the async list */ 515 516 qh->qh_self = 517 htohc32(sc, buf_res.physaddr) | 518 htohc32(sc, EHCI_LINK_QH); 519 520 /* fill the QH */ 521 qh->qh_endp = 522 htohc32(sc, EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 523 qh->qh_endphub = htohc32(sc, EHCI_QH_SET_MULT(1)); 524 qh->qh_link = qh->qh_self; 525 qh->qh_curqtd = 0; 526 527 /* fill the overlay qTD */ 528 qh->qh_qtd.qtd_next = htohc32(sc, EHCI_LINK_TERMINATE); 529 qh->qh_qtd.qtd_altnext = htohc32(sc, EHCI_LINK_TERMINATE); 530 qh->qh_qtd.qtd_status = htohc32(sc, EHCI_QTD_HALTED); 531 } 532 /* flush all cache into memory */ 533 534 usb_bus_mem_flush_all(&sc->sc_bus, &ehci_iterate_hw_softc); 535 536 #ifdef USB_DEBUG 537 if (ehcidebug) { 538 ehci_dump_sqh(sc, sc->sc_async_p_last); 539 } 540 #endif 541 542 /* finial setup */ 543 err = ehci_init_sub(sc); 544 545 if (!err) { 546 /* catch any lost interrupts */ 547 ehci_do_poll(&sc->sc_bus); 548 } 549 return (err); 550 } 551 552 /* 553 * shut down the controller when the system is going down 554 */ 555 void 556 ehci_detach(ehci_softc_t *sc) 557 { 558 USB_BUS_LOCK(&sc->sc_bus); 559 560 usb_callout_stop(&sc->sc_tmo_pcd); 561 usb_callout_stop(&sc->sc_tmo_poll); 562 563 EOWRITE4(sc, EHCI_USBINTR, 0); 564 USB_BUS_UNLOCK(&sc->sc_bus); 565 566 if (ehci_hcreset(sc)) { 567 DPRINTF("reset failed!\n"); 568 } 569 570 /* XXX let stray task complete */ 571 usb_pause_mtx(NULL, hz / 20); 572 573 usb_callout_drain(&sc->sc_tmo_pcd); 574 usb_callout_drain(&sc->sc_tmo_poll); 575 } 576 577 static void 578 ehci_suspend(ehci_softc_t *sc) 579 { 580 DPRINTF("stopping the HC\n"); 581 582 /* reset HC */ 583 ehci_hcreset(sc); 584 } 585 586 static void 587 ehci_resume(ehci_softc_t *sc) 588 { 589 /* reset HC */ 590 ehci_hcreset(sc); 591 592 /* setup HC */ 593 ehci_init_sub(sc); 594 595 /* catch any lost interrupts */ 596 ehci_do_poll(&sc->sc_bus); 597 } 598 599 #ifdef USB_DEBUG 600 static void 601 ehci_dump_regs(ehci_softc_t *sc) 602 { 603 uint32_t i; 604 605 i = EOREAD4(sc, EHCI_USBCMD); 606 printf("cmd=0x%08x\n", i); 607 608 if (i & EHCI_CMD_ITC_1) 609 printf(" EHCI_CMD_ITC_1\n"); 610 if (i & EHCI_CMD_ITC_2) 611 printf(" EHCI_CMD_ITC_2\n"); 612 if (i & EHCI_CMD_ITC_4) 613 printf(" EHCI_CMD_ITC_4\n"); 614 if (i & EHCI_CMD_ITC_8) 615 printf(" EHCI_CMD_ITC_8\n"); 616 if (i & EHCI_CMD_ITC_16) 617 printf(" EHCI_CMD_ITC_16\n"); 618 if (i & EHCI_CMD_ITC_32) 619 printf(" EHCI_CMD_ITC_32\n"); 620 if (i & EHCI_CMD_ITC_64) 621 printf(" EHCI_CMD_ITC_64\n"); 622 if (i & EHCI_CMD_ASPME) 623 printf(" EHCI_CMD_ASPME\n"); 624 if (i & EHCI_CMD_ASPMC) 625 printf(" EHCI_CMD_ASPMC\n"); 626 if (i & EHCI_CMD_LHCR) 627 printf(" EHCI_CMD_LHCR\n"); 628 if (i & EHCI_CMD_IAAD) 629 printf(" EHCI_CMD_IAAD\n"); 630 if (i & EHCI_CMD_ASE) 631 printf(" EHCI_CMD_ASE\n"); 632 if (i & EHCI_CMD_PSE) 633 printf(" EHCI_CMD_PSE\n"); 634 if (i & EHCI_CMD_FLS_M) 635 printf(" EHCI_CMD_FLS_M\n"); 636 if (i & EHCI_CMD_HCRESET) 637 printf(" EHCI_CMD_HCRESET\n"); 638 if (i & EHCI_CMD_RS) 639 printf(" EHCI_CMD_RS\n"); 640 641 i = EOREAD4(sc, EHCI_USBSTS); 642 643 printf("sts=0x%08x\n", i); 644 645 if (i & EHCI_STS_ASS) 646 printf(" EHCI_STS_ASS\n"); 647 if (i & EHCI_STS_PSS) 648 printf(" EHCI_STS_PSS\n"); 649 if (i & EHCI_STS_REC) 650 printf(" EHCI_STS_REC\n"); 651 if (i & EHCI_STS_HCH) 652 printf(" EHCI_STS_HCH\n"); 653 if (i & EHCI_STS_IAA) 654 printf(" EHCI_STS_IAA\n"); 655 if (i & EHCI_STS_HSE) 656 printf(" EHCI_STS_HSE\n"); 657 if (i & EHCI_STS_FLR) 658 printf(" EHCI_STS_FLR\n"); 659 if (i & EHCI_STS_PCD) 660 printf(" EHCI_STS_PCD\n"); 661 if (i & EHCI_STS_ERRINT) 662 printf(" EHCI_STS_ERRINT\n"); 663 if (i & EHCI_STS_INT) 664 printf(" EHCI_STS_INT\n"); 665 666 printf("ien=0x%08x\n", 667 EOREAD4(sc, EHCI_USBINTR)); 668 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 669 EOREAD4(sc, EHCI_FRINDEX), 670 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 671 EOREAD4(sc, EHCI_PERIODICLISTBASE), 672 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 673 for (i = 1; i <= sc->sc_noport; i++) { 674 printf("port %d status=0x%08x\n", i, 675 EOREAD4(sc, EHCI_PORTSC(i))); 676 } 677 } 678 679 static void 680 ehci_dump_link(ehci_softc_t *sc, uint32_t link, int type) 681 { 682 link = hc32toh(sc, link); 683 printf("0x%08x", link); 684 if (link & EHCI_LINK_TERMINATE) 685 printf("<T>"); 686 else { 687 printf("<"); 688 if (type) { 689 switch (EHCI_LINK_TYPE(link)) { 690 case EHCI_LINK_ITD: 691 printf("ITD"); 692 break; 693 case EHCI_LINK_QH: 694 printf("QH"); 695 break; 696 case EHCI_LINK_SITD: 697 printf("SITD"); 698 break; 699 case EHCI_LINK_FSTN: 700 printf("FSTN"); 701 break; 702 } 703 } 704 printf(">"); 705 } 706 } 707 708 static void 709 ehci_dump_qtd(ehci_softc_t *sc, ehci_qtd_t *qtd) 710 { 711 uint32_t s; 712 713 printf(" next="); 714 ehci_dump_link(sc, qtd->qtd_next, 0); 715 printf(" altnext="); 716 ehci_dump_link(sc, qtd->qtd_altnext, 0); 717 printf("\n"); 718 s = hc32toh(sc, qtd->qtd_status); 719 printf(" status=0x%08x: toggle=%d bytes=0x%x ioc=%d c_page=0x%x\n", 720 s, EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_BYTES(s), 721 EHCI_QTD_GET_IOC(s), EHCI_QTD_GET_C_PAGE(s)); 722 printf(" cerr=%d pid=%d stat=%s%s%s%s%s%s%s%s\n", 723 EHCI_QTD_GET_CERR(s), EHCI_QTD_GET_PID(s), 724 (s & EHCI_QTD_ACTIVE) ? "ACTIVE" : "NOT_ACTIVE", 725 (s & EHCI_QTD_HALTED) ? "-HALTED" : "", 726 (s & EHCI_QTD_BUFERR) ? "-BUFERR" : "", 727 (s & EHCI_QTD_BABBLE) ? "-BABBLE" : "", 728 (s & EHCI_QTD_XACTERR) ? "-XACTERR" : "", 729 (s & EHCI_QTD_MISSEDMICRO) ? "-MISSED" : "", 730 (s & EHCI_QTD_SPLITXSTATE) ? "-SPLIT" : "", 731 (s & EHCI_QTD_PINGSTATE) ? "-PING" : ""); 732 733 for (s = 0; s < 5; s++) { 734 printf(" buffer[%d]=0x%08x\n", s, 735 hc32toh(sc, qtd->qtd_buffer[s])); 736 } 737 for (s = 0; s < 5; s++) { 738 printf(" buffer_hi[%d]=0x%08x\n", s, 739 hc32toh(sc, qtd->qtd_buffer_hi[s])); 740 } 741 } 742 743 static uint8_t 744 ehci_dump_sqtd(ehci_softc_t *sc, ehci_qtd_t *sqtd) 745 { 746 uint8_t temp; 747 748 usb_pc_cpu_invalidate(sqtd->page_cache); 749 printf("QTD(%p) at 0x%08x:\n", sqtd, hc32toh(sc, sqtd->qtd_self)); 750 ehci_dump_qtd(sc, sqtd); 751 temp = (sqtd->qtd_next & htohc32(sc, EHCI_LINK_TERMINATE)) ? 1 : 0; 752 return (temp); 753 } 754 755 static void 756 ehci_dump_sqtds(ehci_softc_t *sc, ehci_qtd_t *sqtd) 757 { 758 uint16_t i; 759 uint8_t stop; 760 761 stop = 0; 762 for (i = 0; sqtd && (i < 20) && !stop; sqtd = sqtd->obj_next, i++) { 763 stop = ehci_dump_sqtd(sc, sqtd); 764 } 765 if (sqtd) { 766 printf("dump aborted, too many TDs\n"); 767 } 768 } 769 770 static void 771 ehci_dump_sqh(ehci_softc_t *sc, ehci_qh_t *qh) 772 { 773 uint32_t endp; 774 uint32_t endphub; 775 776 usb_pc_cpu_invalidate(qh->page_cache); 777 printf("QH(%p) at 0x%08x:\n", qh, hc32toh(sc, qh->qh_self) & ~0x1F); 778 printf(" link="); 779 ehci_dump_link(sc, qh->qh_link, 1); 780 printf("\n"); 781 endp = hc32toh(sc, qh->qh_endp); 782 printf(" endp=0x%08x\n", endp); 783 printf(" addr=0x%02x inact=%d endpt=%d eps=%d dtc=%d hrecl=%d\n", 784 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 785 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp), 786 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp)); 787 printf(" mpl=0x%x ctl=%d nrl=%d\n", 788 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_CTL(endp), 789 EHCI_QH_GET_NRL(endp)); 790 endphub = hc32toh(sc, qh->qh_endphub); 791 printf(" endphub=0x%08x\n", endphub); 792 printf(" smask=0x%02x cmask=0x%02x huba=0x%02x port=%d mult=%d\n", 793 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 794 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 795 EHCI_QH_GET_MULT(endphub)); 796 printf(" curqtd="); 797 ehci_dump_link(sc, qh->qh_curqtd, 0); 798 printf("\n"); 799 printf("Overlay qTD:\n"); 800 ehci_dump_qtd(sc, (void *)&qh->qh_qtd); 801 } 802 803 static void 804 ehci_dump_sitd(ehci_softc_t *sc, ehci_sitd_t *sitd) 805 { 806 usb_pc_cpu_invalidate(sitd->page_cache); 807 printf("SITD(%p) at 0x%08x\n", sitd, hc32toh(sc, sitd->sitd_self) & ~0x1F); 808 printf(" next=0x%08x\n", hc32toh(sc, sitd->sitd_next)); 809 printf(" portaddr=0x%08x dir=%s addr=%d endpt=0x%x port=0x%x huba=0x%x\n", 810 hc32toh(sc, sitd->sitd_portaddr), 811 (sitd->sitd_portaddr & htohc32(sc, EHCI_SITD_SET_DIR_IN)) 812 ? "in" : "out", 813 EHCI_SITD_GET_ADDR(hc32toh(sc, sitd->sitd_portaddr)), 814 EHCI_SITD_GET_ENDPT(hc32toh(sc, sitd->sitd_portaddr)), 815 EHCI_SITD_GET_PORT(hc32toh(sc, sitd->sitd_portaddr)), 816 EHCI_SITD_GET_HUBA(hc32toh(sc, sitd->sitd_portaddr))); 817 printf(" mask=0x%08x\n", hc32toh(sc, sitd->sitd_mask)); 818 printf(" status=0x%08x <%s> len=0x%x\n", hc32toh(sc, sitd->sitd_status), 819 (sitd->sitd_status & htohc32(sc, EHCI_SITD_ACTIVE)) ? "ACTIVE" : "", 820 EHCI_SITD_GET_LEN(hc32toh(sc, sitd->sitd_status))); 821 printf(" back=0x%08x, bp=0x%08x,0x%08x,0x%08x,0x%08x\n", 822 hc32toh(sc, sitd->sitd_back), 823 hc32toh(sc, sitd->sitd_bp[0]), 824 hc32toh(sc, sitd->sitd_bp[1]), 825 hc32toh(sc, sitd->sitd_bp_hi[0]), 826 hc32toh(sc, sitd->sitd_bp_hi[1])); 827 } 828 829 static void 830 ehci_dump_itd(ehci_softc_t *sc, ehci_itd_t *itd) 831 { 832 usb_pc_cpu_invalidate(itd->page_cache); 833 printf("ITD(%p) at 0x%08x\n", itd, hc32toh(sc, itd->itd_self) & ~0x1F); 834 printf(" next=0x%08x\n", hc32toh(sc, itd->itd_next)); 835 printf(" status[0]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[0]), 836 (itd->itd_status[0] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 837 printf(" status[1]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[1]), 838 (itd->itd_status[1] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 839 printf(" status[2]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[2]), 840 (itd->itd_status[2] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 841 printf(" status[3]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[3]), 842 (itd->itd_status[3] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 843 printf(" status[4]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[4]), 844 (itd->itd_status[4] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 845 printf(" status[5]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[5]), 846 (itd->itd_status[5] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 847 printf(" status[6]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[6]), 848 (itd->itd_status[6] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 849 printf(" status[7]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[7]), 850 (itd->itd_status[7] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 851 printf(" bp[0]=0x%08x\n", hc32toh(sc, itd->itd_bp[0])); 852 printf(" addr=0x%02x; endpt=0x%01x\n", 853 EHCI_ITD_GET_ADDR(hc32toh(sc, itd->itd_bp[0])), 854 EHCI_ITD_GET_ENDPT(hc32toh(sc, itd->itd_bp[0]))); 855 printf(" bp[1]=0x%08x\n", hc32toh(sc, itd->itd_bp[1])); 856 printf(" dir=%s; mpl=0x%02x\n", 857 (hc32toh(sc, itd->itd_bp[1]) & EHCI_ITD_SET_DIR_IN) ? "in" : "out", 858 EHCI_ITD_GET_MPL(hc32toh(sc, itd->itd_bp[1]))); 859 printf(" bp[2..6]=0x%08x,0x%08x,0x%08x,0x%08x,0x%08x\n", 860 hc32toh(sc, itd->itd_bp[2]), 861 hc32toh(sc, itd->itd_bp[3]), 862 hc32toh(sc, itd->itd_bp[4]), 863 hc32toh(sc, itd->itd_bp[5]), 864 hc32toh(sc, itd->itd_bp[6])); 865 printf(" bp_hi=0x%08x,0x%08x,0x%08x,0x%08x,\n" 866 " 0x%08x,0x%08x,0x%08x\n", 867 hc32toh(sc, itd->itd_bp_hi[0]), 868 hc32toh(sc, itd->itd_bp_hi[1]), 869 hc32toh(sc, itd->itd_bp_hi[2]), 870 hc32toh(sc, itd->itd_bp_hi[3]), 871 hc32toh(sc, itd->itd_bp_hi[4]), 872 hc32toh(sc, itd->itd_bp_hi[5]), 873 hc32toh(sc, itd->itd_bp_hi[6])); 874 } 875 876 static void 877 ehci_dump_isoc(ehci_softc_t *sc) 878 { 879 ehci_itd_t *itd; 880 ehci_sitd_t *sitd; 881 uint16_t max = 1000; 882 uint16_t pos; 883 884 pos = (EOREAD4(sc, EHCI_FRINDEX) / 8) & 885 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 886 887 printf("%s: isochronous dump from frame 0x%03x:\n", 888 __FUNCTION__, pos); 889 890 itd = sc->sc_isoc_hs_p_last[pos]; 891 sitd = sc->sc_isoc_fs_p_last[pos]; 892 893 while (itd && max && max--) { 894 ehci_dump_itd(sc, itd); 895 itd = itd->prev; 896 } 897 898 while (sitd && max && max--) { 899 ehci_dump_sitd(sc, sitd); 900 sitd = sitd->prev; 901 } 902 } 903 904 #endif 905 906 static void 907 ehci_transfer_intr_enqueue(struct usb_xfer *xfer) 908 { 909 /* check for early completion */ 910 if (ehci_check_transfer(xfer)) { 911 return; 912 } 913 /* put transfer on interrupt queue */ 914 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 915 916 /* start timeout, if any */ 917 if (xfer->timeout != 0) { 918 usbd_transfer_timeout_ms(xfer, &ehci_timeout, xfer->timeout); 919 } 920 } 921 922 #define EHCI_APPEND_FS_TD(std,last) (last) = _ehci_append_fs_td(std,last) 923 static ehci_sitd_t * 924 _ehci_append_fs_td(ehci_sitd_t *std, ehci_sitd_t *last) 925 { 926 DPRINTFN(11, "%p to %p\n", std, last); 927 928 /* (sc->sc_bus.mtx) must be locked */ 929 930 std->next = last->next; 931 std->sitd_next = last->sitd_next; 932 933 std->prev = last; 934 935 usb_pc_cpu_flush(std->page_cache); 936 937 /* 938 * the last->next->prev is never followed: std->next->prev = std; 939 */ 940 last->next = std; 941 last->sitd_next = std->sitd_self; 942 943 usb_pc_cpu_flush(last->page_cache); 944 945 return (std); 946 } 947 948 #define EHCI_APPEND_HS_TD(std,last) (last) = _ehci_append_hs_td(std,last) 949 static ehci_itd_t * 950 _ehci_append_hs_td(ehci_itd_t *std, ehci_itd_t *last) 951 { 952 DPRINTFN(11, "%p to %p\n", std, last); 953 954 /* (sc->sc_bus.mtx) must be locked */ 955 956 std->next = last->next; 957 std->itd_next = last->itd_next; 958 959 std->prev = last; 960 961 usb_pc_cpu_flush(std->page_cache); 962 963 /* 964 * the last->next->prev is never followed: std->next->prev = std; 965 */ 966 last->next = std; 967 last->itd_next = std->itd_self; 968 969 usb_pc_cpu_flush(last->page_cache); 970 971 return (std); 972 } 973 974 #define EHCI_APPEND_QH(sqh,last) (last) = _ehci_append_qh(sqh,last) 975 static ehci_qh_t * 976 _ehci_append_qh(ehci_qh_t *sqh, ehci_qh_t *last) 977 { 978 DPRINTFN(11, "%p to %p\n", sqh, last); 979 980 if (sqh->prev != NULL) { 981 /* should not happen */ 982 DPRINTFN(0, "QH already linked!\n"); 983 return (last); 984 } 985 /* (sc->sc_bus.mtx) must be locked */ 986 987 sqh->next = last->next; 988 sqh->qh_link = last->qh_link; 989 990 sqh->prev = last; 991 992 usb_pc_cpu_flush(sqh->page_cache); 993 994 /* 995 * the last->next->prev is never followed: sqh->next->prev = sqh; 996 */ 997 998 last->next = sqh; 999 last->qh_link = sqh->qh_self; 1000 1001 usb_pc_cpu_flush(last->page_cache); 1002 1003 return (sqh); 1004 } 1005 1006 #define EHCI_REMOVE_FS_TD(std,last) (last) = _ehci_remove_fs_td(std,last) 1007 static ehci_sitd_t * 1008 _ehci_remove_fs_td(ehci_sitd_t *std, ehci_sitd_t *last) 1009 { 1010 DPRINTFN(11, "%p from %p\n", std, last); 1011 1012 /* (sc->sc_bus.mtx) must be locked */ 1013 1014 std->prev->next = std->next; 1015 std->prev->sitd_next = std->sitd_next; 1016 1017 usb_pc_cpu_flush(std->prev->page_cache); 1018 1019 if (std->next) { 1020 std->next->prev = std->prev; 1021 usb_pc_cpu_flush(std->next->page_cache); 1022 } 1023 return ((last == std) ? std->prev : last); 1024 } 1025 1026 #define EHCI_REMOVE_HS_TD(std,last) (last) = _ehci_remove_hs_td(std,last) 1027 static ehci_itd_t * 1028 _ehci_remove_hs_td(ehci_itd_t *std, ehci_itd_t *last) 1029 { 1030 DPRINTFN(11, "%p from %p\n", std, last); 1031 1032 /* (sc->sc_bus.mtx) must be locked */ 1033 1034 std->prev->next = std->next; 1035 std->prev->itd_next = std->itd_next; 1036 1037 usb_pc_cpu_flush(std->prev->page_cache); 1038 1039 if (std->next) { 1040 std->next->prev = std->prev; 1041 usb_pc_cpu_flush(std->next->page_cache); 1042 } 1043 return ((last == std) ? std->prev : last); 1044 } 1045 1046 #define EHCI_REMOVE_QH(sqh,last) (last) = _ehci_remove_qh(sqh,last) 1047 static ehci_qh_t * 1048 _ehci_remove_qh(ehci_qh_t *sqh, ehci_qh_t *last) 1049 { 1050 DPRINTFN(11, "%p from %p\n", sqh, last); 1051 1052 /* (sc->sc_bus.mtx) must be locked */ 1053 1054 /* only remove if not removed from a queue */ 1055 if (sqh->prev) { 1056 1057 sqh->prev->next = sqh->next; 1058 sqh->prev->qh_link = sqh->qh_link; 1059 1060 usb_pc_cpu_flush(sqh->prev->page_cache); 1061 1062 if (sqh->next) { 1063 sqh->next->prev = sqh->prev; 1064 usb_pc_cpu_flush(sqh->next->page_cache); 1065 } 1066 last = ((last == sqh) ? sqh->prev : last); 1067 1068 sqh->prev = 0; 1069 1070 usb_pc_cpu_flush(sqh->page_cache); 1071 } 1072 return (last); 1073 } 1074 1075 static void 1076 ehci_data_toggle_update(struct usb_xfer *xfer, uint16_t actlen, uint16_t xlen) 1077 { 1078 uint16_t rem; 1079 uint8_t dt; 1080 1081 /* count number of full packets */ 1082 dt = (actlen / xfer->max_packet_size) & 1; 1083 1084 /* compute remainder */ 1085 rem = actlen % xfer->max_packet_size; 1086 1087 if (rem > 0) 1088 dt ^= 1; /* short packet at the end */ 1089 else if (actlen != xlen) 1090 dt ^= 1; /* zero length packet at the end */ 1091 else if (xlen == 0) 1092 dt ^= 1; /* zero length transfer */ 1093 1094 xfer->endpoint->toggle_next ^= dt; 1095 } 1096 1097 static usb_error_t 1098 ehci_non_isoc_done_sub(struct usb_xfer *xfer) 1099 { 1100 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 1101 ehci_qtd_t *td; 1102 ehci_qtd_t *td_alt_next; 1103 uint32_t status; 1104 uint16_t len; 1105 1106 td = xfer->td_transfer_cache; 1107 td_alt_next = td->alt_next; 1108 1109 if (xfer->aframes != xfer->nframes) { 1110 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0); 1111 } 1112 while (1) { 1113 1114 usb_pc_cpu_invalidate(td->page_cache); 1115 status = hc32toh(sc, td->qtd_status); 1116 1117 len = EHCI_QTD_GET_BYTES(status); 1118 1119 /* 1120 * Verify the status length and 1121 * add the length to "frlengths[]": 1122 */ 1123 if (len > td->len) { 1124 /* should not happen */ 1125 DPRINTF("Invalid status length, " 1126 "0x%04x/0x%04x bytes\n", len, td->len); 1127 status |= EHCI_QTD_HALTED; 1128 } else if (xfer->aframes != xfer->nframes) { 1129 xfer->frlengths[xfer->aframes] += td->len - len; 1130 /* manually update data toggle */ 1131 ehci_data_toggle_update(xfer, td->len - len, td->len); 1132 } 1133 1134 /* Check for last transfer */ 1135 if (((void *)td) == xfer->td_transfer_last) { 1136 td = NULL; 1137 break; 1138 } 1139 /* Check for transfer error */ 1140 if (status & EHCI_QTD_HALTED) { 1141 /* the transfer is finished */ 1142 td = NULL; 1143 break; 1144 } 1145 /* Check for short transfer */ 1146 if (len > 0) { 1147 if (xfer->flags_int.short_frames_ok) { 1148 /* follow alt next */ 1149 td = td->alt_next; 1150 } else { 1151 /* the transfer is finished */ 1152 td = NULL; 1153 } 1154 break; 1155 } 1156 td = td->obj_next; 1157 1158 if (td->alt_next != td_alt_next) { 1159 /* this USB frame is complete */ 1160 break; 1161 } 1162 } 1163 1164 /* update transfer cache */ 1165 1166 xfer->td_transfer_cache = td; 1167 1168 #ifdef USB_DEBUG 1169 if (status & EHCI_QTD_STATERRS) { 1170 DPRINTFN(11, "error, addr=%d, endpt=0x%02x, frame=0x%02x" 1171 "status=%s%s%s%s%s%s%s%s\n", 1172 xfer->address, xfer->endpointno, xfer->aframes, 1173 (status & EHCI_QTD_ACTIVE) ? "[ACTIVE]" : "[NOT_ACTIVE]", 1174 (status & EHCI_QTD_HALTED) ? "[HALTED]" : "", 1175 (status & EHCI_QTD_BUFERR) ? "[BUFERR]" : "", 1176 (status & EHCI_QTD_BABBLE) ? "[BABBLE]" : "", 1177 (status & EHCI_QTD_XACTERR) ? "[XACTERR]" : "", 1178 (status & EHCI_QTD_MISSEDMICRO) ? "[MISSED]" : "", 1179 (status & EHCI_QTD_SPLITXSTATE) ? "[SPLIT]" : "", 1180 (status & EHCI_QTD_PINGSTATE) ? "[PING]" : ""); 1181 } 1182 #endif 1183 if (status & EHCI_QTD_HALTED) { 1184 if ((xfer->xroot->udev->parent_hs_hub != NULL) || 1185 (xfer->xroot->udev->address != 0)) { 1186 /* try to separate I/O errors from STALL */ 1187 if (EHCI_QTD_GET_CERR(status) == 0) 1188 return (USB_ERR_IOERROR); 1189 } 1190 return (USB_ERR_STALLED); 1191 } 1192 return (USB_ERR_NORMAL_COMPLETION); 1193 } 1194 1195 static void 1196 ehci_non_isoc_done(struct usb_xfer *xfer) 1197 { 1198 ehci_qh_t *qh; 1199 usb_error_t err = 0; 1200 1201 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 1202 xfer, xfer->endpoint); 1203 1204 #ifdef USB_DEBUG 1205 if (ehcidebug > 10) { 1206 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 1207 1208 ehci_dump_sqtds(sc, xfer->td_transfer_first); 1209 } 1210 #endif 1211 1212 /* extract data toggle directly from the QH's overlay area */ 1213 1214 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1215 1216 usb_pc_cpu_invalidate(qh->page_cache); 1217 1218 /* reset scanner */ 1219 1220 xfer->td_transfer_cache = xfer->td_transfer_first; 1221 1222 if (xfer->flags_int.control_xfr) { 1223 1224 if (xfer->flags_int.control_hdr) { 1225 1226 err = ehci_non_isoc_done_sub(xfer); 1227 } 1228 xfer->aframes = 1; 1229 1230 if (xfer->td_transfer_cache == NULL) { 1231 goto done; 1232 } 1233 } 1234 while (xfer->aframes != xfer->nframes) { 1235 1236 err = ehci_non_isoc_done_sub(xfer); 1237 xfer->aframes++; 1238 1239 if (xfer->td_transfer_cache == NULL) { 1240 goto done; 1241 } 1242 } 1243 1244 if (xfer->flags_int.control_xfr && 1245 !xfer->flags_int.control_act) { 1246 1247 err = ehci_non_isoc_done_sub(xfer); 1248 } 1249 done: 1250 ehci_device_done(xfer, err); 1251 } 1252 1253 /*------------------------------------------------------------------------* 1254 * ehci_check_transfer 1255 * 1256 * Return values: 1257 * 0: USB transfer is not finished 1258 * Else: USB transfer is finished 1259 *------------------------------------------------------------------------*/ 1260 static uint8_t 1261 ehci_check_transfer(struct usb_xfer *xfer) 1262 { 1263 const struct usb_pipe_methods *methods = xfer->endpoint->methods; 1264 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 1265 1266 uint32_t status; 1267 1268 DPRINTFN(13, "xfer=%p checking transfer\n", xfer); 1269 1270 if (methods == &ehci_device_isoc_fs_methods) { 1271 ehci_sitd_t *td; 1272 1273 /* isochronous full speed transfer */ 1274 1275 td = xfer->td_transfer_last; 1276 usb_pc_cpu_invalidate(td->page_cache); 1277 status = hc32toh(sc, td->sitd_status); 1278 1279 /* also check if first is complete */ 1280 1281 td = xfer->td_transfer_first; 1282 usb_pc_cpu_invalidate(td->page_cache); 1283 status |= hc32toh(sc, td->sitd_status); 1284 1285 if (!(status & EHCI_SITD_ACTIVE)) { 1286 ehci_device_done(xfer, USB_ERR_NORMAL_COMPLETION); 1287 goto transferred; 1288 } 1289 } else if (methods == &ehci_device_isoc_hs_methods) { 1290 ehci_itd_t *td; 1291 1292 /* isochronous high speed transfer */ 1293 1294 /* check last transfer */ 1295 td = xfer->td_transfer_last; 1296 usb_pc_cpu_invalidate(td->page_cache); 1297 status = td->itd_status[0]; 1298 status |= td->itd_status[1]; 1299 status |= td->itd_status[2]; 1300 status |= td->itd_status[3]; 1301 status |= td->itd_status[4]; 1302 status |= td->itd_status[5]; 1303 status |= td->itd_status[6]; 1304 status |= td->itd_status[7]; 1305 1306 /* also check first transfer */ 1307 td = xfer->td_transfer_first; 1308 usb_pc_cpu_invalidate(td->page_cache); 1309 status |= td->itd_status[0]; 1310 status |= td->itd_status[1]; 1311 status |= td->itd_status[2]; 1312 status |= td->itd_status[3]; 1313 status |= td->itd_status[4]; 1314 status |= td->itd_status[5]; 1315 status |= td->itd_status[6]; 1316 status |= td->itd_status[7]; 1317 1318 /* if no transactions are active we continue */ 1319 if (!(status & htohc32(sc, EHCI_ITD_ACTIVE))) { 1320 ehci_device_done(xfer, USB_ERR_NORMAL_COMPLETION); 1321 goto transferred; 1322 } 1323 } else { 1324 ehci_qtd_t *td; 1325 ehci_qh_t *qh; 1326 1327 /* non-isochronous transfer */ 1328 1329 /* 1330 * check whether there is an error somewhere in the middle, 1331 * or whether there was a short packet (SPD and not ACTIVE) 1332 */ 1333 td = xfer->td_transfer_cache; 1334 1335 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1336 1337 usb_pc_cpu_invalidate(qh->page_cache); 1338 1339 status = hc32toh(sc, qh->qh_qtd.qtd_status); 1340 if (status & EHCI_QTD_ACTIVE) { 1341 /* transfer is pending */ 1342 goto done; 1343 } 1344 1345 while (1) { 1346 usb_pc_cpu_invalidate(td->page_cache); 1347 status = hc32toh(sc, td->qtd_status); 1348 1349 /* 1350 * Check if there is an active TD which 1351 * indicates that the transfer isn't done. 1352 */ 1353 if (status & EHCI_QTD_ACTIVE) { 1354 /* update cache */ 1355 xfer->td_transfer_cache = td; 1356 goto done; 1357 } 1358 /* 1359 * last transfer descriptor makes the transfer done 1360 */ 1361 if (((void *)td) == xfer->td_transfer_last) { 1362 break; 1363 } 1364 /* 1365 * any kind of error makes the transfer done 1366 */ 1367 if (status & EHCI_QTD_HALTED) { 1368 break; 1369 } 1370 /* 1371 * if there is no alternate next transfer, a short 1372 * packet also makes the transfer done 1373 */ 1374 if (EHCI_QTD_GET_BYTES(status)) { 1375 if (xfer->flags_int.short_frames_ok) { 1376 /* follow alt next */ 1377 if (td->alt_next) { 1378 td = td->alt_next; 1379 continue; 1380 } 1381 } 1382 /* transfer is done */ 1383 break; 1384 } 1385 td = td->obj_next; 1386 } 1387 ehci_non_isoc_done(xfer); 1388 goto transferred; 1389 } 1390 1391 done: 1392 DPRINTFN(13, "xfer=%p is still active\n", xfer); 1393 return (0); 1394 1395 transferred: 1396 return (1); 1397 } 1398 1399 static void 1400 ehci_pcd_enable(ehci_softc_t *sc) 1401 { 1402 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1403 1404 sc->sc_eintrs |= EHCI_STS_PCD; 1405 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1406 1407 /* acknowledge any PCD interrupt */ 1408 EOWRITE4(sc, EHCI_USBSTS, EHCI_STS_PCD); 1409 1410 ehci_root_intr(sc); 1411 } 1412 1413 static void 1414 ehci_interrupt_poll(ehci_softc_t *sc) 1415 { 1416 struct usb_xfer *xfer; 1417 1418 repeat: 1419 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 1420 /* 1421 * check if transfer is transferred 1422 */ 1423 if (ehci_check_transfer(xfer)) { 1424 /* queue has been modified */ 1425 goto repeat; 1426 } 1427 } 1428 } 1429 1430 /* 1431 * Some EHCI chips from VIA / ATI seem to trigger interrupts before 1432 * writing back the qTD status, or miss signalling occasionally under 1433 * heavy load. If the host machine is too fast, we can miss 1434 * transaction completion - when we scan the active list the 1435 * transaction still seems to be active. This generally exhibits 1436 * itself as a umass stall that never recovers. 1437 * 1438 * We work around this behaviour by setting up this callback after any 1439 * softintr that completes with transactions still pending, giving us 1440 * another chance to check for completion after the writeback has 1441 * taken place. 1442 */ 1443 static void 1444 ehci_poll_timeout(void *arg) 1445 { 1446 ehci_softc_t *sc = arg; 1447 1448 DPRINTFN(3, "\n"); 1449 ehci_interrupt_poll(sc); 1450 } 1451 1452 /*------------------------------------------------------------------------* 1453 * ehci_interrupt - EHCI interrupt handler 1454 * 1455 * NOTE: Do not access "sc->sc_bus.bdev" inside the interrupt handler, 1456 * hence the interrupt handler will be setup before "sc->sc_bus.bdev" 1457 * is present ! 1458 *------------------------------------------------------------------------*/ 1459 void 1460 ehci_interrupt(ehci_softc_t *sc) 1461 { 1462 uint32_t status; 1463 1464 USB_BUS_LOCK(&sc->sc_bus); 1465 1466 DPRINTFN(16, "real interrupt\n"); 1467 1468 #ifdef USB_DEBUG 1469 if (ehcidebug > 15) { 1470 ehci_dump_regs(sc); 1471 } 1472 #endif 1473 1474 status = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1475 if (status == 0) { 1476 /* the interrupt was not for us */ 1477 goto done; 1478 } 1479 if (!(status & sc->sc_eintrs)) { 1480 goto done; 1481 } 1482 EOWRITE4(sc, EHCI_USBSTS, status); /* acknowledge */ 1483 1484 status &= sc->sc_eintrs; 1485 1486 if (status & EHCI_STS_HSE) { 1487 printf("%s: unrecoverable error, " 1488 "controller halted\n", __FUNCTION__); 1489 #ifdef USB_DEBUG 1490 ehci_dump_regs(sc); 1491 ehci_dump_isoc(sc); 1492 #endif 1493 } 1494 if (status & EHCI_STS_PCD) { 1495 /* 1496 * Disable PCD interrupt for now, because it will be 1497 * on until the port has been reset. 1498 */ 1499 sc->sc_eintrs &= ~EHCI_STS_PCD; 1500 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1501 1502 ehci_root_intr(sc); 1503 1504 /* do not allow RHSC interrupts > 1 per second */ 1505 usb_callout_reset(&sc->sc_tmo_pcd, hz, 1506 (void *)&ehci_pcd_enable, sc); 1507 } 1508 status &= ~(EHCI_STS_INT | EHCI_STS_ERRINT | EHCI_STS_PCD | EHCI_STS_IAA); 1509 1510 if (status != 0) { 1511 /* block unprocessed interrupts */ 1512 sc->sc_eintrs &= ~status; 1513 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1514 printf("%s: blocking interrupts 0x%x\n", __FUNCTION__, status); 1515 } 1516 /* poll all the USB transfers */ 1517 ehci_interrupt_poll(sc); 1518 1519 if (sc->sc_flags & EHCI_SCFLG_LOSTINTRBUG) { 1520 usb_callout_reset(&sc->sc_tmo_poll, hz / 128, 1521 (void *)&ehci_poll_timeout, sc); 1522 } 1523 1524 done: 1525 USB_BUS_UNLOCK(&sc->sc_bus); 1526 } 1527 1528 /* 1529 * called when a request does not complete 1530 */ 1531 static void 1532 ehci_timeout(void *arg) 1533 { 1534 struct usb_xfer *xfer = arg; 1535 1536 DPRINTF("xfer=%p\n", xfer); 1537 1538 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1539 1540 /* transfer is transferred */ 1541 ehci_device_done(xfer, USB_ERR_TIMEOUT); 1542 } 1543 1544 static void 1545 ehci_do_poll(struct usb_bus *bus) 1546 { 1547 ehci_softc_t *sc = EHCI_BUS2SC(bus); 1548 1549 USB_BUS_LOCK(&sc->sc_bus); 1550 ehci_interrupt_poll(sc); 1551 USB_BUS_UNLOCK(&sc->sc_bus); 1552 } 1553 1554 static void 1555 ehci_setup_standard_chain_sub(struct ehci_std_temp *temp) 1556 { 1557 struct usb_page_search buf_res; 1558 ehci_qtd_t *td; 1559 ehci_qtd_t *td_next; 1560 ehci_qtd_t *td_alt_next; 1561 uint32_t buf_offset; 1562 uint32_t average; 1563 uint32_t len_old; 1564 uint32_t terminate; 1565 uint32_t qtd_altnext; 1566 uint8_t shortpkt_old; 1567 uint8_t precompute; 1568 1569 terminate = temp->sc->sc_terminate_self; 1570 qtd_altnext = temp->sc->sc_terminate_self; 1571 td_alt_next = NULL; 1572 buf_offset = 0; 1573 shortpkt_old = temp->shortpkt; 1574 len_old = temp->len; 1575 precompute = 1; 1576 1577 restart: 1578 1579 td = temp->td; 1580 td_next = temp->td_next; 1581 1582 while (1) { 1583 1584 if (temp->len == 0) { 1585 1586 if (temp->shortpkt) { 1587 break; 1588 } 1589 /* send a Zero Length Packet, ZLP, last */ 1590 1591 temp->shortpkt = 1; 1592 average = 0; 1593 1594 } else { 1595 1596 average = temp->average; 1597 1598 if (temp->len < average) { 1599 if (temp->len % temp->max_frame_size) { 1600 temp->shortpkt = 1; 1601 } 1602 average = temp->len; 1603 } 1604 } 1605 1606 if (td_next == NULL) { 1607 panic("%s: out of EHCI transfer descriptors!", __FUNCTION__); 1608 } 1609 /* get next TD */ 1610 1611 td = td_next; 1612 td_next = td->obj_next; 1613 1614 /* check if we are pre-computing */ 1615 1616 if (precompute) { 1617 1618 /* update remaining length */ 1619 1620 temp->len -= average; 1621 1622 continue; 1623 } 1624 /* fill out current TD */ 1625 1626 td->qtd_status = 1627 temp->qtd_status | 1628 htohc32(temp->sc, EHCI_QTD_IOC | 1629 EHCI_QTD_SET_BYTES(average)); 1630 1631 if (average == 0) { 1632 1633 if (temp->auto_data_toggle == 0) { 1634 1635 /* update data toggle, ZLP case */ 1636 1637 temp->qtd_status ^= 1638 htohc32(temp->sc, EHCI_QTD_TOGGLE_MASK); 1639 } 1640 td->len = 0; 1641 1642 /* properly reset reserved fields */ 1643 td->qtd_buffer[0] = 0; 1644 td->qtd_buffer[1] = 0; 1645 td->qtd_buffer[2] = 0; 1646 td->qtd_buffer[3] = 0; 1647 td->qtd_buffer[4] = 0; 1648 td->qtd_buffer_hi[0] = 0; 1649 td->qtd_buffer_hi[1] = 0; 1650 td->qtd_buffer_hi[2] = 0; 1651 td->qtd_buffer_hi[3] = 0; 1652 td->qtd_buffer_hi[4] = 0; 1653 } else { 1654 1655 uint8_t x; 1656 1657 if (temp->auto_data_toggle == 0) { 1658 1659 /* update data toggle */ 1660 1661 if (howmany(average, temp->max_frame_size) & 1) { 1662 temp->qtd_status ^= 1663 htohc32(temp->sc, EHCI_QTD_TOGGLE_MASK); 1664 } 1665 } 1666 td->len = average; 1667 1668 /* update remaining length */ 1669 1670 temp->len -= average; 1671 1672 /* fill out buffer pointers */ 1673 1674 usbd_get_page(temp->pc, buf_offset, &buf_res); 1675 td->qtd_buffer[0] = 1676 htohc32(temp->sc, buf_res.physaddr); 1677 td->qtd_buffer_hi[0] = 0; 1678 1679 x = 1; 1680 1681 while (average > EHCI_PAGE_SIZE) { 1682 average -= EHCI_PAGE_SIZE; 1683 buf_offset += EHCI_PAGE_SIZE; 1684 usbd_get_page(temp->pc, buf_offset, &buf_res); 1685 td->qtd_buffer[x] = 1686 htohc32(temp->sc, 1687 buf_res.physaddr & (~0xFFF)); 1688 td->qtd_buffer_hi[x] = 0; 1689 x++; 1690 } 1691 1692 /* 1693 * NOTE: The "average" variable is never zero after 1694 * exiting the loop above ! 1695 * 1696 * NOTE: We have to subtract one from the offset to 1697 * ensure that we are computing the physical address 1698 * of a valid page ! 1699 */ 1700 buf_offset += average; 1701 usbd_get_page(temp->pc, buf_offset - 1, &buf_res); 1702 td->qtd_buffer[x] = 1703 htohc32(temp->sc, 1704 buf_res.physaddr & (~0xFFF)); 1705 td->qtd_buffer_hi[x] = 0; 1706 1707 /* properly reset reserved fields */ 1708 while (++x < EHCI_QTD_NBUFFERS) { 1709 td->qtd_buffer[x] = 0; 1710 td->qtd_buffer_hi[x] = 0; 1711 } 1712 } 1713 1714 if (td_next) { 1715 /* link the current TD with the next one */ 1716 td->qtd_next = td_next->qtd_self; 1717 } 1718 td->qtd_altnext = qtd_altnext; 1719 td->alt_next = td_alt_next; 1720 1721 usb_pc_cpu_flush(td->page_cache); 1722 } 1723 1724 if (precompute) { 1725 precompute = 0; 1726 1727 /* setup alt next pointer, if any */ 1728 if (temp->last_frame) { 1729 td_alt_next = NULL; 1730 qtd_altnext = terminate; 1731 } else { 1732 /* we use this field internally */ 1733 td_alt_next = td_next; 1734 if (temp->setup_alt_next) { 1735 qtd_altnext = td_next->qtd_self; 1736 } else { 1737 qtd_altnext = terminate; 1738 } 1739 } 1740 1741 /* restore */ 1742 temp->shortpkt = shortpkt_old; 1743 temp->len = len_old; 1744 goto restart; 1745 } 1746 temp->td = td; 1747 temp->td_next = td_next; 1748 } 1749 1750 static void 1751 ehci_setup_standard_chain(struct usb_xfer *xfer, ehci_qh_t **qh_last) 1752 { 1753 struct ehci_std_temp temp; 1754 const struct usb_pipe_methods *methods; 1755 ehci_qh_t *qh; 1756 ehci_qtd_t *td; 1757 uint32_t qh_endp; 1758 uint32_t qh_endphub; 1759 uint32_t x; 1760 1761 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 1762 xfer->address, UE_GET_ADDR(xfer->endpointno), 1763 xfer->sumlen, usbd_get_speed(xfer->xroot->udev)); 1764 1765 temp.average = xfer->max_hc_frame_size; 1766 temp.max_frame_size = xfer->max_frame_size; 1767 temp.sc = EHCI_BUS2SC(xfer->xroot->bus); 1768 1769 /* toggle the DMA set we are using */ 1770 xfer->flags_int.curr_dma_set ^= 1; 1771 1772 /* get next DMA set */ 1773 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 1774 1775 xfer->td_transfer_first = td; 1776 xfer->td_transfer_cache = td; 1777 1778 temp.td = NULL; 1779 temp.td_next = td; 1780 temp.qtd_status = 0; 1781 temp.last_frame = 0; 1782 temp.setup_alt_next = xfer->flags_int.short_frames_ok; 1783 1784 if (xfer->flags_int.control_xfr) { 1785 if (xfer->endpoint->toggle_next) { 1786 /* DATA1 is next */ 1787 temp.qtd_status |= 1788 htohc32(temp.sc, EHCI_QTD_SET_TOGGLE(1)); 1789 } 1790 temp.auto_data_toggle = 0; 1791 } else { 1792 temp.auto_data_toggle = 1; 1793 } 1794 1795 if ((xfer->xroot->udev->parent_hs_hub != NULL) || 1796 (xfer->xroot->udev->address != 0)) { 1797 /* max 3 retries */ 1798 temp.qtd_status |= 1799 htohc32(temp.sc, EHCI_QTD_SET_CERR(3)); 1800 } 1801 /* check if we should prepend a setup message */ 1802 1803 if (xfer->flags_int.control_xfr) { 1804 if (xfer->flags_int.control_hdr) { 1805 1806 xfer->endpoint->toggle_next = 0; 1807 1808 temp.qtd_status &= 1809 htohc32(temp.sc, EHCI_QTD_SET_CERR(3)); 1810 temp.qtd_status |= htohc32(temp.sc, 1811 EHCI_QTD_ACTIVE | 1812 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 1813 EHCI_QTD_SET_TOGGLE(0)); 1814 1815 temp.len = xfer->frlengths[0]; 1816 temp.pc = xfer->frbuffers + 0; 1817 temp.shortpkt = temp.len ? 1 : 0; 1818 /* check for last frame */ 1819 if (xfer->nframes == 1) { 1820 /* no STATUS stage yet, SETUP is last */ 1821 if (xfer->flags_int.control_act) { 1822 temp.last_frame = 1; 1823 temp.setup_alt_next = 0; 1824 } 1825 } 1826 ehci_setup_standard_chain_sub(&temp); 1827 } 1828 x = 1; 1829 } else { 1830 x = 0; 1831 } 1832 1833 while (x != xfer->nframes) { 1834 1835 /* DATA0 / DATA1 message */ 1836 1837 temp.len = xfer->frlengths[x]; 1838 temp.pc = xfer->frbuffers + x; 1839 1840 x++; 1841 1842 if (x == xfer->nframes) { 1843 if (xfer->flags_int.control_xfr) { 1844 /* no STATUS stage yet, DATA is last */ 1845 if (xfer->flags_int.control_act) { 1846 temp.last_frame = 1; 1847 temp.setup_alt_next = 0; 1848 } 1849 } else { 1850 temp.last_frame = 1; 1851 temp.setup_alt_next = 0; 1852 } 1853 } 1854 /* keep previous data toggle and error count */ 1855 1856 temp.qtd_status &= 1857 htohc32(temp.sc, EHCI_QTD_SET_CERR(3) | 1858 EHCI_QTD_SET_TOGGLE(1)); 1859 1860 if (temp.len == 0) { 1861 1862 /* make sure that we send an USB packet */ 1863 1864 temp.shortpkt = 0; 1865 1866 } else { 1867 1868 /* regular data transfer */ 1869 1870 temp.shortpkt = (xfer->flags.force_short_xfer) ? 0 : 1; 1871 } 1872 1873 /* set endpoint direction */ 1874 1875 temp.qtd_status |= 1876 (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) ? 1877 htohc32(temp.sc, EHCI_QTD_ACTIVE | 1878 EHCI_QTD_SET_PID(EHCI_QTD_PID_IN)) : 1879 htohc32(temp.sc, EHCI_QTD_ACTIVE | 1880 EHCI_QTD_SET_PID(EHCI_QTD_PID_OUT)); 1881 1882 ehci_setup_standard_chain_sub(&temp); 1883 } 1884 1885 /* check if we should append a status stage */ 1886 1887 if (xfer->flags_int.control_xfr && 1888 !xfer->flags_int.control_act) { 1889 1890 /* 1891 * Send a DATA1 message and invert the current endpoint 1892 * direction. 1893 */ 1894 1895 temp.qtd_status &= htohc32(temp.sc, EHCI_QTD_SET_CERR(3) | 1896 EHCI_QTD_SET_TOGGLE(1)); 1897 temp.qtd_status |= 1898 (UE_GET_DIR(xfer->endpointno) == UE_DIR_OUT) ? 1899 htohc32(temp.sc, EHCI_QTD_ACTIVE | 1900 EHCI_QTD_SET_PID(EHCI_QTD_PID_IN) | 1901 EHCI_QTD_SET_TOGGLE(1)) : 1902 htohc32(temp.sc, EHCI_QTD_ACTIVE | 1903 EHCI_QTD_SET_PID(EHCI_QTD_PID_OUT) | 1904 EHCI_QTD_SET_TOGGLE(1)); 1905 1906 temp.len = 0; 1907 temp.pc = NULL; 1908 temp.shortpkt = 0; 1909 temp.last_frame = 1; 1910 temp.setup_alt_next = 0; 1911 1912 ehci_setup_standard_chain_sub(&temp); 1913 } 1914 td = temp.td; 1915 1916 /* the last TD terminates the transfer: */ 1917 td->qtd_next = htohc32(temp.sc, EHCI_LINK_TERMINATE); 1918 td->qtd_altnext = htohc32(temp.sc, EHCI_LINK_TERMINATE); 1919 1920 usb_pc_cpu_flush(td->page_cache); 1921 1922 /* must have at least one frame! */ 1923 1924 xfer->td_transfer_last = td; 1925 1926 #ifdef USB_DEBUG 1927 if (ehcidebug > 8) { 1928 DPRINTF("nexttog=%d; data before transfer:\n", 1929 xfer->endpoint->toggle_next); 1930 ehci_dump_sqtds(temp.sc, 1931 xfer->td_transfer_first); 1932 } 1933 #endif 1934 1935 methods = xfer->endpoint->methods; 1936 1937 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1938 1939 /* the "qh_link" field is filled when the QH is added */ 1940 1941 qh_endp = 1942 (EHCI_QH_SET_ADDR(xfer->address) | 1943 EHCI_QH_SET_ENDPT(UE_GET_ADDR(xfer->endpointno)) | 1944 EHCI_QH_SET_MPL(xfer->max_packet_size)); 1945 1946 if (usbd_get_speed(xfer->xroot->udev) == USB_SPEED_HIGH) { 1947 qh_endp |= EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH); 1948 if (methods != &ehci_device_intr_methods) 1949 qh_endp |= EHCI_QH_SET_NRL(8); 1950 } else { 1951 1952 if (usbd_get_speed(xfer->xroot->udev) == USB_SPEED_FULL) { 1953 qh_endp |= EHCI_QH_SET_EPS(EHCI_QH_SPEED_FULL); 1954 } else { 1955 qh_endp |= EHCI_QH_SET_EPS(EHCI_QH_SPEED_LOW); 1956 } 1957 1958 if (methods == &ehci_device_ctrl_methods) { 1959 qh_endp |= EHCI_QH_CTL; 1960 } 1961 if (methods != &ehci_device_intr_methods) { 1962 /* Only try one time per microframe! */ 1963 qh_endp |= EHCI_QH_SET_NRL(1); 1964 } 1965 } 1966 1967 if (temp.auto_data_toggle == 0) { 1968 /* software computes the data toggle */ 1969 qh_endp |= EHCI_QH_DTC; 1970 } 1971 1972 qh->qh_endp = htohc32(temp.sc, qh_endp); 1973 1974 qh_endphub = 1975 (EHCI_QH_SET_MULT(xfer->max_packet_count & 3) | 1976 EHCI_QH_SET_CMASK(xfer->endpoint->usb_cmask) | 1977 EHCI_QH_SET_SMASK(xfer->endpoint->usb_smask) | 1978 EHCI_QH_SET_HUBA(xfer->xroot->udev->hs_hub_addr) | 1979 EHCI_QH_SET_PORT(xfer->xroot->udev->hs_port_no)); 1980 1981 qh->qh_endphub = htohc32(temp.sc, qh_endphub); 1982 qh->qh_curqtd = 0; 1983 1984 /* fill the overlay qTD */ 1985 1986 if (temp.auto_data_toggle && xfer->endpoint->toggle_next) { 1987 /* DATA1 is next */ 1988 qh->qh_qtd.qtd_status = htohc32(temp.sc, EHCI_QTD_SET_TOGGLE(1)); 1989 } else { 1990 qh->qh_qtd.qtd_status = 0; 1991 } 1992 1993 td = xfer->td_transfer_first; 1994 1995 qh->qh_qtd.qtd_next = td->qtd_self; 1996 qh->qh_qtd.qtd_altnext = 1997 htohc32(temp.sc, EHCI_LINK_TERMINATE); 1998 1999 /* properly reset reserved fields */ 2000 qh->qh_qtd.qtd_buffer[0] = 0; 2001 qh->qh_qtd.qtd_buffer[1] = 0; 2002 qh->qh_qtd.qtd_buffer[2] = 0; 2003 qh->qh_qtd.qtd_buffer[3] = 0; 2004 qh->qh_qtd.qtd_buffer[4] = 0; 2005 qh->qh_qtd.qtd_buffer_hi[0] = 0; 2006 qh->qh_qtd.qtd_buffer_hi[1] = 0; 2007 qh->qh_qtd.qtd_buffer_hi[2] = 0; 2008 qh->qh_qtd.qtd_buffer_hi[3] = 0; 2009 qh->qh_qtd.qtd_buffer_hi[4] = 0; 2010 2011 usb_pc_cpu_flush(qh->page_cache); 2012 2013 if (xfer->xroot->udev->flags.self_suspended == 0) { 2014 EHCI_APPEND_QH(qh, *qh_last); 2015 } 2016 } 2017 2018 static void 2019 ehci_root_intr(ehci_softc_t *sc) 2020 { 2021 uint16_t i; 2022 uint16_t m; 2023 2024 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2025 2026 /* clear any old interrupt data */ 2027 memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata)); 2028 2029 /* set bits */ 2030 m = (sc->sc_noport + 1); 2031 if (m > (8 * sizeof(sc->sc_hub_idata))) { 2032 m = (8 * sizeof(sc->sc_hub_idata)); 2033 } 2034 for (i = 1; i < m; i++) { 2035 /* pick out CHANGE bits from the status register */ 2036 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) { 2037 sc->sc_hub_idata[i / 8] |= 1 << (i % 8); 2038 DPRINTF("port %d changed\n", i); 2039 } 2040 } 2041 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 2042 sizeof(sc->sc_hub_idata)); 2043 } 2044 2045 static void 2046 ehci_isoc_fs_done(ehci_softc_t *sc, struct usb_xfer *xfer) 2047 { 2048 uint32_t nframes = xfer->nframes; 2049 uint32_t status; 2050 uint32_t *plen = xfer->frlengths; 2051 uint16_t len = 0; 2052 ehci_sitd_t *td = xfer->td_transfer_first; 2053 ehci_sitd_t **pp_last = &sc->sc_isoc_fs_p_last[xfer->qh_pos]; 2054 2055 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 2056 xfer, xfer->endpoint); 2057 2058 while (nframes--) { 2059 if (td == NULL) { 2060 panic("%s:%d: out of TD's\n", 2061 __FUNCTION__, __LINE__); 2062 } 2063 if (pp_last >= &sc->sc_isoc_fs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) { 2064 pp_last = &sc->sc_isoc_fs_p_last[0]; 2065 } 2066 #ifdef USB_DEBUG 2067 if (ehcidebug > 15) { 2068 DPRINTF("isoc FS-TD\n"); 2069 ehci_dump_sitd(sc, td); 2070 } 2071 #endif 2072 usb_pc_cpu_invalidate(td->page_cache); 2073 status = hc32toh(sc, td->sitd_status); 2074 2075 len = EHCI_SITD_GET_LEN(status); 2076 2077 DPRINTFN(2, "status=0x%08x, rem=%u\n", status, len); 2078 2079 if (*plen >= len) { 2080 len = *plen - len; 2081 } else { 2082 len = 0; 2083 } 2084 2085 *plen = len; 2086 2087 /* remove FS-TD from schedule */ 2088 EHCI_REMOVE_FS_TD(td, *pp_last); 2089 2090 pp_last++; 2091 plen++; 2092 td = td->obj_next; 2093 } 2094 2095 xfer->aframes = xfer->nframes; 2096 } 2097 2098 static void 2099 ehci_isoc_hs_done(ehci_softc_t *sc, struct usb_xfer *xfer) 2100 { 2101 uint32_t nframes = xfer->nframes; 2102 uint32_t status; 2103 uint32_t *plen = xfer->frlengths; 2104 uint16_t len = 0; 2105 uint8_t td_no = 0; 2106 ehci_itd_t *td = xfer->td_transfer_first; 2107 ehci_itd_t **pp_last = &sc->sc_isoc_hs_p_last[xfer->qh_pos]; 2108 2109 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 2110 xfer, xfer->endpoint); 2111 2112 while (nframes) { 2113 if (td == NULL) { 2114 panic("%s:%d: out of TD's\n", 2115 __FUNCTION__, __LINE__); 2116 } 2117 if (pp_last >= &sc->sc_isoc_hs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) { 2118 pp_last = &sc->sc_isoc_hs_p_last[0]; 2119 } 2120 #ifdef USB_DEBUG 2121 if (ehcidebug > 15) { 2122 DPRINTF("isoc HS-TD\n"); 2123 ehci_dump_itd(sc, td); 2124 } 2125 #endif 2126 2127 usb_pc_cpu_invalidate(td->page_cache); 2128 status = hc32toh(sc, td->itd_status[td_no]); 2129 2130 len = EHCI_ITD_GET_LEN(status); 2131 2132 DPRINTFN(2, "status=0x%08x, len=%u\n", status, len); 2133 2134 if (xfer->endpoint->usb_smask & (1 << td_no)) { 2135 2136 if (*plen >= len) { 2137 /* 2138 * The length is valid. NOTE: The 2139 * complete length is written back 2140 * into the status field, and not the 2141 * remainder like with other transfer 2142 * descriptor types. 2143 */ 2144 } else { 2145 /* Invalid length - truncate */ 2146 len = 0; 2147 } 2148 2149 *plen = len; 2150 plen++; 2151 nframes--; 2152 } 2153 2154 td_no++; 2155 2156 if ((td_no == 8) || (nframes == 0)) { 2157 /* remove HS-TD from schedule */ 2158 EHCI_REMOVE_HS_TD(td, *pp_last); 2159 pp_last++; 2160 2161 td_no = 0; 2162 td = td->obj_next; 2163 } 2164 } 2165 xfer->aframes = xfer->nframes; 2166 } 2167 2168 /* NOTE: "done" can be run two times in a row, 2169 * from close and from interrupt 2170 */ 2171 static void 2172 ehci_device_done(struct usb_xfer *xfer, usb_error_t error) 2173 { 2174 const struct usb_pipe_methods *methods = xfer->endpoint->methods; 2175 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2176 2177 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2178 2179 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n", 2180 xfer, xfer->endpoint, error); 2181 2182 if ((methods == &ehci_device_bulk_methods) || 2183 (methods == &ehci_device_ctrl_methods)) { 2184 #ifdef USB_DEBUG 2185 if (ehcidebug > 8) { 2186 DPRINTF("nexttog=%d; data after transfer:\n", 2187 xfer->endpoint->toggle_next); 2188 ehci_dump_sqtds(sc, 2189 xfer->td_transfer_first); 2190 } 2191 #endif 2192 2193 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 2194 sc->sc_async_p_last); 2195 } 2196 if (methods == &ehci_device_intr_methods) { 2197 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 2198 sc->sc_intr_p_last[xfer->qh_pos]); 2199 } 2200 /* 2201 * Only finish isochronous transfers once which will update 2202 * "xfer->frlengths". 2203 */ 2204 if (xfer->td_transfer_first && 2205 xfer->td_transfer_last) { 2206 if (methods == &ehci_device_isoc_fs_methods) { 2207 ehci_isoc_fs_done(sc, xfer); 2208 } 2209 if (methods == &ehci_device_isoc_hs_methods) { 2210 ehci_isoc_hs_done(sc, xfer); 2211 } 2212 xfer->td_transfer_first = NULL; 2213 xfer->td_transfer_last = NULL; 2214 } 2215 /* dequeue transfer and start next transfer */ 2216 usbd_transfer_done(xfer, error); 2217 } 2218 2219 /*------------------------------------------------------------------------* 2220 * ehci bulk support 2221 *------------------------------------------------------------------------*/ 2222 static void 2223 ehci_device_bulk_open(struct usb_xfer *xfer) 2224 { 2225 return; 2226 } 2227 2228 static void 2229 ehci_device_bulk_close(struct usb_xfer *xfer) 2230 { 2231 ehci_device_done(xfer, USB_ERR_CANCELLED); 2232 } 2233 2234 static void 2235 ehci_device_bulk_enter(struct usb_xfer *xfer) 2236 { 2237 return; 2238 } 2239 2240 static void 2241 ehci_doorbell_async(struct ehci_softc *sc) 2242 { 2243 uint32_t temp; 2244 2245 /* 2246 * XXX Performance quirk: Some Host Controllers have a too low 2247 * interrupt rate. Issue an IAAD to stimulate the Host 2248 * Controller after queueing the BULK transfer. 2249 * 2250 * XXX Force the host controller to refresh any QH caches. 2251 */ 2252 temp = EOREAD4(sc, EHCI_USBCMD); 2253 if (!(temp & EHCI_CMD_IAAD)) 2254 EOWRITE4(sc, EHCI_USBCMD, temp | EHCI_CMD_IAAD); 2255 } 2256 2257 static void 2258 ehci_device_bulk_start(struct usb_xfer *xfer) 2259 { 2260 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2261 2262 /* setup TD's and QH */ 2263 ehci_setup_standard_chain(xfer, &sc->sc_async_p_last); 2264 2265 /* put transfer on interrupt queue */ 2266 ehci_transfer_intr_enqueue(xfer); 2267 2268 /* 2269 * XXX Certain nVidia chipsets choke when using the IAAD 2270 * feature too frequently. 2271 */ 2272 if (sc->sc_flags & EHCI_SCFLG_IAADBUG) 2273 return; 2274 2275 ehci_doorbell_async(sc); 2276 } 2277 2278 static const struct usb_pipe_methods ehci_device_bulk_methods = 2279 { 2280 .open = ehci_device_bulk_open, 2281 .close = ehci_device_bulk_close, 2282 .enter = ehci_device_bulk_enter, 2283 .start = ehci_device_bulk_start, 2284 }; 2285 2286 /*------------------------------------------------------------------------* 2287 * ehci control support 2288 *------------------------------------------------------------------------*/ 2289 static void 2290 ehci_device_ctrl_open(struct usb_xfer *xfer) 2291 { 2292 return; 2293 } 2294 2295 static void 2296 ehci_device_ctrl_close(struct usb_xfer *xfer) 2297 { 2298 ehci_device_done(xfer, USB_ERR_CANCELLED); 2299 } 2300 2301 static void 2302 ehci_device_ctrl_enter(struct usb_xfer *xfer) 2303 { 2304 return; 2305 } 2306 2307 static void 2308 ehci_device_ctrl_start(struct usb_xfer *xfer) 2309 { 2310 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2311 2312 /* setup TD's and QH */ 2313 ehci_setup_standard_chain(xfer, &sc->sc_async_p_last); 2314 2315 /* put transfer on interrupt queue */ 2316 ehci_transfer_intr_enqueue(xfer); 2317 } 2318 2319 static const struct usb_pipe_methods ehci_device_ctrl_methods = 2320 { 2321 .open = ehci_device_ctrl_open, 2322 .close = ehci_device_ctrl_close, 2323 .enter = ehci_device_ctrl_enter, 2324 .start = ehci_device_ctrl_start, 2325 }; 2326 2327 /*------------------------------------------------------------------------* 2328 * ehci interrupt support 2329 *------------------------------------------------------------------------*/ 2330 static void 2331 ehci_device_intr_open(struct usb_xfer *xfer) 2332 { 2333 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2334 uint16_t best; 2335 uint16_t bit; 2336 uint16_t x; 2337 2338 usb_hs_bandwidth_alloc(xfer); 2339 2340 /* 2341 * Find the best QH position corresponding to the given interval: 2342 */ 2343 2344 best = 0; 2345 bit = EHCI_VIRTUAL_FRAMELIST_COUNT / 2; 2346 while (bit) { 2347 if (xfer->interval >= bit) { 2348 x = bit; 2349 best = bit; 2350 while (x & bit) { 2351 if (sc->sc_intr_stat[x] < 2352 sc->sc_intr_stat[best]) { 2353 best = x; 2354 } 2355 x++; 2356 } 2357 break; 2358 } 2359 bit >>= 1; 2360 } 2361 2362 sc->sc_intr_stat[best]++; 2363 xfer->qh_pos = best; 2364 2365 DPRINTFN(3, "best=%d interval=%d\n", 2366 best, xfer->interval); 2367 } 2368 2369 static void 2370 ehci_device_intr_close(struct usb_xfer *xfer) 2371 { 2372 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2373 2374 sc->sc_intr_stat[xfer->qh_pos]--; 2375 2376 ehci_device_done(xfer, USB_ERR_CANCELLED); 2377 2378 /* bandwidth must be freed after device done */ 2379 usb_hs_bandwidth_free(xfer); 2380 } 2381 2382 static void 2383 ehci_device_intr_enter(struct usb_xfer *xfer) 2384 { 2385 return; 2386 } 2387 2388 static void 2389 ehci_device_intr_start(struct usb_xfer *xfer) 2390 { 2391 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2392 2393 /* setup TD's and QH */ 2394 ehci_setup_standard_chain(xfer, &sc->sc_intr_p_last[xfer->qh_pos]); 2395 2396 /* put transfer on interrupt queue */ 2397 ehci_transfer_intr_enqueue(xfer); 2398 } 2399 2400 static const struct usb_pipe_methods ehci_device_intr_methods = 2401 { 2402 .open = ehci_device_intr_open, 2403 .close = ehci_device_intr_close, 2404 .enter = ehci_device_intr_enter, 2405 .start = ehci_device_intr_start, 2406 }; 2407 2408 /*------------------------------------------------------------------------* 2409 * ehci full speed isochronous support 2410 *------------------------------------------------------------------------*/ 2411 static void 2412 ehci_device_isoc_fs_open(struct usb_xfer *xfer) 2413 { 2414 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2415 ehci_sitd_t *td; 2416 uint32_t sitd_portaddr; 2417 uint8_t ds; 2418 2419 sitd_portaddr = 2420 EHCI_SITD_SET_ADDR(xfer->address) | 2421 EHCI_SITD_SET_ENDPT(UE_GET_ADDR(xfer->endpointno)) | 2422 EHCI_SITD_SET_HUBA(xfer->xroot->udev->hs_hub_addr) | 2423 EHCI_SITD_SET_PORT(xfer->xroot->udev->hs_port_no); 2424 2425 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) 2426 sitd_portaddr |= EHCI_SITD_SET_DIR_IN; 2427 2428 sitd_portaddr = htohc32(sc, sitd_portaddr); 2429 2430 /* initialize all TD's */ 2431 2432 for (ds = 0; ds != 2; ds++) { 2433 2434 for (td = xfer->td_start[ds]; td; td = td->obj_next) { 2435 2436 td->sitd_portaddr = sitd_portaddr; 2437 2438 /* 2439 * TODO: make some kind of automatic 2440 * SMASK/CMASK selection based on micro-frame 2441 * usage 2442 * 2443 * micro-frame usage (8 microframes per 1ms) 2444 */ 2445 td->sitd_back = htohc32(sc, EHCI_LINK_TERMINATE); 2446 2447 usb_pc_cpu_flush(td->page_cache); 2448 } 2449 } 2450 } 2451 2452 static void 2453 ehci_device_isoc_fs_close(struct usb_xfer *xfer) 2454 { 2455 ehci_device_done(xfer, USB_ERR_CANCELLED); 2456 } 2457 2458 static void 2459 ehci_device_isoc_fs_enter(struct usb_xfer *xfer) 2460 { 2461 struct usb_page_search buf_res; 2462 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2463 ehci_sitd_t *td; 2464 ehci_sitd_t *td_last = NULL; 2465 ehci_sitd_t **pp_last; 2466 uint32_t *plen; 2467 uint32_t buf_offset; 2468 uint32_t nframes; 2469 uint32_t temp; 2470 uint32_t sitd_mask; 2471 uint16_t tlen; 2472 uint8_t sa; 2473 uint8_t sb; 2474 2475 #ifdef USB_DEBUG 2476 uint8_t once = 1; 2477 2478 #endif 2479 2480 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 2481 xfer, xfer->endpoint->isoc_next, xfer->nframes); 2482 2483 /* get the current frame index */ 2484 2485 nframes = EOREAD4(sc, EHCI_FRINDEX) / 8; 2486 2487 /* 2488 * check if the frame index is within the window where the frames 2489 * will be inserted 2490 */ 2491 buf_offset = (nframes - xfer->endpoint->isoc_next) & 2492 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2493 2494 if ((xfer->endpoint->is_synced == 0) || 2495 (buf_offset < xfer->nframes)) { 2496 /* 2497 * If there is data underflow or the pipe queue is empty we 2498 * schedule the transfer a few frames ahead of the current 2499 * frame position. Else two isochronous transfers might 2500 * overlap. 2501 */ 2502 xfer->endpoint->isoc_next = (nframes + 3) & 2503 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2504 xfer->endpoint->is_synced = 1; 2505 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 2506 } 2507 /* 2508 * compute how many milliseconds the insertion is ahead of the 2509 * current frame position: 2510 */ 2511 buf_offset = (xfer->endpoint->isoc_next - nframes) & 2512 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2513 2514 /* 2515 * pre-compute when the isochronous transfer will be finished: 2516 */ 2517 xfer->isoc_time_complete = 2518 usb_isoc_time_expand(&sc->sc_bus, nframes) + 2519 buf_offset + xfer->nframes; 2520 2521 /* get the real number of frames */ 2522 2523 nframes = xfer->nframes; 2524 2525 buf_offset = 0; 2526 2527 plen = xfer->frlengths; 2528 2529 /* toggle the DMA set we are using */ 2530 xfer->flags_int.curr_dma_set ^= 1; 2531 2532 /* get next DMA set */ 2533 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 2534 xfer->td_transfer_first = td; 2535 2536 pp_last = &sc->sc_isoc_fs_p_last[xfer->endpoint->isoc_next]; 2537 2538 /* store starting position */ 2539 2540 xfer->qh_pos = xfer->endpoint->isoc_next; 2541 2542 while (nframes--) { 2543 if (td == NULL) { 2544 panic("%s:%d: out of TD's\n", 2545 __FUNCTION__, __LINE__); 2546 } 2547 if (pp_last >= &sc->sc_isoc_fs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) 2548 pp_last = &sc->sc_isoc_fs_p_last[0]; 2549 2550 /* reuse sitd_portaddr and sitd_back from last transfer */ 2551 2552 if (*plen > xfer->max_frame_size) { 2553 #ifdef USB_DEBUG 2554 if (once) { 2555 once = 0; 2556 printf("%s: frame length(%d) exceeds %d " 2557 "bytes (frame truncated)\n", 2558 __FUNCTION__, *plen, 2559 xfer->max_frame_size); 2560 } 2561 #endif 2562 *plen = xfer->max_frame_size; 2563 } 2564 2565 /* allocate a slot */ 2566 2567 sa = usbd_fs_isoc_schedule_alloc_slot(xfer, 2568 xfer->isoc_time_complete - nframes - 1); 2569 2570 if (sa == 255) { 2571 /* 2572 * Schedule is FULL, set length to zero: 2573 */ 2574 2575 *plen = 0; 2576 sa = USB_FS_ISOC_UFRAME_MAX - 1; 2577 } 2578 if (*plen) { 2579 /* 2580 * only call "usbd_get_page()" when we have a 2581 * non-zero length 2582 */ 2583 usbd_get_page(xfer->frbuffers, buf_offset, &buf_res); 2584 td->sitd_bp[0] = htohc32(sc, buf_res.physaddr); 2585 buf_offset += *plen; 2586 /* 2587 * NOTE: We need to subtract one from the offset so 2588 * that we are on a valid page! 2589 */ 2590 usbd_get_page(xfer->frbuffers, buf_offset - 1, 2591 &buf_res); 2592 temp = buf_res.physaddr & ~0xFFF; 2593 } else { 2594 td->sitd_bp[0] = 0; 2595 temp = 0; 2596 } 2597 2598 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_OUT) { 2599 tlen = *plen; 2600 if (tlen <= 188) { 2601 temp |= 1; /* T-count = 1, TP = ALL */ 2602 tlen = 1; 2603 } else { 2604 tlen += 187; 2605 tlen /= 188; 2606 temp |= tlen; /* T-count = [1..6] */ 2607 temp |= 8; /* TP = Begin */ 2608 } 2609 2610 tlen += sa; 2611 2612 if (tlen >= 8) { 2613 sb = 0; 2614 } else { 2615 sb = (1 << tlen); 2616 } 2617 2618 sa = (1 << sa); 2619 sa = (sb - sa) & 0x3F; 2620 sb = 0; 2621 } else { 2622 sb = (-(4 << sa)) & 0xFE; 2623 sa = (1 << sa) & 0x3F; 2624 } 2625 2626 sitd_mask = (EHCI_SITD_SET_SMASK(sa) | 2627 EHCI_SITD_SET_CMASK(sb)); 2628 2629 td->sitd_bp[1] = htohc32(sc, temp); 2630 2631 td->sitd_mask = htohc32(sc, sitd_mask); 2632 2633 if (nframes == 0) { 2634 td->sitd_status = htohc32(sc, 2635 EHCI_SITD_IOC | 2636 EHCI_SITD_ACTIVE | 2637 EHCI_SITD_SET_LEN(*plen)); 2638 } else { 2639 td->sitd_status = htohc32(sc, 2640 EHCI_SITD_ACTIVE | 2641 EHCI_SITD_SET_LEN(*plen)); 2642 } 2643 usb_pc_cpu_flush(td->page_cache); 2644 2645 #ifdef USB_DEBUG 2646 if (ehcidebug > 15) { 2647 DPRINTF("FS-TD %d\n", nframes); 2648 ehci_dump_sitd(sc, td); 2649 } 2650 #endif 2651 /* insert TD into schedule */ 2652 EHCI_APPEND_FS_TD(td, *pp_last); 2653 pp_last++; 2654 2655 plen++; 2656 td_last = td; 2657 td = td->obj_next; 2658 } 2659 2660 xfer->td_transfer_last = td_last; 2661 2662 /* update isoc_next */ 2663 xfer->endpoint->isoc_next = (pp_last - &sc->sc_isoc_fs_p_last[0]) & 2664 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2665 2666 /* 2667 * We don't allow cancelling of the SPLIT transaction USB FULL 2668 * speed transfer, because it disturbs the bandwidth 2669 * computation algorithm. 2670 */ 2671 xfer->flags_int.can_cancel_immed = 0; 2672 } 2673 2674 static void 2675 ehci_device_isoc_fs_start(struct usb_xfer *xfer) 2676 { 2677 /* 2678 * We don't allow cancelling of the SPLIT transaction USB FULL 2679 * speed transfer, because it disturbs the bandwidth 2680 * computation algorithm. 2681 */ 2682 xfer->flags_int.can_cancel_immed = 0; 2683 2684 /* set a default timeout */ 2685 if (xfer->timeout == 0) 2686 xfer->timeout = 500; /* ms */ 2687 2688 /* put transfer on interrupt queue */ 2689 ehci_transfer_intr_enqueue(xfer); 2690 } 2691 2692 static const struct usb_pipe_methods ehci_device_isoc_fs_methods = 2693 { 2694 .open = ehci_device_isoc_fs_open, 2695 .close = ehci_device_isoc_fs_close, 2696 .enter = ehci_device_isoc_fs_enter, 2697 .start = ehci_device_isoc_fs_start, 2698 }; 2699 2700 /*------------------------------------------------------------------------* 2701 * ehci high speed isochronous support 2702 *------------------------------------------------------------------------*/ 2703 static void 2704 ehci_device_isoc_hs_open(struct usb_xfer *xfer) 2705 { 2706 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2707 ehci_itd_t *td; 2708 uint32_t temp; 2709 uint8_t ds; 2710 2711 usb_hs_bandwidth_alloc(xfer); 2712 2713 /* initialize all TD's */ 2714 2715 for (ds = 0; ds != 2; ds++) { 2716 2717 for (td = xfer->td_start[ds]; td; td = td->obj_next) { 2718 2719 /* set TD inactive */ 2720 td->itd_status[0] = 0; 2721 td->itd_status[1] = 0; 2722 td->itd_status[2] = 0; 2723 td->itd_status[3] = 0; 2724 td->itd_status[4] = 0; 2725 td->itd_status[5] = 0; 2726 td->itd_status[6] = 0; 2727 td->itd_status[7] = 0; 2728 2729 /* set endpoint and address */ 2730 td->itd_bp[0] = htohc32(sc, 2731 EHCI_ITD_SET_ADDR(xfer->address) | 2732 EHCI_ITD_SET_ENDPT(UE_GET_ADDR(xfer->endpointno))); 2733 2734 temp = 2735 EHCI_ITD_SET_MPL(xfer->max_packet_size & 0x7FF); 2736 2737 /* set direction */ 2738 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) { 2739 temp |= EHCI_ITD_SET_DIR_IN; 2740 } 2741 /* set maximum packet size */ 2742 td->itd_bp[1] = htohc32(sc, temp); 2743 2744 /* set transfer multiplier */ 2745 td->itd_bp[2] = htohc32(sc, xfer->max_packet_count & 3); 2746 2747 usb_pc_cpu_flush(td->page_cache); 2748 } 2749 } 2750 } 2751 2752 static void 2753 ehci_device_isoc_hs_close(struct usb_xfer *xfer) 2754 { 2755 ehci_device_done(xfer, USB_ERR_CANCELLED); 2756 2757 /* bandwidth must be freed after device done */ 2758 usb_hs_bandwidth_free(xfer); 2759 } 2760 2761 static void 2762 ehci_device_isoc_hs_enter(struct usb_xfer *xfer) 2763 { 2764 struct usb_page_search buf_res; 2765 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2766 ehci_itd_t *td; 2767 ehci_itd_t *td_last = NULL; 2768 ehci_itd_t **pp_last; 2769 bus_size_t page_addr; 2770 uint32_t *plen; 2771 uint32_t status; 2772 uint32_t buf_offset; 2773 uint32_t nframes; 2774 uint32_t itd_offset[8 + 1]; 2775 uint8_t x; 2776 uint8_t td_no; 2777 uint8_t page_no; 2778 uint8_t shift = usbd_xfer_get_fps_shift(xfer); 2779 2780 #ifdef USB_DEBUG 2781 uint8_t once = 1; 2782 2783 #endif 2784 2785 DPRINTFN(6, "xfer=%p next=%d nframes=%d shift=%d\n", 2786 xfer, xfer->endpoint->isoc_next, xfer->nframes, (int)shift); 2787 2788 /* get the current frame index */ 2789 2790 nframes = EOREAD4(sc, EHCI_FRINDEX) / 8; 2791 2792 /* 2793 * check if the frame index is within the window where the frames 2794 * will be inserted 2795 */ 2796 buf_offset = (nframes - xfer->endpoint->isoc_next) & 2797 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2798 2799 if ((xfer->endpoint->is_synced == 0) || 2800 (buf_offset < (((xfer->nframes << shift) + 7) / 8))) { 2801 /* 2802 * If there is data underflow or the pipe queue is empty we 2803 * schedule the transfer a few frames ahead of the current 2804 * frame position. Else two isochronous transfers might 2805 * overlap. 2806 */ 2807 xfer->endpoint->isoc_next = (nframes + 3) & 2808 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2809 xfer->endpoint->is_synced = 1; 2810 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 2811 } 2812 /* 2813 * compute how many milliseconds the insertion is ahead of the 2814 * current frame position: 2815 */ 2816 buf_offset = (xfer->endpoint->isoc_next - nframes) & 2817 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2818 2819 /* 2820 * pre-compute when the isochronous transfer will be finished: 2821 */ 2822 xfer->isoc_time_complete = 2823 usb_isoc_time_expand(&sc->sc_bus, nframes) + buf_offset + 2824 (((xfer->nframes << shift) + 7) / 8); 2825 2826 /* get the real number of frames */ 2827 2828 nframes = xfer->nframes; 2829 2830 buf_offset = 0; 2831 td_no = 0; 2832 2833 plen = xfer->frlengths; 2834 2835 /* toggle the DMA set we are using */ 2836 xfer->flags_int.curr_dma_set ^= 1; 2837 2838 /* get next DMA set */ 2839 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 2840 xfer->td_transfer_first = td; 2841 2842 pp_last = &sc->sc_isoc_hs_p_last[xfer->endpoint->isoc_next]; 2843 2844 /* store starting position */ 2845 2846 xfer->qh_pos = xfer->endpoint->isoc_next; 2847 2848 while (nframes) { 2849 if (td == NULL) { 2850 panic("%s:%d: out of TD's\n", 2851 __FUNCTION__, __LINE__); 2852 } 2853 if (pp_last >= &sc->sc_isoc_hs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) { 2854 pp_last = &sc->sc_isoc_hs_p_last[0]; 2855 } 2856 /* range check */ 2857 if (*plen > xfer->max_frame_size) { 2858 #ifdef USB_DEBUG 2859 if (once) { 2860 once = 0; 2861 printf("%s: frame length(%d) exceeds %d bytes " 2862 "(frame truncated)\n", 2863 __FUNCTION__, *plen, xfer->max_frame_size); 2864 } 2865 #endif 2866 *plen = xfer->max_frame_size; 2867 } 2868 2869 if (xfer->endpoint->usb_smask & (1 << td_no)) { 2870 status = (EHCI_ITD_SET_LEN(*plen) | 2871 EHCI_ITD_ACTIVE | 2872 EHCI_ITD_SET_PG(0)); 2873 td->itd_status[td_no] = htohc32(sc, status); 2874 itd_offset[td_no] = buf_offset; 2875 buf_offset += *plen; 2876 plen++; 2877 nframes --; 2878 } else { 2879 td->itd_status[td_no] = 0; /* not active */ 2880 itd_offset[td_no] = buf_offset; 2881 } 2882 2883 td_no++; 2884 2885 if ((td_no == 8) || (nframes == 0)) { 2886 2887 /* the rest of the transfers are not active, if any */ 2888 for (x = td_no; x != 8; x++) { 2889 td->itd_status[x] = 0; /* not active */ 2890 } 2891 2892 /* check if there is any data to be transferred */ 2893 if (itd_offset[0] != buf_offset) { 2894 page_no = 0; 2895 itd_offset[td_no] = buf_offset; 2896 2897 /* get first page offset */ 2898 usbd_get_page(xfer->frbuffers, itd_offset[0], &buf_res); 2899 /* get page address */ 2900 page_addr = buf_res.physaddr & ~0xFFF; 2901 /* update page address */ 2902 td->itd_bp[0] &= htohc32(sc, 0xFFF); 2903 td->itd_bp[0] |= htohc32(sc, page_addr); 2904 2905 for (x = 0; x != td_no; x++) { 2906 /* set page number and page offset */ 2907 status = (EHCI_ITD_SET_PG(page_no) | 2908 (buf_res.physaddr & 0xFFF)); 2909 td->itd_status[x] |= htohc32(sc, status); 2910 2911 /* get next page offset */ 2912 if (itd_offset[x + 1] == buf_offset) { 2913 /* 2914 * We subtract one so that 2915 * we don't go off the last 2916 * page! 2917 */ 2918 usbd_get_page(xfer->frbuffers, buf_offset - 1, &buf_res); 2919 } else { 2920 usbd_get_page(xfer->frbuffers, itd_offset[x + 1], &buf_res); 2921 } 2922 2923 /* check if we need a new page */ 2924 if ((buf_res.physaddr ^ page_addr) & ~0xFFF) { 2925 /* new page needed */ 2926 page_addr = buf_res.physaddr & ~0xFFF; 2927 if (page_no == 6) { 2928 panic("%s: too many pages\n", __FUNCTION__); 2929 } 2930 page_no++; 2931 /* update page address */ 2932 td->itd_bp[page_no] &= htohc32(sc, 0xFFF); 2933 td->itd_bp[page_no] |= htohc32(sc, page_addr); 2934 } 2935 } 2936 } 2937 /* set IOC bit if we are complete */ 2938 if (nframes == 0) { 2939 td->itd_status[td_no - 1] |= htohc32(sc, EHCI_ITD_IOC); 2940 } 2941 usb_pc_cpu_flush(td->page_cache); 2942 #ifdef USB_DEBUG 2943 if (ehcidebug > 15) { 2944 DPRINTF("HS-TD %d\n", nframes); 2945 ehci_dump_itd(sc, td); 2946 } 2947 #endif 2948 /* insert TD into schedule */ 2949 EHCI_APPEND_HS_TD(td, *pp_last); 2950 pp_last++; 2951 2952 td_no = 0; 2953 td_last = td; 2954 td = td->obj_next; 2955 } 2956 } 2957 2958 xfer->td_transfer_last = td_last; 2959 2960 /* update isoc_next */ 2961 xfer->endpoint->isoc_next = (pp_last - &sc->sc_isoc_hs_p_last[0]) & 2962 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2963 } 2964 2965 static void 2966 ehci_device_isoc_hs_start(struct usb_xfer *xfer) 2967 { 2968 /* put transfer on interrupt queue */ 2969 ehci_transfer_intr_enqueue(xfer); 2970 } 2971 2972 static const struct usb_pipe_methods ehci_device_isoc_hs_methods = 2973 { 2974 .open = ehci_device_isoc_hs_open, 2975 .close = ehci_device_isoc_hs_close, 2976 .enter = ehci_device_isoc_hs_enter, 2977 .start = ehci_device_isoc_hs_start, 2978 }; 2979 2980 /*------------------------------------------------------------------------* 2981 * ehci root control support 2982 *------------------------------------------------------------------------* 2983 * Simulate a hardware hub by handling all the necessary requests. 2984 *------------------------------------------------------------------------*/ 2985 2986 static const 2987 struct usb_device_descriptor ehci_devd = 2988 { 2989 sizeof(struct usb_device_descriptor), 2990 UDESC_DEVICE, /* type */ 2991 {0x00, 0x02}, /* USB version */ 2992 UDCLASS_HUB, /* class */ 2993 UDSUBCLASS_HUB, /* subclass */ 2994 UDPROTO_HSHUBSTT, /* protocol */ 2995 64, /* max packet */ 2996 {0}, {0}, {0x00, 0x01}, /* device id */ 2997 1, 2, 0, /* string indexes */ 2998 1 /* # of configurations */ 2999 }; 3000 3001 static const 3002 struct usb_device_qualifier ehci_odevd = 3003 { 3004 sizeof(struct usb_device_qualifier), 3005 UDESC_DEVICE_QUALIFIER, /* type */ 3006 {0x00, 0x02}, /* USB version */ 3007 UDCLASS_HUB, /* class */ 3008 UDSUBCLASS_HUB, /* subclass */ 3009 UDPROTO_FSHUB, /* protocol */ 3010 0, /* max packet */ 3011 0, /* # of configurations */ 3012 0 3013 }; 3014 3015 static const struct ehci_config_desc ehci_confd = { 3016 .confd = { 3017 .bLength = sizeof(struct usb_config_descriptor), 3018 .bDescriptorType = UDESC_CONFIG, 3019 .wTotalLength[0] = sizeof(ehci_confd), 3020 .bNumInterface = 1, 3021 .bConfigurationValue = 1, 3022 .iConfiguration = 0, 3023 .bmAttributes = UC_SELF_POWERED, 3024 .bMaxPower = 0 /* max power */ 3025 }, 3026 .ifcd = { 3027 .bLength = sizeof(struct usb_interface_descriptor), 3028 .bDescriptorType = UDESC_INTERFACE, 3029 .bNumEndpoints = 1, 3030 .bInterfaceClass = UICLASS_HUB, 3031 .bInterfaceSubClass = UISUBCLASS_HUB, 3032 .bInterfaceProtocol = 0, 3033 }, 3034 .endpd = { 3035 .bLength = sizeof(struct usb_endpoint_descriptor), 3036 .bDescriptorType = UDESC_ENDPOINT, 3037 .bEndpointAddress = UE_DIR_IN | EHCI_INTR_ENDPT, 3038 .bmAttributes = UE_INTERRUPT, 3039 .wMaxPacketSize[0] = 8, /* max packet (63 ports) */ 3040 .bInterval = 255, 3041 }, 3042 }; 3043 3044 static const 3045 struct usb_hub_descriptor ehci_hubd = 3046 { 3047 .bDescLength = 0, /* dynamic length */ 3048 .bDescriptorType = UDESC_HUB, 3049 }; 3050 3051 uint16_t 3052 ehci_get_port_speed_portsc(struct ehci_softc *sc, uint16_t index) 3053 { 3054 uint32_t v; 3055 3056 v = EOREAD4(sc, EHCI_PORTSC(index)); 3057 v = (v >> EHCI_PORTSC_PSPD_SHIFT) & EHCI_PORTSC_PSPD_MASK; 3058 3059 if (v == EHCI_PORT_SPEED_HIGH) 3060 return (UPS_HIGH_SPEED); 3061 if (v == EHCI_PORT_SPEED_LOW) 3062 return (UPS_LOW_SPEED); 3063 return (0); 3064 } 3065 3066 uint16_t 3067 ehci_get_port_speed_hostc(struct ehci_softc *sc, uint16_t index) 3068 { 3069 uint32_t v; 3070 3071 v = EOREAD4(sc, EHCI_HOSTC(index)); 3072 v = (v >> EHCI_HOSTC_PSPD_SHIFT) & EHCI_HOSTC_PSPD_MASK; 3073 3074 if (v == EHCI_PORT_SPEED_HIGH) 3075 return (UPS_HIGH_SPEED); 3076 if (v == EHCI_PORT_SPEED_LOW) 3077 return (UPS_LOW_SPEED); 3078 return (0); 3079 } 3080 3081 static void 3082 ehci_disown(ehci_softc_t *sc, uint16_t index, uint8_t lowspeed) 3083 { 3084 uint32_t port; 3085 uint32_t v; 3086 3087 DPRINTF("index=%d lowspeed=%d\n", index, lowspeed); 3088 3089 port = EHCI_PORTSC(index); 3090 v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR; 3091 EOWRITE4(sc, port, v | EHCI_PS_PO); 3092 } 3093 3094 static usb_error_t 3095 ehci_roothub_exec(struct usb_device *udev, 3096 struct usb_device_request *req, const void **pptr, uint16_t *plength) 3097 { 3098 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus); 3099 const char *str_ptr; 3100 const void *ptr; 3101 uint32_t port; 3102 uint32_t v; 3103 uint16_t len; 3104 uint16_t i; 3105 uint16_t value; 3106 uint16_t index; 3107 usb_error_t err; 3108 3109 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 3110 3111 /* buffer reset */ 3112 ptr = (const void *)&sc->sc_hub_desc; 3113 len = 0; 3114 err = 0; 3115 3116 value = UGETW(req->wValue); 3117 index = UGETW(req->wIndex); 3118 3119 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x " 3120 "wValue=0x%04x wIndex=0x%04x\n", 3121 req->bmRequestType, req->bRequest, 3122 UGETW(req->wLength), value, index); 3123 3124 #define C(x,y) ((x) | ((y) << 8)) 3125 switch (C(req->bRequest, req->bmRequestType)) { 3126 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 3127 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 3128 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 3129 /* 3130 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 3131 * for the integrated root hub. 3132 */ 3133 break; 3134 case C(UR_GET_CONFIG, UT_READ_DEVICE): 3135 len = 1; 3136 sc->sc_hub_desc.temp[0] = sc->sc_conf; 3137 break; 3138 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3139 switch (value >> 8) { 3140 case UDESC_DEVICE: 3141 if ((value & 0xff) != 0) { 3142 err = USB_ERR_IOERROR; 3143 goto done; 3144 } 3145 len = sizeof(ehci_devd); 3146 ptr = (const void *)&ehci_devd; 3147 break; 3148 /* 3149 * We can't really operate at another speed, 3150 * but the specification says we need this 3151 * descriptor: 3152 */ 3153 case UDESC_DEVICE_QUALIFIER: 3154 if ((value & 0xff) != 0) { 3155 err = USB_ERR_IOERROR; 3156 goto done; 3157 } 3158 len = sizeof(ehci_odevd); 3159 ptr = (const void *)&ehci_odevd; 3160 break; 3161 3162 case UDESC_CONFIG: 3163 if ((value & 0xff) != 0) { 3164 err = USB_ERR_IOERROR; 3165 goto done; 3166 } 3167 len = sizeof(ehci_confd); 3168 ptr = (const void *)&ehci_confd; 3169 break; 3170 3171 case UDESC_STRING: 3172 switch (value & 0xff) { 3173 case 0: /* Language table */ 3174 str_ptr = "\001"; 3175 break; 3176 3177 case 1: /* Vendor */ 3178 str_ptr = sc->sc_vendor; 3179 break; 3180 3181 case 2: /* Product */ 3182 str_ptr = "EHCI root HUB"; 3183 break; 3184 3185 default: 3186 str_ptr = ""; 3187 break; 3188 } 3189 3190 len = usb_make_str_desc( 3191 sc->sc_hub_desc.temp, 3192 sizeof(sc->sc_hub_desc.temp), 3193 str_ptr); 3194 break; 3195 default: 3196 err = USB_ERR_IOERROR; 3197 goto done; 3198 } 3199 break; 3200 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 3201 len = 1; 3202 sc->sc_hub_desc.temp[0] = 0; 3203 break; 3204 case C(UR_GET_STATUS, UT_READ_DEVICE): 3205 len = 2; 3206 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED); 3207 break; 3208 case C(UR_GET_STATUS, UT_READ_INTERFACE): 3209 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 3210 len = 2; 3211 USETW(sc->sc_hub_desc.stat.wStatus, 0); 3212 break; 3213 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 3214 if (value >= EHCI_MAX_DEVICES) { 3215 err = USB_ERR_IOERROR; 3216 goto done; 3217 } 3218 sc->sc_addr = value; 3219 break; 3220 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 3221 if ((value != 0) && (value != 1)) { 3222 err = USB_ERR_IOERROR; 3223 goto done; 3224 } 3225 sc->sc_conf = value; 3226 break; 3227 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 3228 break; 3229 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 3230 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 3231 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 3232 err = USB_ERR_IOERROR; 3233 goto done; 3234 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 3235 break; 3236 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 3237 break; 3238 /* Hub requests */ 3239 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3240 break; 3241 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3242 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n"); 3243 3244 if ((index < 1) || 3245 (index > sc->sc_noport)) { 3246 err = USB_ERR_IOERROR; 3247 goto done; 3248 } 3249 port = EHCI_PORTSC(index); 3250 v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR; 3251 switch (value) { 3252 case UHF_PORT_ENABLE: 3253 EOWRITE4(sc, port, v & ~EHCI_PS_PE); 3254 break; 3255 case UHF_PORT_SUSPEND: 3256 if ((v & EHCI_PS_SUSP) && (!(v & EHCI_PS_FPR))) { 3257 3258 /* 3259 * waking up a High Speed device is rather 3260 * complicated if 3261 */ 3262 EOWRITE4(sc, port, v | EHCI_PS_FPR); 3263 } 3264 /* wait 20ms for resume sequence to complete */ 3265 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50); 3266 3267 EOWRITE4(sc, port, v & ~(EHCI_PS_SUSP | 3268 EHCI_PS_FPR | (3 << 10) /* High Speed */ )); 3269 3270 /* 4ms settle time */ 3271 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250); 3272 break; 3273 case UHF_PORT_POWER: 3274 EOWRITE4(sc, port, v & ~EHCI_PS_PP); 3275 break; 3276 case UHF_PORT_TEST: 3277 DPRINTFN(3, "clear port test " 3278 "%d\n", index); 3279 break; 3280 case UHF_PORT_INDICATOR: 3281 DPRINTFN(3, "clear port ind " 3282 "%d\n", index); 3283 EOWRITE4(sc, port, v & ~EHCI_PS_PIC); 3284 break; 3285 case UHF_C_PORT_CONNECTION: 3286 EOWRITE4(sc, port, v | EHCI_PS_CSC); 3287 break; 3288 case UHF_C_PORT_ENABLE: 3289 EOWRITE4(sc, port, v | EHCI_PS_PEC); 3290 break; 3291 case UHF_C_PORT_SUSPEND: 3292 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 3293 break; 3294 case UHF_C_PORT_OVER_CURRENT: 3295 EOWRITE4(sc, port, v | EHCI_PS_OCC); 3296 break; 3297 case UHF_C_PORT_RESET: 3298 sc->sc_isreset = 0; 3299 break; 3300 default: 3301 err = USB_ERR_IOERROR; 3302 goto done; 3303 } 3304 break; 3305 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3306 if ((value & 0xff) != 0) { 3307 err = USB_ERR_IOERROR; 3308 goto done; 3309 } 3310 v = EREAD4(sc, EHCI_HCSPARAMS); 3311 3312 sc->sc_hub_desc.hubd = ehci_hubd; 3313 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport; 3314 3315 if (EHCI_HCS_PPC(v)) 3316 i = UHD_PWR_INDIVIDUAL; 3317 else 3318 i = UHD_PWR_NO_SWITCH; 3319 3320 if (EHCI_HCS_P_INDICATOR(v)) 3321 i |= UHD_PORT_IND; 3322 3323 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, i); 3324 /* XXX can't find out? */ 3325 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 200; 3326 /* XXX don't know if ports are removable or not */ 3327 sc->sc_hub_desc.hubd.bDescLength = 3328 8 + ((sc->sc_noport + 7) / 8); 3329 len = sc->sc_hub_desc.hubd.bDescLength; 3330 break; 3331 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3332 len = 16; 3333 memset(sc->sc_hub_desc.temp, 0, 16); 3334 break; 3335 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3336 DPRINTFN(9, "get port status i=%d\n", 3337 index); 3338 if ((index < 1) || 3339 (index > sc->sc_noport)) { 3340 err = USB_ERR_IOERROR; 3341 goto done; 3342 } 3343 v = EOREAD4(sc, EHCI_PORTSC(index)); 3344 DPRINTFN(9, "port status=0x%04x\n", v); 3345 if (sc->sc_flags & EHCI_SCFLG_TT) { 3346 if (sc->sc_vendor_get_port_speed != NULL) { 3347 i = sc->sc_vendor_get_port_speed(sc, index); 3348 } else { 3349 device_printf(sc->sc_bus.bdev, 3350 "EHCI_SCFLG_TT quirk is set but " 3351 "sc_vendor_get_hub_speed() is NULL\n"); 3352 i = UPS_HIGH_SPEED; 3353 } 3354 } else { 3355 i = UPS_HIGH_SPEED; 3356 } 3357 if (v & EHCI_PS_CS) 3358 i |= UPS_CURRENT_CONNECT_STATUS; 3359 if (v & EHCI_PS_PE) 3360 i |= UPS_PORT_ENABLED; 3361 if ((v & EHCI_PS_SUSP) && !(v & EHCI_PS_FPR)) 3362 i |= UPS_SUSPEND; 3363 if (v & EHCI_PS_OCA) 3364 i |= UPS_OVERCURRENT_INDICATOR; 3365 if (v & EHCI_PS_PR) 3366 i |= UPS_RESET; 3367 if (v & EHCI_PS_PP) 3368 i |= UPS_PORT_POWER; 3369 USETW(sc->sc_hub_desc.ps.wPortStatus, i); 3370 i = 0; 3371 if (v & EHCI_PS_CSC) 3372 i |= UPS_C_CONNECT_STATUS; 3373 if (v & EHCI_PS_PEC) 3374 i |= UPS_C_PORT_ENABLED; 3375 if (v & EHCI_PS_OCC) 3376 i |= UPS_C_OVERCURRENT_INDICATOR; 3377 if (v & EHCI_PS_FPR) 3378 i |= UPS_C_SUSPEND; 3379 if (sc->sc_isreset) 3380 i |= UPS_C_PORT_RESET; 3381 USETW(sc->sc_hub_desc.ps.wPortChange, i); 3382 len = sizeof(sc->sc_hub_desc.ps); 3383 break; 3384 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3385 err = USB_ERR_IOERROR; 3386 goto done; 3387 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3388 break; 3389 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 3390 if ((index < 1) || 3391 (index > sc->sc_noport)) { 3392 err = USB_ERR_IOERROR; 3393 goto done; 3394 } 3395 port = EHCI_PORTSC(index); 3396 v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR; 3397 switch (value) { 3398 case UHF_PORT_ENABLE: 3399 EOWRITE4(sc, port, v | EHCI_PS_PE); 3400 break; 3401 case UHF_PORT_SUSPEND: 3402 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 3403 break; 3404 case UHF_PORT_RESET: 3405 DPRINTFN(6, "reset port %d\n", index); 3406 #ifdef USB_DEBUG 3407 if (ehcinohighspeed) { 3408 /* 3409 * Connect USB device to companion 3410 * controller. 3411 */ 3412 ehci_disown(sc, index, 1); 3413 break; 3414 } 3415 #endif 3416 if (EHCI_PS_IS_LOWSPEED(v) && 3417 (sc->sc_flags & EHCI_SCFLG_TT) == 0) { 3418 /* Low speed device, give up ownership. */ 3419 ehci_disown(sc, index, 1); 3420 break; 3421 } 3422 /* Start reset sequence. */ 3423 v &= ~(EHCI_PS_PE | EHCI_PS_PR); 3424 EOWRITE4(sc, port, v | EHCI_PS_PR); 3425 3426 /* Wait for reset to complete. */ 3427 usb_pause_mtx(&sc->sc_bus.bus_mtx, 3428 USB_MS_TO_TICKS(usb_port_root_reset_delay)); 3429 3430 /* Terminate reset sequence. */ 3431 if (!(sc->sc_flags & EHCI_SCFLG_NORESTERM)) 3432 EOWRITE4(sc, port, v); 3433 3434 /* Wait for HC to complete reset. */ 3435 usb_pause_mtx(&sc->sc_bus.bus_mtx, 3436 USB_MS_TO_TICKS(EHCI_PORT_RESET_COMPLETE)); 3437 3438 v = EOREAD4(sc, port); 3439 DPRINTF("ehci after reset, status=0x%08x\n", v); 3440 if (v & EHCI_PS_PR) { 3441 device_printf(sc->sc_bus.bdev, 3442 "port reset timeout\n"); 3443 err = USB_ERR_TIMEOUT; 3444 goto done; 3445 } 3446 if (!(v & EHCI_PS_PE) && 3447 (sc->sc_flags & EHCI_SCFLG_TT) == 0) { 3448 /* Not a high speed device, give up ownership.*/ 3449 ehci_disown(sc, index, 0); 3450 break; 3451 } 3452 sc->sc_isreset = 1; 3453 DPRINTF("ehci port %d reset, status = 0x%08x\n", 3454 index, v); 3455 break; 3456 3457 case UHF_PORT_POWER: 3458 DPRINTFN(3, "set port power %d\n", index); 3459 EOWRITE4(sc, port, v | EHCI_PS_PP); 3460 break; 3461 3462 case UHF_PORT_TEST: 3463 DPRINTFN(3, "set port test %d\n", index); 3464 break; 3465 3466 case UHF_PORT_INDICATOR: 3467 DPRINTFN(3, "set port ind %d\n", index); 3468 EOWRITE4(sc, port, v | EHCI_PS_PIC); 3469 break; 3470 3471 default: 3472 err = USB_ERR_IOERROR; 3473 goto done; 3474 } 3475 break; 3476 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 3477 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 3478 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 3479 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 3480 break; 3481 default: 3482 err = USB_ERR_IOERROR; 3483 goto done; 3484 } 3485 done: 3486 *plength = len; 3487 *pptr = ptr; 3488 return (err); 3489 } 3490 3491 static void 3492 ehci_xfer_setup(struct usb_setup_params *parm) 3493 { 3494 struct usb_page_search page_info; 3495 struct usb_page_cache *pc; 3496 ehci_softc_t *sc; 3497 struct usb_xfer *xfer; 3498 void *last_obj; 3499 uint32_t nqtd; 3500 uint32_t nqh; 3501 uint32_t nsitd; 3502 uint32_t nitd; 3503 uint32_t n; 3504 3505 sc = EHCI_BUS2SC(parm->udev->bus); 3506 xfer = parm->curr_xfer; 3507 3508 nqtd = 0; 3509 nqh = 0; 3510 nsitd = 0; 3511 nitd = 0; 3512 3513 /* 3514 * compute maximum number of some structures 3515 */ 3516 if (parm->methods == &ehci_device_ctrl_methods) { 3517 3518 /* 3519 * The proof for the "nqtd" formula is illustrated like 3520 * this: 3521 * 3522 * +------------------------------------+ 3523 * | | 3524 * | |remainder -> | 3525 * | +-----+---+ | 3526 * | | xxx | x | frm 0 | 3527 * | +-----+---++ | 3528 * | | xxx | xx | frm 1 | 3529 * | +-----+----+ | 3530 * | ... | 3531 * +------------------------------------+ 3532 * 3533 * "xxx" means a completely full USB transfer descriptor 3534 * 3535 * "x" and "xx" means a short USB packet 3536 * 3537 * For the remainder of an USB transfer modulo 3538 * "max_data_length" we need two USB transfer descriptors. 3539 * One to transfer the remaining data and one to finalise 3540 * with a zero length packet in case the "force_short_xfer" 3541 * flag is set. We only need two USB transfer descriptors in 3542 * the case where the transfer length of the first one is a 3543 * factor of "max_frame_size". The rest of the needed USB 3544 * transfer descriptors is given by the buffer size divided 3545 * by the maximum data payload. 3546 */ 3547 parm->hc_max_packet_size = 0x400; 3548 parm->hc_max_packet_count = 1; 3549 parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX; 3550 xfer->flags_int.bdma_enable = 1; 3551 3552 usbd_transfer_setup_sub(parm); 3553 3554 nqh = 1; 3555 nqtd = ((2 * xfer->nframes) + 1 /* STATUS */ 3556 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3557 3558 } else if (parm->methods == &ehci_device_bulk_methods) { 3559 3560 parm->hc_max_packet_size = 0x400; 3561 parm->hc_max_packet_count = 1; 3562 parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX; 3563 xfer->flags_int.bdma_enable = 1; 3564 3565 usbd_transfer_setup_sub(parm); 3566 3567 nqh = 1; 3568 nqtd = ((2 * xfer->nframes) 3569 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3570 3571 } else if (parm->methods == &ehci_device_intr_methods) { 3572 3573 if (parm->speed == USB_SPEED_HIGH) { 3574 parm->hc_max_packet_size = 0x400; 3575 parm->hc_max_packet_count = 3; 3576 } else if (parm->speed == USB_SPEED_FULL) { 3577 parm->hc_max_packet_size = USB_FS_BYTES_PER_HS_UFRAME; 3578 parm->hc_max_packet_count = 1; 3579 } else { 3580 parm->hc_max_packet_size = USB_FS_BYTES_PER_HS_UFRAME / 8; 3581 parm->hc_max_packet_count = 1; 3582 } 3583 3584 parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX; 3585 xfer->flags_int.bdma_enable = 1; 3586 3587 usbd_transfer_setup_sub(parm); 3588 3589 nqh = 1; 3590 nqtd = ((2 * xfer->nframes) 3591 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3592 3593 } else if (parm->methods == &ehci_device_isoc_fs_methods) { 3594 3595 parm->hc_max_packet_size = 0x3FF; 3596 parm->hc_max_packet_count = 1; 3597 parm->hc_max_frame_size = 0x3FF; 3598 xfer->flags_int.bdma_enable = 1; 3599 3600 usbd_transfer_setup_sub(parm); 3601 3602 nsitd = xfer->nframes; 3603 3604 } else if (parm->methods == &ehci_device_isoc_hs_methods) { 3605 3606 parm->hc_max_packet_size = 0x400; 3607 parm->hc_max_packet_count = 3; 3608 parm->hc_max_frame_size = 0xC00; 3609 xfer->flags_int.bdma_enable = 1; 3610 3611 usbd_transfer_setup_sub(parm); 3612 3613 nitd = ((xfer->nframes + 7) / 8) << 3614 usbd_xfer_get_fps_shift(xfer); 3615 3616 } else { 3617 3618 parm->hc_max_packet_size = 0x400; 3619 parm->hc_max_packet_count = 1; 3620 parm->hc_max_frame_size = 0x400; 3621 3622 usbd_transfer_setup_sub(parm); 3623 } 3624 3625 alloc_dma_set: 3626 3627 if (parm->err) { 3628 return; 3629 } 3630 /* 3631 * Allocate queue heads and transfer descriptors 3632 */ 3633 last_obj = NULL; 3634 3635 if (usbd_transfer_setup_sub_malloc( 3636 parm, &pc, sizeof(ehci_itd_t), 3637 EHCI_ITD_ALIGN, nitd)) { 3638 parm->err = USB_ERR_NOMEM; 3639 return; 3640 } 3641 if (parm->buf) { 3642 for (n = 0; n != nitd; n++) { 3643 ehci_itd_t *td; 3644 3645 usbd_get_page(pc + n, 0, &page_info); 3646 3647 td = page_info.buffer; 3648 3649 /* init TD */ 3650 td->itd_self = htohc32(sc, page_info.physaddr | EHCI_LINK_ITD); 3651 td->obj_next = last_obj; 3652 td->page_cache = pc + n; 3653 3654 last_obj = td; 3655 3656 usb_pc_cpu_flush(pc + n); 3657 } 3658 } 3659 if (usbd_transfer_setup_sub_malloc( 3660 parm, &pc, sizeof(ehci_sitd_t), 3661 EHCI_SITD_ALIGN, nsitd)) { 3662 parm->err = USB_ERR_NOMEM; 3663 return; 3664 } 3665 if (parm->buf) { 3666 for (n = 0; n != nsitd; n++) { 3667 ehci_sitd_t *td; 3668 3669 usbd_get_page(pc + n, 0, &page_info); 3670 3671 td = page_info.buffer; 3672 3673 /* init TD */ 3674 td->sitd_self = htohc32(sc, page_info.physaddr | EHCI_LINK_SITD); 3675 td->obj_next = last_obj; 3676 td->page_cache = pc + n; 3677 3678 last_obj = td; 3679 3680 usb_pc_cpu_flush(pc + n); 3681 } 3682 } 3683 if (usbd_transfer_setup_sub_malloc( 3684 parm, &pc, sizeof(ehci_qtd_t), 3685 EHCI_QTD_ALIGN, nqtd)) { 3686 parm->err = USB_ERR_NOMEM; 3687 return; 3688 } 3689 if (parm->buf) { 3690 for (n = 0; n != nqtd; n++) { 3691 ehci_qtd_t *qtd; 3692 3693 usbd_get_page(pc + n, 0, &page_info); 3694 3695 qtd = page_info.buffer; 3696 3697 /* init TD */ 3698 qtd->qtd_self = htohc32(sc, page_info.physaddr); 3699 qtd->obj_next = last_obj; 3700 qtd->page_cache = pc + n; 3701 3702 last_obj = qtd; 3703 3704 usb_pc_cpu_flush(pc + n); 3705 } 3706 } 3707 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj; 3708 3709 last_obj = NULL; 3710 3711 if (usbd_transfer_setup_sub_malloc( 3712 parm, &pc, sizeof(ehci_qh_t), 3713 EHCI_QH_ALIGN, nqh)) { 3714 parm->err = USB_ERR_NOMEM; 3715 return; 3716 } 3717 if (parm->buf) { 3718 for (n = 0; n != nqh; n++) { 3719 ehci_qh_t *qh; 3720 3721 usbd_get_page(pc + n, 0, &page_info); 3722 3723 qh = page_info.buffer; 3724 3725 /* init QH */ 3726 qh->qh_self = htohc32(sc, page_info.physaddr | EHCI_LINK_QH); 3727 qh->obj_next = last_obj; 3728 qh->page_cache = pc + n; 3729 3730 last_obj = qh; 3731 3732 usb_pc_cpu_flush(pc + n); 3733 } 3734 } 3735 xfer->qh_start[xfer->flags_int.curr_dma_set] = last_obj; 3736 3737 if (!xfer->flags_int.curr_dma_set) { 3738 xfer->flags_int.curr_dma_set = 1; 3739 goto alloc_dma_set; 3740 } 3741 } 3742 3743 static void 3744 ehci_xfer_unsetup(struct usb_xfer *xfer) 3745 { 3746 return; 3747 } 3748 3749 static void 3750 ehci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 3751 struct usb_endpoint *ep) 3752 { 3753 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus); 3754 3755 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d)\n", 3756 ep, udev->address, 3757 edesc->bEndpointAddress, udev->flags.usb_mode, 3758 sc->sc_addr); 3759 3760 if (udev->device_index != sc->sc_addr) { 3761 3762 if ((udev->speed != USB_SPEED_HIGH) && 3763 ((udev->hs_hub_addr == 0) || 3764 (udev->hs_port_no == 0) || 3765 (udev->parent_hs_hub == NULL) || 3766 (udev->parent_hs_hub->hub == NULL))) { 3767 /* We need a transaction translator */ 3768 goto done; 3769 } 3770 switch (edesc->bmAttributes & UE_XFERTYPE) { 3771 case UE_CONTROL: 3772 ep->methods = &ehci_device_ctrl_methods; 3773 break; 3774 case UE_INTERRUPT: 3775 ep->methods = &ehci_device_intr_methods; 3776 break; 3777 case UE_ISOCHRONOUS: 3778 if (udev->speed == USB_SPEED_HIGH) { 3779 ep->methods = &ehci_device_isoc_hs_methods; 3780 } else if (udev->speed == USB_SPEED_FULL) { 3781 ep->methods = &ehci_device_isoc_fs_methods; 3782 } 3783 break; 3784 case UE_BULK: 3785 ep->methods = &ehci_device_bulk_methods; 3786 break; 3787 default: 3788 /* do nothing */ 3789 break; 3790 } 3791 } 3792 done: 3793 return; 3794 } 3795 3796 static void 3797 ehci_get_dma_delay(struct usb_device *udev, uint32_t *pus) 3798 { 3799 /* 3800 * Wait until the hardware has finished any possible use of 3801 * the transfer descriptor(s) and QH 3802 */ 3803 *pus = (1125); /* microseconds */ 3804 } 3805 3806 static void 3807 ehci_device_resume(struct usb_device *udev) 3808 { 3809 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus); 3810 struct usb_xfer *xfer; 3811 const struct usb_pipe_methods *methods; 3812 3813 DPRINTF("\n"); 3814 3815 USB_BUS_LOCK(udev->bus); 3816 3817 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3818 3819 if (xfer->xroot->udev == udev) { 3820 3821 methods = xfer->endpoint->methods; 3822 3823 if ((methods == &ehci_device_bulk_methods) || 3824 (methods == &ehci_device_ctrl_methods)) { 3825 EHCI_APPEND_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 3826 sc->sc_async_p_last); 3827 } 3828 if (methods == &ehci_device_intr_methods) { 3829 EHCI_APPEND_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 3830 sc->sc_intr_p_last[xfer->qh_pos]); 3831 } 3832 } 3833 } 3834 3835 USB_BUS_UNLOCK(udev->bus); 3836 3837 return; 3838 } 3839 3840 static void 3841 ehci_device_suspend(struct usb_device *udev) 3842 { 3843 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus); 3844 struct usb_xfer *xfer; 3845 const struct usb_pipe_methods *methods; 3846 3847 DPRINTF("\n"); 3848 3849 USB_BUS_LOCK(udev->bus); 3850 3851 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3852 3853 if (xfer->xroot->udev == udev) { 3854 3855 methods = xfer->endpoint->methods; 3856 3857 if ((methods == &ehci_device_bulk_methods) || 3858 (methods == &ehci_device_ctrl_methods)) { 3859 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 3860 sc->sc_async_p_last); 3861 } 3862 if (methods == &ehci_device_intr_methods) { 3863 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 3864 sc->sc_intr_p_last[xfer->qh_pos]); 3865 } 3866 } 3867 } 3868 3869 USB_BUS_UNLOCK(udev->bus); 3870 } 3871 3872 static void 3873 ehci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 3874 { 3875 struct ehci_softc *sc = EHCI_BUS2SC(bus); 3876 3877 switch (state) { 3878 case USB_HW_POWER_SUSPEND: 3879 case USB_HW_POWER_SHUTDOWN: 3880 ehci_suspend(sc); 3881 break; 3882 case USB_HW_POWER_RESUME: 3883 ehci_resume(sc); 3884 break; 3885 default: 3886 break; 3887 } 3888 } 3889 3890 static void 3891 ehci_set_hw_power(struct usb_bus *bus) 3892 { 3893 ehci_softc_t *sc = EHCI_BUS2SC(bus); 3894 uint32_t temp; 3895 uint32_t flags; 3896 3897 DPRINTF("\n"); 3898 3899 USB_BUS_LOCK(bus); 3900 3901 flags = bus->hw_power_state; 3902 3903 temp = EOREAD4(sc, EHCI_USBCMD); 3904 3905 temp &= ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 3906 3907 if (flags & (USB_HW_POWER_CONTROL | 3908 USB_HW_POWER_BULK)) { 3909 DPRINTF("Async is active\n"); 3910 temp |= EHCI_CMD_ASE; 3911 } 3912 if (flags & (USB_HW_POWER_INTERRUPT | 3913 USB_HW_POWER_ISOC)) { 3914 DPRINTF("Periodic is active\n"); 3915 temp |= EHCI_CMD_PSE; 3916 } 3917 EOWRITE4(sc, EHCI_USBCMD, temp); 3918 3919 USB_BUS_UNLOCK(bus); 3920 3921 return; 3922 } 3923 3924 static void 3925 ehci_start_dma_delay_second(struct usb_xfer *xfer) 3926 { 3927 struct ehci_softc *sc = EHCI_BUS2SC(xfer->xroot->bus); 3928 3929 DPRINTF("\n"); 3930 3931 /* trigger doorbell */ 3932 ehci_doorbell_async(sc); 3933 3934 /* give the doorbell 4ms */ 3935 usbd_transfer_timeout_ms(xfer, 3936 (void (*)(void *))&usb_dma_delay_done_cb, 4); 3937 } 3938 3939 /* 3940 * Ring the doorbell twice before freeing any DMA descriptors. Some host 3941 * controllers apparently cache the QH descriptors and need a message 3942 * that the cache needs to be discarded. 3943 */ 3944 static void 3945 ehci_start_dma_delay(struct usb_xfer *xfer) 3946 { 3947 struct ehci_softc *sc = EHCI_BUS2SC(xfer->xroot->bus); 3948 3949 DPRINTF("\n"); 3950 3951 /* trigger doorbell */ 3952 ehci_doorbell_async(sc); 3953 3954 /* give the doorbell 4ms */ 3955 usbd_transfer_timeout_ms(xfer, 3956 (void (*)(void *))&ehci_start_dma_delay_second, 4); 3957 } 3958 3959 static const struct usb_bus_methods ehci_bus_methods = 3960 { 3961 .endpoint_init = ehci_ep_init, 3962 .xfer_setup = ehci_xfer_setup, 3963 .xfer_unsetup = ehci_xfer_unsetup, 3964 .get_dma_delay = ehci_get_dma_delay, 3965 .device_resume = ehci_device_resume, 3966 .device_suspend = ehci_device_suspend, 3967 .set_hw_power = ehci_set_hw_power, 3968 .set_hw_power_sleep = ehci_set_hw_power_sleep, 3969 .roothub_exec = ehci_roothub_exec, 3970 .xfer_poll = ehci_do_poll, 3971 .start_dma_delay = ehci_start_dma_delay, 3972 }; 3973