1 /* $FreeBSD$ */ 2 /*- 3 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 4 * 5 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * Thanks to Mentor Graphics for providing a reference driver for this USB chip 31 * at their homepage. 32 */ 33 34 /* 35 * This file contains the driver for the Mentor Graphics Inventra USB 36 * 2.0 High Speed Dual-Role controller. 37 * 38 */ 39 40 #ifdef USB_GLOBAL_INCLUDE_FILE 41 #include USB_GLOBAL_INCLUDE_FILE 42 #else 43 #include <sys/stdint.h> 44 #include <sys/stddef.h> 45 #include <sys/param.h> 46 #include <sys/queue.h> 47 #include <sys/types.h> 48 #include <sys/systm.h> 49 #include <sys/kernel.h> 50 #include <sys/bus.h> 51 #include <sys/module.h> 52 #include <sys/lock.h> 53 #include <sys/mutex.h> 54 #include <sys/condvar.h> 55 #include <sys/sysctl.h> 56 #include <sys/sx.h> 57 #include <sys/unistd.h> 58 #include <sys/callout.h> 59 #include <sys/malloc.h> 60 #include <sys/priv.h> 61 62 #include <dev/usb/usb.h> 63 #include <dev/usb/usbdi.h> 64 65 #define USB_DEBUG_VAR musbotgdebug 66 67 #include <dev/usb/usb_core.h> 68 #include <dev/usb/usb_debug.h> 69 #include <dev/usb/usb_busdma.h> 70 #include <dev/usb/usb_process.h> 71 #include <dev/usb/usb_transfer.h> 72 #include <dev/usb/usb_device.h> 73 #include <dev/usb/usb_hub.h> 74 #include <dev/usb/usb_util.h> 75 76 #include <dev/usb/usb_controller.h> 77 #include <dev/usb/usb_bus.h> 78 #endif /* USB_GLOBAL_INCLUDE_FILE */ 79 80 #include <dev/usb/controller/musb_otg.h> 81 82 #define MUSBOTG_INTR_ENDPT 1 83 84 #define MUSBOTG_BUS2SC(bus) \ 85 ((struct musbotg_softc *)(((uint8_t *)(bus)) - \ 86 USB_P2U(&(((struct musbotg_softc *)0)->sc_bus)))) 87 88 #define MUSBOTG_PC2SC(pc) \ 89 MUSBOTG_BUS2SC(USB_DMATAG_TO_XROOT((pc)->tag_parent)->bus) 90 91 #ifdef USB_DEBUG 92 static int musbotgdebug = 0; 93 94 static SYSCTL_NODE(_hw_usb, OID_AUTO, musbotg, CTLFLAG_RW | CTLFLAG_MPSAFE, 0, 95 "USB musbotg"); 96 SYSCTL_INT(_hw_usb_musbotg, OID_AUTO, debug, CTLFLAG_RWTUN, 97 &musbotgdebug, 0, "Debug level"); 98 #endif 99 100 #define MAX_NAK_TO 16 101 102 /* prototypes */ 103 104 static const struct usb_bus_methods musbotg_bus_methods; 105 static const struct usb_pipe_methods musbotg_device_bulk_methods; 106 static const struct usb_pipe_methods musbotg_device_ctrl_methods; 107 static const struct usb_pipe_methods musbotg_device_intr_methods; 108 static const struct usb_pipe_methods musbotg_device_isoc_methods; 109 110 /* Control transfers: Device mode */ 111 static musbotg_cmd_t musbotg_dev_ctrl_setup_rx; 112 static musbotg_cmd_t musbotg_dev_ctrl_data_rx; 113 static musbotg_cmd_t musbotg_dev_ctrl_data_tx; 114 static musbotg_cmd_t musbotg_dev_ctrl_status; 115 116 /* Control transfers: Host mode */ 117 static musbotg_cmd_t musbotg_host_ctrl_setup_tx; 118 static musbotg_cmd_t musbotg_host_ctrl_data_rx; 119 static musbotg_cmd_t musbotg_host_ctrl_data_tx; 120 static musbotg_cmd_t musbotg_host_ctrl_status_rx; 121 static musbotg_cmd_t musbotg_host_ctrl_status_tx; 122 123 /* Bulk, Interrupt, Isochronous: Device mode */ 124 static musbotg_cmd_t musbotg_dev_data_rx; 125 static musbotg_cmd_t musbotg_dev_data_tx; 126 127 /* Bulk, Interrupt, Isochronous: Host mode */ 128 static musbotg_cmd_t musbotg_host_data_rx; 129 static musbotg_cmd_t musbotg_host_data_tx; 130 131 static void musbotg_device_done(struct usb_xfer *, usb_error_t); 132 static void musbotg_do_poll(struct usb_bus *); 133 static void musbotg_standard_done(struct usb_xfer *); 134 static void musbotg_interrupt_poll(struct musbotg_softc *); 135 static void musbotg_root_intr(struct musbotg_softc *); 136 static int musbotg_channel_alloc(struct musbotg_softc *, struct musbotg_td *td, uint8_t); 137 static void musbotg_channel_free(struct musbotg_softc *, struct musbotg_td *td); 138 static void musbotg_ep_int_set(struct musbotg_softc *sc, int channel, int on); 139 140 /* 141 * Here is a configuration that the chip supports. 142 */ 143 static const struct usb_hw_ep_profile musbotg_ep_profile[1] = { 144 145 [0] = { 146 .max_in_frame_size = 64,/* fixed */ 147 .max_out_frame_size = 64, /* fixed */ 148 .is_simplex = 1, 149 .support_control = 1, 150 } 151 }; 152 153 static const struct musb_otg_ep_cfg musbotg_ep_default[] = { 154 { 155 .ep_end = 1, 156 .ep_fifosz_shift = 12, 157 .ep_fifosz_reg = MUSB2_VAL_FIFOSZ_4096 | MUSB2_MASK_FIFODB, 158 }, 159 { 160 .ep_end = 7, 161 .ep_fifosz_shift = 10, 162 .ep_fifosz_reg = MUSB2_VAL_FIFOSZ_512 | MUSB2_MASK_FIFODB, 163 }, 164 { 165 .ep_end = 15, 166 .ep_fifosz_shift = 7, 167 .ep_fifosz_reg = MUSB2_VAL_FIFOSZ_128, 168 }, 169 { 170 .ep_end = -1, 171 }, 172 }; 173 174 static int 175 musbotg_channel_alloc(struct musbotg_softc *sc, struct musbotg_td *td, uint8_t is_tx) 176 { 177 int ch; 178 int ep; 179 180 ep = td->ep_no; 181 182 /* In device mode each EP got its own channel */ 183 if (sc->sc_mode == MUSB2_DEVICE_MODE) { 184 musbotg_ep_int_set(sc, ep, 1); 185 return (ep); 186 } 187 188 /* 189 * All control transactions go through EP0 190 */ 191 if (ep == 0) { 192 if (sc->sc_channel_mask & (1 << 0)) 193 return (-1); 194 sc->sc_channel_mask |= (1 << 0); 195 musbotg_ep_int_set(sc, ep, 1); 196 return (0); 197 } 198 199 for (ch = sc->sc_ep_max; ch != 0; ch--) { 200 if (sc->sc_channel_mask & (1 << ch)) 201 continue; 202 203 /* check FIFO size requirement */ 204 if (is_tx) { 205 if (td->max_frame_size > 206 sc->sc_hw_ep_profile[ch].max_in_frame_size) 207 continue; 208 } else { 209 if (td->max_frame_size > 210 sc->sc_hw_ep_profile[ch].max_out_frame_size) 211 continue; 212 } 213 sc->sc_channel_mask |= (1 << ch); 214 musbotg_ep_int_set(sc, ch, 1); 215 return (ch); 216 } 217 218 DPRINTFN(-1, "No available channels. Mask: %04x\n", sc->sc_channel_mask); 219 220 return (-1); 221 } 222 223 static void 224 musbotg_channel_free(struct musbotg_softc *sc, struct musbotg_td *td) 225 { 226 227 DPRINTFN(1, "ep_no=%d\n", td->channel); 228 229 if (sc->sc_mode == MUSB2_DEVICE_MODE) 230 return; 231 232 if (td == NULL) 233 return; 234 if (td->channel == -1) 235 return; 236 237 musbotg_ep_int_set(sc, td->channel, 0); 238 sc->sc_channel_mask &= ~(1 << td->channel); 239 240 td->channel = -1; 241 } 242 243 static void 244 musbotg_get_hw_ep_profile(struct usb_device *udev, 245 const struct usb_hw_ep_profile **ppf, uint8_t ep_addr) 246 { 247 struct musbotg_softc *sc; 248 249 sc = MUSBOTG_BUS2SC(udev->bus); 250 251 if (ep_addr == 0) { 252 /* control endpoint */ 253 *ppf = musbotg_ep_profile; 254 } else if (ep_addr <= sc->sc_ep_max) { 255 /* other endpoints */ 256 *ppf = sc->sc_hw_ep_profile + ep_addr; 257 } else { 258 *ppf = NULL; 259 } 260 } 261 262 static void 263 musbotg_clocks_on(struct musbotg_softc *sc) 264 { 265 if (sc->sc_flags.clocks_off && 266 sc->sc_flags.port_powered) { 267 268 DPRINTFN(4, "\n"); 269 270 if (sc->sc_clocks_on) { 271 (sc->sc_clocks_on) (sc->sc_clocks_arg); 272 } 273 sc->sc_flags.clocks_off = 0; 274 275 /* XXX enable Transceiver */ 276 } 277 } 278 279 static void 280 musbotg_clocks_off(struct musbotg_softc *sc) 281 { 282 if (!sc->sc_flags.clocks_off) { 283 284 DPRINTFN(4, "\n"); 285 286 /* XXX disable Transceiver */ 287 288 if (sc->sc_clocks_off) { 289 (sc->sc_clocks_off) (sc->sc_clocks_arg); 290 } 291 sc->sc_flags.clocks_off = 1; 292 } 293 } 294 295 static void 296 musbotg_pull_common(struct musbotg_softc *sc, uint8_t on) 297 { 298 uint8_t temp; 299 300 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); 301 if (on) 302 temp |= MUSB2_MASK_SOFTC; 303 else 304 temp &= ~MUSB2_MASK_SOFTC; 305 306 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp); 307 } 308 309 static void 310 musbotg_pull_up(struct musbotg_softc *sc) 311 { 312 /* pullup D+, if possible */ 313 314 if (!sc->sc_flags.d_pulled_up && 315 sc->sc_flags.port_powered) { 316 sc->sc_flags.d_pulled_up = 1; 317 musbotg_pull_common(sc, 1); 318 } 319 } 320 321 static void 322 musbotg_pull_down(struct musbotg_softc *sc) 323 { 324 /* pulldown D+, if possible */ 325 326 if (sc->sc_flags.d_pulled_up) { 327 sc->sc_flags.d_pulled_up = 0; 328 musbotg_pull_common(sc, 0); 329 } 330 } 331 332 static void 333 musbotg_suspend_host(struct musbotg_softc *sc) 334 { 335 uint8_t temp; 336 337 if (sc->sc_flags.status_suspend) { 338 return; 339 } 340 341 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); 342 temp |= MUSB2_MASK_SUSPMODE; 343 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp); 344 sc->sc_flags.status_suspend = 1; 345 } 346 347 static void 348 musbotg_wakeup_host(struct musbotg_softc *sc) 349 { 350 uint8_t temp; 351 352 if (!(sc->sc_flags.status_suspend)) { 353 return; 354 } 355 356 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); 357 temp &= ~MUSB2_MASK_SUSPMODE; 358 temp |= MUSB2_MASK_RESUME; 359 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp); 360 361 /* wait 20 milliseconds */ 362 /* Wait for reset to complete. */ 363 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50); 364 365 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); 366 temp &= ~MUSB2_MASK_RESUME; 367 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp); 368 369 sc->sc_flags.status_suspend = 0; 370 } 371 372 static void 373 musbotg_wakeup_peer(struct musbotg_softc *sc) 374 { 375 uint8_t temp; 376 377 if (!(sc->sc_flags.status_suspend)) { 378 return; 379 } 380 381 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); 382 temp |= MUSB2_MASK_RESUME; 383 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp); 384 385 /* wait 8 milliseconds */ 386 /* Wait for reset to complete. */ 387 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125); 388 389 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); 390 temp &= ~MUSB2_MASK_RESUME; 391 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp); 392 } 393 394 static void 395 musbotg_set_address(struct musbotg_softc *sc, uint8_t addr) 396 { 397 DPRINTFN(4, "addr=%d\n", addr); 398 addr &= 0x7F; 399 MUSB2_WRITE_1(sc, MUSB2_REG_FADDR, addr); 400 } 401 402 static uint8_t 403 musbotg_dev_ctrl_setup_rx(struct musbotg_td *td) 404 { 405 struct musbotg_softc *sc; 406 struct usb_device_request req; 407 uint16_t count; 408 uint8_t csr; 409 410 /* get pointer to softc */ 411 sc = MUSBOTG_PC2SC(td->pc); 412 413 if (td->channel == -1) 414 td->channel = musbotg_channel_alloc(sc, td, 0); 415 416 /* EP0 is busy, wait */ 417 if (td->channel == -1) 418 return (1); 419 420 DPRINTFN(1, "ep_no=%d\n", td->channel); 421 422 /* select endpoint 0 */ 423 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 424 425 /* read out FIFO status */ 426 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 427 428 DPRINTFN(4, "csr=0x%02x\n", csr); 429 430 /* 431 * NOTE: If DATAEND is set we should not call the 432 * callback, hence the status stage is not complete. 433 */ 434 if (csr & MUSB2_MASK_CSR0L_DATAEND) { 435 /* do not stall at this point */ 436 td->did_stall = 1; 437 /* wait for interrupt */ 438 DPRINTFN(1, "CSR0 DATAEND\n"); 439 goto not_complete; 440 } 441 442 if (csr & MUSB2_MASK_CSR0L_SENTSTALL) { 443 /* clear SENTSTALL */ 444 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 445 /* get latest status */ 446 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 447 /* update EP0 state */ 448 sc->sc_ep0_busy = 0; 449 } 450 if (csr & MUSB2_MASK_CSR0L_SETUPEND) { 451 /* clear SETUPEND */ 452 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 453 MUSB2_MASK_CSR0L_SETUPEND_CLR); 454 /* get latest status */ 455 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 456 /* update EP0 state */ 457 sc->sc_ep0_busy = 0; 458 } 459 if (sc->sc_ep0_busy) { 460 DPRINTFN(1, "EP0 BUSY\n"); 461 goto not_complete; 462 } 463 if (!(csr & MUSB2_MASK_CSR0L_RXPKTRDY)) { 464 goto not_complete; 465 } 466 /* get the packet byte count */ 467 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT); 468 469 /* verify data length */ 470 if (count != td->remainder) { 471 DPRINTFN(1, "Invalid SETUP packet " 472 "length, %d bytes\n", count); 473 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 474 MUSB2_MASK_CSR0L_RXPKTRDY_CLR); 475 /* don't clear stall */ 476 td->did_stall = 1; 477 goto not_complete; 478 } 479 if (count != sizeof(req)) { 480 DPRINTFN(1, "Unsupported SETUP packet " 481 "length, %d bytes\n", count); 482 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 483 MUSB2_MASK_CSR0L_RXPKTRDY_CLR); 484 /* don't clear stall */ 485 td->did_stall = 1; 486 goto not_complete; 487 } 488 /* clear did stall flag */ 489 td->did_stall = 0; 490 491 /* receive data */ 492 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 493 MUSB2_REG_EPFIFO(0), (void *)&req, sizeof(req)); 494 495 /* copy data into real buffer */ 496 usbd_copy_in(td->pc, 0, &req, sizeof(req)); 497 498 td->offset = sizeof(req); 499 td->remainder = 0; 500 501 /* set pending command */ 502 sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_RXPKTRDY_CLR; 503 504 /* we need set stall or dataend after this */ 505 sc->sc_ep0_busy = 1; 506 507 /* sneak peek the set address */ 508 if ((req.bmRequestType == UT_WRITE_DEVICE) && 509 (req.bRequest == UR_SET_ADDRESS)) { 510 sc->sc_dv_addr = req.wValue[0] & 0x7F; 511 } else { 512 sc->sc_dv_addr = 0xFF; 513 } 514 515 musbotg_channel_free(sc, td); 516 return (0); /* complete */ 517 518 not_complete: 519 /* abort any ongoing transfer */ 520 if (!td->did_stall) { 521 DPRINTFN(4, "stalling\n"); 522 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 523 MUSB2_MASK_CSR0L_SENDSTALL); 524 td->did_stall = 1; 525 } 526 return (1); /* not complete */ 527 } 528 529 static uint8_t 530 musbotg_host_ctrl_setup_tx(struct musbotg_td *td) 531 { 532 struct musbotg_softc *sc; 533 struct usb_device_request req; 534 uint8_t csr, csrh; 535 536 /* get pointer to softc */ 537 sc = MUSBOTG_PC2SC(td->pc); 538 539 if (td->channel == -1) 540 td->channel = musbotg_channel_alloc(sc, td, 1); 541 542 /* EP0 is busy, wait */ 543 if (td->channel == -1) 544 return (1); 545 546 DPRINTFN(1, "ep_no=%d\n", td->channel); 547 548 /* select endpoint 0 */ 549 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 550 551 /* read out FIFO status */ 552 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 553 DPRINTFN(4, "csr=0x%02x\n", csr); 554 555 /* Not ready yet yet */ 556 if (csr & MUSB2_MASK_CSR0L_TXPKTRDY) 557 return (1); 558 559 /* Failed */ 560 if (csr & (MUSB2_MASK_CSR0L_RXSTALL | 561 MUSB2_MASK_CSR0L_ERROR)) 562 { 563 /* Clear status bit */ 564 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 565 DPRINTFN(1, "error bit set, csr=0x%02x\n", csr); 566 td->error = 1; 567 } 568 569 if (csr & MUSB2_MASK_CSR0L_NAKTIMO) { 570 DPRINTFN(1, "NAK timeout\n"); 571 572 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) { 573 csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH); 574 csrh |= MUSB2_MASK_CSR0H_FFLUSH; 575 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh); 576 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 577 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) { 578 csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH); 579 csrh |= MUSB2_MASK_CSR0H_FFLUSH; 580 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh); 581 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 582 } 583 } 584 585 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO; 586 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr); 587 588 td->error = 1; 589 } 590 591 if (td->error) { 592 musbotg_channel_free(sc, td); 593 return (0); 594 } 595 596 /* Fifo is not empty and there is no NAK timeout */ 597 if (csr & MUSB2_MASK_CSR0L_TXPKTRDY) 598 return (1); 599 600 /* check if we are complete */ 601 if (td->remainder == 0) { 602 /* we are complete */ 603 musbotg_channel_free(sc, td); 604 return (0); 605 } 606 607 /* copy data into real buffer */ 608 usbd_copy_out(td->pc, 0, &req, sizeof(req)); 609 610 /* send data */ 611 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 612 MUSB2_REG_EPFIFO(0), (void *)&req, sizeof(req)); 613 614 /* update offset and remainder */ 615 td->offset += sizeof(req); 616 td->remainder -= sizeof(req); 617 618 619 MUSB2_WRITE_1(sc, MUSB2_REG_TXNAKLIMIT, MAX_NAK_TO); 620 MUSB2_WRITE_1(sc, MUSB2_REG_TXFADDR(0), td->dev_addr); 621 MUSB2_WRITE_1(sc, MUSB2_REG_TXHADDR(0), td->haddr); 622 MUSB2_WRITE_1(sc, MUSB2_REG_TXHUBPORT(0), td->hport); 623 MUSB2_WRITE_1(sc, MUSB2_REG_TXTI, td->transfer_type); 624 625 /* write command */ 626 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 627 MUSB2_MASK_CSR0L_TXPKTRDY | 628 MUSB2_MASK_CSR0L_SETUPPKT); 629 630 /* Just to be consistent, not used above */ 631 td->transaction_started = 1; 632 633 return (1); /* in progress */ 634 } 635 636 /* Control endpoint only data handling functions (RX/TX/SYNC) */ 637 638 static uint8_t 639 musbotg_dev_ctrl_data_rx(struct musbotg_td *td) 640 { 641 struct usb_page_search buf_res; 642 struct musbotg_softc *sc; 643 uint16_t count; 644 uint8_t csr; 645 uint8_t got_short; 646 647 /* get pointer to softc */ 648 sc = MUSBOTG_PC2SC(td->pc); 649 650 /* select endpoint 0 */ 651 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 652 653 /* check if a command is pending */ 654 if (sc->sc_ep0_cmd) { 655 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, sc->sc_ep0_cmd); 656 sc->sc_ep0_cmd = 0; 657 } 658 /* read out FIFO status */ 659 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 660 661 DPRINTFN(4, "csr=0x%02x\n", csr); 662 663 got_short = 0; 664 665 if (csr & (MUSB2_MASK_CSR0L_SETUPEND | 666 MUSB2_MASK_CSR0L_SENTSTALL)) { 667 if (td->remainder == 0) { 668 /* 669 * We are actually complete and have 670 * received the next SETUP 671 */ 672 DPRINTFN(4, "faking complete\n"); 673 return (0); /* complete */ 674 } 675 /* 676 * USB Host Aborted the transfer. 677 */ 678 td->error = 1; 679 return (0); /* complete */ 680 } 681 if (!(csr & MUSB2_MASK_CSR0L_RXPKTRDY)) { 682 return (1); /* not complete */ 683 } 684 /* get the packet byte count */ 685 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT); 686 687 /* verify the packet byte count */ 688 if (count != td->max_frame_size) { 689 if (count < td->max_frame_size) { 690 /* we have a short packet */ 691 td->short_pkt = 1; 692 got_short = 1; 693 } else { 694 /* invalid USB packet */ 695 td->error = 1; 696 return (0); /* we are complete */ 697 } 698 } 699 /* verify the packet byte count */ 700 if (count > td->remainder) { 701 /* invalid USB packet */ 702 td->error = 1; 703 return (0); /* we are complete */ 704 } 705 while (count > 0) { 706 uint32_t temp; 707 708 usbd_get_page(td->pc, td->offset, &buf_res); 709 710 /* get correct length */ 711 if (buf_res.length > count) { 712 buf_res.length = count; 713 } 714 /* check for unaligned memory address */ 715 if (USB_P2U(buf_res.buffer) & 3) { 716 717 temp = count & ~3; 718 719 if (temp) { 720 /* receive data 4 bytes at a time */ 721 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 722 MUSB2_REG_EPFIFO(0), sc->sc_bounce_buf, 723 temp / 4); 724 } 725 temp = count & 3; 726 if (temp) { 727 /* receive data 1 byte at a time */ 728 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 729 MUSB2_REG_EPFIFO(0), 730 (void *)(&sc->sc_bounce_buf[count / 4]), temp); 731 } 732 usbd_copy_in(td->pc, td->offset, 733 sc->sc_bounce_buf, count); 734 735 /* update offset and remainder */ 736 td->offset += count; 737 td->remainder -= count; 738 break; 739 } 740 /* check if we can optimise */ 741 if (buf_res.length >= 4) { 742 743 /* receive data 4 bytes at a time */ 744 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 745 MUSB2_REG_EPFIFO(0), buf_res.buffer, 746 buf_res.length / 4); 747 748 temp = buf_res.length & ~3; 749 750 /* update counters */ 751 count -= temp; 752 td->offset += temp; 753 td->remainder -= temp; 754 continue; 755 } 756 /* receive data */ 757 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 758 MUSB2_REG_EPFIFO(0), buf_res.buffer, buf_res.length); 759 760 /* update counters */ 761 count -= buf_res.length; 762 td->offset += buf_res.length; 763 td->remainder -= buf_res.length; 764 } 765 766 /* check if we are complete */ 767 if ((td->remainder == 0) || got_short) { 768 if (td->short_pkt) { 769 /* we are complete */ 770 sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_RXPKTRDY_CLR; 771 return (0); 772 } 773 /* else need to receive a zero length packet */ 774 } 775 /* write command - need more data */ 776 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 777 MUSB2_MASK_CSR0L_RXPKTRDY_CLR); 778 return (1); /* not complete */ 779 } 780 781 static uint8_t 782 musbotg_dev_ctrl_data_tx(struct musbotg_td *td) 783 { 784 struct usb_page_search buf_res; 785 struct musbotg_softc *sc; 786 uint16_t count; 787 uint8_t csr; 788 789 /* get pointer to softc */ 790 sc = MUSBOTG_PC2SC(td->pc); 791 792 /* select endpoint 0 */ 793 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 794 795 /* check if a command is pending */ 796 if (sc->sc_ep0_cmd) { 797 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, sc->sc_ep0_cmd); 798 sc->sc_ep0_cmd = 0; 799 } 800 /* read out FIFO status */ 801 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 802 803 DPRINTFN(4, "csr=0x%02x\n", csr); 804 805 if (csr & (MUSB2_MASK_CSR0L_SETUPEND | 806 MUSB2_MASK_CSR0L_SENTSTALL)) { 807 /* 808 * The current transfer was aborted 809 * by the USB Host 810 */ 811 td->error = 1; 812 return (0); /* complete */ 813 } 814 if (csr & MUSB2_MASK_CSR0L_TXPKTRDY) { 815 return (1); /* not complete */ 816 } 817 count = td->max_frame_size; 818 if (td->remainder < count) { 819 /* we have a short packet */ 820 td->short_pkt = 1; 821 count = td->remainder; 822 } 823 while (count > 0) { 824 uint32_t temp; 825 826 usbd_get_page(td->pc, td->offset, &buf_res); 827 828 /* get correct length */ 829 if (buf_res.length > count) { 830 buf_res.length = count; 831 } 832 /* check for unaligned memory address */ 833 if (USB_P2U(buf_res.buffer) & 3) { 834 835 usbd_copy_out(td->pc, td->offset, 836 sc->sc_bounce_buf, count); 837 838 temp = count & ~3; 839 840 if (temp) { 841 /* transmit data 4 bytes at a time */ 842 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 843 MUSB2_REG_EPFIFO(0), sc->sc_bounce_buf, 844 temp / 4); 845 } 846 temp = count & 3; 847 if (temp) { 848 /* receive data 1 byte at a time */ 849 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 850 MUSB2_REG_EPFIFO(0), 851 ((void *)&sc->sc_bounce_buf[count / 4]), temp); 852 } 853 /* update offset and remainder */ 854 td->offset += count; 855 td->remainder -= count; 856 break; 857 } 858 /* check if we can optimise */ 859 if (buf_res.length >= 4) { 860 861 /* transmit data 4 bytes at a time */ 862 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 863 MUSB2_REG_EPFIFO(0), buf_res.buffer, 864 buf_res.length / 4); 865 866 temp = buf_res.length & ~3; 867 868 /* update counters */ 869 count -= temp; 870 td->offset += temp; 871 td->remainder -= temp; 872 continue; 873 } 874 /* transmit data */ 875 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 876 MUSB2_REG_EPFIFO(0), buf_res.buffer, buf_res.length); 877 878 /* update counters */ 879 count -= buf_res.length; 880 td->offset += buf_res.length; 881 td->remainder -= buf_res.length; 882 } 883 884 /* check remainder */ 885 if (td->remainder == 0) { 886 if (td->short_pkt) { 887 sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_TXPKTRDY; 888 return (0); /* complete */ 889 } 890 /* else we need to transmit a short packet */ 891 } 892 /* write command */ 893 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 894 MUSB2_MASK_CSR0L_TXPKTRDY); 895 896 return (1); /* not complete */ 897 } 898 899 static uint8_t 900 musbotg_host_ctrl_data_rx(struct musbotg_td *td) 901 { 902 struct usb_page_search buf_res; 903 struct musbotg_softc *sc; 904 uint16_t count; 905 uint8_t csr; 906 uint8_t got_short; 907 908 /* get pointer to softc */ 909 sc = MUSBOTG_PC2SC(td->pc); 910 911 if (td->channel == -1) 912 td->channel = musbotg_channel_alloc(sc, td, 0); 913 914 /* EP0 is busy, wait */ 915 if (td->channel == -1) 916 return (1); 917 918 DPRINTFN(1, "ep_no=%d\n", td->channel); 919 920 /* select endpoint 0 */ 921 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 922 923 /* read out FIFO status */ 924 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 925 926 DPRINTFN(4, "csr=0x%02x\n", csr); 927 928 got_short = 0; 929 if (!td->transaction_started) { 930 td->transaction_started = 1; 931 932 MUSB2_WRITE_1(sc, MUSB2_REG_RXNAKLIMIT, MAX_NAK_TO); 933 934 MUSB2_WRITE_1(sc, MUSB2_REG_RXFADDR(0), 935 td->dev_addr); 936 MUSB2_WRITE_1(sc, MUSB2_REG_RXHADDR(0), td->haddr); 937 MUSB2_WRITE_1(sc, MUSB2_REG_RXHUBPORT(0), td->hport); 938 MUSB2_WRITE_1(sc, MUSB2_REG_RXTI, td->transfer_type); 939 940 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 941 MUSB2_MASK_CSR0L_REQPKT); 942 943 return (1); 944 } 945 946 if (csr & MUSB2_MASK_CSR0L_NAKTIMO) { 947 csr &= ~MUSB2_MASK_CSR0L_REQPKT; 948 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr); 949 950 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO; 951 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr); 952 953 td->error = 1; 954 } 955 956 /* Failed */ 957 if (csr & (MUSB2_MASK_CSR0L_RXSTALL | 958 MUSB2_MASK_CSR0L_ERROR)) 959 { 960 /* Clear status bit */ 961 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 962 DPRINTFN(1, "error bit set, csr=0x%02x\n", csr); 963 td->error = 1; 964 } 965 966 if (td->error) { 967 musbotg_channel_free(sc, td); 968 return (0); /* we are complete */ 969 } 970 971 if (!(csr & MUSB2_MASK_CSR0L_RXPKTRDY)) 972 return (1); /* not yet */ 973 974 /* get the packet byte count */ 975 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT); 976 977 /* verify the packet byte count */ 978 if (count != td->max_frame_size) { 979 if (count < td->max_frame_size) { 980 /* we have a short packet */ 981 td->short_pkt = 1; 982 got_short = 1; 983 } else { 984 /* invalid USB packet */ 985 td->error = 1; 986 musbotg_channel_free(sc, td); 987 return (0); /* we are complete */ 988 } 989 } 990 /* verify the packet byte count */ 991 if (count > td->remainder) { 992 /* invalid USB packet */ 993 td->error = 1; 994 musbotg_channel_free(sc, td); 995 return (0); /* we are complete */ 996 } 997 while (count > 0) { 998 uint32_t temp; 999 1000 usbd_get_page(td->pc, td->offset, &buf_res); 1001 1002 /* get correct length */ 1003 if (buf_res.length > count) { 1004 buf_res.length = count; 1005 } 1006 /* check for unaligned memory address */ 1007 if (USB_P2U(buf_res.buffer) & 3) { 1008 1009 temp = count & ~3; 1010 1011 if (temp) { 1012 /* receive data 4 bytes at a time */ 1013 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 1014 MUSB2_REG_EPFIFO(0), sc->sc_bounce_buf, 1015 temp / 4); 1016 } 1017 temp = count & 3; 1018 if (temp) { 1019 /* receive data 1 byte at a time */ 1020 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 1021 MUSB2_REG_EPFIFO(0), 1022 (void *)(&sc->sc_bounce_buf[count / 4]), temp); 1023 } 1024 usbd_copy_in(td->pc, td->offset, 1025 sc->sc_bounce_buf, count); 1026 1027 /* update offset and remainder */ 1028 td->offset += count; 1029 td->remainder -= count; 1030 break; 1031 } 1032 /* check if we can optimise */ 1033 if (buf_res.length >= 4) { 1034 1035 /* receive data 4 bytes at a time */ 1036 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 1037 MUSB2_REG_EPFIFO(0), buf_res.buffer, 1038 buf_res.length / 4); 1039 1040 temp = buf_res.length & ~3; 1041 1042 /* update counters */ 1043 count -= temp; 1044 td->offset += temp; 1045 td->remainder -= temp; 1046 continue; 1047 } 1048 /* receive data */ 1049 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 1050 MUSB2_REG_EPFIFO(0), buf_res.buffer, buf_res.length); 1051 1052 /* update counters */ 1053 count -= buf_res.length; 1054 td->offset += buf_res.length; 1055 td->remainder -= buf_res.length; 1056 } 1057 1058 csr &= ~MUSB2_MASK_CSR0L_RXPKTRDY; 1059 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr); 1060 1061 /* check if we are complete */ 1062 if ((td->remainder == 0) || got_short) { 1063 if (td->short_pkt) { 1064 /* we are complete */ 1065 1066 musbotg_channel_free(sc, td); 1067 return (0); 1068 } 1069 /* else need to receive a zero length packet */ 1070 } 1071 1072 td->transaction_started = 1; 1073 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 1074 MUSB2_MASK_CSR0L_REQPKT); 1075 1076 return (1); /* not complete */ 1077 } 1078 1079 static uint8_t 1080 musbotg_host_ctrl_data_tx(struct musbotg_td *td) 1081 { 1082 struct usb_page_search buf_res; 1083 struct musbotg_softc *sc; 1084 uint16_t count; 1085 uint8_t csr, csrh; 1086 1087 /* get pointer to softc */ 1088 sc = MUSBOTG_PC2SC(td->pc); 1089 1090 if (td->channel == -1) 1091 td->channel = musbotg_channel_alloc(sc, td, 1); 1092 1093 /* No free EPs */ 1094 if (td->channel == -1) 1095 return (1); 1096 1097 DPRINTFN(1, "ep_no=%d\n", td->channel); 1098 1099 /* select endpoint */ 1100 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 1101 1102 /* read out FIFO status */ 1103 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1104 DPRINTFN(4, "csr=0x%02x\n", csr); 1105 1106 if (csr & (MUSB2_MASK_CSR0L_RXSTALL | 1107 MUSB2_MASK_CSR0L_ERROR)) { 1108 /* clear status bits */ 1109 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 1110 td->error = 1; 1111 } 1112 1113 if (csr & MUSB2_MASK_CSR0L_NAKTIMO ) { 1114 1115 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) { 1116 csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH); 1117 csrh |= MUSB2_MASK_CSR0H_FFLUSH; 1118 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh); 1119 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1120 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) { 1121 csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH); 1122 csrh |= MUSB2_MASK_CSR0H_FFLUSH; 1123 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh); 1124 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1125 } 1126 } 1127 1128 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO; 1129 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr); 1130 1131 td->error = 1; 1132 } 1133 1134 1135 if (td->error) { 1136 musbotg_channel_free(sc, td); 1137 return (0); /* complete */ 1138 } 1139 1140 /* 1141 * Wait while FIFO is empty. 1142 * Do not flush it because it will cause transactions 1143 * with size more then packet size. It might upset 1144 * some devices 1145 */ 1146 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) 1147 return (1); 1148 1149 /* Packet still being processed */ 1150 if (csr & MUSB2_MASK_CSR0L_TXPKTRDY) 1151 return (1); 1152 1153 if (td->transaction_started) { 1154 /* check remainder */ 1155 if (td->remainder == 0) { 1156 if (td->short_pkt) { 1157 musbotg_channel_free(sc, td); 1158 return (0); /* complete */ 1159 } 1160 /* else we need to transmit a short packet */ 1161 } 1162 1163 /* We're not complete - more transactions required */ 1164 td->transaction_started = 0; 1165 } 1166 1167 /* check for short packet */ 1168 count = td->max_frame_size; 1169 if (td->remainder < count) { 1170 /* we have a short packet */ 1171 td->short_pkt = 1; 1172 count = td->remainder; 1173 } 1174 1175 while (count > 0) { 1176 uint32_t temp; 1177 1178 usbd_get_page(td->pc, td->offset, &buf_res); 1179 1180 /* get correct length */ 1181 if (buf_res.length > count) { 1182 buf_res.length = count; 1183 } 1184 /* check for unaligned memory address */ 1185 if (USB_P2U(buf_res.buffer) & 3) { 1186 1187 usbd_copy_out(td->pc, td->offset, 1188 sc->sc_bounce_buf, count); 1189 1190 temp = count & ~3; 1191 1192 if (temp) { 1193 /* transmit data 4 bytes at a time */ 1194 bus_space_write_multi_4(sc->sc_io_tag, 1195 sc->sc_io_hdl, MUSB2_REG_EPFIFO(0), 1196 sc->sc_bounce_buf, temp / 4); 1197 } 1198 temp = count & 3; 1199 if (temp) { 1200 /* receive data 1 byte at a time */ 1201 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 1202 MUSB2_REG_EPFIFO(0), 1203 ((void *)&sc->sc_bounce_buf[count / 4]), temp); 1204 } 1205 /* update offset and remainder */ 1206 td->offset += count; 1207 td->remainder -= count; 1208 break; 1209 } 1210 /* check if we can optimise */ 1211 if (buf_res.length >= 4) { 1212 1213 /* transmit data 4 bytes at a time */ 1214 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 1215 MUSB2_REG_EPFIFO(0), buf_res.buffer, 1216 buf_res.length / 4); 1217 1218 temp = buf_res.length & ~3; 1219 1220 /* update counters */ 1221 count -= temp; 1222 td->offset += temp; 1223 td->remainder -= temp; 1224 continue; 1225 } 1226 /* transmit data */ 1227 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 1228 MUSB2_REG_EPFIFO(0), buf_res.buffer, 1229 buf_res.length); 1230 1231 /* update counters */ 1232 count -= buf_res.length; 1233 td->offset += buf_res.length; 1234 td->remainder -= buf_res.length; 1235 } 1236 1237 /* Function address */ 1238 MUSB2_WRITE_1(sc, MUSB2_REG_TXFADDR(0), td->dev_addr); 1239 MUSB2_WRITE_1(sc, MUSB2_REG_TXHADDR(0), td->haddr); 1240 MUSB2_WRITE_1(sc, MUSB2_REG_TXHUBPORT(0), td->hport); 1241 MUSB2_WRITE_1(sc, MUSB2_REG_TXTI, td->transfer_type); 1242 1243 /* TX NAK timeout */ 1244 MUSB2_WRITE_1(sc, MUSB2_REG_TXNAKLIMIT, MAX_NAK_TO); 1245 1246 /* write command */ 1247 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 1248 MUSB2_MASK_CSR0L_TXPKTRDY); 1249 1250 td->transaction_started = 1; 1251 1252 return (1); /* not complete */ 1253 } 1254 1255 static uint8_t 1256 musbotg_dev_ctrl_status(struct musbotg_td *td) 1257 { 1258 struct musbotg_softc *sc; 1259 uint8_t csr; 1260 1261 /* get pointer to softc */ 1262 sc = MUSBOTG_PC2SC(td->pc); 1263 1264 /* select endpoint 0 */ 1265 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 1266 1267 if (sc->sc_ep0_busy) { 1268 sc->sc_ep0_busy = 0; 1269 sc->sc_ep0_cmd |= MUSB2_MASK_CSR0L_DATAEND; 1270 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, sc->sc_ep0_cmd); 1271 sc->sc_ep0_cmd = 0; 1272 } 1273 /* read out FIFO status */ 1274 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1275 1276 DPRINTFN(4, "csr=0x%02x\n", csr); 1277 1278 if (csr & MUSB2_MASK_CSR0L_DATAEND) { 1279 /* wait for interrupt */ 1280 return (1); /* not complete */ 1281 } 1282 if (sc->sc_dv_addr != 0xFF) { 1283 /* write function address */ 1284 musbotg_set_address(sc, sc->sc_dv_addr); 1285 } 1286 1287 musbotg_channel_free(sc, td); 1288 return (0); /* complete */ 1289 } 1290 1291 static uint8_t 1292 musbotg_host_ctrl_status_rx(struct musbotg_td *td) 1293 { 1294 struct musbotg_softc *sc; 1295 uint8_t csr, csrh; 1296 1297 /* get pointer to softc */ 1298 sc = MUSBOTG_PC2SC(td->pc); 1299 1300 if (td->channel == -1) 1301 td->channel = musbotg_channel_alloc(sc, td, 0); 1302 1303 /* EP0 is busy, wait */ 1304 if (td->channel == -1) 1305 return (1); 1306 1307 DPRINTFN(1, "ep_no=%d\n", td->channel); 1308 1309 /* select endpoint 0 */ 1310 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 1311 1312 if (!td->transaction_started) { 1313 MUSB2_WRITE_1(sc, MUSB2_REG_RXFADDR(0), 1314 td->dev_addr); 1315 1316 MUSB2_WRITE_1(sc, MUSB2_REG_RXHADDR(0), td->haddr); 1317 MUSB2_WRITE_1(sc, MUSB2_REG_RXHUBPORT(0), td->hport); 1318 MUSB2_WRITE_1(sc, MUSB2_REG_RXTI, td->transfer_type); 1319 1320 /* RX NAK timeout */ 1321 MUSB2_WRITE_1(sc, MUSB2_REG_RXNAKLIMIT, MAX_NAK_TO); 1322 1323 td->transaction_started = 1; 1324 1325 /* Disable PING */ 1326 csrh = MUSB2_READ_1(sc, MUSB2_REG_RXCSRH); 1327 csrh |= MUSB2_MASK_CSR0H_PING_DIS; 1328 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, csrh); 1329 1330 /* write command */ 1331 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 1332 MUSB2_MASK_CSR0L_STATUSPKT | 1333 MUSB2_MASK_CSR0L_REQPKT); 1334 1335 return (1); /* Just started */ 1336 1337 } 1338 1339 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1340 1341 DPRINTFN(4, "IN STATUS csr=0x%02x\n", csr); 1342 1343 if (csr & MUSB2_MASK_CSR0L_RXPKTRDY) { 1344 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 1345 MUSB2_MASK_CSR0L_RXPKTRDY_CLR); 1346 musbotg_channel_free(sc, td); 1347 return (0); /* complete */ 1348 } 1349 1350 if (csr & MUSB2_MASK_CSR0L_NAKTIMO) { 1351 csr &= ~ (MUSB2_MASK_CSR0L_STATUSPKT | 1352 MUSB2_MASK_CSR0L_REQPKT); 1353 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr); 1354 1355 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO; 1356 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr); 1357 td->error = 1; 1358 } 1359 1360 /* Failed */ 1361 if (csr & (MUSB2_MASK_CSR0L_RXSTALL | 1362 MUSB2_MASK_CSR0L_ERROR)) 1363 { 1364 /* Clear status bit */ 1365 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 1366 DPRINTFN(1, "error bit set, csr=0x%02x\n", csr); 1367 td->error = 1; 1368 } 1369 1370 if (td->error) { 1371 musbotg_channel_free(sc, td); 1372 return (0); 1373 } 1374 1375 return (1); /* Not ready yet */ 1376 } 1377 1378 static uint8_t 1379 musbotg_host_ctrl_status_tx(struct musbotg_td *td) 1380 { 1381 struct musbotg_softc *sc; 1382 uint8_t csr; 1383 1384 /* get pointer to softc */ 1385 sc = MUSBOTG_PC2SC(td->pc); 1386 1387 if (td->channel == -1) 1388 td->channel = musbotg_channel_alloc(sc, td, 1); 1389 1390 /* EP0 is busy, wait */ 1391 if (td->channel == -1) 1392 return (1); 1393 1394 DPRINTFN(1, "ep_no=%d/%d [%d@%d.%d/%02x]\n", td->channel, td->transaction_started, 1395 td->dev_addr,td->haddr,td->hport, td->transfer_type); 1396 1397 /* select endpoint 0 */ 1398 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 1399 1400 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1401 DPRINTFN(4, "csr=0x%02x\n", csr); 1402 1403 /* Not yet */ 1404 if (csr & MUSB2_MASK_CSR0L_TXPKTRDY) 1405 return (1); 1406 1407 /* Failed */ 1408 if (csr & (MUSB2_MASK_CSR0L_RXSTALL | 1409 MUSB2_MASK_CSR0L_ERROR)) 1410 { 1411 /* Clear status bit */ 1412 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 1413 DPRINTFN(1, "error bit set, csr=0x%02x\n", csr); 1414 td->error = 1; 1415 musbotg_channel_free(sc, td); 1416 return (0); /* complete */ 1417 } 1418 1419 if (td->transaction_started) { 1420 musbotg_channel_free(sc, td); 1421 return (0); /* complete */ 1422 } 1423 1424 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, MUSB2_MASK_CSR0H_PING_DIS); 1425 1426 MUSB2_WRITE_1(sc, MUSB2_REG_TXFADDR(0), td->dev_addr); 1427 MUSB2_WRITE_1(sc, MUSB2_REG_TXHADDR(0), td->haddr); 1428 MUSB2_WRITE_1(sc, MUSB2_REG_TXHUBPORT(0), td->hport); 1429 MUSB2_WRITE_1(sc, MUSB2_REG_TXTI, td->transfer_type); 1430 1431 /* TX NAK timeout */ 1432 MUSB2_WRITE_1(sc, MUSB2_REG_TXNAKLIMIT, MAX_NAK_TO); 1433 1434 td->transaction_started = 1; 1435 1436 /* write command */ 1437 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 1438 MUSB2_MASK_CSR0L_STATUSPKT | 1439 MUSB2_MASK_CSR0L_TXPKTRDY); 1440 1441 return (1); /* wait for interrupt */ 1442 } 1443 1444 static uint8_t 1445 musbotg_dev_data_rx(struct musbotg_td *td) 1446 { 1447 struct usb_page_search buf_res; 1448 struct musbotg_softc *sc; 1449 uint16_t count; 1450 uint8_t csr; 1451 uint8_t to; 1452 uint8_t got_short; 1453 1454 to = 8; /* don't loop forever! */ 1455 got_short = 0; 1456 1457 /* get pointer to softc */ 1458 sc = MUSBOTG_PC2SC(td->pc); 1459 1460 if (td->channel == -1) 1461 td->channel = musbotg_channel_alloc(sc, td, 0); 1462 1463 /* EP0 is busy, wait */ 1464 if (td->channel == -1) 1465 return (1); 1466 1467 /* select endpoint */ 1468 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->channel); 1469 1470 repeat: 1471 /* read out FIFO status */ 1472 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 1473 1474 DPRINTFN(4, "csr=0x%02x\n", csr); 1475 1476 /* clear overrun */ 1477 if (csr & MUSB2_MASK_CSRL_RXOVERRUN) { 1478 /* make sure we don't clear "RXPKTRDY" */ 1479 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 1480 MUSB2_MASK_CSRL_RXPKTRDY); 1481 } 1482 1483 /* check status */ 1484 if (!(csr & MUSB2_MASK_CSRL_RXPKTRDY)) 1485 return (1); /* not complete */ 1486 1487 /* get the packet byte count */ 1488 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT); 1489 1490 DPRINTFN(4, "count=0x%04x\n", count); 1491 1492 /* 1493 * Check for short or invalid packet: 1494 */ 1495 if (count != td->max_frame_size) { 1496 if (count < td->max_frame_size) { 1497 /* we have a short packet */ 1498 td->short_pkt = 1; 1499 got_short = 1; 1500 } else { 1501 /* invalid USB packet */ 1502 td->error = 1; 1503 musbotg_channel_free(sc, td); 1504 return (0); /* we are complete */ 1505 } 1506 } 1507 /* verify the packet byte count */ 1508 if (count > td->remainder) { 1509 /* invalid USB packet */ 1510 td->error = 1; 1511 musbotg_channel_free(sc, td); 1512 return (0); /* we are complete */ 1513 } 1514 while (count > 0) { 1515 uint32_t temp; 1516 1517 usbd_get_page(td->pc, td->offset, &buf_res); 1518 1519 /* get correct length */ 1520 if (buf_res.length > count) { 1521 buf_res.length = count; 1522 } 1523 /* check for unaligned memory address */ 1524 if (USB_P2U(buf_res.buffer) & 3) { 1525 1526 temp = count & ~3; 1527 1528 if (temp) { 1529 /* receive data 4 bytes at a time */ 1530 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 1531 MUSB2_REG_EPFIFO(td->channel), sc->sc_bounce_buf, 1532 temp / 4); 1533 } 1534 temp = count & 3; 1535 if (temp) { 1536 /* receive data 1 byte at a time */ 1537 bus_space_read_multi_1(sc->sc_io_tag, 1538 sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->channel), 1539 ((void *)&sc->sc_bounce_buf[count / 4]), temp); 1540 } 1541 usbd_copy_in(td->pc, td->offset, 1542 sc->sc_bounce_buf, count); 1543 1544 /* update offset and remainder */ 1545 td->offset += count; 1546 td->remainder -= count; 1547 break; 1548 } 1549 /* check if we can optimise */ 1550 if (buf_res.length >= 4) { 1551 1552 /* receive data 4 bytes at a time */ 1553 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 1554 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer, 1555 buf_res.length / 4); 1556 1557 temp = buf_res.length & ~3; 1558 1559 /* update counters */ 1560 count -= temp; 1561 td->offset += temp; 1562 td->remainder -= temp; 1563 continue; 1564 } 1565 /* receive data */ 1566 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 1567 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer, 1568 buf_res.length); 1569 1570 /* update counters */ 1571 count -= buf_res.length; 1572 td->offset += buf_res.length; 1573 td->remainder -= buf_res.length; 1574 } 1575 1576 /* clear status bits */ 1577 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0); 1578 1579 /* check if we are complete */ 1580 if ((td->remainder == 0) || got_short) { 1581 if (td->short_pkt) { 1582 /* we are complete */ 1583 musbotg_channel_free(sc, td); 1584 return (0); 1585 } 1586 /* else need to receive a zero length packet */ 1587 } 1588 if (--to) { 1589 goto repeat; 1590 } 1591 return (1); /* not complete */ 1592 } 1593 1594 static uint8_t 1595 musbotg_dev_data_tx(struct musbotg_td *td) 1596 { 1597 struct usb_page_search buf_res; 1598 struct musbotg_softc *sc; 1599 uint16_t count; 1600 uint8_t csr; 1601 uint8_t to; 1602 1603 to = 8; /* don't loop forever! */ 1604 1605 /* get pointer to softc */ 1606 sc = MUSBOTG_PC2SC(td->pc); 1607 1608 if (td->channel == -1) 1609 td->channel = musbotg_channel_alloc(sc, td, 1); 1610 1611 /* EP0 is busy, wait */ 1612 if (td->channel == -1) 1613 return (1); 1614 1615 /* select endpoint */ 1616 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->channel); 1617 1618 repeat: 1619 1620 /* read out FIFO status */ 1621 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1622 1623 DPRINTFN(4, "csr=0x%02x\n", csr); 1624 1625 if (csr & (MUSB2_MASK_CSRL_TXINCOMP | 1626 MUSB2_MASK_CSRL_TXUNDERRUN)) { 1627 /* clear status bits */ 1628 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 1629 } 1630 if (csr & MUSB2_MASK_CSRL_TXPKTRDY) { 1631 return (1); /* not complete */ 1632 } 1633 /* check for short packet */ 1634 count = td->max_frame_size; 1635 if (td->remainder < count) { 1636 /* we have a short packet */ 1637 td->short_pkt = 1; 1638 count = td->remainder; 1639 } 1640 while (count > 0) { 1641 uint32_t temp; 1642 1643 usbd_get_page(td->pc, td->offset, &buf_res); 1644 1645 /* get correct length */ 1646 if (buf_res.length > count) { 1647 buf_res.length = count; 1648 } 1649 /* check for unaligned memory address */ 1650 if (USB_P2U(buf_res.buffer) & 3) { 1651 1652 usbd_copy_out(td->pc, td->offset, 1653 sc->sc_bounce_buf, count); 1654 1655 temp = count & ~3; 1656 1657 if (temp) { 1658 /* transmit data 4 bytes at a time */ 1659 bus_space_write_multi_4(sc->sc_io_tag, 1660 sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->channel), 1661 sc->sc_bounce_buf, temp / 4); 1662 } 1663 temp = count & 3; 1664 if (temp) { 1665 /* receive data 1 byte at a time */ 1666 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 1667 MUSB2_REG_EPFIFO(td->channel), 1668 ((void *)&sc->sc_bounce_buf[count / 4]), temp); 1669 } 1670 /* update offset and remainder */ 1671 td->offset += count; 1672 td->remainder -= count; 1673 break; 1674 } 1675 /* check if we can optimise */ 1676 if (buf_res.length >= 4) { 1677 1678 /* transmit data 4 bytes at a time */ 1679 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 1680 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer, 1681 buf_res.length / 4); 1682 1683 temp = buf_res.length & ~3; 1684 1685 /* update counters */ 1686 count -= temp; 1687 td->offset += temp; 1688 td->remainder -= temp; 1689 continue; 1690 } 1691 /* transmit data */ 1692 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 1693 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer, 1694 buf_res.length); 1695 1696 /* update counters */ 1697 count -= buf_res.length; 1698 td->offset += buf_res.length; 1699 td->remainder -= buf_res.length; 1700 } 1701 1702 /* Max packet size */ 1703 MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, td->reg_max_packet); 1704 1705 /* write command */ 1706 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 1707 MUSB2_MASK_CSRL_TXPKTRDY); 1708 1709 /* check remainder */ 1710 if (td->remainder == 0) { 1711 if (td->short_pkt) { 1712 musbotg_channel_free(sc, td); 1713 return (0); /* complete */ 1714 } 1715 /* else we need to transmit a short packet */ 1716 } 1717 if (--to) { 1718 goto repeat; 1719 } 1720 return (1); /* not complete */ 1721 } 1722 1723 static uint8_t 1724 musbotg_host_data_rx(struct musbotg_td *td) 1725 { 1726 struct usb_page_search buf_res; 1727 struct musbotg_softc *sc; 1728 uint16_t count; 1729 uint8_t csr, csrh; 1730 uint8_t to; 1731 uint8_t got_short; 1732 1733 /* get pointer to softc */ 1734 sc = MUSBOTG_PC2SC(td->pc); 1735 1736 if (td->channel == -1) 1737 td->channel = musbotg_channel_alloc(sc, td, 0); 1738 1739 /* No free EPs */ 1740 if (td->channel == -1) 1741 return (1); 1742 1743 DPRINTFN(1, "ep_no=%d\n", td->channel); 1744 1745 to = 8; /* don't loop forever! */ 1746 got_short = 0; 1747 1748 /* select endpoint */ 1749 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->channel); 1750 1751 repeat: 1752 /* read out FIFO status */ 1753 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 1754 DPRINTFN(4, "csr=0x%02x\n", csr); 1755 1756 if (!td->transaction_started) { 1757 /* Function address */ 1758 MUSB2_WRITE_1(sc, MUSB2_REG_RXFADDR(td->channel), 1759 td->dev_addr); 1760 1761 /* SPLIT transaction */ 1762 MUSB2_WRITE_1(sc, MUSB2_REG_RXHADDR(td->channel), 1763 td->haddr); 1764 MUSB2_WRITE_1(sc, MUSB2_REG_RXHUBPORT(td->channel), 1765 td->hport); 1766 1767 /* RX NAK timeout */ 1768 if (td->transfer_type & MUSB2_MASK_TI_PROTO_ISOC) 1769 MUSB2_WRITE_1(sc, MUSB2_REG_RXNAKLIMIT, 0); 1770 else 1771 MUSB2_WRITE_1(sc, MUSB2_REG_RXNAKLIMIT, MAX_NAK_TO); 1772 1773 /* Protocol, speed, device endpoint */ 1774 MUSB2_WRITE_1(sc, MUSB2_REG_RXTI, td->transfer_type); 1775 1776 /* Max packet size */ 1777 MUSB2_WRITE_2(sc, MUSB2_REG_RXMAXP, td->reg_max_packet); 1778 1779 /* Data Toggle */ 1780 csrh = MUSB2_READ_1(sc, MUSB2_REG_RXCSRH); 1781 DPRINTFN(4, "csrh=0x%02x\n", csrh); 1782 1783 csrh |= MUSB2_MASK_CSRH_RXDT_WREN; 1784 if (td->toggle) 1785 csrh |= MUSB2_MASK_CSRH_RXDT_VAL; 1786 else 1787 csrh &= ~MUSB2_MASK_CSRH_RXDT_VAL; 1788 1789 /* Set data toggle */ 1790 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, csrh); 1791 1792 /* write command */ 1793 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 1794 MUSB2_MASK_CSRL_RXREQPKT); 1795 1796 td->transaction_started = 1; 1797 return (1); 1798 } 1799 1800 /* clear NAK timeout */ 1801 if (csr & MUSB2_MASK_CSRL_RXNAKTO) { 1802 DPRINTFN(4, "NAK Timeout\n"); 1803 if (csr & MUSB2_MASK_CSRL_RXREQPKT) { 1804 csr &= ~MUSB2_MASK_CSRL_RXREQPKT; 1805 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, csr); 1806 1807 csr &= ~MUSB2_MASK_CSRL_RXNAKTO; 1808 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, csr); 1809 } 1810 1811 td->error = 1; 1812 } 1813 1814 if (csr & MUSB2_MASK_CSRL_RXERROR) { 1815 DPRINTFN(4, "RXERROR\n"); 1816 td->error = 1; 1817 } 1818 1819 if (csr & MUSB2_MASK_CSRL_RXSTALL) { 1820 DPRINTFN(4, "RXSTALL\n"); 1821 td->error = 1; 1822 } 1823 1824 if (td->error) { 1825 musbotg_channel_free(sc, td); 1826 return (0); /* we are complete */ 1827 } 1828 1829 if (!(csr & MUSB2_MASK_CSRL_RXPKTRDY)) { 1830 /* No data available yet */ 1831 return (1); 1832 } 1833 1834 td->toggle ^= 1; 1835 /* get the packet byte count */ 1836 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT); 1837 DPRINTFN(4, "count=0x%04x\n", count); 1838 1839 /* 1840 * Check for short or invalid packet: 1841 */ 1842 if (count != td->max_frame_size) { 1843 if (count < td->max_frame_size) { 1844 /* we have a short packet */ 1845 td->short_pkt = 1; 1846 got_short = 1; 1847 } else { 1848 /* invalid USB packet */ 1849 td->error = 1; 1850 musbotg_channel_free(sc, td); 1851 return (0); /* we are complete */ 1852 } 1853 } 1854 1855 /* verify the packet byte count */ 1856 if (count > td->remainder) { 1857 /* invalid USB packet */ 1858 td->error = 1; 1859 musbotg_channel_free(sc, td); 1860 return (0); /* we are complete */ 1861 } 1862 1863 while (count > 0) { 1864 uint32_t temp; 1865 1866 usbd_get_page(td->pc, td->offset, &buf_res); 1867 1868 /* get correct length */ 1869 if (buf_res.length > count) { 1870 buf_res.length = count; 1871 } 1872 /* check for unaligned memory address */ 1873 if (USB_P2U(buf_res.buffer) & 3) { 1874 1875 temp = count & ~3; 1876 1877 if (temp) { 1878 /* receive data 4 bytes at a time */ 1879 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 1880 MUSB2_REG_EPFIFO(td->channel), sc->sc_bounce_buf, 1881 temp / 4); 1882 } 1883 temp = count & 3; 1884 if (temp) { 1885 /* receive data 1 byte at a time */ 1886 bus_space_read_multi_1(sc->sc_io_tag, 1887 sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->channel), 1888 ((void *)&sc->sc_bounce_buf[count / 4]), temp); 1889 } 1890 usbd_copy_in(td->pc, td->offset, 1891 sc->sc_bounce_buf, count); 1892 1893 /* update offset and remainder */ 1894 td->offset += count; 1895 td->remainder -= count; 1896 break; 1897 } 1898 /* check if we can optimise */ 1899 if (buf_res.length >= 4) { 1900 1901 /* receive data 4 bytes at a time */ 1902 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 1903 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer, 1904 buf_res.length / 4); 1905 1906 temp = buf_res.length & ~3; 1907 1908 /* update counters */ 1909 count -= temp; 1910 td->offset += temp; 1911 td->remainder -= temp; 1912 continue; 1913 } 1914 /* receive data */ 1915 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 1916 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer, 1917 buf_res.length); 1918 1919 /* update counters */ 1920 count -= buf_res.length; 1921 td->offset += buf_res.length; 1922 td->remainder -= buf_res.length; 1923 } 1924 1925 /* clear status bits */ 1926 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0); 1927 1928 /* check if we are complete */ 1929 if ((td->remainder == 0) || got_short) { 1930 if (td->short_pkt) { 1931 /* we are complete */ 1932 musbotg_channel_free(sc, td); 1933 return (0); 1934 } 1935 /* else need to receive a zero length packet */ 1936 } 1937 1938 /* Reset transaction state and restart */ 1939 td->transaction_started = 0; 1940 1941 if (--to) 1942 goto repeat; 1943 1944 return (1); /* not complete */ 1945 } 1946 1947 static uint8_t 1948 musbotg_host_data_tx(struct musbotg_td *td) 1949 { 1950 struct usb_page_search buf_res; 1951 struct musbotg_softc *sc; 1952 uint16_t count; 1953 uint8_t csr, csrh; 1954 1955 /* get pointer to softc */ 1956 sc = MUSBOTG_PC2SC(td->pc); 1957 1958 if (td->channel == -1) 1959 td->channel = musbotg_channel_alloc(sc, td, 1); 1960 1961 /* No free EPs */ 1962 if (td->channel == -1) 1963 return (1); 1964 1965 DPRINTFN(1, "ep_no=%d\n", td->channel); 1966 1967 /* select endpoint */ 1968 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->channel); 1969 1970 /* read out FIFO status */ 1971 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1972 DPRINTFN(4, "csr=0x%02x\n", csr); 1973 1974 if (csr & (MUSB2_MASK_CSRL_TXSTALLED | 1975 MUSB2_MASK_CSRL_TXERROR)) { 1976 /* clear status bits */ 1977 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 1978 td->error = 1; 1979 musbotg_channel_free(sc, td); 1980 return (0); /* complete */ 1981 } 1982 1983 if (csr & MUSB2_MASK_CSRL_TXNAKTO) { 1984 /* 1985 * Flush TX FIFO before clearing NAK TO 1986 */ 1987 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) { 1988 csr |= MUSB2_MASK_CSRL_TXFFLUSH; 1989 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr); 1990 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1991 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) { 1992 csr |= MUSB2_MASK_CSRL_TXFFLUSH; 1993 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr); 1994 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1995 } 1996 } 1997 1998 csr &= ~MUSB2_MASK_CSRL_TXNAKTO; 1999 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr); 2000 2001 td->error = 1; 2002 musbotg_channel_free(sc, td); 2003 return (0); /* complete */ 2004 } 2005 2006 /* 2007 * Wait while FIFO is empty. 2008 * Do not flush it because it will cause transactions 2009 * with size more then packet size. It might upset 2010 * some devices 2011 */ 2012 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) 2013 return (1); 2014 2015 /* Packet still being processed */ 2016 if (csr & MUSB2_MASK_CSRL_TXPKTRDY) 2017 return (1); 2018 2019 if (td->transaction_started) { 2020 /* check remainder */ 2021 if (td->remainder == 0) { 2022 if (td->short_pkt) { 2023 musbotg_channel_free(sc, td); 2024 return (0); /* complete */ 2025 } 2026 /* else we need to transmit a short packet */ 2027 } 2028 2029 /* We're not complete - more transactions required */ 2030 td->transaction_started = 0; 2031 } 2032 2033 /* check for short packet */ 2034 count = td->max_frame_size; 2035 if (td->remainder < count) { 2036 /* we have a short packet */ 2037 td->short_pkt = 1; 2038 count = td->remainder; 2039 } 2040 2041 while (count > 0) { 2042 uint32_t temp; 2043 2044 usbd_get_page(td->pc, td->offset, &buf_res); 2045 2046 /* get correct length */ 2047 if (buf_res.length > count) { 2048 buf_res.length = count; 2049 } 2050 /* check for unaligned memory address */ 2051 if (USB_P2U(buf_res.buffer) & 3) { 2052 2053 usbd_copy_out(td->pc, td->offset, 2054 sc->sc_bounce_buf, count); 2055 2056 temp = count & ~3; 2057 2058 if (temp) { 2059 /* transmit data 4 bytes at a time */ 2060 bus_space_write_multi_4(sc->sc_io_tag, 2061 sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->channel), 2062 sc->sc_bounce_buf, temp / 4); 2063 } 2064 temp = count & 3; 2065 if (temp) { 2066 /* receive data 1 byte at a time */ 2067 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 2068 MUSB2_REG_EPFIFO(td->channel), 2069 ((void *)&sc->sc_bounce_buf[count / 4]), temp); 2070 } 2071 /* update offset and remainder */ 2072 td->offset += count; 2073 td->remainder -= count; 2074 break; 2075 } 2076 /* check if we can optimise */ 2077 if (buf_res.length >= 4) { 2078 2079 /* transmit data 4 bytes at a time */ 2080 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 2081 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer, 2082 buf_res.length / 4); 2083 2084 temp = buf_res.length & ~3; 2085 2086 /* update counters */ 2087 count -= temp; 2088 td->offset += temp; 2089 td->remainder -= temp; 2090 continue; 2091 } 2092 /* transmit data */ 2093 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 2094 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer, 2095 buf_res.length); 2096 2097 /* update counters */ 2098 count -= buf_res.length; 2099 td->offset += buf_res.length; 2100 td->remainder -= buf_res.length; 2101 } 2102 2103 /* Function address */ 2104 MUSB2_WRITE_1(sc, MUSB2_REG_TXFADDR(td->channel), 2105 td->dev_addr); 2106 2107 /* SPLIT transaction */ 2108 MUSB2_WRITE_1(sc, MUSB2_REG_TXHADDR(td->channel), 2109 td->haddr); 2110 MUSB2_WRITE_1(sc, MUSB2_REG_TXHUBPORT(td->channel), 2111 td->hport); 2112 2113 /* TX NAK timeout */ 2114 if (td->transfer_type & MUSB2_MASK_TI_PROTO_ISOC) 2115 MUSB2_WRITE_1(sc, MUSB2_REG_TXNAKLIMIT, 0); 2116 else 2117 MUSB2_WRITE_1(sc, MUSB2_REG_TXNAKLIMIT, MAX_NAK_TO); 2118 2119 /* Protocol, speed, device endpoint */ 2120 MUSB2_WRITE_1(sc, MUSB2_REG_TXTI, td->transfer_type); 2121 2122 /* Max packet size */ 2123 MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, td->reg_max_packet); 2124 2125 if (!td->transaction_started) { 2126 csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH); 2127 DPRINTFN(4, "csrh=0x%02x\n", csrh); 2128 2129 csrh |= MUSB2_MASK_CSRH_TXDT_WREN; 2130 if (td->toggle) 2131 csrh |= MUSB2_MASK_CSRH_TXDT_VAL; 2132 else 2133 csrh &= ~MUSB2_MASK_CSRH_TXDT_VAL; 2134 2135 /* Set data toggle */ 2136 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh); 2137 } 2138 2139 /* write command */ 2140 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 2141 MUSB2_MASK_CSRL_TXPKTRDY); 2142 2143 /* Update Data Toggle */ 2144 td->toggle ^= 1; 2145 td->transaction_started = 1; 2146 2147 return (1); /* not complete */ 2148 } 2149 2150 static uint8_t 2151 musbotg_xfer_do_fifo(struct usb_xfer *xfer) 2152 { 2153 struct musbotg_softc *sc; 2154 struct musbotg_td *td; 2155 2156 DPRINTFN(8, "\n"); 2157 sc = MUSBOTG_BUS2SC(xfer->xroot->bus); 2158 2159 td = xfer->td_transfer_cache; 2160 while (1) { 2161 2162 if ((td->func) (td)) { 2163 /* operation in progress */ 2164 break; 2165 } 2166 2167 if (((void *)td) == xfer->td_transfer_last) { 2168 goto done; 2169 } 2170 if (td->error) { 2171 goto done; 2172 } else if (td->remainder > 0) { 2173 /* 2174 * We had a short transfer. If there is no alternate 2175 * next, stop processing ! 2176 */ 2177 if (!td->alt_next) { 2178 goto done; 2179 } 2180 } 2181 /* 2182 * Fetch the next transfer descriptor and transfer 2183 * some flags to the next transfer descriptor 2184 */ 2185 td = td->obj_next; 2186 xfer->td_transfer_cache = td; 2187 } 2188 2189 return (1); /* not complete */ 2190 done: 2191 /* compute all actual lengths */ 2192 musbotg_standard_done(xfer); 2193 2194 return (0); /* complete */ 2195 } 2196 2197 static void 2198 musbotg_interrupt_poll(struct musbotg_softc *sc) 2199 { 2200 struct usb_xfer *xfer; 2201 2202 repeat: 2203 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 2204 if (!musbotg_xfer_do_fifo(xfer)) { 2205 /* queue has been modified */ 2206 goto repeat; 2207 } 2208 } 2209 } 2210 2211 void 2212 musbotg_vbus_interrupt(struct musbotg_softc *sc, uint8_t is_on) 2213 { 2214 DPRINTFN(4, "vbus = %u\n", is_on); 2215 2216 USB_BUS_LOCK(&sc->sc_bus); 2217 if (is_on) { 2218 if (!sc->sc_flags.status_vbus) { 2219 sc->sc_flags.status_vbus = 1; 2220 2221 /* complete root HUB interrupt endpoint */ 2222 musbotg_root_intr(sc); 2223 } 2224 } else { 2225 if (sc->sc_flags.status_vbus) { 2226 sc->sc_flags.status_vbus = 0; 2227 sc->sc_flags.status_bus_reset = 0; 2228 sc->sc_flags.status_suspend = 0; 2229 sc->sc_flags.change_suspend = 0; 2230 sc->sc_flags.change_connect = 1; 2231 2232 /* complete root HUB interrupt endpoint */ 2233 musbotg_root_intr(sc); 2234 } 2235 } 2236 2237 USB_BUS_UNLOCK(&sc->sc_bus); 2238 } 2239 2240 void 2241 musbotg_connect_interrupt(struct musbotg_softc *sc) 2242 { 2243 USB_BUS_LOCK(&sc->sc_bus); 2244 sc->sc_flags.change_connect = 1; 2245 2246 /* complete root HUB interrupt endpoint */ 2247 musbotg_root_intr(sc); 2248 USB_BUS_UNLOCK(&sc->sc_bus); 2249 } 2250 2251 void 2252 musbotg_interrupt(struct musbotg_softc *sc, 2253 uint16_t rxstat, uint16_t txstat, uint8_t stat) 2254 { 2255 uint16_t rx_status; 2256 uint16_t tx_status; 2257 uint8_t usb_status; 2258 uint8_t temp; 2259 uint8_t to = 2; 2260 2261 USB_BUS_LOCK(&sc->sc_bus); 2262 2263 repeat: 2264 2265 /* read all interrupt registers */ 2266 usb_status = MUSB2_READ_1(sc, MUSB2_REG_INTUSB); 2267 2268 /* read all FIFO interrupts */ 2269 rx_status = MUSB2_READ_2(sc, MUSB2_REG_INTRX); 2270 tx_status = MUSB2_READ_2(sc, MUSB2_REG_INTTX); 2271 rx_status |= rxstat; 2272 tx_status |= txstat; 2273 usb_status |= stat; 2274 2275 /* Clear platform flags after first time */ 2276 rxstat = 0; 2277 txstat = 0; 2278 stat = 0; 2279 2280 /* check for any bus state change interrupts */ 2281 2282 if (usb_status & (MUSB2_MASK_IRESET | 2283 MUSB2_MASK_IRESUME | MUSB2_MASK_ISUSP | 2284 MUSB2_MASK_ICONN | MUSB2_MASK_IDISC | 2285 MUSB2_MASK_IVBUSERR)) { 2286 2287 DPRINTFN(4, "real bus interrupt 0x%08x\n", usb_status); 2288 2289 if (usb_status & MUSB2_MASK_IRESET) { 2290 2291 /* set correct state */ 2292 sc->sc_flags.status_bus_reset = 1; 2293 sc->sc_flags.status_suspend = 0; 2294 sc->sc_flags.change_suspend = 0; 2295 sc->sc_flags.change_connect = 1; 2296 2297 /* determine line speed */ 2298 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); 2299 if (temp & MUSB2_MASK_HSMODE) 2300 sc->sc_flags.status_high_speed = 1; 2301 else 2302 sc->sc_flags.status_high_speed = 0; 2303 2304 /* 2305 * After reset all interrupts are on and we need to 2306 * turn them off! 2307 */ 2308 temp = MUSB2_MASK_IRESET; 2309 /* disable resume interrupt */ 2310 temp &= ~MUSB2_MASK_IRESUME; 2311 /* enable suspend interrupt */ 2312 temp |= MUSB2_MASK_ISUSP; 2313 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, temp); 2314 /* disable TX and RX interrupts */ 2315 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, 0); 2316 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, 0); 2317 } 2318 /* 2319 * If RXRSM and RXSUSP is set at the same time we interpret 2320 * that like RESUME. Resume is set when there is at least 3 2321 * milliseconds of inactivity on the USB BUS. 2322 */ 2323 if (usb_status & MUSB2_MASK_IRESUME) { 2324 if (sc->sc_flags.status_suspend) { 2325 sc->sc_flags.status_suspend = 0; 2326 sc->sc_flags.change_suspend = 1; 2327 2328 temp = MUSB2_READ_1(sc, MUSB2_REG_INTUSBE); 2329 /* disable resume interrupt */ 2330 temp &= ~MUSB2_MASK_IRESUME; 2331 /* enable suspend interrupt */ 2332 temp |= MUSB2_MASK_ISUSP; 2333 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, temp); 2334 } 2335 } else if (usb_status & MUSB2_MASK_ISUSP) { 2336 if (!sc->sc_flags.status_suspend) { 2337 sc->sc_flags.status_suspend = 1; 2338 sc->sc_flags.change_suspend = 1; 2339 2340 temp = MUSB2_READ_1(sc, MUSB2_REG_INTUSBE); 2341 /* disable suspend interrupt */ 2342 temp &= ~MUSB2_MASK_ISUSP; 2343 /* enable resume interrupt */ 2344 temp |= MUSB2_MASK_IRESUME; 2345 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, temp); 2346 } 2347 } 2348 if (usb_status & 2349 (MUSB2_MASK_ICONN | MUSB2_MASK_IDISC)) 2350 sc->sc_flags.change_connect = 1; 2351 2352 /* 2353 * Host Mode: There is no IRESET so assume bus is 2354 * always in reset state once device is connected. 2355 */ 2356 if (sc->sc_mode == MUSB2_HOST_MODE) { 2357 /* check for VBUS error in USB host mode */ 2358 if (usb_status & MUSB2_MASK_IVBUSERR) { 2359 temp = MUSB2_READ_1(sc, MUSB2_REG_DEVCTL); 2360 temp |= MUSB2_MASK_SESS; 2361 MUSB2_WRITE_1(sc, MUSB2_REG_DEVCTL, temp); 2362 } 2363 if (usb_status & MUSB2_MASK_ICONN) 2364 sc->sc_flags.status_bus_reset = 1; 2365 if (usb_status & MUSB2_MASK_IDISC) 2366 sc->sc_flags.status_bus_reset = 0; 2367 } 2368 2369 /* complete root HUB interrupt endpoint */ 2370 musbotg_root_intr(sc); 2371 } 2372 /* check for any endpoint interrupts */ 2373 2374 if (rx_status || tx_status) { 2375 DPRINTFN(4, "real endpoint interrupt " 2376 "rx=0x%04x, tx=0x%04x\n", rx_status, tx_status); 2377 } 2378 /* poll one time regardless of FIFO status */ 2379 2380 musbotg_interrupt_poll(sc); 2381 2382 if (--to) 2383 goto repeat; 2384 2385 USB_BUS_UNLOCK(&sc->sc_bus); 2386 } 2387 2388 static void 2389 musbotg_setup_standard_chain_sub(struct musbotg_std_temp *temp) 2390 { 2391 struct musbotg_td *td; 2392 2393 /* get current Transfer Descriptor */ 2394 td = temp->td_next; 2395 temp->td = td; 2396 2397 /* prepare for next TD */ 2398 temp->td_next = td->obj_next; 2399 2400 /* fill out the Transfer Descriptor */ 2401 td->func = temp->func; 2402 td->pc = temp->pc; 2403 td->offset = temp->offset; 2404 td->remainder = temp->len; 2405 td->error = 0; 2406 td->transaction_started = 0; 2407 td->did_stall = temp->did_stall; 2408 td->short_pkt = temp->short_pkt; 2409 td->alt_next = temp->setup_alt_next; 2410 td->channel = temp->channel; 2411 td->dev_addr = temp->dev_addr; 2412 td->haddr = temp->haddr; 2413 td->hport = temp->hport; 2414 td->transfer_type = temp->transfer_type; 2415 } 2416 2417 static void 2418 musbotg_setup_standard_chain(struct usb_xfer *xfer) 2419 { 2420 struct musbotg_std_temp temp; 2421 struct musbotg_softc *sc; 2422 struct musbotg_td *td; 2423 uint32_t x; 2424 uint8_t ep_no; 2425 uint8_t xfer_type; 2426 enum usb_dev_speed speed; 2427 int tx; 2428 int dev_addr; 2429 2430 DPRINTFN(8, "addr=%d endpt=%d sumlen=%d speed=%d\n", 2431 xfer->address, UE_GET_ADDR(xfer->endpointno), 2432 xfer->sumlen, usbd_get_speed(xfer->xroot->udev)); 2433 2434 sc = MUSBOTG_BUS2SC(xfer->xroot->bus); 2435 ep_no = (xfer->endpointno & UE_ADDR); 2436 2437 temp.max_frame_size = xfer->max_frame_size; 2438 2439 td = xfer->td_start[0]; 2440 xfer->td_transfer_first = td; 2441 xfer->td_transfer_cache = td; 2442 2443 /* setup temp */ 2444 dev_addr = xfer->address; 2445 2446 xfer_type = xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE; 2447 2448 temp.pc = NULL; 2449 temp.td = NULL; 2450 temp.td_next = xfer->td_start[0]; 2451 temp.offset = 0; 2452 temp.setup_alt_next = xfer->flags_int.short_frames_ok || 2453 xfer->flags_int.isochronous_xfr; 2454 temp.did_stall = !xfer->flags_int.control_stall; 2455 temp.channel = -1; 2456 temp.dev_addr = dev_addr; 2457 temp.haddr = xfer->xroot->udev->hs_hub_addr; 2458 temp.hport = xfer->xroot->udev->hs_port_no; 2459 2460 if (xfer->flags_int.usb_mode == USB_MODE_HOST) { 2461 speed = usbd_get_speed(xfer->xroot->udev); 2462 2463 switch (speed) { 2464 case USB_SPEED_LOW: 2465 temp.transfer_type = MUSB2_MASK_TI_SPEED_LO; 2466 break; 2467 case USB_SPEED_FULL: 2468 temp.transfer_type = MUSB2_MASK_TI_SPEED_FS; 2469 break; 2470 case USB_SPEED_HIGH: 2471 temp.transfer_type = MUSB2_MASK_TI_SPEED_HS; 2472 break; 2473 default: 2474 temp.transfer_type = 0; 2475 DPRINTFN(-1, "Invalid USB speed: %d\n", speed); 2476 break; 2477 } 2478 2479 switch (xfer_type) { 2480 case UE_CONTROL: 2481 temp.transfer_type |= MUSB2_MASK_TI_PROTO_CTRL; 2482 break; 2483 case UE_ISOCHRONOUS: 2484 temp.transfer_type |= MUSB2_MASK_TI_PROTO_ISOC; 2485 break; 2486 case UE_BULK: 2487 temp.transfer_type |= MUSB2_MASK_TI_PROTO_BULK; 2488 break; 2489 case UE_INTERRUPT: 2490 temp.transfer_type |= MUSB2_MASK_TI_PROTO_INTR; 2491 break; 2492 default: 2493 DPRINTFN(-1, "Invalid USB transfer type: %d\n", 2494 xfer_type); 2495 break; 2496 } 2497 2498 temp.transfer_type |= ep_no; 2499 td->toggle = xfer->endpoint->toggle_next; 2500 } 2501 2502 /* check if we should prepend a setup message */ 2503 2504 if (xfer->flags_int.control_xfr) { 2505 if (xfer->flags_int.control_hdr) { 2506 2507 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) 2508 temp.func = &musbotg_dev_ctrl_setup_rx; 2509 else 2510 temp.func = &musbotg_host_ctrl_setup_tx; 2511 2512 temp.len = xfer->frlengths[0]; 2513 temp.pc = xfer->frbuffers + 0; 2514 temp.short_pkt = temp.len ? 1 : 0; 2515 2516 musbotg_setup_standard_chain_sub(&temp); 2517 } 2518 x = 1; 2519 } else { 2520 x = 0; 2521 } 2522 2523 tx = 0; 2524 2525 if (x != xfer->nframes) { 2526 if (xfer->endpointno & UE_DIR_IN) 2527 tx = 1; 2528 2529 if (xfer->flags_int.usb_mode == USB_MODE_HOST) { 2530 tx = !tx; 2531 2532 if (tx) { 2533 if (xfer->flags_int.control_xfr) 2534 temp.func = &musbotg_host_ctrl_data_tx; 2535 else 2536 temp.func = &musbotg_host_data_tx; 2537 } else { 2538 if (xfer->flags_int.control_xfr) 2539 temp.func = &musbotg_host_ctrl_data_rx; 2540 else 2541 temp.func = &musbotg_host_data_rx; 2542 } 2543 2544 } else { 2545 if (tx) { 2546 if (xfer->flags_int.control_xfr) 2547 temp.func = &musbotg_dev_ctrl_data_tx; 2548 else 2549 temp.func = &musbotg_dev_data_tx; 2550 } else { 2551 if (xfer->flags_int.control_xfr) 2552 temp.func = &musbotg_dev_ctrl_data_rx; 2553 else 2554 temp.func = &musbotg_dev_data_rx; 2555 } 2556 } 2557 2558 /* setup "pc" pointer */ 2559 temp.pc = xfer->frbuffers + x; 2560 } 2561 while (x != xfer->nframes) { 2562 2563 /* DATA0 / DATA1 message */ 2564 2565 temp.len = xfer->frlengths[x]; 2566 2567 x++; 2568 2569 if (x == xfer->nframes) { 2570 if (xfer->flags_int.control_xfr) { 2571 if (xfer->flags_int.control_act) { 2572 temp.setup_alt_next = 0; 2573 } 2574 } else { 2575 temp.setup_alt_next = 0; 2576 } 2577 } 2578 if (temp.len == 0) { 2579 2580 /* make sure that we send an USB packet */ 2581 2582 temp.short_pkt = 0; 2583 2584 } else { 2585 2586 if (xfer->flags_int.isochronous_xfr) { 2587 /* isochronous data transfer */ 2588 /* don't force short */ 2589 temp.short_pkt = 1; 2590 } else { 2591 /* regular data transfer */ 2592 temp.short_pkt = (xfer->flags.force_short_xfer ? 0 : 1); 2593 } 2594 } 2595 2596 musbotg_setup_standard_chain_sub(&temp); 2597 2598 if (xfer->flags_int.isochronous_xfr) { 2599 temp.offset += temp.len; 2600 } else { 2601 /* get next Page Cache pointer */ 2602 temp.pc = xfer->frbuffers + x; 2603 } 2604 } 2605 2606 /* check for control transfer */ 2607 if (xfer->flags_int.control_xfr) { 2608 2609 /* always setup a valid "pc" pointer for status and sync */ 2610 temp.pc = xfer->frbuffers + 0; 2611 temp.len = 0; 2612 temp.short_pkt = 0; 2613 temp.setup_alt_next = 0; 2614 2615 /* check if we should append a status stage */ 2616 if (!xfer->flags_int.control_act) { 2617 /* 2618 * Send a DATA1 message and invert the current 2619 * endpoint direction. 2620 */ 2621 if (sc->sc_mode == MUSB2_DEVICE_MODE) 2622 temp.func = &musbotg_dev_ctrl_status; 2623 else { 2624 if (xfer->endpointno & UE_DIR_IN) 2625 temp.func = musbotg_host_ctrl_status_tx; 2626 else 2627 temp.func = musbotg_host_ctrl_status_rx; 2628 } 2629 musbotg_setup_standard_chain_sub(&temp); 2630 } 2631 } 2632 /* must have at least one frame! */ 2633 td = temp.td; 2634 xfer->td_transfer_last = td; 2635 } 2636 2637 static void 2638 musbotg_timeout(void *arg) 2639 { 2640 struct usb_xfer *xfer = arg; 2641 2642 DPRINTFN(1, "xfer=%p\n", xfer); 2643 2644 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 2645 2646 /* transfer is transferred */ 2647 musbotg_device_done(xfer, USB_ERR_TIMEOUT); 2648 } 2649 2650 static void 2651 musbotg_ep_int_set(struct musbotg_softc *sc, int channel, int on) 2652 { 2653 uint16_t temp; 2654 2655 /* 2656 * Only enable the endpoint interrupt when we are 2657 * actually waiting for data, hence we are dealing 2658 * with level triggered interrupts ! 2659 */ 2660 DPRINTFN(1, "ep_no=%d, on=%d\n", channel, on); 2661 2662 if (channel == -1) 2663 return; 2664 2665 if (channel == 0) { 2666 temp = MUSB2_READ_2(sc, MUSB2_REG_INTTXE); 2667 if (on) 2668 temp |= MUSB2_MASK_EPINT(0); 2669 else 2670 temp &= ~MUSB2_MASK_EPINT(0); 2671 2672 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, temp); 2673 } else { 2674 temp = MUSB2_READ_2(sc, MUSB2_REG_INTRXE); 2675 if (on) 2676 temp |= MUSB2_MASK_EPINT(channel); 2677 else 2678 temp &= ~MUSB2_MASK_EPINT(channel); 2679 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, temp); 2680 2681 temp = MUSB2_READ_2(sc, MUSB2_REG_INTTXE); 2682 if (on) 2683 temp |= MUSB2_MASK_EPINT(channel); 2684 else 2685 temp &= ~MUSB2_MASK_EPINT(channel); 2686 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, temp); 2687 } 2688 2689 if (sc->sc_ep_int_set) 2690 sc->sc_ep_int_set(sc, channel, on); 2691 } 2692 2693 static void 2694 musbotg_start_standard_chain(struct usb_xfer *xfer) 2695 { 2696 DPRINTFN(8, "\n"); 2697 2698 /* poll one time */ 2699 if (musbotg_xfer_do_fifo(xfer)) { 2700 2701 DPRINTFN(14, "enabled interrupts on endpoint\n"); 2702 2703 /* put transfer on interrupt queue */ 2704 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 2705 2706 /* start timeout, if any */ 2707 if (xfer->timeout != 0) { 2708 usbd_transfer_timeout_ms(xfer, 2709 &musbotg_timeout, xfer->timeout); 2710 } 2711 } 2712 } 2713 2714 static void 2715 musbotg_root_intr(struct musbotg_softc *sc) 2716 { 2717 DPRINTFN(8, "\n"); 2718 2719 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2720 2721 /* set port bit */ 2722 sc->sc_hub_idata[0] = 0x02; /* we only have one port */ 2723 2724 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 2725 sizeof(sc->sc_hub_idata)); 2726 } 2727 2728 static usb_error_t 2729 musbotg_standard_done_sub(struct usb_xfer *xfer) 2730 { 2731 struct musbotg_td *td; 2732 uint32_t len; 2733 uint8_t error; 2734 2735 DPRINTFN(8, "\n"); 2736 2737 td = xfer->td_transfer_cache; 2738 2739 do { 2740 len = td->remainder; 2741 2742 xfer->endpoint->toggle_next = td->toggle; 2743 2744 if (xfer->aframes != xfer->nframes) { 2745 /* 2746 * Verify the length and subtract 2747 * the remainder from "frlengths[]": 2748 */ 2749 if (len > xfer->frlengths[xfer->aframes]) { 2750 td->error = 1; 2751 } else { 2752 xfer->frlengths[xfer->aframes] -= len; 2753 } 2754 } 2755 /* Check for transfer error */ 2756 if (td->error) { 2757 /* the transfer is finished */ 2758 error = 1; 2759 td = NULL; 2760 break; 2761 } 2762 /* Check for short transfer */ 2763 if (len > 0) { 2764 if (xfer->flags_int.short_frames_ok || 2765 xfer->flags_int.isochronous_xfr) { 2766 /* follow alt next */ 2767 if (td->alt_next) { 2768 td = td->obj_next; 2769 } else { 2770 td = NULL; 2771 } 2772 } else { 2773 /* the transfer is finished */ 2774 td = NULL; 2775 } 2776 error = 0; 2777 break; 2778 } 2779 td = td->obj_next; 2780 2781 /* this USB frame is complete */ 2782 error = 0; 2783 break; 2784 2785 } while (0); 2786 2787 /* update transfer cache */ 2788 2789 xfer->td_transfer_cache = td; 2790 2791 return (error ? 2792 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION); 2793 } 2794 2795 static void 2796 musbotg_standard_done(struct usb_xfer *xfer) 2797 { 2798 usb_error_t err = 0; 2799 2800 DPRINTFN(12, "xfer=%p endpoint=%p transfer done\n", 2801 xfer, xfer->endpoint); 2802 2803 /* reset scanner */ 2804 2805 xfer->td_transfer_cache = xfer->td_transfer_first; 2806 2807 if (xfer->flags_int.control_xfr) { 2808 2809 if (xfer->flags_int.control_hdr) { 2810 2811 err = musbotg_standard_done_sub(xfer); 2812 } 2813 xfer->aframes = 1; 2814 2815 if (xfer->td_transfer_cache == NULL) { 2816 goto done; 2817 } 2818 } 2819 while (xfer->aframes != xfer->nframes) { 2820 2821 err = musbotg_standard_done_sub(xfer); 2822 xfer->aframes++; 2823 2824 if (xfer->td_transfer_cache == NULL) { 2825 goto done; 2826 } 2827 } 2828 2829 if (xfer->flags_int.control_xfr && 2830 !xfer->flags_int.control_act) { 2831 2832 err = musbotg_standard_done_sub(xfer); 2833 } 2834 done: 2835 musbotg_device_done(xfer, err); 2836 } 2837 2838 /*------------------------------------------------------------------------* 2839 * musbotg_device_done 2840 * 2841 * NOTE: this function can be called more than one time on the 2842 * same USB transfer! 2843 *------------------------------------------------------------------------*/ 2844 static void 2845 musbotg_device_done(struct usb_xfer *xfer, usb_error_t error) 2846 { 2847 struct musbotg_td *td; 2848 struct musbotg_softc *sc; 2849 2850 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 2851 2852 DPRINTFN(1, "xfer=%p, endpoint=%p, error=%d\n", 2853 xfer, xfer->endpoint, error); 2854 2855 DPRINTFN(14, "disabled interrupts on endpoint\n"); 2856 2857 sc = MUSBOTG_BUS2SC(xfer->xroot->bus); 2858 td = xfer->td_transfer_cache; 2859 2860 if (td && (td->channel != -1)) 2861 musbotg_channel_free(sc, td); 2862 2863 /* dequeue transfer and start next transfer */ 2864 usbd_transfer_done(xfer, error); 2865 } 2866 2867 static void 2868 musbotg_xfer_stall(struct usb_xfer *xfer) 2869 { 2870 musbotg_device_done(xfer, USB_ERR_STALLED); 2871 } 2872 2873 static void 2874 musbotg_set_stall(struct usb_device *udev, 2875 struct usb_endpoint *ep, uint8_t *did_stall) 2876 { 2877 struct musbotg_softc *sc; 2878 uint8_t ep_no; 2879 2880 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 2881 2882 DPRINTFN(4, "endpoint=%p\n", ep); 2883 2884 /* set FORCESTALL */ 2885 sc = MUSBOTG_BUS2SC(udev->bus); 2886 2887 ep_no = (ep->edesc->bEndpointAddress & UE_ADDR); 2888 2889 /* select endpoint */ 2890 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, ep_no); 2891 2892 if (ep->edesc->bEndpointAddress & UE_DIR_IN) { 2893 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 2894 MUSB2_MASK_CSRL_TXSENDSTALL); 2895 } else { 2896 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 2897 MUSB2_MASK_CSRL_RXSENDSTALL); 2898 } 2899 } 2900 2901 static void 2902 musbotg_clear_stall_sub(struct musbotg_softc *sc, uint16_t wMaxPacket, 2903 uint8_t ep_no, uint8_t ep_type, uint8_t ep_dir) 2904 { 2905 uint16_t mps; 2906 uint16_t temp; 2907 uint8_t csr; 2908 2909 if (ep_type == UE_CONTROL) { 2910 /* clearing stall is not needed */ 2911 return; 2912 } 2913 /* select endpoint */ 2914 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, ep_no); 2915 2916 /* compute max frame size */ 2917 mps = wMaxPacket & 0x7FF; 2918 switch ((wMaxPacket >> 11) & 3) { 2919 case 1: 2920 mps *= 2; 2921 break; 2922 case 2: 2923 mps *= 3; 2924 break; 2925 default: 2926 break; 2927 } 2928 2929 if (ep_dir == UE_DIR_IN) { 2930 2931 temp = 0; 2932 2933 /* Configure endpoint */ 2934 switch (ep_type) { 2935 case UE_INTERRUPT: 2936 MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, wMaxPacket); 2937 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, 2938 MUSB2_MASK_CSRH_TXMODE | temp); 2939 break; 2940 case UE_ISOCHRONOUS: 2941 MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, wMaxPacket); 2942 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, 2943 MUSB2_MASK_CSRH_TXMODE | 2944 MUSB2_MASK_CSRH_TXISO | temp); 2945 break; 2946 case UE_BULK: 2947 MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, wMaxPacket); 2948 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, 2949 MUSB2_MASK_CSRH_TXMODE | temp); 2950 break; 2951 default: 2952 break; 2953 } 2954 2955 /* Need to flush twice in case of double bufring */ 2956 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 2957 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) { 2958 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 2959 MUSB2_MASK_CSRL_TXFFLUSH); 2960 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 2961 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) { 2962 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 2963 MUSB2_MASK_CSRL_TXFFLUSH); 2964 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 2965 } 2966 } 2967 /* reset data toggle */ 2968 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 2969 MUSB2_MASK_CSRL_TXDT_CLR); 2970 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 2971 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 2972 2973 /* set double/single buffering */ 2974 temp = MUSB2_READ_2(sc, MUSB2_REG_TXDBDIS); 2975 if (mps <= (sc->sc_hw_ep_profile[ep_no]. 2976 max_in_frame_size / 2)) { 2977 /* double buffer */ 2978 temp &= ~(1 << ep_no); 2979 } else { 2980 /* single buffer */ 2981 temp |= (1 << ep_no); 2982 } 2983 MUSB2_WRITE_2(sc, MUSB2_REG_TXDBDIS, temp); 2984 2985 /* clear sent stall */ 2986 if (csr & MUSB2_MASK_CSRL_TXSENTSTALL) { 2987 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 2988 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 2989 } 2990 } else { 2991 2992 temp = 0; 2993 2994 /* Configure endpoint */ 2995 switch (ep_type) { 2996 case UE_INTERRUPT: 2997 MUSB2_WRITE_2(sc, MUSB2_REG_RXMAXP, wMaxPacket); 2998 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, 2999 MUSB2_MASK_CSRH_RXNYET | temp); 3000 break; 3001 case UE_ISOCHRONOUS: 3002 MUSB2_WRITE_2(sc, MUSB2_REG_RXMAXP, wMaxPacket); 3003 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, 3004 MUSB2_MASK_CSRH_RXNYET | 3005 MUSB2_MASK_CSRH_RXISO | temp); 3006 break; 3007 case UE_BULK: 3008 MUSB2_WRITE_2(sc, MUSB2_REG_RXMAXP, wMaxPacket); 3009 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, temp); 3010 break; 3011 default: 3012 break; 3013 } 3014 3015 /* Need to flush twice in case of double bufring */ 3016 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 3017 if (csr & MUSB2_MASK_CSRL_RXPKTRDY) { 3018 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 3019 MUSB2_MASK_CSRL_RXFFLUSH); 3020 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 3021 if (csr & MUSB2_MASK_CSRL_RXPKTRDY) { 3022 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 3023 MUSB2_MASK_CSRL_RXFFLUSH); 3024 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 3025 } 3026 } 3027 /* reset data toggle */ 3028 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 3029 MUSB2_MASK_CSRL_RXDT_CLR); 3030 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0); 3031 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 3032 3033 /* set double/single buffering */ 3034 temp = MUSB2_READ_2(sc, MUSB2_REG_RXDBDIS); 3035 if (mps <= (sc->sc_hw_ep_profile[ep_no]. 3036 max_out_frame_size / 2)) { 3037 /* double buffer */ 3038 temp &= ~(1 << ep_no); 3039 } else { 3040 /* single buffer */ 3041 temp |= (1 << ep_no); 3042 } 3043 MUSB2_WRITE_2(sc, MUSB2_REG_RXDBDIS, temp); 3044 3045 /* clear sent stall */ 3046 if (csr & MUSB2_MASK_CSRL_RXSENTSTALL) { 3047 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0); 3048 } 3049 } 3050 } 3051 3052 static void 3053 musbotg_clear_stall(struct usb_device *udev, struct usb_endpoint *ep) 3054 { 3055 struct musbotg_softc *sc; 3056 struct usb_endpoint_descriptor *ed; 3057 3058 DPRINTFN(4, "endpoint=%p\n", ep); 3059 3060 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 3061 3062 /* check mode */ 3063 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 3064 /* not supported */ 3065 return; 3066 } 3067 /* get softc */ 3068 sc = MUSBOTG_BUS2SC(udev->bus); 3069 3070 /* get endpoint descriptor */ 3071 ed = ep->edesc; 3072 3073 /* reset endpoint */ 3074 musbotg_clear_stall_sub(sc, 3075 UGETW(ed->wMaxPacketSize), 3076 (ed->bEndpointAddress & UE_ADDR), 3077 (ed->bmAttributes & UE_XFERTYPE), 3078 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT))); 3079 } 3080 3081 usb_error_t 3082 musbotg_init(struct musbotg_softc *sc) 3083 { 3084 const struct musb_otg_ep_cfg *cfg; 3085 struct usb_hw_ep_profile *pf; 3086 int i; 3087 uint16_t offset; 3088 uint8_t nrx; 3089 uint8_t ntx; 3090 uint8_t temp; 3091 uint8_t fsize; 3092 uint8_t frx; 3093 uint8_t ftx; 3094 uint8_t dynfifo; 3095 3096 DPRINTFN(1, "start\n"); 3097 3098 /* set up the bus structure */ 3099 sc->sc_bus.usbrev = USB_REV_2_0; 3100 sc->sc_bus.methods = &musbotg_bus_methods; 3101 3102 /* Set a default endpoint configuration */ 3103 if (sc->sc_ep_cfg == NULL) 3104 sc->sc_ep_cfg = musbotg_ep_default; 3105 3106 USB_BUS_LOCK(&sc->sc_bus); 3107 3108 /* turn on clocks */ 3109 3110 if (sc->sc_clocks_on) { 3111 (sc->sc_clocks_on) (sc->sc_clocks_arg); 3112 } 3113 3114 /* wait a little for things to stabilise */ 3115 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000); 3116 3117 /* disable all interrupts */ 3118 3119 temp = MUSB2_READ_1(sc, MUSB2_REG_DEVCTL); 3120 DPRINTF("pre-DEVCTL=0x%02x\n", temp); 3121 3122 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 0); 3123 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, 0); 3124 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, 0); 3125 3126 /* disable pullup */ 3127 3128 musbotg_pull_common(sc, 0); 3129 3130 /* wait a little bit (10ms) */ 3131 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); 3132 3133 3134 /* disable double packet buffering */ 3135 MUSB2_WRITE_2(sc, MUSB2_REG_RXDBDIS, 0xFFFF); 3136 MUSB2_WRITE_2(sc, MUSB2_REG_TXDBDIS, 0xFFFF); 3137 3138 /* enable HighSpeed and ISO Update flags */ 3139 3140 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, 3141 MUSB2_MASK_HSENAB | MUSB2_MASK_ISOUPD); 3142 3143 if (sc->sc_mode == MUSB2_DEVICE_MODE) { 3144 /* clear Session bit, if set */ 3145 temp = MUSB2_READ_1(sc, MUSB2_REG_DEVCTL); 3146 temp &= ~MUSB2_MASK_SESS; 3147 MUSB2_WRITE_1(sc, MUSB2_REG_DEVCTL, temp); 3148 } else { 3149 /* Enter session for Host mode */ 3150 temp = MUSB2_READ_1(sc, MUSB2_REG_DEVCTL); 3151 temp |= MUSB2_MASK_SESS; 3152 MUSB2_WRITE_1(sc, MUSB2_REG_DEVCTL, temp); 3153 } 3154 3155 /* wait a little for things to stabilise */ 3156 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 10); 3157 3158 DPRINTF("DEVCTL=0x%02x\n", temp); 3159 3160 /* disable testmode */ 3161 3162 MUSB2_WRITE_1(sc, MUSB2_REG_TESTMODE, 0); 3163 3164 /* set default value */ 3165 3166 MUSB2_WRITE_1(sc, MUSB2_REG_MISC, 0); 3167 3168 /* select endpoint index 0 */ 3169 3170 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 3171 3172 if (sc->sc_ep_max == 0) { 3173 /* read out number of endpoints */ 3174 3175 nrx = 3176 (MUSB2_READ_1(sc, MUSB2_REG_EPINFO) / 16); 3177 3178 ntx = 3179 (MUSB2_READ_1(sc, MUSB2_REG_EPINFO) % 16); 3180 3181 sc->sc_ep_max = (nrx > ntx) ? nrx : ntx; 3182 } else { 3183 nrx = ntx = sc->sc_ep_max; 3184 } 3185 3186 /* these numbers exclude the control endpoint */ 3187 3188 DPRINTFN(2, "RX/TX endpoints: %u/%u\n", nrx, ntx); 3189 3190 if (sc->sc_ep_max == 0) { 3191 DPRINTFN(2, "ERROR: Looks like the clocks are off!\n"); 3192 } 3193 /* read out configuration data */ 3194 3195 sc->sc_conf_data = MUSB2_READ_1(sc, MUSB2_REG_CONFDATA); 3196 3197 DPRINTFN(2, "Config Data: 0x%02x\n", 3198 sc->sc_conf_data); 3199 3200 dynfifo = (sc->sc_conf_data & MUSB2_MASK_CD_DYNFIFOSZ) ? 1 : 0; 3201 3202 if (dynfifo) { 3203 device_printf(sc->sc_bus.bdev, "Dynamic FIFO sizing detected, " 3204 "assuming 16Kbytes of FIFO RAM\n"); 3205 } 3206 3207 DPRINTFN(2, "HW version: 0x%04x\n", 3208 MUSB2_READ_1(sc, MUSB2_REG_HWVERS)); 3209 3210 /* initialise endpoint profiles */ 3211 3212 offset = 0; 3213 3214 for (temp = 1; temp <= sc->sc_ep_max; temp++) { 3215 pf = sc->sc_hw_ep_profile + temp; 3216 3217 /* select endpoint */ 3218 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, temp); 3219 3220 fsize = MUSB2_READ_1(sc, MUSB2_REG_FSIZE); 3221 frx = (fsize & MUSB2_MASK_RX_FSIZE) / 16; 3222 ftx = (fsize & MUSB2_MASK_TX_FSIZE); 3223 3224 DPRINTF("Endpoint %u FIFO size: IN=%u, OUT=%u, DYN=%d\n", 3225 temp, ftx, frx, dynfifo); 3226 3227 if (dynfifo) { 3228 if (frx && (temp <= nrx)) { 3229 for (i = 0; sc->sc_ep_cfg[i].ep_end >= 0; i++) { 3230 cfg = &sc->sc_ep_cfg[i]; 3231 if (temp <= cfg->ep_end) { 3232 frx = cfg->ep_fifosz_shift; 3233 MUSB2_WRITE_1(sc, 3234 MUSB2_REG_RXFIFOSZ, 3235 cfg->ep_fifosz_reg); 3236 break; 3237 } 3238 } 3239 3240 MUSB2_WRITE_2(sc, MUSB2_REG_RXFIFOADD, 3241 offset >> 3); 3242 3243 offset += (1 << frx); 3244 } 3245 if (ftx && (temp <= ntx)) { 3246 for (i = 0; sc->sc_ep_cfg[i].ep_end >= 0; i++) { 3247 cfg = &sc->sc_ep_cfg[i]; 3248 if (temp <= cfg->ep_end) { 3249 ftx = cfg->ep_fifosz_shift; 3250 MUSB2_WRITE_1(sc, 3251 MUSB2_REG_TXFIFOSZ, 3252 cfg->ep_fifosz_reg); 3253 break; 3254 } 3255 } 3256 3257 MUSB2_WRITE_2(sc, MUSB2_REG_TXFIFOADD, 3258 offset >> 3); 3259 3260 offset += (1 << ftx); 3261 } 3262 } 3263 3264 if (frx && ftx && (temp <= nrx) && (temp <= ntx)) { 3265 pf->max_in_frame_size = 1 << ftx; 3266 pf->max_out_frame_size = 1 << frx; 3267 pf->is_simplex = 0; /* duplex */ 3268 pf->support_multi_buffer = 1; 3269 pf->support_bulk = 1; 3270 pf->support_interrupt = 1; 3271 pf->support_isochronous = 1; 3272 pf->support_in = 1; 3273 pf->support_out = 1; 3274 } else if (frx && (temp <= nrx)) { 3275 pf->max_out_frame_size = 1 << frx; 3276 pf->max_in_frame_size = 0; 3277 pf->is_simplex = 1; /* simplex */ 3278 pf->support_multi_buffer = 1; 3279 pf->support_bulk = 1; 3280 pf->support_interrupt = 1; 3281 pf->support_isochronous = 1; 3282 pf->support_out = 1; 3283 } else if (ftx && (temp <= ntx)) { 3284 pf->max_in_frame_size = 1 << ftx; 3285 pf->max_out_frame_size = 0; 3286 pf->is_simplex = 1; /* simplex */ 3287 pf->support_multi_buffer = 1; 3288 pf->support_bulk = 1; 3289 pf->support_interrupt = 1; 3290 pf->support_isochronous = 1; 3291 pf->support_in = 1; 3292 } 3293 } 3294 3295 DPRINTFN(2, "Dynamic FIFO size = %d bytes\n", offset); 3296 3297 /* turn on default interrupts */ 3298 3299 if (sc->sc_mode == MUSB2_HOST_MODE) 3300 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 0xff); 3301 else 3302 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 3303 MUSB2_MASK_IRESET); 3304 3305 musbotg_clocks_off(sc); 3306 3307 USB_BUS_UNLOCK(&sc->sc_bus); 3308 3309 /* catch any lost interrupts */ 3310 3311 musbotg_do_poll(&sc->sc_bus); 3312 3313 return (0); /* success */ 3314 } 3315 3316 void 3317 musbotg_uninit(struct musbotg_softc *sc) 3318 { 3319 USB_BUS_LOCK(&sc->sc_bus); 3320 3321 /* disable all interrupts */ 3322 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 0); 3323 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, 0); 3324 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, 0); 3325 3326 sc->sc_flags.port_powered = 0; 3327 sc->sc_flags.status_vbus = 0; 3328 sc->sc_flags.status_bus_reset = 0; 3329 sc->sc_flags.status_suspend = 0; 3330 sc->sc_flags.change_suspend = 0; 3331 sc->sc_flags.change_connect = 1; 3332 3333 musbotg_pull_down(sc); 3334 musbotg_clocks_off(sc); 3335 USB_BUS_UNLOCK(&sc->sc_bus); 3336 } 3337 3338 static void 3339 musbotg_do_poll(struct usb_bus *bus) 3340 { 3341 struct musbotg_softc *sc = MUSBOTG_BUS2SC(bus); 3342 3343 USB_BUS_LOCK(&sc->sc_bus); 3344 musbotg_interrupt_poll(sc); 3345 USB_BUS_UNLOCK(&sc->sc_bus); 3346 } 3347 3348 /*------------------------------------------------------------------------* 3349 * musbotg bulk support 3350 *------------------------------------------------------------------------*/ 3351 static void 3352 musbotg_device_bulk_open(struct usb_xfer *xfer) 3353 { 3354 return; 3355 } 3356 3357 static void 3358 musbotg_device_bulk_close(struct usb_xfer *xfer) 3359 { 3360 musbotg_device_done(xfer, USB_ERR_CANCELLED); 3361 } 3362 3363 static void 3364 musbotg_device_bulk_enter(struct usb_xfer *xfer) 3365 { 3366 return; 3367 } 3368 3369 static void 3370 musbotg_device_bulk_start(struct usb_xfer *xfer) 3371 { 3372 /* setup TDs */ 3373 musbotg_setup_standard_chain(xfer); 3374 musbotg_start_standard_chain(xfer); 3375 } 3376 3377 static const struct usb_pipe_methods musbotg_device_bulk_methods = 3378 { 3379 .open = musbotg_device_bulk_open, 3380 .close = musbotg_device_bulk_close, 3381 .enter = musbotg_device_bulk_enter, 3382 .start = musbotg_device_bulk_start, 3383 }; 3384 3385 /*------------------------------------------------------------------------* 3386 * musbotg control support 3387 *------------------------------------------------------------------------*/ 3388 static void 3389 musbotg_device_ctrl_open(struct usb_xfer *xfer) 3390 { 3391 return; 3392 } 3393 3394 static void 3395 musbotg_device_ctrl_close(struct usb_xfer *xfer) 3396 { 3397 musbotg_device_done(xfer, USB_ERR_CANCELLED); 3398 } 3399 3400 static void 3401 musbotg_device_ctrl_enter(struct usb_xfer *xfer) 3402 { 3403 return; 3404 } 3405 3406 static void 3407 musbotg_device_ctrl_start(struct usb_xfer *xfer) 3408 { 3409 /* setup TDs */ 3410 musbotg_setup_standard_chain(xfer); 3411 musbotg_start_standard_chain(xfer); 3412 } 3413 3414 static const struct usb_pipe_methods musbotg_device_ctrl_methods = 3415 { 3416 .open = musbotg_device_ctrl_open, 3417 .close = musbotg_device_ctrl_close, 3418 .enter = musbotg_device_ctrl_enter, 3419 .start = musbotg_device_ctrl_start, 3420 }; 3421 3422 /*------------------------------------------------------------------------* 3423 * musbotg interrupt support 3424 *------------------------------------------------------------------------*/ 3425 static void 3426 musbotg_device_intr_open(struct usb_xfer *xfer) 3427 { 3428 return; 3429 } 3430 3431 static void 3432 musbotg_device_intr_close(struct usb_xfer *xfer) 3433 { 3434 musbotg_device_done(xfer, USB_ERR_CANCELLED); 3435 } 3436 3437 static void 3438 musbotg_device_intr_enter(struct usb_xfer *xfer) 3439 { 3440 return; 3441 } 3442 3443 static void 3444 musbotg_device_intr_start(struct usb_xfer *xfer) 3445 { 3446 /* setup TDs */ 3447 musbotg_setup_standard_chain(xfer); 3448 musbotg_start_standard_chain(xfer); 3449 } 3450 3451 static const struct usb_pipe_methods musbotg_device_intr_methods = 3452 { 3453 .open = musbotg_device_intr_open, 3454 .close = musbotg_device_intr_close, 3455 .enter = musbotg_device_intr_enter, 3456 .start = musbotg_device_intr_start, 3457 }; 3458 3459 /*------------------------------------------------------------------------* 3460 * musbotg full speed isochronous support 3461 *------------------------------------------------------------------------*/ 3462 static void 3463 musbotg_device_isoc_open(struct usb_xfer *xfer) 3464 { 3465 return; 3466 } 3467 3468 static void 3469 musbotg_device_isoc_close(struct usb_xfer *xfer) 3470 { 3471 musbotg_device_done(xfer, USB_ERR_CANCELLED); 3472 } 3473 3474 static void 3475 musbotg_device_isoc_enter(struct usb_xfer *xfer) 3476 { 3477 struct musbotg_softc *sc = MUSBOTG_BUS2SC(xfer->xroot->bus); 3478 uint32_t temp; 3479 uint32_t nframes; 3480 uint32_t fs_frames; 3481 3482 DPRINTFN(5, "xfer=%p next=%d nframes=%d\n", 3483 xfer, xfer->endpoint->isoc_next, xfer->nframes); 3484 3485 /* get the current frame index */ 3486 3487 nframes = MUSB2_READ_2(sc, MUSB2_REG_FRAME); 3488 3489 /* 3490 * check if the frame index is within the window where the frames 3491 * will be inserted 3492 */ 3493 temp = (nframes - xfer->endpoint->isoc_next) & MUSB2_MASK_FRAME; 3494 3495 if (usbd_get_speed(xfer->xroot->udev) == USB_SPEED_HIGH) { 3496 fs_frames = (xfer->nframes + 7) / 8; 3497 } else { 3498 fs_frames = xfer->nframes; 3499 } 3500 3501 if ((xfer->endpoint->is_synced == 0) || 3502 (temp < fs_frames)) { 3503 /* 3504 * If there is data underflow or the pipe queue is 3505 * empty we schedule the transfer a few frames ahead 3506 * of the current frame position. Else two isochronous 3507 * transfers might overlap. 3508 */ 3509 xfer->endpoint->isoc_next = (nframes + 3) & MUSB2_MASK_FRAME; 3510 xfer->endpoint->is_synced = 1; 3511 DPRINTFN(2, "start next=%d\n", xfer->endpoint->isoc_next); 3512 } 3513 /* 3514 * compute how many milliseconds the insertion is ahead of the 3515 * current frame position: 3516 */ 3517 temp = (xfer->endpoint->isoc_next - nframes) & MUSB2_MASK_FRAME; 3518 3519 /* 3520 * pre-compute when the isochronous transfer will be finished: 3521 */ 3522 xfer->isoc_time_complete = 3523 usb_isoc_time_expand(&sc->sc_bus, nframes) + temp + 3524 fs_frames; 3525 3526 /* compute frame number for next insertion */ 3527 xfer->endpoint->isoc_next += fs_frames; 3528 3529 /* setup TDs */ 3530 musbotg_setup_standard_chain(xfer); 3531 } 3532 3533 static void 3534 musbotg_device_isoc_start(struct usb_xfer *xfer) 3535 { 3536 /* start TD chain */ 3537 musbotg_start_standard_chain(xfer); 3538 } 3539 3540 static const struct usb_pipe_methods musbotg_device_isoc_methods = 3541 { 3542 .open = musbotg_device_isoc_open, 3543 .close = musbotg_device_isoc_close, 3544 .enter = musbotg_device_isoc_enter, 3545 .start = musbotg_device_isoc_start, 3546 }; 3547 3548 /*------------------------------------------------------------------------* 3549 * musbotg root control support 3550 *------------------------------------------------------------------------* 3551 * Simulate a hardware HUB by handling all the necessary requests. 3552 *------------------------------------------------------------------------*/ 3553 3554 static const struct usb_device_descriptor musbotg_devd = { 3555 .bLength = sizeof(struct usb_device_descriptor), 3556 .bDescriptorType = UDESC_DEVICE, 3557 .bcdUSB = {0x00, 0x02}, 3558 .bDeviceClass = UDCLASS_HUB, 3559 .bDeviceSubClass = UDSUBCLASS_HUB, 3560 .bDeviceProtocol = UDPROTO_HSHUBSTT, 3561 .bMaxPacketSize = 64, 3562 .bcdDevice = {0x00, 0x01}, 3563 .iManufacturer = 1, 3564 .iProduct = 2, 3565 .bNumConfigurations = 1, 3566 }; 3567 3568 static const struct usb_device_qualifier musbotg_odevd = { 3569 .bLength = sizeof(struct usb_device_qualifier), 3570 .bDescriptorType = UDESC_DEVICE_QUALIFIER, 3571 .bcdUSB = {0x00, 0x02}, 3572 .bDeviceClass = UDCLASS_HUB, 3573 .bDeviceSubClass = UDSUBCLASS_HUB, 3574 .bDeviceProtocol = UDPROTO_FSHUB, 3575 .bMaxPacketSize0 = 0, 3576 .bNumConfigurations = 0, 3577 }; 3578 3579 static const struct musbotg_config_desc musbotg_confd = { 3580 .confd = { 3581 .bLength = sizeof(struct usb_config_descriptor), 3582 .bDescriptorType = UDESC_CONFIG, 3583 .wTotalLength[0] = sizeof(musbotg_confd), 3584 .bNumInterface = 1, 3585 .bConfigurationValue = 1, 3586 .iConfiguration = 0, 3587 .bmAttributes = UC_SELF_POWERED, 3588 .bMaxPower = 0, 3589 }, 3590 .ifcd = { 3591 .bLength = sizeof(struct usb_interface_descriptor), 3592 .bDescriptorType = UDESC_INTERFACE, 3593 .bNumEndpoints = 1, 3594 .bInterfaceClass = UICLASS_HUB, 3595 .bInterfaceSubClass = UISUBCLASS_HUB, 3596 .bInterfaceProtocol = 0, 3597 }, 3598 .endpd = { 3599 .bLength = sizeof(struct usb_endpoint_descriptor), 3600 .bDescriptorType = UDESC_ENDPOINT, 3601 .bEndpointAddress = (UE_DIR_IN | MUSBOTG_INTR_ENDPT), 3602 .bmAttributes = UE_INTERRUPT, 3603 .wMaxPacketSize[0] = 8, 3604 .bInterval = 255, 3605 }, 3606 }; 3607 3608 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) } 3609 3610 static const struct usb_hub_descriptor_min musbotg_hubd = { 3611 .bDescLength = sizeof(musbotg_hubd), 3612 .bDescriptorType = UDESC_HUB, 3613 .bNbrPorts = 1, 3614 HSETW(.wHubCharacteristics, (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL)), 3615 .bPwrOn2PwrGood = 50, 3616 .bHubContrCurrent = 0, 3617 .DeviceRemovable = {0}, /* port is removable */ 3618 }; 3619 3620 #define STRING_VENDOR \ 3621 "M\0e\0n\0t\0o\0r\0 \0G\0r\0a\0p\0h\0i\0c\0s" 3622 3623 #define STRING_PRODUCT \ 3624 "O\0T\0G\0 \0R\0o\0o\0t\0 \0H\0U\0B" 3625 3626 USB_MAKE_STRING_DESC(STRING_VENDOR, musbotg_vendor); 3627 USB_MAKE_STRING_DESC(STRING_PRODUCT, musbotg_product); 3628 3629 static usb_error_t 3630 musbotg_roothub_exec(struct usb_device *udev, 3631 struct usb_device_request *req, const void **pptr, uint16_t *plength) 3632 { 3633 struct musbotg_softc *sc = MUSBOTG_BUS2SC(udev->bus); 3634 const void *ptr; 3635 uint16_t len; 3636 uint16_t value; 3637 uint16_t index; 3638 uint8_t reg; 3639 usb_error_t err; 3640 3641 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 3642 3643 /* buffer reset */ 3644 ptr = (const void *)&sc->sc_hub_temp; 3645 len = 0; 3646 err = 0; 3647 3648 value = UGETW(req->wValue); 3649 index = UGETW(req->wIndex); 3650 3651 /* demultiplex the control request */ 3652 3653 switch (req->bmRequestType) { 3654 case UT_READ_DEVICE: 3655 switch (req->bRequest) { 3656 case UR_GET_DESCRIPTOR: 3657 goto tr_handle_get_descriptor; 3658 case UR_GET_CONFIG: 3659 goto tr_handle_get_config; 3660 case UR_GET_STATUS: 3661 goto tr_handle_get_status; 3662 default: 3663 goto tr_stalled; 3664 } 3665 break; 3666 3667 case UT_WRITE_DEVICE: 3668 switch (req->bRequest) { 3669 case UR_SET_ADDRESS: 3670 goto tr_handle_set_address; 3671 case UR_SET_CONFIG: 3672 goto tr_handle_set_config; 3673 case UR_CLEAR_FEATURE: 3674 goto tr_valid; /* nop */ 3675 case UR_SET_DESCRIPTOR: 3676 goto tr_valid; /* nop */ 3677 case UR_SET_FEATURE: 3678 default: 3679 goto tr_stalled; 3680 } 3681 break; 3682 3683 case UT_WRITE_ENDPOINT: 3684 switch (req->bRequest) { 3685 case UR_CLEAR_FEATURE: 3686 switch (UGETW(req->wValue)) { 3687 case UF_ENDPOINT_HALT: 3688 goto tr_handle_clear_halt; 3689 case UF_DEVICE_REMOTE_WAKEUP: 3690 goto tr_handle_clear_wakeup; 3691 default: 3692 goto tr_stalled; 3693 } 3694 break; 3695 case UR_SET_FEATURE: 3696 switch (UGETW(req->wValue)) { 3697 case UF_ENDPOINT_HALT: 3698 goto tr_handle_set_halt; 3699 case UF_DEVICE_REMOTE_WAKEUP: 3700 goto tr_handle_set_wakeup; 3701 default: 3702 goto tr_stalled; 3703 } 3704 break; 3705 case UR_SYNCH_FRAME: 3706 goto tr_valid; /* nop */ 3707 default: 3708 goto tr_stalled; 3709 } 3710 break; 3711 3712 case UT_READ_ENDPOINT: 3713 switch (req->bRequest) { 3714 case UR_GET_STATUS: 3715 goto tr_handle_get_ep_status; 3716 default: 3717 goto tr_stalled; 3718 } 3719 break; 3720 3721 case UT_WRITE_INTERFACE: 3722 switch (req->bRequest) { 3723 case UR_SET_INTERFACE: 3724 goto tr_handle_set_interface; 3725 case UR_CLEAR_FEATURE: 3726 goto tr_valid; /* nop */ 3727 case UR_SET_FEATURE: 3728 default: 3729 goto tr_stalled; 3730 } 3731 break; 3732 3733 case UT_READ_INTERFACE: 3734 switch (req->bRequest) { 3735 case UR_GET_INTERFACE: 3736 goto tr_handle_get_interface; 3737 case UR_GET_STATUS: 3738 goto tr_handle_get_iface_status; 3739 default: 3740 goto tr_stalled; 3741 } 3742 break; 3743 3744 case UT_WRITE_CLASS_INTERFACE: 3745 case UT_WRITE_VENDOR_INTERFACE: 3746 /* XXX forward */ 3747 break; 3748 3749 case UT_READ_CLASS_INTERFACE: 3750 case UT_READ_VENDOR_INTERFACE: 3751 /* XXX forward */ 3752 break; 3753 3754 case UT_WRITE_CLASS_DEVICE: 3755 switch (req->bRequest) { 3756 case UR_CLEAR_FEATURE: 3757 goto tr_valid; 3758 case UR_SET_DESCRIPTOR: 3759 case UR_SET_FEATURE: 3760 break; 3761 default: 3762 goto tr_stalled; 3763 } 3764 break; 3765 3766 case UT_WRITE_CLASS_OTHER: 3767 switch (req->bRequest) { 3768 case UR_CLEAR_FEATURE: 3769 goto tr_handle_clear_port_feature; 3770 case UR_SET_FEATURE: 3771 goto tr_handle_set_port_feature; 3772 case UR_CLEAR_TT_BUFFER: 3773 case UR_RESET_TT: 3774 case UR_STOP_TT: 3775 goto tr_valid; 3776 3777 default: 3778 goto tr_stalled; 3779 } 3780 break; 3781 3782 case UT_READ_CLASS_OTHER: 3783 switch (req->bRequest) { 3784 case UR_GET_TT_STATE: 3785 goto tr_handle_get_tt_state; 3786 case UR_GET_STATUS: 3787 goto tr_handle_get_port_status; 3788 default: 3789 goto tr_stalled; 3790 } 3791 break; 3792 3793 case UT_READ_CLASS_DEVICE: 3794 switch (req->bRequest) { 3795 case UR_GET_DESCRIPTOR: 3796 goto tr_handle_get_class_descriptor; 3797 case UR_GET_STATUS: 3798 goto tr_handle_get_class_status; 3799 3800 default: 3801 goto tr_stalled; 3802 } 3803 break; 3804 default: 3805 goto tr_stalled; 3806 } 3807 goto tr_valid; 3808 3809 tr_handle_get_descriptor: 3810 switch (value >> 8) { 3811 case UDESC_DEVICE: 3812 if (value & 0xff) { 3813 goto tr_stalled; 3814 } 3815 len = sizeof(musbotg_devd); 3816 ptr = (const void *)&musbotg_devd; 3817 goto tr_valid; 3818 case UDESC_DEVICE_QUALIFIER: 3819 if (value & 0xff) { 3820 goto tr_stalled; 3821 } 3822 len = sizeof(musbotg_odevd); 3823 ptr = (const void *)&musbotg_odevd; 3824 goto tr_valid; 3825 case UDESC_CONFIG: 3826 if (value & 0xff) { 3827 goto tr_stalled; 3828 } 3829 len = sizeof(musbotg_confd); 3830 ptr = (const void *)&musbotg_confd; 3831 goto tr_valid; 3832 case UDESC_STRING: 3833 switch (value & 0xff) { 3834 case 0: /* Language table */ 3835 len = sizeof(usb_string_lang_en); 3836 ptr = (const void *)&usb_string_lang_en; 3837 goto tr_valid; 3838 3839 case 1: /* Vendor */ 3840 len = sizeof(musbotg_vendor); 3841 ptr = (const void *)&musbotg_vendor; 3842 goto tr_valid; 3843 3844 case 2: /* Product */ 3845 len = sizeof(musbotg_product); 3846 ptr = (const void *)&musbotg_product; 3847 goto tr_valid; 3848 default: 3849 break; 3850 } 3851 break; 3852 default: 3853 goto tr_stalled; 3854 } 3855 goto tr_stalled; 3856 3857 tr_handle_get_config: 3858 len = 1; 3859 sc->sc_hub_temp.wValue[0] = sc->sc_conf; 3860 goto tr_valid; 3861 3862 tr_handle_get_status: 3863 len = 2; 3864 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED); 3865 goto tr_valid; 3866 3867 tr_handle_set_address: 3868 if (value & 0xFF00) { 3869 goto tr_stalled; 3870 } 3871 sc->sc_rt_addr = value; 3872 goto tr_valid; 3873 3874 tr_handle_set_config: 3875 if (value >= 2) { 3876 goto tr_stalled; 3877 } 3878 sc->sc_conf = value; 3879 goto tr_valid; 3880 3881 tr_handle_get_interface: 3882 len = 1; 3883 sc->sc_hub_temp.wValue[0] = 0; 3884 goto tr_valid; 3885 3886 tr_handle_get_tt_state: 3887 tr_handle_get_class_status: 3888 tr_handle_get_iface_status: 3889 tr_handle_get_ep_status: 3890 len = 2; 3891 USETW(sc->sc_hub_temp.wValue, 0); 3892 goto tr_valid; 3893 3894 tr_handle_set_halt: 3895 tr_handle_set_interface: 3896 tr_handle_set_wakeup: 3897 tr_handle_clear_wakeup: 3898 tr_handle_clear_halt: 3899 goto tr_valid; 3900 3901 tr_handle_clear_port_feature: 3902 if (index != 1) { 3903 goto tr_stalled; 3904 } 3905 DPRINTFN(8, "UR_CLEAR_PORT_FEATURE on port %d\n", index); 3906 3907 switch (value) { 3908 case UHF_PORT_SUSPEND: 3909 if (sc->sc_mode == MUSB2_HOST_MODE) 3910 musbotg_wakeup_host(sc); 3911 else 3912 musbotg_wakeup_peer(sc); 3913 break; 3914 3915 case UHF_PORT_ENABLE: 3916 sc->sc_flags.port_enabled = 0; 3917 break; 3918 3919 case UHF_C_PORT_ENABLE: 3920 sc->sc_flags.change_enabled = 0; 3921 break; 3922 3923 case UHF_C_PORT_OVER_CURRENT: 3924 sc->sc_flags.change_over_current = 0; 3925 break; 3926 3927 case UHF_C_PORT_RESET: 3928 sc->sc_flags.change_reset = 0; 3929 break; 3930 3931 case UHF_PORT_TEST: 3932 case UHF_PORT_INDICATOR: 3933 /* nops */ 3934 break; 3935 3936 case UHF_PORT_POWER: 3937 sc->sc_flags.port_powered = 0; 3938 musbotg_pull_down(sc); 3939 musbotg_clocks_off(sc); 3940 break; 3941 case UHF_C_PORT_CONNECTION: 3942 sc->sc_flags.change_connect = 0; 3943 break; 3944 case UHF_C_PORT_SUSPEND: 3945 sc->sc_flags.change_suspend = 0; 3946 break; 3947 default: 3948 err = USB_ERR_IOERROR; 3949 goto done; 3950 } 3951 goto tr_valid; 3952 3953 tr_handle_set_port_feature: 3954 if (index != 1) { 3955 goto tr_stalled; 3956 } 3957 DPRINTFN(8, "UR_SET_PORT_FEATURE\n"); 3958 3959 switch (value) { 3960 case UHF_PORT_ENABLE: 3961 sc->sc_flags.port_enabled = 1; 3962 break; 3963 case UHF_PORT_SUSPEND: 3964 if (sc->sc_mode == MUSB2_HOST_MODE) 3965 musbotg_suspend_host(sc); 3966 break; 3967 3968 case UHF_PORT_RESET: 3969 if (sc->sc_mode == MUSB2_HOST_MODE) { 3970 reg = MUSB2_READ_1(sc, MUSB2_REG_POWER); 3971 reg |= MUSB2_MASK_RESET; 3972 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, reg); 3973 3974 /* Wait for 20 msec */ 3975 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 5); 3976 3977 reg = MUSB2_READ_1(sc, MUSB2_REG_POWER); 3978 reg &= ~MUSB2_MASK_RESET; 3979 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, reg); 3980 3981 /* determine line speed */ 3982 reg = MUSB2_READ_1(sc, MUSB2_REG_POWER); 3983 if (reg & MUSB2_MASK_HSMODE) 3984 sc->sc_flags.status_high_speed = 1; 3985 else 3986 sc->sc_flags.status_high_speed = 0; 3987 3988 sc->sc_flags.change_reset = 1; 3989 } else 3990 err = USB_ERR_IOERROR; 3991 break; 3992 3993 case UHF_PORT_TEST: 3994 case UHF_PORT_INDICATOR: 3995 /* nops */ 3996 break; 3997 case UHF_PORT_POWER: 3998 sc->sc_flags.port_powered = 1; 3999 break; 4000 default: 4001 err = USB_ERR_IOERROR; 4002 goto done; 4003 } 4004 goto tr_valid; 4005 4006 tr_handle_get_port_status: 4007 4008 DPRINTFN(8, "UR_GET_PORT_STATUS\n"); 4009 4010 if (index != 1) { 4011 goto tr_stalled; 4012 } 4013 if (sc->sc_flags.status_vbus) { 4014 musbotg_clocks_on(sc); 4015 musbotg_pull_up(sc); 4016 } else { 4017 musbotg_pull_down(sc); 4018 musbotg_clocks_off(sc); 4019 } 4020 4021 /* Select Device Side Mode */ 4022 if (sc->sc_mode == MUSB2_DEVICE_MODE) 4023 value = UPS_PORT_MODE_DEVICE; 4024 else 4025 value = 0; 4026 4027 if (sc->sc_flags.status_high_speed) { 4028 value |= UPS_HIGH_SPEED; 4029 } 4030 if (sc->sc_flags.port_powered) { 4031 value |= UPS_PORT_POWER; 4032 } 4033 if (sc->sc_flags.port_enabled) { 4034 value |= UPS_PORT_ENABLED; 4035 } 4036 4037 if (sc->sc_flags.port_over_current) 4038 value |= UPS_OVERCURRENT_INDICATOR; 4039 4040 if (sc->sc_flags.status_vbus && 4041 sc->sc_flags.status_bus_reset) { 4042 value |= UPS_CURRENT_CONNECT_STATUS; 4043 } 4044 if (sc->sc_flags.status_suspend) { 4045 value |= UPS_SUSPEND; 4046 } 4047 USETW(sc->sc_hub_temp.ps.wPortStatus, value); 4048 4049 value = 0; 4050 4051 if (sc->sc_flags.change_connect) { 4052 value |= UPS_C_CONNECT_STATUS; 4053 4054 if (sc->sc_mode == MUSB2_DEVICE_MODE) { 4055 if (sc->sc_flags.status_vbus && 4056 sc->sc_flags.status_bus_reset) { 4057 /* reset EP0 state */ 4058 sc->sc_ep0_busy = 0; 4059 sc->sc_ep0_cmd = 0; 4060 } 4061 } 4062 } 4063 if (sc->sc_flags.change_suspend) 4064 value |= UPS_C_SUSPEND; 4065 if (sc->sc_flags.change_reset) 4066 value |= UPS_C_PORT_RESET; 4067 if (sc->sc_flags.change_over_current) 4068 value |= UPS_C_OVERCURRENT_INDICATOR; 4069 4070 USETW(sc->sc_hub_temp.ps.wPortChange, value); 4071 len = sizeof(sc->sc_hub_temp.ps); 4072 goto tr_valid; 4073 4074 tr_handle_get_class_descriptor: 4075 if (value & 0xFF) { 4076 goto tr_stalled; 4077 } 4078 ptr = (const void *)&musbotg_hubd; 4079 len = sizeof(musbotg_hubd); 4080 goto tr_valid; 4081 4082 tr_stalled: 4083 err = USB_ERR_STALLED; 4084 tr_valid: 4085 done: 4086 *plength = len; 4087 *pptr = ptr; 4088 return (err); 4089 } 4090 4091 static void 4092 musbotg_xfer_setup(struct usb_setup_params *parm) 4093 { 4094 struct musbotg_softc *sc; 4095 struct usb_xfer *xfer; 4096 void *last_obj; 4097 uint32_t ntd; 4098 uint32_t n; 4099 uint8_t ep_no; 4100 4101 sc = MUSBOTG_BUS2SC(parm->udev->bus); 4102 xfer = parm->curr_xfer; 4103 4104 /* 4105 * NOTE: This driver does not use any of the parameters that 4106 * are computed from the following values. Just set some 4107 * reasonable dummies: 4108 */ 4109 parm->hc_max_packet_size = 0x400; 4110 parm->hc_max_frame_size = 0xc00; 4111 4112 if ((parm->methods == &musbotg_device_isoc_methods) || 4113 (parm->methods == &musbotg_device_intr_methods)) 4114 parm->hc_max_packet_count = 3; 4115 else 4116 parm->hc_max_packet_count = 1; 4117 4118 usbd_transfer_setup_sub(parm); 4119 4120 /* 4121 * compute maximum number of TDs 4122 */ 4123 if (parm->methods == &musbotg_device_ctrl_methods) { 4124 4125 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC */ ; 4126 4127 } else if (parm->methods == &musbotg_device_bulk_methods) { 4128 4129 ntd = xfer->nframes + 1 /* SYNC */ ; 4130 4131 } else if (parm->methods == &musbotg_device_intr_methods) { 4132 4133 ntd = xfer->nframes + 1 /* SYNC */ ; 4134 4135 } else if (parm->methods == &musbotg_device_isoc_methods) { 4136 4137 ntd = xfer->nframes + 1 /* SYNC */ ; 4138 4139 } else { 4140 4141 ntd = 0; 4142 } 4143 4144 /* 4145 * check if "usbd_transfer_setup_sub" set an error 4146 */ 4147 if (parm->err) { 4148 return; 4149 } 4150 /* 4151 * allocate transfer descriptors 4152 */ 4153 last_obj = NULL; 4154 4155 ep_no = xfer->endpointno & UE_ADDR; 4156 4157 /* 4158 * Check for a valid endpoint profile in USB device mode: 4159 */ 4160 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) { 4161 const struct usb_hw_ep_profile *pf; 4162 4163 musbotg_get_hw_ep_profile(parm->udev, &pf, ep_no); 4164 4165 if (pf == NULL) { 4166 /* should not happen */ 4167 parm->err = USB_ERR_INVAL; 4168 return; 4169 } 4170 } 4171 4172 /* align data */ 4173 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1)); 4174 4175 for (n = 0; n != ntd; n++) { 4176 4177 struct musbotg_td *td; 4178 4179 if (parm->buf) { 4180 4181 td = USB_ADD_BYTES(parm->buf, parm->size[0]); 4182 4183 /* init TD */ 4184 td->max_frame_size = xfer->max_frame_size; 4185 td->reg_max_packet = xfer->max_packet_size | 4186 ((xfer->max_packet_count - 1) << 11); 4187 td->ep_no = ep_no; 4188 td->obj_next = last_obj; 4189 4190 last_obj = td; 4191 } 4192 parm->size[0] += sizeof(*td); 4193 } 4194 4195 xfer->td_start[0] = last_obj; 4196 } 4197 4198 static void 4199 musbotg_xfer_unsetup(struct usb_xfer *xfer) 4200 { 4201 return; 4202 } 4203 4204 static void 4205 musbotg_get_dma_delay(struct usb_device *udev, uint32_t *pus) 4206 { 4207 struct musbotg_softc *sc = MUSBOTG_BUS2SC(udev->bus); 4208 4209 if (sc->sc_mode == MUSB2_HOST_MODE) 4210 *pus = 2000; /* microseconds */ 4211 else 4212 *pus = 0; 4213 } 4214 4215 static void 4216 musbotg_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 4217 struct usb_endpoint *ep) 4218 { 4219 struct musbotg_softc *sc = MUSBOTG_BUS2SC(udev->bus); 4220 4221 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d)\n", 4222 ep, udev->address, 4223 edesc->bEndpointAddress, udev->flags.usb_mode, 4224 sc->sc_rt_addr); 4225 4226 if (udev->device_index != sc->sc_rt_addr) { 4227 switch (edesc->bmAttributes & UE_XFERTYPE) { 4228 case UE_CONTROL: 4229 ep->methods = &musbotg_device_ctrl_methods; 4230 break; 4231 case UE_INTERRUPT: 4232 ep->methods = &musbotg_device_intr_methods; 4233 break; 4234 case UE_ISOCHRONOUS: 4235 ep->methods = &musbotg_device_isoc_methods; 4236 break; 4237 case UE_BULK: 4238 ep->methods = &musbotg_device_bulk_methods; 4239 break; 4240 default: 4241 /* do nothing */ 4242 break; 4243 } 4244 } 4245 } 4246 4247 static void 4248 musbotg_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 4249 { 4250 struct musbotg_softc *sc = MUSBOTG_BUS2SC(bus); 4251 4252 switch (state) { 4253 case USB_HW_POWER_SUSPEND: 4254 musbotg_uninit(sc); 4255 break; 4256 case USB_HW_POWER_SHUTDOWN: 4257 musbotg_uninit(sc); 4258 break; 4259 case USB_HW_POWER_RESUME: 4260 musbotg_init(sc); 4261 break; 4262 default: 4263 break; 4264 } 4265 } 4266 4267 static const struct usb_bus_methods musbotg_bus_methods = 4268 { 4269 .endpoint_init = &musbotg_ep_init, 4270 .get_dma_delay = &musbotg_get_dma_delay, 4271 .xfer_setup = &musbotg_xfer_setup, 4272 .xfer_unsetup = &musbotg_xfer_unsetup, 4273 .get_hw_ep_profile = &musbotg_get_hw_ep_profile, 4274 .xfer_stall = &musbotg_xfer_stall, 4275 .set_stall = &musbotg_set_stall, 4276 .clear_stall = &musbotg_clear_stall, 4277 .roothub_exec = &musbotg_roothub_exec, 4278 .xfer_poll = &musbotg_do_poll, 4279 .set_hw_power_sleep = &musbotg_set_hw_power_sleep, 4280 }; 4281