1 /* $FreeBSD$ */ 2 /*- 3 * SPDX-License-Identifier: BSD-2-Clause 4 * 5 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * This header file defines the registers of the Mentor Graphics USB OnTheGo 31 * Inventra chip. 32 */ 33 34 #ifndef _MUSB2_OTG_H_ 35 #define _MUSB2_OTG_H_ 36 37 #define MUSB2_MAX_DEVICES USB_MAX_DEVICES 38 39 /* Common registers */ 40 41 #define MUSB2_REG_FADDR 0x0000 /* function address register */ 42 #define MUSB2_MASK_FADDR 0x7F 43 44 #define MUSB2_REG_POWER 0x0001 /* power register */ 45 #define MUSB2_MASK_SUSPM_ENA 0x01 46 #define MUSB2_MASK_SUSPMODE 0x02 47 #define MUSB2_MASK_RESUME 0x04 48 #define MUSB2_MASK_RESET 0x08 49 #define MUSB2_MASK_HSMODE 0x10 50 #define MUSB2_MASK_HSENAB 0x20 51 #define MUSB2_MASK_SOFTC 0x40 52 #define MUSB2_MASK_ISOUPD 0x80 53 54 /* Endpoint interrupt handling */ 55 56 #define MUSB2_REG_INTTX 0x0002 /* transmit interrupt register */ 57 #define MUSB2_REG_INTRX 0x0004 /* receive interrupt register */ 58 #define MUSB2_REG_INTTXE 0x0006 /* transmit interrupt enable register */ 59 #define MUSB2_REG_INTRXE 0x0008 /* receive interrupt enable register */ 60 #define MUSB2_MASK_EPINT(epn) (1 << (epn)) /* epn = [0..15] */ 61 62 /* Common interrupt handling */ 63 64 #define MUSB2_REG_INTUSB 0x000A /* USB interrupt register */ 65 #define MUSB2_MASK_ISUSP 0x01 66 #define MUSB2_MASK_IRESUME 0x02 67 #define MUSB2_MASK_IRESET 0x04 68 #define MUSB2_MASK_IBABBLE 0x04 69 #define MUSB2_MASK_ISOF 0x08 70 #define MUSB2_MASK_ICONN 0x10 71 #define MUSB2_MASK_IDISC 0x20 72 #define MUSB2_MASK_ISESSRQ 0x40 73 #define MUSB2_MASK_IVBUSERR 0x80 74 75 #define MUSB2_REG_INTUSBE 0x000B /* USB interrupt enable register */ 76 #define MUSB2_REG_FRAME 0x000C /* USB frame register */ 77 #define MUSB2_MASK_FRAME 0x3FF /* 0..1023 */ 78 79 #define MUSB2_REG_EPINDEX 0x000E /* endpoint index register */ 80 #define MUSB2_MASK_EPINDEX 0x0F 81 82 #define MUSB2_REG_TESTMODE 0x000F /* test mode register */ 83 #define MUSB2_MASK_TSE0_NAK 0x01 84 #define MUSB2_MASK_TJ 0x02 85 #define MUSB2_MASK_TK 0x04 86 #define MUSB2_MASK_TPACKET 0x08 87 #define MUSB2_MASK_TFORCE_HS 0x10 88 #define MUSB2_MASK_TFORCE_LS 0x20 89 #define MUSB2_MASK_TFIFO_ACC 0x40 90 #define MUSB2_MASK_TFORCE_HC 0x80 91 92 #define MUSB2_REG_INDEXED_CSR 0x0010 /* EP control status register offset */ 93 94 #define MUSB2_REG_TXMAXP (0x0000 + MUSB2_REG_INDEXED_CSR) 95 #define MUSB2_REG_RXMAXP (0x0004 + MUSB2_REG_INDEXED_CSR) 96 #define MUSB2_MASK_PKTSIZE 0x03FF /* in bytes, should be even */ 97 #define MUSB2_MASK_PKTMULT 0xFC00 /* HS packet multiplier: 0..2 */ 98 99 #define MUSB2_REG_TXCSRL (0x0002 + MUSB2_REG_INDEXED_CSR) 100 #define MUSB2_MASK_CSRL_TXPKTRDY 0x01 101 #define MUSB2_MASK_CSRL_TXFIFONEMPTY 0x02 102 #define MUSB2_MASK_CSRL_TXUNDERRUN 0x04 /* Device Mode */ 103 #define MUSB2_MASK_CSRL_TXERROR 0x04 /* Host Mode */ 104 #define MUSB2_MASK_CSRL_TXFFLUSH 0x08 105 #define MUSB2_MASK_CSRL_TXSENDSTALL 0x10/* Device Mode */ 106 #define MUSB2_MASK_CSRL_TXSETUPPKT 0x10 /* Host Mode */ 107 #define MUSB2_MASK_CSRL_TXSENTSTALL 0x20/* Device Mode */ 108 #define MUSB2_MASK_CSRL_TXSTALLED 0x20 /* Host Mode */ 109 #define MUSB2_MASK_CSRL_TXDT_CLR 0x40 110 #define MUSB2_MASK_CSRL_TXINCOMP 0x80 /* Device mode */ 111 #define MUSB2_MASK_CSRL_TXNAKTO 0x80 /* Host mode */ 112 113 /* Device Side Mode */ 114 #define MUSB2_MASK_CSR0L_RXPKTRDY 0x01 115 #define MUSB2_MASK_CSR0L_TXPKTRDY 0x02 116 #define MUSB2_MASK_CSR0L_SENTSTALL 0x04 117 #define MUSB2_MASK_CSR0L_DATAEND 0x08 118 #define MUSB2_MASK_CSR0L_SETUPEND 0x10 119 #define MUSB2_MASK_CSR0L_SENDSTALL 0x20 120 #define MUSB2_MASK_CSR0L_RXPKTRDY_CLR 0x40 121 #define MUSB2_MASK_CSR0L_SETUPEND_CLR 0x80 122 123 /* Host Side Mode */ 124 #define MUSB2_MASK_CSR0L_TXFIFONEMPTY 0x02 125 #define MUSB2_MASK_CSR0L_RXSTALL 0x04 126 #define MUSB2_MASK_CSR0L_SETUPPKT 0x08 127 #define MUSB2_MASK_CSR0L_ERROR 0x10 128 #define MUSB2_MASK_CSR0L_REQPKT 0x20 129 #define MUSB2_MASK_CSR0L_STATUSPKT 0x40 130 #define MUSB2_MASK_CSR0L_NAKTIMO 0x80 131 132 #define MUSB2_REG_TXCSRH (0x0003 + MUSB2_REG_INDEXED_CSR) 133 #define MUSB2_MASK_CSRH_TXDT_VAL 0x01 /* Host Mode */ 134 #define MUSB2_MASK_CSRH_TXDT_WREN 0x02 /* Host Mode */ 135 #define MUSB2_MASK_CSRH_TXDMAREQMODE 0x04 136 #define MUSB2_MASK_CSRH_TXDT_SWITCH 0x08 137 #define MUSB2_MASK_CSRH_TXDMAREQENA 0x10 138 #define MUSB2_MASK_CSRH_RXMODE 0x00 139 #define MUSB2_MASK_CSRH_TXMODE 0x20 140 #define MUSB2_MASK_CSRH_TXISO 0x40 /* Device Mode */ 141 #define MUSB2_MASK_CSRH_TXAUTOSET 0x80 142 143 #define MUSB2_MASK_CSR0H_FFLUSH 0x01 /* Device Side flush FIFO */ 144 #define MUSB2_MASK_CSR0H_DT 0x02 /* Host Side data toggle */ 145 #define MUSB2_MASK_CSR0H_DT_WREN 0x04 /* Host Side */ 146 #define MUSB2_MASK_CSR0H_PING_DIS 0x08 /* Host Side */ 147 148 #define MUSB2_REG_RXCSRL (0x0006 + MUSB2_REG_INDEXED_CSR) 149 #define MUSB2_MASK_CSRL_RXPKTRDY 0x01 150 #define MUSB2_MASK_CSRL_RXFIFOFULL 0x02 151 #define MUSB2_MASK_CSRL_RXOVERRUN 0x04 /* Device Mode */ 152 #define MUSB2_MASK_CSRL_RXERROR 0x04 /* Host Mode */ 153 #define MUSB2_MASK_CSRL_RXDATAERR 0x08 /* Device Mode */ 154 #define MUSB2_MASK_CSRL_RXNAKTO 0x08 /* Host Mode */ 155 #define MUSB2_MASK_CSRL_RXFFLUSH 0x10 156 #define MUSB2_MASK_CSRL_RXSENDSTALL 0x20/* Device Mode */ 157 #define MUSB2_MASK_CSRL_RXREQPKT 0x20 /* Host Mode */ 158 #define MUSB2_MASK_CSRL_RXSENTSTALL 0x40/* Device Mode */ 159 #define MUSB2_MASK_CSRL_RXSTALL 0x40 /* Host Mode */ 160 #define MUSB2_MASK_CSRL_RXDT_CLR 0x80 161 162 #define MUSB2_REG_RXCSRH (0x0007 + MUSB2_REG_INDEXED_CSR) 163 #define MUSB2_MASK_CSRH_RXINCOMP 0x01 164 #define MUSB2_MASK_CSRH_RXDT_VAL 0x02 /* Host Mode */ 165 #define MUSB2_MASK_CSRH_RXDT_WREN 0x04 /* Host Mode */ 166 #define MUSB2_MASK_CSRH_RXDMAREQMODE 0x08 167 #define MUSB2_MASK_CSRH_RXNYET 0x10 168 #define MUSB2_MASK_CSRH_RXDMAREQENA 0x20 169 #define MUSB2_MASK_CSRH_RXISO 0x40 /* Device Mode */ 170 #define MUSB2_MASK_CSRH_RXAUTOREQ 0x40 /* Host Mode */ 171 #define MUSB2_MASK_CSRH_RXAUTOCLEAR 0x80 172 173 #define MUSB2_REG_RXCOUNT (0x0008 + MUSB2_REG_INDEXED_CSR) 174 #define MUSB2_MASK_RXCOUNT 0xFFFF 175 176 #define MUSB2_REG_TXTI (0x000A + MUSB2_REG_INDEXED_CSR) 177 #define MUSB2_REG_RXTI (0x000C + MUSB2_REG_INDEXED_CSR) 178 179 /* Host Mode */ 180 #define MUSB2_MASK_TI_SPEED 0xC0 181 #define MUSB2_MASK_TI_SPEED_LO 0xC0 182 #define MUSB2_MASK_TI_SPEED_FS 0x80 183 #define MUSB2_MASK_TI_SPEED_HS 0x40 184 #define MUSB2_MASK_TI_PROTO_CTRL 0x00 185 #define MUSB2_MASK_TI_PROTO_ISOC 0x10 186 #define MUSB2_MASK_TI_PROTO_BULK 0x20 187 #define MUSB2_MASK_TI_PROTO_INTR 0x30 188 #define MUSB2_MASK_TI_EP_NUM 0x0F 189 190 #define MUSB2_REG_TXNAKLIMIT (0x000B /* EPN=0 */ + MUSB2_REG_INDEXED_CSR) 191 #define MUSB2_REG_RXNAKLIMIT (0x000D /* EPN=0 */ + MUSB2_REG_INDEXED_CSR) 192 #define MUSB2_MASK_NAKLIMIT 0xFF 193 194 #define MUSB2_REG_FSIZE (0x000F + MUSB2_REG_INDEXED_CSR) 195 #define MUSB2_MASK_RX_FSIZE 0xF0 /* 3..13, 2**n bytes */ 196 #define MUSB2_MASK_TX_FSIZE 0x0F /* 3..13, 2**n bytes */ 197 198 #define MUSB2_REG_EPFIFO(n) (0x0020 + (4*(n))) 199 200 #define MUSB2_REG_CONFDATA (0x000F + MUSB2_REG_INDEXED_CSR) /* EPN=0 */ 201 #define MUSB2_MASK_CD_UTMI_DW 0x01 202 #define MUSB2_MASK_CD_SOFTCONE 0x02 203 #define MUSB2_MASK_CD_DYNFIFOSZ 0x04 204 #define MUSB2_MASK_CD_HBTXE 0x08 205 #define MUSB2_MASK_CD_HBRXE 0x10 206 #define MUSB2_MASK_CD_BIGEND 0x20 207 #define MUSB2_MASK_CD_MPTXE 0x40 208 #define MUSB2_MASK_CD_MPRXE 0x80 209 210 /* Various registers */ 211 212 #define MUSB2_REG_DEVCTL 0x0060 213 #define MUSB2_MASK_SESS 0x01 214 #define MUSB2_MASK_HOSTREQ 0x02 215 #define MUSB2_MASK_HOSTMD 0x04 216 #define MUSB2_MASK_VBUS0 0x08 217 #define MUSB2_MASK_VBUS1 0x10 218 #define MUSB2_MASK_LSDEV 0x20 219 #define MUSB2_MASK_FSDEV 0x40 220 #define MUSB2_MASK_BDEV 0x80 221 222 #define MUSB2_REG_MISC 0x0061 223 #define MUSB2_MASK_RXEDMA 0x01 224 #define MUSB2_MASK_TXEDMA 0x02 225 226 #define MUSB2_REG_TXFIFOSZ 0x0062 227 #define MUSB2_REG_RXFIFOSZ 0x0063 228 #define MUSB2_MASK_FIFODB 0x10 /* set if double buffering, r/w */ 229 #define MUSB2_MASK_FIFOSZ 0x0F 230 #define MUSB2_VAL_FIFOSZ_8 0 231 #define MUSB2_VAL_FIFOSZ_16 1 232 #define MUSB2_VAL_FIFOSZ_32 2 233 #define MUSB2_VAL_FIFOSZ_64 3 234 #define MUSB2_VAL_FIFOSZ_128 4 235 #define MUSB2_VAL_FIFOSZ_256 5 236 #define MUSB2_VAL_FIFOSZ_512 6 237 #define MUSB2_VAL_FIFOSZ_1024 7 238 #define MUSB2_VAL_FIFOSZ_2048 8 239 #define MUSB2_VAL_FIFOSZ_4096 9 240 241 #define MUSB2_REG_TXFIFOADD 0x0064 242 #define MUSB2_REG_RXFIFOADD 0x0066 243 #define MUSB2_MASK_FIFOADD 0xFFF /* unit is 8-bytes */ 244 245 #define MUSB2_REG_VSTATUS 0x0068 246 #define MUSB2_REG_VCONTROL 0x0068 247 #define MUSB2_REG_HWVERS 0x006C 248 #define MUSB2_REG_ULPI_BASE 0x0070 249 250 #define MUSB2_REG_EPINFO 0x0078 251 #define MUSB2_MASK_NRXEP 0xF0 252 #define MUSB2_MASK_NTXEP 0x0F 253 254 #define MUSB2_REG_RAMINFO 0x0079 255 #define MUSB2_REG_LINKINFO 0x007A 256 257 #define MUSB2_REG_VPLEN 0x007B 258 #define MUSB2_MASK_VPLEN 0xFF 259 260 #define MUSB2_REG_HS_EOF1 0x007C 261 #define MUSB2_REG_FS_EOF1 0x007D 262 #define MUSB2_REG_LS_EOF1 0x007E 263 #define MUSB2_REG_SOFT_RST 0x007F 264 #define MUSB2_MASK_SRST 0x01 265 #define MUSB2_MASK_SRSTX 0x02 266 267 #define MUSB2_REG_RQPKTCOUNT(n) (0x0300 + (4*(n)) 268 #define MUSB2_REG_RXDBDIS 0x0340 269 #define MUSB2_REG_TXDBDIS 0x0342 270 #define MUSB2_MASK_DB(n) (1 << (n)) /* disable double buffer, n = [0..15] */ 271 272 #define MUSB2_REG_CHIRPTO 0x0344 273 #define MUSB2_REG_HSRESUM 0x0346 274 275 /* Host Mode only registers */ 276 277 #define MUSB2_REG_TXFADDR(n) (0x0080 + (8*(n))) 278 #define MUSB2_REG_TXHADDR(n) (0x0082 + (8*(n))) 279 #define MUSB2_REG_TXHUBPORT(n) (0x0083 + (8*(n))) 280 #define MUSB2_REG_RXFADDR(n) (0x0084 + (8*(n))) 281 #define MUSB2_REG_RXHADDR(n) (0x0086 + (8*(n))) 282 #define MUSB2_REG_RXHUBPORT(n) (0x0087 + (8*(n))) 283 284 #define MUSB2_EP_MAX 16 /* maximum number of endpoints */ 285 286 #define MUSB2_DEVICE_MODE 0 287 #define MUSB2_HOST_MODE 1 288 289 #define MUSB2_READ_2(sc, reg) \ 290 bus_space_read_2((sc)->sc_io_tag, (sc)->sc_io_hdl, reg) 291 292 #define MUSB2_WRITE_2(sc, reg, data) \ 293 bus_space_write_2((sc)->sc_io_tag, (sc)->sc_io_hdl, reg, data) 294 295 #define MUSB2_READ_1(sc, reg) \ 296 bus_space_read_1((sc)->sc_io_tag, (sc)->sc_io_hdl, reg) 297 298 #define MUSB2_WRITE_1(sc, reg, data) \ 299 bus_space_write_1((sc)->sc_io_tag, (sc)->sc_io_hdl, reg, data) 300 301 struct musbotg_td; 302 struct musbotg_softc; 303 304 typedef uint8_t (musbotg_cmd_t)(struct musbotg_td *td); 305 306 struct musbotg_dma { 307 struct musbotg_softc *sc; 308 uint32_t dma_chan; 309 uint8_t busy:1; 310 uint8_t complete:1; 311 uint8_t error:1; 312 }; 313 314 struct musbotg_td { 315 struct musbotg_td *obj_next; 316 musbotg_cmd_t *func; 317 struct usb_page_cache *pc; 318 uint32_t offset; 319 uint32_t remainder; 320 uint16_t max_frame_size; /* packet_size * mult */ 321 uint16_t reg_max_packet; 322 uint8_t ep_no; 323 uint8_t transfer_type; 324 uint8_t error:1; 325 uint8_t alt_next:1; 326 uint8_t short_pkt:1; 327 uint8_t support_multi_buffer:1; 328 uint8_t did_stall:1; 329 uint8_t dma_enabled:1; 330 uint8_t transaction_started:1; 331 uint8_t dev_addr; 332 uint8_t toggle; 333 int8_t channel; 334 uint8_t haddr; 335 uint8_t hport; 336 }; 337 338 struct musbotg_std_temp { 339 musbotg_cmd_t *func; 340 struct usb_page_cache *pc; 341 struct musbotg_td *td; 342 struct musbotg_td *td_next; 343 uint32_t len; 344 uint32_t offset; 345 uint16_t max_frame_size; 346 uint8_t short_pkt; 347 /* 348 * short_pkt = 0: transfer should be short terminated 349 * short_pkt = 1: transfer should not be short terminated 350 */ 351 uint8_t setup_alt_next; 352 uint8_t did_stall; 353 uint8_t dev_addr; 354 int8_t channel; 355 uint8_t haddr; 356 uint8_t hport; 357 uint8_t transfer_type; 358 }; 359 360 struct musbotg_config_desc { 361 struct usb_config_descriptor confd; 362 struct usb_interface_descriptor ifcd; 363 struct usb_endpoint_descriptor endpd; 364 } __packed; 365 366 union musbotg_hub_temp { 367 uWord wValue; 368 struct usb_port_status ps; 369 }; 370 371 struct musbotg_flags { 372 uint8_t change_connect:1; 373 uint8_t change_suspend:1; 374 uint8_t change_reset:1; 375 uint8_t change_over_current:1; 376 uint8_t change_enabled:1; 377 uint8_t status_suspend:1; /* set if suspended */ 378 uint8_t status_vbus:1; /* set if present */ 379 uint8_t status_bus_reset:1; /* set if reset complete */ 380 uint8_t status_high_speed:1; /* set if High Speed is selected */ 381 uint8_t remote_wakeup:1; 382 uint8_t self_powered:1; 383 uint8_t clocks_off:1; 384 uint8_t port_powered:1; 385 uint8_t port_enabled:1; 386 uint8_t port_over_current:1; 387 uint8_t d_pulled_up:1; 388 }; 389 390 struct musb_otg_ep_cfg { 391 int ep_end; 392 int ep_fifosz_shift; 393 uint8_t ep_fifosz_reg; 394 }; 395 396 struct musbotg_softc { 397 struct usb_bus sc_bus; 398 union musbotg_hub_temp sc_hub_temp; 399 struct usb_hw_ep_profile sc_hw_ep_profile[MUSB2_EP_MAX]; 400 401 struct usb_device *sc_devices[MUSB2_MAX_DEVICES]; 402 struct resource *sc_io_res; 403 struct resource *sc_irq_res; 404 void *sc_intr_hdl; 405 bus_size_t sc_io_size; 406 bus_space_tag_t sc_io_tag; 407 bus_space_handle_t sc_io_hdl; 408 409 void (*sc_clocks_on) (void *arg); 410 void (*sc_clocks_off) (void *arg); 411 void (*sc_ep_int_set) (struct musbotg_softc *sc, int ep, int on); 412 void *sc_clocks_arg; 413 414 uint32_t sc_bounce_buf[(1024 * 3) / 4]; /* bounce buffer */ 415 416 uint8_t sc_ep_max; /* maximum number of RX and TX 417 * endpoints supported */ 418 uint8_t sc_rt_addr; /* root HUB address */ 419 uint8_t sc_dv_addr; /* device address */ 420 uint8_t sc_conf; /* root HUB config */ 421 uint8_t sc_ep0_busy; /* set if ep0 is busy */ 422 uint8_t sc_ep0_cmd; /* pending commands */ 423 uint8_t sc_conf_data; /* copy of hardware register */ 424 425 uint8_t sc_hub_idata[1]; 426 uint16_t sc_channel_mask; /* 16 endpoints */ 427 428 struct musbotg_flags sc_flags; 429 uint8_t sc_id; 430 uint8_t sc_mode; 431 void *sc_platform_data; 432 const struct musb_otg_ep_cfg *sc_ep_cfg; 433 }; 434 435 /* prototypes */ 436 437 usb_error_t musbotg_init(struct musbotg_softc *sc); 438 void musbotg_uninit(struct musbotg_softc *sc); 439 void musbotg_interrupt(struct musbotg_softc *sc, 440 uint16_t rxstat, uint16_t txstat, uint8_t stat); 441 void musbotg_vbus_interrupt(struct musbotg_softc *sc, uint8_t is_on); 442 void musbotg_connect_interrupt(struct musbotg_softc *sc); 443 444 #endif /* _MUSB2_OTG_H_ */ 445