1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved. 5 * Copyright (c) 1998 The NetBSD Foundation, Inc. All rights reserved. 6 * Copyright (c) 1998 Lennart Augustsson. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* 31 * USB Open Host Controller driver. 32 * 33 * OHCI spec: http://www.compaq.com/productinfo/development/openhci.html 34 * USB spec: http://www.usb.org/developers/docs/usbspec.zip 35 */ 36 37 #ifdef USB_GLOBAL_INCLUDE_FILE 38 #include USB_GLOBAL_INCLUDE_FILE 39 #else 40 #include <sys/stdint.h> 41 #include <sys/stddef.h> 42 #include <sys/param.h> 43 #include <sys/queue.h> 44 #include <sys/types.h> 45 #include <sys/systm.h> 46 #include <sys/kernel.h> 47 #include <sys/bus.h> 48 #include <sys/module.h> 49 #include <sys/lock.h> 50 #include <sys/mutex.h> 51 #include <sys/condvar.h> 52 #include <sys/sysctl.h> 53 #include <sys/sx.h> 54 #include <sys/unistd.h> 55 #include <sys/callout.h> 56 #include <sys/malloc.h> 57 #include <sys/priv.h> 58 59 #include <dev/usb/usb.h> 60 #include <dev/usb/usbdi.h> 61 62 #define USB_DEBUG_VAR ohcidebug 63 64 #include <dev/usb/usb_core.h> 65 #include <dev/usb/usb_debug.h> 66 #include <dev/usb/usb_busdma.h> 67 #include <dev/usb/usb_process.h> 68 #include <dev/usb/usb_transfer.h> 69 #include <dev/usb/usb_device.h> 70 #include <dev/usb/usb_hub.h> 71 #include <dev/usb/usb_util.h> 72 73 #include <dev/usb/usb_controller.h> 74 #include <dev/usb/usb_bus.h> 75 #endif /* USB_GLOBAL_INCLUDE_FILE */ 76 77 #include <dev/usb/controller/ohci.h> 78 #include <dev/usb/controller/ohcireg.h> 79 80 #define OHCI_BUS2SC(bus) \ 81 __containerof(bus, ohci_softc_t, sc_bus) 82 83 #ifdef USB_DEBUG 84 static int ohcidebug = 0; 85 86 static SYSCTL_NODE(_hw_usb, OID_AUTO, ohci, CTLFLAG_RW | CTLFLAG_MPSAFE, 0, 87 "USB ohci"); 88 SYSCTL_INT(_hw_usb_ohci, OID_AUTO, debug, CTLFLAG_RWTUN, 89 &ohcidebug, 0, "ohci debug level"); 90 91 static void ohci_dumpregs(ohci_softc_t *); 92 static void ohci_dump_tds(ohci_td_t *); 93 static uint8_t ohci_dump_td(ohci_td_t *); 94 static void ohci_dump_ed(ohci_ed_t *); 95 static uint8_t ohci_dump_itd(ohci_itd_t *); 96 static void ohci_dump_itds(ohci_itd_t *); 97 98 #endif 99 100 #define OBARR(sc) bus_space_barrier((sc)->sc_io_tag, (sc)->sc_io_hdl, 0, (sc)->sc_io_size, \ 101 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 102 #define OWRITE1(sc, r, x) \ 103 do { OBARR(sc); bus_space_write_1((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); } while (0) 104 #define OWRITE2(sc, r, x) \ 105 do { OBARR(sc); bus_space_write_2((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); } while (0) 106 #define OWRITE4(sc, r, x) \ 107 do { OBARR(sc); bus_space_write_4((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); } while (0) 108 #define OREAD1(sc, r) (OBARR(sc), bus_space_read_1((sc)->sc_io_tag, (sc)->sc_io_hdl, (r))) 109 #define OREAD2(sc, r) (OBARR(sc), bus_space_read_2((sc)->sc_io_tag, (sc)->sc_io_hdl, (r))) 110 #define OREAD4(sc, r) (OBARR(sc), bus_space_read_4((sc)->sc_io_tag, (sc)->sc_io_hdl, (r))) 111 112 #define OHCI_INTR_ENDPT 1 113 114 static const struct usb_bus_methods ohci_bus_methods; 115 static const struct usb_pipe_methods ohci_device_bulk_methods; 116 static const struct usb_pipe_methods ohci_device_ctrl_methods; 117 static const struct usb_pipe_methods ohci_device_intr_methods; 118 static const struct usb_pipe_methods ohci_device_isoc_methods; 119 120 static void ohci_do_poll(struct usb_bus *bus); 121 static void ohci_device_done(struct usb_xfer *xfer, usb_error_t error); 122 static void ohci_timeout(void *arg); 123 static uint8_t ohci_check_transfer(struct usb_xfer *xfer); 124 static void ohci_root_intr(ohci_softc_t *sc); 125 126 struct ohci_std_temp { 127 struct usb_page_cache *pc; 128 ohci_td_t *td; 129 ohci_td_t *td_next; 130 uint32_t average; 131 uint32_t td_flags; 132 uint32_t len; 133 uint16_t max_frame_size; 134 uint8_t shortpkt; 135 uint8_t setup_alt_next; 136 uint8_t last_frame; 137 }; 138 139 static struct ohci_hcca * 140 ohci_get_hcca(ohci_softc_t *sc) 141 { 142 usb_pc_cpu_invalidate(&sc->sc_hw.hcca_pc); 143 return (sc->sc_hcca_p); 144 } 145 146 void 147 ohci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb) 148 { 149 struct ohci_softc *sc = OHCI_BUS2SC(bus); 150 uint32_t i; 151 152 cb(bus, &sc->sc_hw.hcca_pc, &sc->sc_hw.hcca_pg, 153 sizeof(ohci_hcca_t), OHCI_HCCA_ALIGN); 154 155 cb(bus, &sc->sc_hw.ctrl_start_pc, &sc->sc_hw.ctrl_start_pg, 156 sizeof(ohci_ed_t), OHCI_ED_ALIGN); 157 158 cb(bus, &sc->sc_hw.bulk_start_pc, &sc->sc_hw.bulk_start_pg, 159 sizeof(ohci_ed_t), OHCI_ED_ALIGN); 160 161 cb(bus, &sc->sc_hw.isoc_start_pc, &sc->sc_hw.isoc_start_pg, 162 sizeof(ohci_ed_t), OHCI_ED_ALIGN); 163 164 for (i = 0; i != OHCI_NO_EDS; i++) { 165 cb(bus, sc->sc_hw.intr_start_pc + i, sc->sc_hw.intr_start_pg + i, 166 sizeof(ohci_ed_t), OHCI_ED_ALIGN); 167 } 168 } 169 170 static usb_error_t 171 ohci_controller_init(ohci_softc_t *sc, int do_suspend) 172 { 173 struct usb_page_search buf_res; 174 uint32_t i; 175 uint32_t ctl; 176 uint32_t ival; 177 uint32_t hcr; 178 uint32_t fm; 179 uint32_t per; 180 uint32_t desca; 181 182 /* Determine in what context we are running. */ 183 ctl = OREAD4(sc, OHCI_CONTROL); 184 if (ctl & OHCI_IR) { 185 /* SMM active, request change */ 186 DPRINTF("SMM active, request owner change\n"); 187 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_OCR); 188 for (i = 0; (i < 100) && (ctl & OHCI_IR); i++) { 189 usb_pause_mtx(NULL, hz / 1000); 190 ctl = OREAD4(sc, OHCI_CONTROL); 191 } 192 if (ctl & OHCI_IR) { 193 device_printf(sc->sc_bus.bdev, 194 "SMM does not respond, resetting\n"); 195 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 196 goto reset; 197 } 198 } else { 199 DPRINTF("cold started\n"); 200 reset: 201 /* controller was cold started */ 202 usb_pause_mtx(NULL, 203 USB_MS_TO_TICKS(USB_BUS_RESET_DELAY)); 204 } 205 206 /* 207 * This reset should not be necessary according to the OHCI spec, but 208 * without it some controllers do not start. 209 */ 210 DPRINTF("%s: resetting\n", device_get_nameunit(sc->sc_bus.bdev)); 211 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 212 213 usb_pause_mtx(NULL, 214 USB_MS_TO_TICKS(USB_BUS_RESET_DELAY)); 215 216 /* we now own the host controller and the bus has been reset */ 217 ival = OHCI_GET_IVAL(OREAD4(sc, OHCI_FM_INTERVAL)); 218 219 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_HCR); /* Reset HC */ 220 /* nominal time for a reset is 10 us */ 221 for (i = 0; i < 10; i++) { 222 DELAY(10); 223 hcr = OREAD4(sc, OHCI_COMMAND_STATUS) & OHCI_HCR; 224 if (!hcr) { 225 break; 226 } 227 } 228 if (hcr) { 229 device_printf(sc->sc_bus.bdev, "reset timeout\n"); 230 return (USB_ERR_IOERROR); 231 } 232 #ifdef USB_DEBUG 233 if (ohcidebug > 15) { 234 ohci_dumpregs(sc); 235 } 236 #endif 237 238 if (do_suspend) { 239 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_SUSPEND); 240 return (USB_ERR_NORMAL_COMPLETION); 241 } 242 243 /* The controller is now in SUSPEND state, we have 2ms to finish. */ 244 245 /* set up HC registers */ 246 usbd_get_page(&sc->sc_hw.hcca_pc, 0, &buf_res); 247 OWRITE4(sc, OHCI_HCCA, buf_res.physaddr); 248 249 usbd_get_page(&sc->sc_hw.ctrl_start_pc, 0, &buf_res); 250 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, buf_res.physaddr); 251 252 usbd_get_page(&sc->sc_hw.bulk_start_pc, 0, &buf_res); 253 OWRITE4(sc, OHCI_BULK_HEAD_ED, buf_res.physaddr); 254 255 /* disable all interrupts and then switch on all desired interrupts */ 256 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 257 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_eintrs | OHCI_MIE); 258 /* switch on desired functional features */ 259 ctl = OREAD4(sc, OHCI_CONTROL); 260 ctl &= ~(OHCI_CBSR_MASK | OHCI_LES | OHCI_HCFS_MASK | OHCI_IR); 261 ctl |= OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE | 262 OHCI_RATIO_1_4 | OHCI_HCFS_OPERATIONAL; 263 /* And finally start it! */ 264 OWRITE4(sc, OHCI_CONTROL, ctl); 265 266 /* 267 * The controller is now OPERATIONAL. Set a some final 268 * registers that should be set earlier, but that the 269 * controller ignores when in the SUSPEND state. 270 */ 271 fm = (OREAD4(sc, OHCI_FM_INTERVAL) & OHCI_FIT) ^ OHCI_FIT; 272 fm |= OHCI_FSMPS(ival) | ival; 273 OWRITE4(sc, OHCI_FM_INTERVAL, fm); 274 per = OHCI_PERIODIC(ival); /* 90% periodic */ 275 OWRITE4(sc, OHCI_PERIODIC_START, per); 276 277 /* Fiddle the No OverCurrent Protection bit to avoid chip bug. */ 278 desca = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 279 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca | OHCI_NOCP); 280 OWRITE4(sc, OHCI_RH_STATUS, OHCI_LPSC); /* Enable port power */ 281 usb_pause_mtx(NULL, 282 USB_MS_TO_TICKS(OHCI_ENABLE_POWER_DELAY)); 283 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca); 284 285 /* 286 * The AMD756 requires a delay before re-reading the register, 287 * otherwise it will occasionally report 0 ports. 288 */ 289 sc->sc_noport = 0; 290 for (i = 0; (i < 10) && (sc->sc_noport == 0); i++) { 291 usb_pause_mtx(NULL, 292 USB_MS_TO_TICKS(OHCI_READ_DESC_DELAY)); 293 sc->sc_noport = OHCI_GET_NDP(OREAD4(sc, OHCI_RH_DESCRIPTOR_A)); 294 } 295 296 #ifdef USB_DEBUG 297 if (ohcidebug > 5) { 298 ohci_dumpregs(sc); 299 } 300 #endif 301 return (USB_ERR_NORMAL_COMPLETION); 302 } 303 304 static struct ohci_ed * 305 ohci_init_ed(struct usb_page_cache *pc) 306 { 307 struct usb_page_search buf_res; 308 struct ohci_ed *ed; 309 310 usbd_get_page(pc, 0, &buf_res); 311 312 ed = buf_res.buffer; 313 314 ed->ed_self = htole32(buf_res.physaddr); 315 ed->ed_flags = htole32(OHCI_ED_SKIP); 316 ed->page_cache = pc; 317 318 return (ed); 319 } 320 321 usb_error_t 322 ohci_init(ohci_softc_t *sc) 323 { 324 struct usb_page_search buf_res; 325 uint16_t i; 326 uint16_t bit; 327 uint16_t x; 328 uint16_t y; 329 330 DPRINTF("start\n"); 331 332 sc->sc_eintrs = OHCI_NORMAL_INTRS; 333 334 /* 335 * Setup all ED's 336 */ 337 338 sc->sc_ctrl_p_last = 339 ohci_init_ed(&sc->sc_hw.ctrl_start_pc); 340 341 sc->sc_bulk_p_last = 342 ohci_init_ed(&sc->sc_hw.bulk_start_pc); 343 344 sc->sc_isoc_p_last = 345 ohci_init_ed(&sc->sc_hw.isoc_start_pc); 346 347 for (i = 0; i != OHCI_NO_EDS; i++) { 348 sc->sc_intr_p_last[i] = 349 ohci_init_ed(sc->sc_hw.intr_start_pc + i); 350 } 351 352 /* 353 * the QHs are arranged to give poll intervals that are 354 * powers of 2 times 1ms 355 */ 356 bit = OHCI_NO_EDS / 2; 357 while (bit) { 358 x = bit; 359 while (x & bit) { 360 ohci_ed_t *ed_x; 361 ohci_ed_t *ed_y; 362 363 y = (x ^ bit) | (bit / 2); 364 365 /* 366 * the next QH has half the poll interval 367 */ 368 ed_x = sc->sc_intr_p_last[x]; 369 ed_y = sc->sc_intr_p_last[y]; 370 371 ed_x->next = NULL; 372 ed_x->ed_next = ed_y->ed_self; 373 374 x++; 375 } 376 bit >>= 1; 377 } 378 379 if (1) { 380 ohci_ed_t *ed_int; 381 ohci_ed_t *ed_isc; 382 383 ed_int = sc->sc_intr_p_last[0]; 384 ed_isc = sc->sc_isoc_p_last; 385 386 /* the last (1ms) QH */ 387 ed_int->next = ed_isc; 388 ed_int->ed_next = ed_isc->ed_self; 389 } 390 usbd_get_page(&sc->sc_hw.hcca_pc, 0, &buf_res); 391 392 sc->sc_hcca_p = buf_res.buffer; 393 394 /* 395 * Fill HCCA interrupt table. The bit reversal is to get 396 * the tree set up properly to spread the interrupts. 397 */ 398 for (i = 0; i != OHCI_NO_INTRS; i++) { 399 sc->sc_hcca_p->hcca_interrupt_table[i] = 400 sc->sc_intr_p_last[i | (OHCI_NO_EDS / 2)]->ed_self; 401 } 402 /* flush all cache into memory */ 403 404 usb_bus_mem_flush_all(&sc->sc_bus, &ohci_iterate_hw_softc); 405 406 /* set up the bus struct */ 407 sc->sc_bus.methods = &ohci_bus_methods; 408 409 usb_callout_init_mtx(&sc->sc_tmo_rhsc, &sc->sc_bus.bus_mtx, 0); 410 411 #ifdef USB_DEBUG 412 if (ohcidebug > 15) { 413 for (i = 0; i != OHCI_NO_EDS; i++) { 414 printf("ed#%d ", i); 415 ohci_dump_ed(sc->sc_intr_p_last[i]); 416 } 417 printf("iso "); 418 ohci_dump_ed(sc->sc_isoc_p_last); 419 } 420 #endif 421 422 sc->sc_bus.usbrev = USB_REV_1_0; 423 424 if (ohci_controller_init(sc, 0) != 0) 425 return (USB_ERR_INVAL); 426 427 /* catch any lost interrupts */ 428 ohci_do_poll(&sc->sc_bus); 429 return (USB_ERR_NORMAL_COMPLETION); 430 } 431 432 /* 433 * shut down the controller when the system is going down 434 */ 435 void 436 ohci_detach(struct ohci_softc *sc) 437 { 438 USB_BUS_LOCK(&sc->sc_bus); 439 440 usb_callout_stop(&sc->sc_tmo_rhsc); 441 442 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 443 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 444 445 USB_BUS_UNLOCK(&sc->sc_bus); 446 447 /* XXX let stray task complete */ 448 usb_pause_mtx(NULL, hz / 20); 449 450 usb_callout_drain(&sc->sc_tmo_rhsc); 451 } 452 453 static void 454 ohci_suspend(ohci_softc_t *sc) 455 { 456 DPRINTF("\n"); 457 458 #ifdef USB_DEBUG 459 if (ohcidebug > 2) 460 ohci_dumpregs(sc); 461 #endif 462 463 /* reset HC and leave it suspended */ 464 ohci_controller_init(sc, 1); 465 } 466 467 static void 468 ohci_resume(ohci_softc_t *sc) 469 { 470 DPRINTF("\n"); 471 472 #ifdef USB_DEBUG 473 if (ohcidebug > 2) 474 ohci_dumpregs(sc); 475 #endif 476 477 /* some broken BIOSes never initialize the Controller chip */ 478 ohci_controller_init(sc, 0); 479 480 /* catch any lost interrupts */ 481 ohci_do_poll(&sc->sc_bus); 482 } 483 484 #ifdef USB_DEBUG 485 static void 486 ohci_dumpregs(ohci_softc_t *sc) 487 { 488 struct ohci_hcca *hcca; 489 490 DPRINTF("ohci_dumpregs: rev=0x%08x control=0x%08x command=0x%08x\n", 491 OREAD4(sc, OHCI_REVISION), 492 OREAD4(sc, OHCI_CONTROL), 493 OREAD4(sc, OHCI_COMMAND_STATUS)); 494 DPRINTF(" intrstat=0x%08x intre=0x%08x intrd=0x%08x\n", 495 OREAD4(sc, OHCI_INTERRUPT_STATUS), 496 OREAD4(sc, OHCI_INTERRUPT_ENABLE), 497 OREAD4(sc, OHCI_INTERRUPT_DISABLE)); 498 DPRINTF(" hcca=0x%08x percur=0x%08x ctrlhd=0x%08x\n", 499 OREAD4(sc, OHCI_HCCA), 500 OREAD4(sc, OHCI_PERIOD_CURRENT_ED), 501 OREAD4(sc, OHCI_CONTROL_HEAD_ED)); 502 DPRINTF(" ctrlcur=0x%08x bulkhd=0x%08x bulkcur=0x%08x\n", 503 OREAD4(sc, OHCI_CONTROL_CURRENT_ED), 504 OREAD4(sc, OHCI_BULK_HEAD_ED), 505 OREAD4(sc, OHCI_BULK_CURRENT_ED)); 506 DPRINTF(" done=0x%08x fmival=0x%08x fmrem=0x%08x\n", 507 OREAD4(sc, OHCI_DONE_HEAD), 508 OREAD4(sc, OHCI_FM_INTERVAL), 509 OREAD4(sc, OHCI_FM_REMAINING)); 510 DPRINTF(" fmnum=0x%08x perst=0x%08x lsthrs=0x%08x\n", 511 OREAD4(sc, OHCI_FM_NUMBER), 512 OREAD4(sc, OHCI_PERIODIC_START), 513 OREAD4(sc, OHCI_LS_THRESHOLD)); 514 DPRINTF(" desca=0x%08x descb=0x%08x stat=0x%08x\n", 515 OREAD4(sc, OHCI_RH_DESCRIPTOR_A), 516 OREAD4(sc, OHCI_RH_DESCRIPTOR_B), 517 OREAD4(sc, OHCI_RH_STATUS)); 518 DPRINTF(" port1=0x%08x port2=0x%08x\n", 519 OREAD4(sc, OHCI_RH_PORT_STATUS(1)), 520 OREAD4(sc, OHCI_RH_PORT_STATUS(2))); 521 522 hcca = ohci_get_hcca(sc); 523 524 DPRINTF(" HCCA: frame_number=0x%04x done_head=0x%08x\n", 525 le32toh(hcca->hcca_frame_number), 526 le32toh(hcca->hcca_done_head)); 527 } 528 static void 529 ohci_dump_tds(ohci_td_t *std) 530 { 531 for (; std; std = std->obj_next) { 532 if (ohci_dump_td(std)) { 533 break; 534 } 535 } 536 } 537 538 static uint8_t 539 ohci_dump_td(ohci_td_t *std) 540 { 541 uint32_t td_flags; 542 uint8_t temp; 543 544 usb_pc_cpu_invalidate(std->page_cache); 545 546 td_flags = le32toh(std->td_flags); 547 temp = (std->td_next == 0); 548 549 printf("TD(%p) at 0x%08x: %s%s%s%s%s delay=%d ec=%d " 550 "cc=%d\ncbp=0x%08x next=0x%08x be=0x%08x\n", 551 std, le32toh(std->td_self), 552 (td_flags & OHCI_TD_R) ? "-R" : "", 553 (td_flags & OHCI_TD_OUT) ? "-OUT" : "", 554 (td_flags & OHCI_TD_IN) ? "-IN" : "", 555 ((td_flags & OHCI_TD_TOGGLE_MASK) == OHCI_TD_TOGGLE_1) ? "-TOG1" : "", 556 ((td_flags & OHCI_TD_TOGGLE_MASK) == OHCI_TD_TOGGLE_0) ? "-TOG0" : "", 557 OHCI_TD_GET_DI(td_flags), 558 OHCI_TD_GET_EC(td_flags), 559 OHCI_TD_GET_CC(td_flags), 560 le32toh(std->td_cbp), 561 le32toh(std->td_next), 562 le32toh(std->td_be)); 563 564 return (temp); 565 } 566 567 static uint8_t 568 ohci_dump_itd(ohci_itd_t *sitd) 569 { 570 uint32_t itd_flags; 571 uint16_t i; 572 uint8_t temp; 573 574 usb_pc_cpu_invalidate(sitd->page_cache); 575 576 itd_flags = le32toh(sitd->itd_flags); 577 temp = (sitd->itd_next == 0); 578 579 printf("ITD(%p) at 0x%08x: sf=%d di=%d fc=%d cc=%d\n" 580 "bp0=0x%08x next=0x%08x be=0x%08x\n", 581 sitd, le32toh(sitd->itd_self), 582 OHCI_ITD_GET_SF(itd_flags), 583 OHCI_ITD_GET_DI(itd_flags), 584 OHCI_ITD_GET_FC(itd_flags), 585 OHCI_ITD_GET_CC(itd_flags), 586 le32toh(sitd->itd_bp0), 587 le32toh(sitd->itd_next), 588 le32toh(sitd->itd_be)); 589 for (i = 0; i < OHCI_ITD_NOFFSET; i++) { 590 printf("offs[%d]=0x%04x ", i, 591 (uint32_t)le16toh(sitd->itd_offset[i])); 592 } 593 printf("\n"); 594 595 return (temp); 596 } 597 598 static void 599 ohci_dump_itds(ohci_itd_t *sitd) 600 { 601 for (; sitd; sitd = sitd->obj_next) { 602 if (ohci_dump_itd(sitd)) { 603 break; 604 } 605 } 606 } 607 608 static void 609 ohci_dump_ed(ohci_ed_t *sed) 610 { 611 uint32_t ed_flags; 612 uint32_t ed_headp; 613 614 usb_pc_cpu_invalidate(sed->page_cache); 615 616 ed_flags = le32toh(sed->ed_flags); 617 ed_headp = le32toh(sed->ed_headp); 618 619 printf("ED(%p) at 0x%08x: addr=%d endpt=%d maxp=%d flags=%s%s%s%s%s\n" 620 "tailp=0x%08x headflags=%s%s headp=0x%08x nexted=0x%08x\n", 621 sed, le32toh(sed->ed_self), 622 OHCI_ED_GET_FA(ed_flags), 623 OHCI_ED_GET_EN(ed_flags), 624 OHCI_ED_GET_MAXP(ed_flags), 625 (ed_flags & OHCI_ED_DIR_OUT) ? "-OUT" : "", 626 (ed_flags & OHCI_ED_DIR_IN) ? "-IN" : "", 627 (ed_flags & OHCI_ED_SPEED) ? "-LOWSPEED" : "", 628 (ed_flags & OHCI_ED_SKIP) ? "-SKIP" : "", 629 (ed_flags & OHCI_ED_FORMAT_ISO) ? "-ISO" : "", 630 le32toh(sed->ed_tailp), 631 (ed_headp & OHCI_HALTED) ? "-HALTED" : "", 632 (ed_headp & OHCI_TOGGLECARRY) ? "-CARRY" : "", 633 le32toh(sed->ed_headp), 634 le32toh(sed->ed_next)); 635 } 636 637 #endif 638 639 static void 640 ohci_transfer_intr_enqueue(struct usb_xfer *xfer) 641 { 642 /* check for early completion */ 643 if (ohci_check_transfer(xfer)) { 644 return; 645 } 646 /* put transfer on interrupt queue */ 647 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 648 649 /* start timeout, if any */ 650 if (xfer->timeout != 0) { 651 usbd_transfer_timeout_ms(xfer, &ohci_timeout, xfer->timeout); 652 } 653 } 654 655 #define OHCI_APPEND_QH(sed,last) (last) = _ohci_append_qh(sed,last) 656 static ohci_ed_t * 657 _ohci_append_qh(ohci_ed_t *sed, ohci_ed_t *last) 658 { 659 DPRINTFN(11, "%p to %p\n", sed, last); 660 661 if (sed->prev != NULL) { 662 /* should not happen */ 663 DPRINTFN(0, "ED already linked!\n"); 664 return (last); 665 } 666 /* (sc->sc_bus.bus_mtx) must be locked */ 667 668 sed->next = last->next; 669 sed->ed_next = last->ed_next; 670 sed->ed_tailp = 0; 671 672 sed->prev = last; 673 674 usb_pc_cpu_flush(sed->page_cache); 675 676 /* 677 * the last->next->prev is never followed: sed->next->prev = sed; 678 */ 679 680 last->next = sed; 681 last->ed_next = sed->ed_self; 682 683 usb_pc_cpu_flush(last->page_cache); 684 685 return (sed); 686 } 687 688 #define OHCI_REMOVE_QH(sed,last) (last) = _ohci_remove_qh(sed,last) 689 static ohci_ed_t * 690 _ohci_remove_qh(ohci_ed_t *sed, ohci_ed_t *last) 691 { 692 DPRINTFN(11, "%p from %p\n", sed, last); 693 694 /* (sc->sc_bus.bus_mtx) must be locked */ 695 696 /* only remove if not removed from a queue */ 697 if (sed->prev) { 698 sed->prev->next = sed->next; 699 sed->prev->ed_next = sed->ed_next; 700 701 usb_pc_cpu_flush(sed->prev->page_cache); 702 703 if (sed->next) { 704 sed->next->prev = sed->prev; 705 usb_pc_cpu_flush(sed->next->page_cache); 706 } 707 last = ((last == sed) ? sed->prev : last); 708 709 sed->prev = 0; 710 711 usb_pc_cpu_flush(sed->page_cache); 712 } 713 return (last); 714 } 715 716 static void 717 ohci_isoc_done(struct usb_xfer *xfer) 718 { 719 uint8_t nframes; 720 uint32_t *plen = xfer->frlengths; 721 volatile uint16_t *olen; 722 uint16_t len = 0; 723 ohci_itd_t *td = xfer->td_transfer_first; 724 725 while (1) { 726 if (td == NULL) { 727 panic("%s:%d: out of TD's\n", 728 __FUNCTION__, __LINE__); 729 } 730 #ifdef USB_DEBUG 731 if (ohcidebug > 5) { 732 DPRINTF("isoc TD\n"); 733 ohci_dump_itd(td); 734 } 735 #endif 736 usb_pc_cpu_invalidate(td->page_cache); 737 738 nframes = td->frames; 739 olen = &td->itd_offset[0]; 740 741 if (nframes > 8) { 742 nframes = 8; 743 } 744 while (nframes--) { 745 len = le16toh(*olen); 746 747 if ((len >> 12) == OHCI_CC_NOT_ACCESSED) { 748 len = 0; 749 } else { 750 len &= ((1 << 12) - 1); 751 } 752 753 if (len > *plen) { 754 len = 0;/* invalid length */ 755 } 756 *plen = len; 757 plen++; 758 olen++; 759 } 760 761 if (((void *)td) == xfer->td_transfer_last) { 762 break; 763 } 764 td = td->obj_next; 765 } 766 767 xfer->aframes = xfer->nframes; 768 ohci_device_done(xfer, USB_ERR_NORMAL_COMPLETION); 769 } 770 771 #ifdef USB_DEBUG 772 static const char *const 773 ohci_cc_strs[] = 774 { 775 "NO_ERROR", 776 "CRC", 777 "BIT_STUFFING", 778 "DATA_TOGGLE_MISMATCH", 779 780 "STALL", 781 "DEVICE_NOT_RESPONDING", 782 "PID_CHECK_FAILURE", 783 "UNEXPECTED_PID", 784 785 "DATA_OVERRUN", 786 "DATA_UNDERRUN", 787 "BUFFER_OVERRUN", 788 "BUFFER_UNDERRUN", 789 790 "reserved", 791 "reserved", 792 "NOT_ACCESSED", 793 "NOT_ACCESSED" 794 }; 795 796 #endif 797 798 static usb_error_t 799 ohci_non_isoc_done_sub(struct usb_xfer *xfer) 800 { 801 ohci_td_t *td; 802 ohci_td_t *td_alt_next; 803 uint32_t temp; 804 uint32_t phy_start; 805 uint32_t phy_end; 806 uint32_t td_flags; 807 uint16_t cc; 808 809 td = xfer->td_transfer_cache; 810 td_alt_next = td->alt_next; 811 td_flags = 0; 812 813 if (xfer->aframes != xfer->nframes) { 814 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0); 815 } 816 while (1) { 817 usb_pc_cpu_invalidate(td->page_cache); 818 phy_start = le32toh(td->td_cbp); 819 td_flags = le32toh(td->td_flags); 820 cc = OHCI_TD_GET_CC(td_flags); 821 822 if (phy_start) { 823 /* 824 * short transfer - compute the number of remaining 825 * bytes in the hardware buffer: 826 */ 827 phy_end = le32toh(td->td_be); 828 temp = (OHCI_PAGE(phy_start ^ phy_end) ? 829 (OHCI_PAGE_SIZE + 1) : 0x0001); 830 temp += OHCI_PAGE_OFFSET(phy_end); 831 temp -= OHCI_PAGE_OFFSET(phy_start); 832 833 if (temp > td->len) { 834 /* guard against corruption */ 835 cc = OHCI_CC_STALL; 836 } else if (xfer->aframes != xfer->nframes) { 837 /* 838 * Sum up total transfer length 839 * in "frlengths[]": 840 */ 841 xfer->frlengths[xfer->aframes] += td->len - temp; 842 } 843 } else { 844 if (xfer->aframes != xfer->nframes) { 845 /* transfer was complete */ 846 xfer->frlengths[xfer->aframes] += td->len; 847 } 848 } 849 /* Check for last transfer */ 850 if (((void *)td) == xfer->td_transfer_last) { 851 td = NULL; 852 break; 853 } 854 /* Check transfer status */ 855 if (cc) { 856 /* the transfer is finished */ 857 td = NULL; 858 break; 859 } 860 /* Check for short transfer */ 861 if (phy_start) { 862 if (xfer->flags_int.short_frames_ok) { 863 /* follow alt next */ 864 td = td->alt_next; 865 } else { 866 /* the transfer is finished */ 867 td = NULL; 868 } 869 break; 870 } 871 td = td->obj_next; 872 873 if (td->alt_next != td_alt_next) { 874 /* this USB frame is complete */ 875 break; 876 } 877 } 878 879 /* update transfer cache */ 880 881 xfer->td_transfer_cache = td; 882 883 DPRINTFN(16, "error cc=%d (%s)\n", 884 cc, ohci_cc_strs[cc]); 885 886 return ((cc == 0) ? USB_ERR_NORMAL_COMPLETION : 887 (cc == OHCI_CC_STALL) ? USB_ERR_STALLED : USB_ERR_IOERROR); 888 } 889 890 static void 891 ohci_non_isoc_done(struct usb_xfer *xfer) 892 { 893 usb_error_t err = 0; 894 895 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 896 xfer, xfer->endpoint); 897 898 #ifdef USB_DEBUG 899 if (ohcidebug > 10) { 900 ohci_dump_tds(xfer->td_transfer_first); 901 } 902 #endif 903 904 /* reset scanner */ 905 906 xfer->td_transfer_cache = xfer->td_transfer_first; 907 908 if (xfer->flags_int.control_xfr) { 909 if (xfer->flags_int.control_hdr) { 910 err = ohci_non_isoc_done_sub(xfer); 911 } 912 xfer->aframes = 1; 913 914 if (xfer->td_transfer_cache == NULL) { 915 goto done; 916 } 917 } 918 while (xfer->aframes != xfer->nframes) { 919 err = ohci_non_isoc_done_sub(xfer); 920 xfer->aframes++; 921 922 if (xfer->td_transfer_cache == NULL) { 923 goto done; 924 } 925 } 926 927 if (xfer->flags_int.control_xfr && 928 !xfer->flags_int.control_act) { 929 err = ohci_non_isoc_done_sub(xfer); 930 } 931 done: 932 ohci_device_done(xfer, err); 933 } 934 935 /*------------------------------------------------------------------------* 936 * ohci_check_transfer_sub 937 *------------------------------------------------------------------------*/ 938 static void 939 ohci_check_transfer_sub(struct usb_xfer *xfer) 940 { 941 ohci_td_t *td; 942 ohci_ed_t *ed; 943 uint32_t phy_start; 944 uint32_t td_flags; 945 uint32_t td_next; 946 uint16_t cc; 947 948 td = xfer->td_transfer_cache; 949 950 while (1) { 951 usb_pc_cpu_invalidate(td->page_cache); 952 phy_start = le32toh(td->td_cbp); 953 td_flags = le32toh(td->td_flags); 954 td_next = le32toh(td->td_next); 955 956 /* Check for last transfer */ 957 if (((void *)td) == xfer->td_transfer_last) { 958 /* the transfer is finished */ 959 td = NULL; 960 break; 961 } 962 /* Check transfer status */ 963 cc = OHCI_TD_GET_CC(td_flags); 964 if (cc) { 965 /* the transfer is finished */ 966 td = NULL; 967 break; 968 } 969 /* 970 * Check if we reached the last packet 971 * or if there is a short packet: 972 */ 973 974 if (((td_next & (~0xF)) == OHCI_TD_NEXT_END) || phy_start) { 975 /* follow alt next */ 976 td = td->alt_next; 977 break; 978 } 979 td = td->obj_next; 980 } 981 982 /* update transfer cache */ 983 984 xfer->td_transfer_cache = td; 985 986 if (td) { 987 ed = xfer->qh_start[xfer->flags_int.curr_dma_set]; 988 989 ed->ed_headp = td->td_self; 990 usb_pc_cpu_flush(ed->page_cache); 991 992 DPRINTFN(13, "xfer=%p following alt next\n", xfer); 993 994 /* 995 * Make sure that the OHCI re-scans the schedule by 996 * writing the BLF and CLF bits: 997 */ 998 999 if (xfer->xroot->udev->flags.self_suspended) { 1000 /* nothing to do */ 1001 } else if (xfer->endpoint->methods == &ohci_device_bulk_methods) { 1002 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1003 1004 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF); 1005 } else if (xfer->endpoint->methods == &ohci_device_ctrl_methods) { 1006 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1007 1008 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 1009 } 1010 } 1011 } 1012 1013 /*------------------------------------------------------------------------* 1014 * ohci_check_transfer 1015 * 1016 * Return values: 1017 * 0: USB transfer is not finished 1018 * Else: USB transfer is finished 1019 *------------------------------------------------------------------------*/ 1020 static uint8_t 1021 ohci_check_transfer(struct usb_xfer *xfer) 1022 { 1023 ohci_ed_t *ed; 1024 uint32_t ed_headp; 1025 uint32_t ed_tailp; 1026 1027 DPRINTFN(13, "xfer=%p checking transfer\n", xfer); 1028 1029 ed = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1030 1031 usb_pc_cpu_invalidate(ed->page_cache); 1032 ed_headp = le32toh(ed->ed_headp); 1033 ed_tailp = le32toh(ed->ed_tailp); 1034 1035 if ((ed_headp & OHCI_HALTED) || 1036 (((ed_headp ^ ed_tailp) & (~0xF)) == 0)) { 1037 if (xfer->endpoint->methods == &ohci_device_isoc_methods) { 1038 /* isochronous transfer */ 1039 ohci_isoc_done(xfer); 1040 } else { 1041 if (xfer->flags_int.short_frames_ok) { 1042 ohci_check_transfer_sub(xfer); 1043 if (xfer->td_transfer_cache) { 1044 /* not finished yet */ 1045 return (0); 1046 } 1047 } 1048 /* store data-toggle */ 1049 if (ed_headp & OHCI_TOGGLECARRY) { 1050 xfer->endpoint->toggle_next = 1; 1051 } else { 1052 xfer->endpoint->toggle_next = 0; 1053 } 1054 1055 /* non-isochronous transfer */ 1056 ohci_non_isoc_done(xfer); 1057 } 1058 return (1); 1059 } 1060 DPRINTFN(13, "xfer=%p is still active\n", xfer); 1061 return (0); 1062 } 1063 1064 static void 1065 ohci_rhsc_enable(ohci_softc_t *sc) 1066 { 1067 DPRINTFN(5, "\n"); 1068 1069 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1070 1071 sc->sc_eintrs |= OHCI_RHSC; 1072 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_RHSC); 1073 1074 /* acknowledge any RHSC interrupt */ 1075 OWRITE4(sc, OHCI_INTERRUPT_STATUS, OHCI_RHSC); 1076 1077 ohci_root_intr(sc); 1078 } 1079 1080 static void 1081 ohci_interrupt_poll(ohci_softc_t *sc) 1082 { 1083 struct usb_xfer *xfer; 1084 1085 repeat: 1086 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 1087 /* 1088 * check if transfer is transferred 1089 */ 1090 if (ohci_check_transfer(xfer)) { 1091 /* queue has been modified */ 1092 goto repeat; 1093 } 1094 } 1095 } 1096 1097 /*------------------------------------------------------------------------* 1098 * ohci_interrupt - OHCI interrupt handler 1099 * 1100 * NOTE: Do not access "sc->sc_bus.bdev" inside the interrupt handler, 1101 * hence the interrupt handler will be setup before "sc->sc_bus.bdev" 1102 * is present ! 1103 *------------------------------------------------------------------------*/ 1104 void 1105 ohci_interrupt(ohci_softc_t *sc) 1106 { 1107 struct ohci_hcca *hcca; 1108 uint32_t status; 1109 uint32_t done; 1110 1111 USB_BUS_LOCK(&sc->sc_bus); 1112 1113 hcca = ohci_get_hcca(sc); 1114 1115 DPRINTFN(16, "real interrupt\n"); 1116 1117 #ifdef USB_DEBUG 1118 if (ohcidebug > 15) { 1119 ohci_dumpregs(sc); 1120 } 1121 #endif 1122 1123 done = le32toh(hcca->hcca_done_head); 1124 1125 /* 1126 * The LSb of done is used to inform the HC Driver that an interrupt 1127 * condition exists for both the Done list and for another event 1128 * recorded in HcInterruptStatus. On an interrupt from the HC, the 1129 * HC Driver checks the HccaDoneHead Value. If this value is 0, then 1130 * the interrupt was caused by other than the HccaDoneHead update 1131 * and the HcInterruptStatus register needs to be accessed to 1132 * determine that exact interrupt cause. If HccaDoneHead is nonzero, 1133 * then a Done list update interrupt is indicated and if the LSb of 1134 * done is nonzero, then an additional interrupt event is indicated 1135 * and HcInterruptStatus should be checked to determine its cause. 1136 */ 1137 if (done != 0) { 1138 status = 0; 1139 1140 if (done & ~OHCI_DONE_INTRS) { 1141 status |= OHCI_WDH; 1142 } 1143 if (done & OHCI_DONE_INTRS) { 1144 status |= OREAD4(sc, OHCI_INTERRUPT_STATUS); 1145 } 1146 hcca->hcca_done_head = 0; 1147 1148 usb_pc_cpu_flush(&sc->sc_hw.hcca_pc); 1149 } else { 1150 status = OREAD4(sc, OHCI_INTERRUPT_STATUS) & ~OHCI_WDH; 1151 } 1152 1153 status &= ~OHCI_MIE; 1154 if (status == 0) { 1155 /* 1156 * nothing to be done (PCI shared 1157 * interrupt) 1158 */ 1159 goto done; 1160 } 1161 OWRITE4(sc, OHCI_INTERRUPT_STATUS, status); /* Acknowledge */ 1162 1163 status &= sc->sc_eintrs; 1164 if (status == 0) { 1165 goto done; 1166 } 1167 if (status & (OHCI_SO | OHCI_RD | OHCI_UE | OHCI_RHSC)) { 1168 #if 0 1169 if (status & OHCI_SO) { 1170 /* XXX do what */ 1171 } 1172 #endif 1173 if (status & OHCI_RD) { 1174 printf("%s: resume detect\n", __FUNCTION__); 1175 /* XXX process resume detect */ 1176 } 1177 if (status & OHCI_UE) { 1178 printf("%s: unrecoverable error, " 1179 "controller halted\n", __FUNCTION__); 1180 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 1181 /* XXX what else */ 1182 } 1183 if (status & OHCI_RHSC) { 1184 /* 1185 * Disable RHSC interrupt for now, because it will be 1186 * on until the port has been reset. 1187 */ 1188 sc->sc_eintrs &= ~OHCI_RHSC; 1189 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_RHSC); 1190 1191 ohci_root_intr(sc); 1192 1193 /* do not allow RHSC interrupts > 1 per second */ 1194 usb_callout_reset(&sc->sc_tmo_rhsc, hz, 1195 (void *)&ohci_rhsc_enable, sc); 1196 } 1197 } 1198 status &= ~(OHCI_RHSC | OHCI_WDH | OHCI_SO); 1199 if (status != 0) { 1200 /* Block unprocessed interrupts. XXX */ 1201 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, status); 1202 sc->sc_eintrs &= ~status; 1203 printf("%s: blocking intrs 0x%x\n", 1204 __FUNCTION__, status); 1205 } 1206 /* poll all the USB transfers */ 1207 ohci_interrupt_poll(sc); 1208 1209 done: 1210 USB_BUS_UNLOCK(&sc->sc_bus); 1211 } 1212 1213 /* 1214 * called when a request does not complete 1215 */ 1216 static void 1217 ohci_timeout(void *arg) 1218 { 1219 struct usb_xfer *xfer = arg; 1220 1221 DPRINTF("xfer=%p\n", xfer); 1222 1223 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1224 1225 /* transfer is transferred */ 1226 ohci_device_done(xfer, USB_ERR_TIMEOUT); 1227 } 1228 1229 static void 1230 ohci_do_poll(struct usb_bus *bus) 1231 { 1232 struct ohci_softc *sc = OHCI_BUS2SC(bus); 1233 1234 USB_BUS_LOCK(&sc->sc_bus); 1235 ohci_interrupt_poll(sc); 1236 USB_BUS_UNLOCK(&sc->sc_bus); 1237 } 1238 1239 static void 1240 ohci_setup_standard_chain_sub(struct ohci_std_temp *temp) 1241 { 1242 struct usb_page_search buf_res; 1243 ohci_td_t *td; 1244 ohci_td_t *td_next; 1245 ohci_td_t *td_alt_next; 1246 uint32_t buf_offset; 1247 uint32_t average; 1248 uint32_t len_old; 1249 uint8_t shortpkt_old; 1250 uint8_t precompute; 1251 1252 td_alt_next = NULL; 1253 buf_offset = 0; 1254 shortpkt_old = temp->shortpkt; 1255 len_old = temp->len; 1256 precompute = 1; 1257 1258 /* software is used to detect short incoming transfers */ 1259 1260 if ((temp->td_flags & htole32(OHCI_TD_DP_MASK)) == htole32(OHCI_TD_IN)) { 1261 temp->td_flags |= htole32(OHCI_TD_R); 1262 } else { 1263 temp->td_flags &= ~htole32(OHCI_TD_R); 1264 } 1265 1266 restart: 1267 1268 td = temp->td; 1269 td_next = temp->td_next; 1270 1271 while (1) { 1272 if (temp->len == 0) { 1273 if (temp->shortpkt) { 1274 break; 1275 } 1276 /* send a Zero Length Packet, ZLP, last */ 1277 1278 temp->shortpkt = 1; 1279 average = 0; 1280 1281 } else { 1282 average = temp->average; 1283 1284 if (temp->len < average) { 1285 if (temp->len % temp->max_frame_size) { 1286 temp->shortpkt = 1; 1287 } 1288 average = temp->len; 1289 } 1290 } 1291 1292 if (td_next == NULL) { 1293 panic("%s: out of OHCI transfer descriptors!", __FUNCTION__); 1294 } 1295 /* get next TD */ 1296 1297 td = td_next; 1298 td_next = td->obj_next; 1299 1300 /* check if we are pre-computing */ 1301 1302 if (precompute) { 1303 /* update remaining length */ 1304 1305 temp->len -= average; 1306 1307 continue; 1308 } 1309 /* fill out current TD */ 1310 td->td_flags = temp->td_flags; 1311 1312 /* the next TD uses TOGGLE_CARRY */ 1313 temp->td_flags &= ~htole32(OHCI_TD_TOGGLE_MASK); 1314 1315 if (average == 0) { 1316 /* 1317 * The buffer start and end phys addresses should be 1318 * 0x0 for a zero length packet. 1319 */ 1320 td->td_cbp = 0; 1321 td->td_be = 0; 1322 td->len = 0; 1323 1324 } else { 1325 usbd_get_page(temp->pc, buf_offset, &buf_res); 1326 td->td_cbp = htole32(buf_res.physaddr); 1327 buf_offset += (average - 1); 1328 1329 usbd_get_page(temp->pc, buf_offset, &buf_res); 1330 td->td_be = htole32(buf_res.physaddr); 1331 buf_offset++; 1332 1333 td->len = average; 1334 1335 /* update remaining length */ 1336 1337 temp->len -= average; 1338 } 1339 1340 if ((td_next == td_alt_next) && temp->setup_alt_next) { 1341 /* we need to receive these frames one by one ! */ 1342 td->td_flags &= htole32(~OHCI_TD_INTR_MASK); 1343 td->td_flags |= htole32(OHCI_TD_SET_DI(1)); 1344 td->td_next = htole32(OHCI_TD_NEXT_END); 1345 } else { 1346 if (td_next) { 1347 /* link the current TD with the next one */ 1348 td->td_next = td_next->td_self; 1349 } 1350 } 1351 1352 td->alt_next = td_alt_next; 1353 1354 usb_pc_cpu_flush(td->page_cache); 1355 } 1356 1357 if (precompute) { 1358 precompute = 0; 1359 1360 /* setup alt next pointer, if any */ 1361 if (temp->last_frame) { 1362 /* no alternate next */ 1363 td_alt_next = NULL; 1364 } else { 1365 /* we use this field internally */ 1366 td_alt_next = td_next; 1367 } 1368 1369 /* restore */ 1370 temp->shortpkt = shortpkt_old; 1371 temp->len = len_old; 1372 goto restart; 1373 } 1374 temp->td = td; 1375 temp->td_next = td_next; 1376 } 1377 1378 static void 1379 ohci_setup_standard_chain(struct usb_xfer *xfer, ohci_ed_t **ed_last) 1380 { 1381 struct ohci_std_temp temp; 1382 const struct usb_pipe_methods *methods; 1383 ohci_ed_t *ed; 1384 ohci_td_t *td; 1385 uint32_t ed_flags; 1386 uint32_t x; 1387 1388 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 1389 xfer->address, UE_GET_ADDR(xfer->endpointno), 1390 xfer->sumlen, usbd_get_speed(xfer->xroot->udev)); 1391 1392 temp.average = xfer->max_hc_frame_size; 1393 temp.max_frame_size = xfer->max_frame_size; 1394 1395 /* toggle the DMA set we are using */ 1396 xfer->flags_int.curr_dma_set ^= 1; 1397 1398 /* get next DMA set */ 1399 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 1400 1401 xfer->td_transfer_first = td; 1402 xfer->td_transfer_cache = td; 1403 1404 temp.td = NULL; 1405 temp.td_next = td; 1406 temp.last_frame = 0; 1407 temp.setup_alt_next = xfer->flags_int.short_frames_ok; 1408 1409 methods = xfer->endpoint->methods; 1410 1411 /* check if we should prepend a setup message */ 1412 1413 if (xfer->flags_int.control_xfr) { 1414 if (xfer->flags_int.control_hdr) { 1415 temp.td_flags = htole32(OHCI_TD_SETUP | OHCI_TD_NOCC | 1416 OHCI_TD_TOGGLE_0 | OHCI_TD_NOINTR); 1417 1418 temp.len = xfer->frlengths[0]; 1419 temp.pc = xfer->frbuffers + 0; 1420 temp.shortpkt = temp.len ? 1 : 0; 1421 /* check for last frame */ 1422 if (xfer->nframes == 1) { 1423 /* no STATUS stage yet, SETUP is last */ 1424 if (xfer->flags_int.control_act) { 1425 temp.last_frame = 1; 1426 temp.setup_alt_next = 0; 1427 } 1428 } 1429 ohci_setup_standard_chain_sub(&temp); 1430 1431 /* 1432 * XXX assume that the setup message is 1433 * contained within one USB packet: 1434 */ 1435 xfer->endpoint->toggle_next = 1; 1436 } 1437 x = 1; 1438 } else { 1439 x = 0; 1440 } 1441 temp.td_flags = htole32(OHCI_TD_NOCC | OHCI_TD_NOINTR); 1442 1443 /* set data toggle */ 1444 1445 if (xfer->endpoint->toggle_next) { 1446 temp.td_flags |= htole32(OHCI_TD_TOGGLE_1); 1447 } else { 1448 temp.td_flags |= htole32(OHCI_TD_TOGGLE_0); 1449 } 1450 1451 /* set endpoint direction */ 1452 1453 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) { 1454 temp.td_flags |= htole32(OHCI_TD_IN); 1455 } else { 1456 temp.td_flags |= htole32(OHCI_TD_OUT); 1457 } 1458 1459 while (x != xfer->nframes) { 1460 /* DATA0 / DATA1 message */ 1461 1462 temp.len = xfer->frlengths[x]; 1463 temp.pc = xfer->frbuffers + x; 1464 1465 x++; 1466 1467 if (x == xfer->nframes) { 1468 if (xfer->flags_int.control_xfr) { 1469 /* no STATUS stage yet, DATA is last */ 1470 if (xfer->flags_int.control_act) { 1471 temp.last_frame = 1; 1472 temp.setup_alt_next = 0; 1473 } 1474 } else { 1475 temp.last_frame = 1; 1476 temp.setup_alt_next = 0; 1477 } 1478 } 1479 if (temp.len == 0) { 1480 /* make sure that we send an USB packet */ 1481 1482 temp.shortpkt = 0; 1483 1484 } else { 1485 /* regular data transfer */ 1486 1487 temp.shortpkt = (xfer->flags.force_short_xfer) ? 0 : 1; 1488 } 1489 1490 ohci_setup_standard_chain_sub(&temp); 1491 } 1492 1493 /* check if we should append a status stage */ 1494 1495 if (xfer->flags_int.control_xfr && 1496 !xfer->flags_int.control_act) { 1497 /* 1498 * Send a DATA1 message and invert the current endpoint 1499 * direction. 1500 */ 1501 1502 /* set endpoint direction and data toggle */ 1503 1504 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) { 1505 temp.td_flags = htole32(OHCI_TD_OUT | 1506 OHCI_TD_NOCC | OHCI_TD_TOGGLE_1 | OHCI_TD_SET_DI(1)); 1507 } else { 1508 temp.td_flags = htole32(OHCI_TD_IN | 1509 OHCI_TD_NOCC | OHCI_TD_TOGGLE_1 | OHCI_TD_SET_DI(1)); 1510 } 1511 1512 temp.len = 0; 1513 temp.pc = NULL; 1514 temp.shortpkt = 0; 1515 temp.last_frame = 1; 1516 temp.setup_alt_next = 0; 1517 1518 ohci_setup_standard_chain_sub(&temp); 1519 } 1520 td = temp.td; 1521 1522 /* Ensure that last TD is terminating: */ 1523 td->td_next = htole32(OHCI_TD_NEXT_END); 1524 td->td_flags &= ~htole32(OHCI_TD_INTR_MASK); 1525 td->td_flags |= htole32(OHCI_TD_SET_DI(1)); 1526 1527 usb_pc_cpu_flush(td->page_cache); 1528 1529 /* must have at least one frame! */ 1530 1531 xfer->td_transfer_last = td; 1532 1533 #ifdef USB_DEBUG 1534 if (ohcidebug > 8) { 1535 DPRINTF("nexttog=%d; data before transfer:\n", 1536 xfer->endpoint->toggle_next); 1537 ohci_dump_tds(xfer->td_transfer_first); 1538 } 1539 #endif 1540 1541 ed = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1542 1543 ed_flags = (OHCI_ED_SET_FA(xfer->address) | 1544 OHCI_ED_SET_EN(UE_GET_ADDR(xfer->endpointno)) | 1545 OHCI_ED_SET_MAXP(xfer->max_frame_size)); 1546 1547 ed_flags |= (OHCI_ED_FORMAT_GEN | OHCI_ED_DIR_TD); 1548 1549 if (xfer->xroot->udev->speed == USB_SPEED_LOW) { 1550 ed_flags |= OHCI_ED_SPEED; 1551 } 1552 ed->ed_flags = htole32(ed_flags); 1553 1554 td = xfer->td_transfer_first; 1555 1556 ed->ed_headp = td->td_self; 1557 1558 if (xfer->xroot->udev->flags.self_suspended == 0) { 1559 /* the append function will flush the endpoint descriptor */ 1560 OHCI_APPEND_QH(ed, *ed_last); 1561 1562 if (methods == &ohci_device_bulk_methods) { 1563 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1564 1565 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF); 1566 } 1567 if (methods == &ohci_device_ctrl_methods) { 1568 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1569 1570 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 1571 } 1572 } else { 1573 usb_pc_cpu_flush(ed->page_cache); 1574 } 1575 } 1576 1577 static void 1578 ohci_root_intr(ohci_softc_t *sc) 1579 { 1580 uint32_t hstatus __usbdebug_used; 1581 uint16_t i; 1582 uint16_t m; 1583 1584 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1585 1586 /* clear any old interrupt data */ 1587 memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata)); 1588 1589 hstatus = OREAD4(sc, OHCI_RH_STATUS); 1590 DPRINTF("sc=%p hstatus=0x%08x\n", 1591 sc, hstatus); 1592 1593 /* set bits */ 1594 m = (sc->sc_noport + 1); 1595 if (m > (8 * sizeof(sc->sc_hub_idata))) { 1596 m = (8 * sizeof(sc->sc_hub_idata)); 1597 } 1598 for (i = 1; i < m; i++) { 1599 /* pick out CHANGE bits from the status register */ 1600 if (OREAD4(sc, OHCI_RH_PORT_STATUS(i)) >> 16) { 1601 sc->sc_hub_idata[i / 8] |= 1 << (i % 8); 1602 DPRINTF("port %d changed\n", i); 1603 } 1604 } 1605 1606 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 1607 sizeof(sc->sc_hub_idata)); 1608 } 1609 1610 /* NOTE: "done" can be run two times in a row, 1611 * from close and from interrupt 1612 */ 1613 static void 1614 ohci_device_done(struct usb_xfer *xfer, usb_error_t error) 1615 { 1616 const struct usb_pipe_methods *methods = xfer->endpoint->methods; 1617 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1618 ohci_ed_t *ed; 1619 1620 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1621 1622 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n", 1623 xfer, xfer->endpoint, error); 1624 1625 ed = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1626 if (ed) { 1627 usb_pc_cpu_invalidate(ed->page_cache); 1628 } 1629 if (methods == &ohci_device_bulk_methods) { 1630 OHCI_REMOVE_QH(ed, sc->sc_bulk_p_last); 1631 } 1632 if (methods == &ohci_device_ctrl_methods) { 1633 OHCI_REMOVE_QH(ed, sc->sc_ctrl_p_last); 1634 } 1635 if (methods == &ohci_device_intr_methods) { 1636 OHCI_REMOVE_QH(ed, sc->sc_intr_p_last[xfer->qh_pos]); 1637 } 1638 if (methods == &ohci_device_isoc_methods) { 1639 OHCI_REMOVE_QH(ed, sc->sc_isoc_p_last); 1640 } 1641 xfer->td_transfer_first = NULL; 1642 xfer->td_transfer_last = NULL; 1643 1644 /* dequeue transfer and start next transfer */ 1645 usbd_transfer_done(xfer, error); 1646 } 1647 1648 /*------------------------------------------------------------------------* 1649 * ohci bulk support 1650 *------------------------------------------------------------------------*/ 1651 static void 1652 ohci_device_bulk_open(struct usb_xfer *xfer) 1653 { 1654 return; 1655 } 1656 1657 static void 1658 ohci_device_bulk_close(struct usb_xfer *xfer) 1659 { 1660 ohci_device_done(xfer, USB_ERR_CANCELLED); 1661 } 1662 1663 static void 1664 ohci_device_bulk_enter(struct usb_xfer *xfer) 1665 { 1666 return; 1667 } 1668 1669 static void 1670 ohci_device_bulk_start(struct usb_xfer *xfer) 1671 { 1672 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1673 1674 /* setup TD's and QH */ 1675 ohci_setup_standard_chain(xfer, &sc->sc_bulk_p_last); 1676 1677 /* put transfer on interrupt queue */ 1678 ohci_transfer_intr_enqueue(xfer); 1679 } 1680 1681 static const struct usb_pipe_methods ohci_device_bulk_methods = 1682 { 1683 .open = ohci_device_bulk_open, 1684 .close = ohci_device_bulk_close, 1685 .enter = ohci_device_bulk_enter, 1686 .start = ohci_device_bulk_start, 1687 }; 1688 1689 /*------------------------------------------------------------------------* 1690 * ohci control support 1691 *------------------------------------------------------------------------*/ 1692 static void 1693 ohci_device_ctrl_open(struct usb_xfer *xfer) 1694 { 1695 return; 1696 } 1697 1698 static void 1699 ohci_device_ctrl_close(struct usb_xfer *xfer) 1700 { 1701 ohci_device_done(xfer, USB_ERR_CANCELLED); 1702 } 1703 1704 static void 1705 ohci_device_ctrl_enter(struct usb_xfer *xfer) 1706 { 1707 return; 1708 } 1709 1710 static void 1711 ohci_device_ctrl_start(struct usb_xfer *xfer) 1712 { 1713 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1714 1715 /* setup TD's and QH */ 1716 ohci_setup_standard_chain(xfer, &sc->sc_ctrl_p_last); 1717 1718 /* put transfer on interrupt queue */ 1719 ohci_transfer_intr_enqueue(xfer); 1720 } 1721 1722 static const struct usb_pipe_methods ohci_device_ctrl_methods = 1723 { 1724 .open = ohci_device_ctrl_open, 1725 .close = ohci_device_ctrl_close, 1726 .enter = ohci_device_ctrl_enter, 1727 .start = ohci_device_ctrl_start, 1728 }; 1729 1730 /*------------------------------------------------------------------------* 1731 * ohci interrupt support 1732 *------------------------------------------------------------------------*/ 1733 static void 1734 ohci_device_intr_open(struct usb_xfer *xfer) 1735 { 1736 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1737 uint16_t best; 1738 uint16_t bit; 1739 uint16_t x; 1740 1741 best = 0; 1742 bit = OHCI_NO_EDS / 2; 1743 while (bit) { 1744 if (xfer->interval >= bit) { 1745 x = bit; 1746 best = bit; 1747 while (x & bit) { 1748 if (sc->sc_intr_stat[x] < 1749 sc->sc_intr_stat[best]) { 1750 best = x; 1751 } 1752 x++; 1753 } 1754 break; 1755 } 1756 bit >>= 1; 1757 } 1758 1759 sc->sc_intr_stat[best]++; 1760 xfer->qh_pos = best; 1761 1762 DPRINTFN(3, "best=%d interval=%d\n", 1763 best, xfer->interval); 1764 } 1765 1766 static void 1767 ohci_device_intr_close(struct usb_xfer *xfer) 1768 { 1769 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1770 1771 sc->sc_intr_stat[xfer->qh_pos]--; 1772 1773 ohci_device_done(xfer, USB_ERR_CANCELLED); 1774 } 1775 1776 static void 1777 ohci_device_intr_enter(struct usb_xfer *xfer) 1778 { 1779 return; 1780 } 1781 1782 static void 1783 ohci_device_intr_start(struct usb_xfer *xfer) 1784 { 1785 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1786 1787 /* setup TD's and QH */ 1788 ohci_setup_standard_chain(xfer, &sc->sc_intr_p_last[xfer->qh_pos]); 1789 1790 /* put transfer on interrupt queue */ 1791 ohci_transfer_intr_enqueue(xfer); 1792 } 1793 1794 static const struct usb_pipe_methods ohci_device_intr_methods = 1795 { 1796 .open = ohci_device_intr_open, 1797 .close = ohci_device_intr_close, 1798 .enter = ohci_device_intr_enter, 1799 .start = ohci_device_intr_start, 1800 }; 1801 1802 /*------------------------------------------------------------------------* 1803 * ohci isochronous support 1804 *------------------------------------------------------------------------*/ 1805 static void 1806 ohci_device_isoc_open(struct usb_xfer *xfer) 1807 { 1808 return; 1809 } 1810 1811 static void 1812 ohci_device_isoc_close(struct usb_xfer *xfer) 1813 { 1814 /**/ 1815 ohci_device_done(xfer, USB_ERR_CANCELLED); 1816 } 1817 1818 static void 1819 ohci_device_isoc_enter(struct usb_xfer *xfer) 1820 { 1821 struct usb_page_search buf_res; 1822 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1823 struct ohci_hcca *hcca; 1824 uint32_t buf_offset; 1825 uint32_t nframes; 1826 uint32_t startframe; 1827 uint32_t ed_flags; 1828 uint32_t *plen; 1829 uint16_t itd_offset[OHCI_ITD_NOFFSET]; 1830 uint16_t length; 1831 uint8_t ncur; 1832 ohci_itd_t *td; 1833 ohci_itd_t *td_last = NULL; 1834 ohci_ed_t *ed; 1835 1836 hcca = ohci_get_hcca(sc); 1837 1838 nframes = le32toh(hcca->hcca_frame_number); 1839 1840 DPRINTFN(6, "xfer=%p isoc_next=%u nframes=%u hcca_fn=%u\n", 1841 xfer, xfer->endpoint->isoc_next, xfer->nframes, nframes); 1842 1843 if (usbd_xfer_get_isochronous_start_frame( 1844 xfer, nframes, 0, 1, 0xFFFF, &startframe)) 1845 DPRINTFN(3, "start next=%d\n", startframe); 1846 1847 /* get the real number of frames */ 1848 1849 nframes = xfer->nframes; 1850 1851 buf_offset = 0; 1852 1853 plen = xfer->frlengths; 1854 1855 /* toggle the DMA set we are using */ 1856 xfer->flags_int.curr_dma_set ^= 1; 1857 1858 /* get next DMA set */ 1859 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 1860 1861 xfer->td_transfer_first = td; 1862 1863 ncur = 0; 1864 length = 0; 1865 1866 while (nframes--) { 1867 if (td == NULL) { 1868 panic("%s:%d: out of TD's\n", 1869 __FUNCTION__, __LINE__); 1870 } 1871 itd_offset[ncur] = length; 1872 buf_offset += *plen; 1873 length += *plen; 1874 plen++; 1875 ncur++; 1876 1877 if ( /* check if the ITD is full */ 1878 (ncur == OHCI_ITD_NOFFSET) || 1879 /* check if we have put more than 4K into the ITD */ 1880 (length & 0xF000) || 1881 /* check if it is the last frame */ 1882 (nframes == 0)) { 1883 /* fill current ITD */ 1884 td->itd_flags = htole32( 1885 OHCI_ITD_NOCC | 1886 OHCI_ITD_SET_SF(startframe) | 1887 OHCI_ITD_NOINTR | 1888 OHCI_ITD_SET_FC(ncur)); 1889 1890 td->frames = ncur; 1891 startframe += ncur; 1892 1893 if (length == 0) { 1894 /* all zero */ 1895 td->itd_bp0 = 0; 1896 td->itd_be = ~0; 1897 1898 while (ncur--) { 1899 td->itd_offset[ncur] = 1900 htole16(OHCI_ITD_MK_OFFS(0)); 1901 } 1902 } else { 1903 usbd_get_page(xfer->frbuffers, buf_offset - length, &buf_res); 1904 length = OHCI_PAGE_MASK(buf_res.physaddr); 1905 buf_res.physaddr = 1906 OHCI_PAGE(buf_res.physaddr); 1907 td->itd_bp0 = htole32(buf_res.physaddr); 1908 usbd_get_page(xfer->frbuffers, buf_offset - 1, &buf_res); 1909 td->itd_be = htole32(buf_res.physaddr); 1910 1911 while (ncur--) { 1912 itd_offset[ncur] += length; 1913 itd_offset[ncur] = 1914 OHCI_ITD_MK_OFFS(itd_offset[ncur]); 1915 td->itd_offset[ncur] = 1916 htole16(itd_offset[ncur]); 1917 } 1918 } 1919 ncur = 0; 1920 length = 0; 1921 td_last = td; 1922 td = td->obj_next; 1923 1924 if (td) { 1925 /* link the last TD with the next one */ 1926 td_last->itd_next = td->itd_self; 1927 } 1928 usb_pc_cpu_flush(td_last->page_cache); 1929 } 1930 } 1931 1932 /* update the last TD */ 1933 td_last->itd_flags &= ~htole32(OHCI_ITD_NOINTR); 1934 td_last->itd_flags |= htole32(OHCI_ITD_SET_DI(0)); 1935 td_last->itd_next = 0; 1936 1937 usb_pc_cpu_flush(td_last->page_cache); 1938 1939 xfer->td_transfer_last = td_last; 1940 1941 #ifdef USB_DEBUG 1942 if (ohcidebug > 8) { 1943 DPRINTF("data before transfer:\n"); 1944 ohci_dump_itds(xfer->td_transfer_first); 1945 } 1946 #endif 1947 ed = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1948 1949 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) 1950 ed_flags = (OHCI_ED_DIR_IN | OHCI_ED_FORMAT_ISO); 1951 else 1952 ed_flags = (OHCI_ED_DIR_OUT | OHCI_ED_FORMAT_ISO); 1953 1954 ed_flags |= (OHCI_ED_SET_FA(xfer->address) | 1955 OHCI_ED_SET_EN(UE_GET_ADDR(xfer->endpointno)) | 1956 OHCI_ED_SET_MAXP(xfer->max_frame_size)); 1957 1958 if (xfer->xroot->udev->speed == USB_SPEED_LOW) { 1959 ed_flags |= OHCI_ED_SPEED; 1960 } 1961 ed->ed_flags = htole32(ed_flags); 1962 1963 td = xfer->td_transfer_first; 1964 1965 ed->ed_headp = td->itd_self; 1966 1967 /* isochronous transfers are not affected by suspend / resume */ 1968 /* the append function will flush the endpoint descriptor */ 1969 1970 OHCI_APPEND_QH(ed, sc->sc_isoc_p_last); 1971 } 1972 1973 static void 1974 ohci_device_isoc_start(struct usb_xfer *xfer) 1975 { 1976 /* put transfer on interrupt queue */ 1977 ohci_transfer_intr_enqueue(xfer); 1978 } 1979 1980 static const struct usb_pipe_methods ohci_device_isoc_methods = 1981 { 1982 .open = ohci_device_isoc_open, 1983 .close = ohci_device_isoc_close, 1984 .enter = ohci_device_isoc_enter, 1985 .start = ohci_device_isoc_start, 1986 }; 1987 1988 /*------------------------------------------------------------------------* 1989 * ohci root control support 1990 *------------------------------------------------------------------------* 1991 * Simulate a hardware hub by handling all the necessary requests. 1992 *------------------------------------------------------------------------*/ 1993 1994 static const 1995 struct usb_device_descriptor ohci_devd = 1996 { 1997 sizeof(struct usb_device_descriptor), 1998 UDESC_DEVICE, /* type */ 1999 {0x00, 0x01}, /* USB version */ 2000 UDCLASS_HUB, /* class */ 2001 UDSUBCLASS_HUB, /* subclass */ 2002 UDPROTO_FSHUB, /* protocol */ 2003 64, /* max packet */ 2004 {0}, {0}, {0x00, 0x01}, /* device id */ 2005 1, 2, 0, /* string indexes */ 2006 1 /* # of configurations */ 2007 }; 2008 2009 static const 2010 struct ohci_config_desc ohci_confd = 2011 { 2012 .confd = { 2013 .bLength = sizeof(struct usb_config_descriptor), 2014 .bDescriptorType = UDESC_CONFIG, 2015 .wTotalLength[0] = sizeof(ohci_confd), 2016 .bNumInterface = 1, 2017 .bConfigurationValue = 1, 2018 .iConfiguration = 0, 2019 .bmAttributes = UC_SELF_POWERED, 2020 .bMaxPower = 0, /* max power */ 2021 }, 2022 .ifcd = { 2023 .bLength = sizeof(struct usb_interface_descriptor), 2024 .bDescriptorType = UDESC_INTERFACE, 2025 .bNumEndpoints = 1, 2026 .bInterfaceClass = UICLASS_HUB, 2027 .bInterfaceSubClass = UISUBCLASS_HUB, 2028 .bInterfaceProtocol = 0, 2029 }, 2030 .endpd = { 2031 .bLength = sizeof(struct usb_endpoint_descriptor), 2032 .bDescriptorType = UDESC_ENDPOINT, 2033 .bEndpointAddress = UE_DIR_IN | OHCI_INTR_ENDPT, 2034 .bmAttributes = UE_INTERRUPT, 2035 .wMaxPacketSize[0] = 32,/* max packet (255 ports) */ 2036 .bInterval = 255, 2037 }, 2038 }; 2039 2040 static const 2041 struct usb_hub_descriptor ohci_hubd = 2042 { 2043 .bDescLength = 0, /* dynamic length */ 2044 .bDescriptorType = UDESC_HUB, 2045 }; 2046 2047 static usb_error_t 2048 ohci_roothub_exec(struct usb_device *udev, 2049 struct usb_device_request *req, const void **pptr, uint16_t *plength) 2050 { 2051 ohci_softc_t *sc = OHCI_BUS2SC(udev->bus); 2052 const void *ptr; 2053 const char *str_ptr; 2054 uint32_t port; 2055 uint32_t v; 2056 uint16_t len; 2057 uint16_t value; 2058 uint16_t index; 2059 uint8_t l; 2060 usb_error_t err; 2061 2062 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2063 2064 /* buffer reset */ 2065 ptr = (const void *)&sc->sc_hub_desc.temp; 2066 len = 0; 2067 err = 0; 2068 2069 value = UGETW(req->wValue); 2070 index = UGETW(req->wIndex); 2071 2072 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x " 2073 "wValue=0x%04x wIndex=0x%04x\n", 2074 req->bmRequestType, req->bRequest, 2075 UGETW(req->wLength), value, index); 2076 2077 #define C(x,y) ((x) | ((y) << 8)) 2078 switch (C(req->bRequest, req->bmRequestType)) { 2079 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 2080 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 2081 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 2082 /* 2083 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 2084 * for the integrated root hub. 2085 */ 2086 break; 2087 case C(UR_GET_CONFIG, UT_READ_DEVICE): 2088 len = 1; 2089 sc->sc_hub_desc.temp[0] = sc->sc_conf; 2090 break; 2091 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2092 switch (value >> 8) { 2093 case UDESC_DEVICE: 2094 if ((value & 0xff) != 0) { 2095 err = USB_ERR_IOERROR; 2096 goto done; 2097 } 2098 len = sizeof(ohci_devd); 2099 ptr = (const void *)&ohci_devd; 2100 break; 2101 2102 case UDESC_CONFIG: 2103 if ((value & 0xff) != 0) { 2104 err = USB_ERR_IOERROR; 2105 goto done; 2106 } 2107 len = sizeof(ohci_confd); 2108 ptr = (const void *)&ohci_confd; 2109 break; 2110 2111 case UDESC_STRING: 2112 switch (value & 0xff) { 2113 case 0: /* Language table */ 2114 str_ptr = "\001"; 2115 break; 2116 2117 case 1: /* Vendor */ 2118 str_ptr = sc->sc_vendor; 2119 break; 2120 2121 case 2: /* Product */ 2122 str_ptr = "OHCI root HUB"; 2123 break; 2124 2125 default: 2126 str_ptr = ""; 2127 break; 2128 } 2129 2130 len = usb_make_str_desc( 2131 sc->sc_hub_desc.temp, 2132 sizeof(sc->sc_hub_desc.temp), 2133 str_ptr); 2134 break; 2135 2136 default: 2137 err = USB_ERR_IOERROR; 2138 goto done; 2139 } 2140 break; 2141 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2142 len = 1; 2143 sc->sc_hub_desc.temp[0] = 0; 2144 break; 2145 case C(UR_GET_STATUS, UT_READ_DEVICE): 2146 len = 2; 2147 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED); 2148 break; 2149 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2150 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2151 len = 2; 2152 USETW(sc->sc_hub_desc.stat.wStatus, 0); 2153 break; 2154 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2155 if (value >= OHCI_MAX_DEVICES) { 2156 err = USB_ERR_IOERROR; 2157 goto done; 2158 } 2159 sc->sc_addr = value; 2160 break; 2161 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2162 if ((value != 0) && (value != 1)) { 2163 err = USB_ERR_IOERROR; 2164 goto done; 2165 } 2166 sc->sc_conf = value; 2167 break; 2168 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2169 break; 2170 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2171 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2172 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2173 err = USB_ERR_IOERROR; 2174 goto done; 2175 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2176 break; 2177 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2178 break; 2179 /* Hub requests */ 2180 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2181 break; 2182 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2183 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE " 2184 "port=%d feature=%d\n", 2185 index, value); 2186 if ((index < 1) || 2187 (index > sc->sc_noport)) { 2188 err = USB_ERR_IOERROR; 2189 goto done; 2190 } 2191 port = OHCI_RH_PORT_STATUS(index); 2192 switch (value) { 2193 case UHF_PORT_ENABLE: 2194 OWRITE4(sc, port, UPS_CURRENT_CONNECT_STATUS); 2195 break; 2196 case UHF_PORT_SUSPEND: 2197 OWRITE4(sc, port, UPS_OVERCURRENT_INDICATOR); 2198 break; 2199 case UHF_PORT_POWER: 2200 /* Yes, writing to the LOW_SPEED bit clears power. */ 2201 OWRITE4(sc, port, UPS_LOW_SPEED); 2202 break; 2203 case UHF_C_PORT_CONNECTION: 2204 OWRITE4(sc, port, UPS_C_CONNECT_STATUS << 16); 2205 break; 2206 case UHF_C_PORT_ENABLE: 2207 OWRITE4(sc, port, UPS_C_PORT_ENABLED << 16); 2208 break; 2209 case UHF_C_PORT_SUSPEND: 2210 OWRITE4(sc, port, UPS_C_SUSPEND << 16); 2211 break; 2212 case UHF_C_PORT_OVER_CURRENT: 2213 OWRITE4(sc, port, UPS_C_OVERCURRENT_INDICATOR << 16); 2214 break; 2215 case UHF_C_PORT_RESET: 2216 OWRITE4(sc, port, UPS_C_PORT_RESET << 16); 2217 break; 2218 default: 2219 err = USB_ERR_IOERROR; 2220 goto done; 2221 } 2222 switch (value) { 2223 case UHF_C_PORT_CONNECTION: 2224 case UHF_C_PORT_ENABLE: 2225 case UHF_C_PORT_SUSPEND: 2226 case UHF_C_PORT_OVER_CURRENT: 2227 case UHF_C_PORT_RESET: 2228 /* enable RHSC interrupt if condition is cleared. */ 2229 if ((OREAD4(sc, port) >> 16) == 0) 2230 ohci_rhsc_enable(sc); 2231 break; 2232 default: 2233 break; 2234 } 2235 break; 2236 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2237 if ((value & 0xff) != 0) { 2238 err = USB_ERR_IOERROR; 2239 goto done; 2240 } 2241 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 2242 2243 sc->sc_hub_desc.hubd = ohci_hubd; 2244 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport; 2245 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, 2246 (v & OHCI_NPS ? UHD_PWR_NO_SWITCH : 2247 v & OHCI_PSM ? UHD_PWR_GANGED : UHD_PWR_INDIVIDUAL) 2248 /* XXX overcurrent */ 2249 ); 2250 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = OHCI_GET_POTPGT(v); 2251 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); 2252 2253 for (l = 0; l < sc->sc_noport; l++) { 2254 if (v & 1) { 2255 sc->sc_hub_desc.hubd.DeviceRemovable[l / 8] |= (1 << (l % 8)); 2256 } 2257 v >>= 1; 2258 } 2259 sc->sc_hub_desc.hubd.bDescLength = 2260 8 + ((sc->sc_noport + 7) / 8); 2261 len = sc->sc_hub_desc.hubd.bDescLength; 2262 break; 2263 2264 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2265 len = 16; 2266 memset(sc->sc_hub_desc.temp, 0, 16); 2267 break; 2268 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2269 DPRINTFN(9, "get port status i=%d\n", 2270 index); 2271 if ((index < 1) || 2272 (index > sc->sc_noport)) { 2273 err = USB_ERR_IOERROR; 2274 goto done; 2275 } 2276 v = OREAD4(sc, OHCI_RH_PORT_STATUS(index)); 2277 DPRINTFN(9, "port status=0x%04x\n", v); 2278 v &= ~UPS_PORT_MODE_DEVICE; /* force host mode */ 2279 USETW(sc->sc_hub_desc.ps.wPortStatus, v); 2280 USETW(sc->sc_hub_desc.ps.wPortChange, v >> 16); 2281 len = sizeof(sc->sc_hub_desc.ps); 2282 break; 2283 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2284 err = USB_ERR_IOERROR; 2285 goto done; 2286 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2287 break; 2288 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2289 if ((index < 1) || 2290 (index > sc->sc_noport)) { 2291 err = USB_ERR_IOERROR; 2292 goto done; 2293 } 2294 port = OHCI_RH_PORT_STATUS(index); 2295 switch (value) { 2296 case UHF_PORT_ENABLE: 2297 OWRITE4(sc, port, UPS_PORT_ENABLED); 2298 break; 2299 case UHF_PORT_SUSPEND: 2300 OWRITE4(sc, port, UPS_SUSPEND); 2301 break; 2302 case UHF_PORT_RESET: 2303 DPRINTFN(6, "reset port %d\n", index); 2304 OWRITE4(sc, port, UPS_RESET); 2305 for (v = 0;; v++) { 2306 if (v < 12) { 2307 usb_pause_mtx(&sc->sc_bus.bus_mtx, 2308 USB_MS_TO_TICKS(usb_port_root_reset_delay)); 2309 2310 if ((OREAD4(sc, port) & UPS_RESET) == 0) { 2311 break; 2312 } 2313 } else { 2314 err = USB_ERR_TIMEOUT; 2315 goto done; 2316 } 2317 } 2318 DPRINTFN(9, "ohci port %d reset, status = 0x%04x\n", 2319 index, OREAD4(sc, port)); 2320 break; 2321 case UHF_PORT_POWER: 2322 DPRINTFN(3, "set port power %d\n", index); 2323 OWRITE4(sc, port, UPS_PORT_POWER); 2324 break; 2325 default: 2326 err = USB_ERR_IOERROR; 2327 goto done; 2328 } 2329 break; 2330 default: 2331 err = USB_ERR_IOERROR; 2332 goto done; 2333 } 2334 done: 2335 *plength = len; 2336 *pptr = ptr; 2337 return (err); 2338 } 2339 2340 static void 2341 ohci_xfer_setup(struct usb_setup_params *parm) 2342 { 2343 struct usb_page_search page_info; 2344 struct usb_page_cache *pc; 2345 struct usb_xfer *xfer; 2346 void *last_obj; 2347 uint32_t ntd; 2348 uint32_t nitd; 2349 uint32_t nqh; 2350 uint32_t n; 2351 2352 xfer = parm->curr_xfer; 2353 2354 parm->hc_max_packet_size = 0x500; 2355 parm->hc_max_packet_count = 1; 2356 parm->hc_max_frame_size = OHCI_PAGE_SIZE; 2357 2358 /* 2359 * calculate ntd and nqh 2360 */ 2361 if (parm->methods == &ohci_device_ctrl_methods) { 2362 xfer->flags_int.bdma_enable = 1; 2363 2364 usbd_transfer_setup_sub(parm); 2365 2366 nitd = 0; 2367 ntd = ((2 * xfer->nframes) + 1 /* STATUS */ 2368 + (xfer->max_data_length / xfer->max_hc_frame_size)); 2369 nqh = 1; 2370 2371 } else if (parm->methods == &ohci_device_bulk_methods) { 2372 xfer->flags_int.bdma_enable = 1; 2373 2374 usbd_transfer_setup_sub(parm); 2375 2376 nitd = 0; 2377 ntd = ((2 * xfer->nframes) 2378 + (xfer->max_data_length / xfer->max_hc_frame_size)); 2379 nqh = 1; 2380 2381 } else if (parm->methods == &ohci_device_intr_methods) { 2382 xfer->flags_int.bdma_enable = 1; 2383 2384 usbd_transfer_setup_sub(parm); 2385 2386 nitd = 0; 2387 ntd = ((2 * xfer->nframes) 2388 + (xfer->max_data_length / xfer->max_hc_frame_size)); 2389 nqh = 1; 2390 2391 } else if (parm->methods == &ohci_device_isoc_methods) { 2392 xfer->flags_int.bdma_enable = 1; 2393 2394 usbd_transfer_setup_sub(parm); 2395 2396 nitd = ((xfer->max_data_length / OHCI_PAGE_SIZE) + 2397 howmany(xfer->nframes, OHCI_ITD_NOFFSET) + 2398 1 /* EXTRA */ ); 2399 ntd = 0; 2400 nqh = 1; 2401 2402 } else { 2403 usbd_transfer_setup_sub(parm); 2404 2405 nitd = 0; 2406 ntd = 0; 2407 nqh = 0; 2408 } 2409 2410 alloc_dma_set: 2411 2412 if (parm->err) { 2413 return; 2414 } 2415 last_obj = NULL; 2416 2417 if (usbd_transfer_setup_sub_malloc( 2418 parm, &pc, sizeof(ohci_td_t), 2419 OHCI_TD_ALIGN, ntd)) { 2420 parm->err = USB_ERR_NOMEM; 2421 return; 2422 } 2423 if (parm->buf) { 2424 for (n = 0; n != ntd; n++) { 2425 ohci_td_t *td; 2426 2427 usbd_get_page(pc + n, 0, &page_info); 2428 2429 td = page_info.buffer; 2430 2431 /* init TD */ 2432 td->td_self = htole32(page_info.physaddr); 2433 td->obj_next = last_obj; 2434 td->page_cache = pc + n; 2435 2436 last_obj = td; 2437 2438 usb_pc_cpu_flush(pc + n); 2439 } 2440 } 2441 if (usbd_transfer_setup_sub_malloc( 2442 parm, &pc, sizeof(ohci_itd_t), 2443 OHCI_ITD_ALIGN, nitd)) { 2444 parm->err = USB_ERR_NOMEM; 2445 return; 2446 } 2447 if (parm->buf) { 2448 for (n = 0; n != nitd; n++) { 2449 ohci_itd_t *itd; 2450 2451 usbd_get_page(pc + n, 0, &page_info); 2452 2453 itd = page_info.buffer; 2454 2455 /* init TD */ 2456 itd->itd_self = htole32(page_info.physaddr); 2457 itd->obj_next = last_obj; 2458 itd->page_cache = pc + n; 2459 2460 last_obj = itd; 2461 2462 usb_pc_cpu_flush(pc + n); 2463 } 2464 } 2465 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj; 2466 2467 last_obj = NULL; 2468 2469 if (usbd_transfer_setup_sub_malloc( 2470 parm, &pc, sizeof(ohci_ed_t), 2471 OHCI_ED_ALIGN, nqh)) { 2472 parm->err = USB_ERR_NOMEM; 2473 return; 2474 } 2475 if (parm->buf) { 2476 for (n = 0; n != nqh; n++) { 2477 ohci_ed_t *ed; 2478 2479 usbd_get_page(pc + n, 0, &page_info); 2480 2481 ed = page_info.buffer; 2482 2483 /* init QH */ 2484 ed->ed_self = htole32(page_info.physaddr); 2485 ed->obj_next = last_obj; 2486 ed->page_cache = pc + n; 2487 2488 last_obj = ed; 2489 2490 usb_pc_cpu_flush(pc + n); 2491 } 2492 } 2493 xfer->qh_start[xfer->flags_int.curr_dma_set] = last_obj; 2494 2495 if (!xfer->flags_int.curr_dma_set) { 2496 xfer->flags_int.curr_dma_set = 1; 2497 goto alloc_dma_set; 2498 } 2499 } 2500 2501 static void 2502 ohci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 2503 struct usb_endpoint *ep) 2504 { 2505 ohci_softc_t *sc = OHCI_BUS2SC(udev->bus); 2506 2507 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d)\n", 2508 ep, udev->address, 2509 edesc->bEndpointAddress, udev->flags.usb_mode, 2510 sc->sc_addr); 2511 2512 if (udev->device_index != sc->sc_addr) { 2513 switch (edesc->bmAttributes & UE_XFERTYPE) { 2514 case UE_CONTROL: 2515 ep->methods = &ohci_device_ctrl_methods; 2516 break; 2517 case UE_INTERRUPT: 2518 ep->methods = &ohci_device_intr_methods; 2519 break; 2520 case UE_ISOCHRONOUS: 2521 if (udev->speed == USB_SPEED_FULL) { 2522 ep->methods = &ohci_device_isoc_methods; 2523 } 2524 break; 2525 case UE_BULK: 2526 ep->methods = &ohci_device_bulk_methods; 2527 break; 2528 default: 2529 /* do nothing */ 2530 break; 2531 } 2532 } 2533 } 2534 2535 static void 2536 ohci_xfer_unsetup(struct usb_xfer *xfer) 2537 { 2538 return; 2539 } 2540 2541 static void 2542 ohci_get_dma_delay(struct usb_device *udev, uint32_t *pus) 2543 { 2544 /* 2545 * Wait until hardware has finished any possible use of the 2546 * transfer descriptor(s) and QH 2547 */ 2548 *pus = (1125); /* microseconds */ 2549 } 2550 2551 static void 2552 ohci_device_resume(struct usb_device *udev) 2553 { 2554 struct ohci_softc *sc = OHCI_BUS2SC(udev->bus); 2555 struct usb_xfer *xfer; 2556 const struct usb_pipe_methods *methods; 2557 ohci_ed_t *ed; 2558 2559 DPRINTF("\n"); 2560 2561 USB_BUS_LOCK(udev->bus); 2562 2563 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 2564 if (xfer->xroot->udev == udev) { 2565 methods = xfer->endpoint->methods; 2566 ed = xfer->qh_start[xfer->flags_int.curr_dma_set]; 2567 2568 if (methods == &ohci_device_bulk_methods) { 2569 OHCI_APPEND_QH(ed, sc->sc_bulk_p_last); 2570 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF); 2571 } 2572 if (methods == &ohci_device_ctrl_methods) { 2573 OHCI_APPEND_QH(ed, sc->sc_ctrl_p_last); 2574 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 2575 } 2576 if (methods == &ohci_device_intr_methods) { 2577 OHCI_APPEND_QH(ed, sc->sc_intr_p_last[xfer->qh_pos]); 2578 } 2579 } 2580 } 2581 2582 USB_BUS_UNLOCK(udev->bus); 2583 2584 return; 2585 } 2586 2587 static void 2588 ohci_device_suspend(struct usb_device *udev) 2589 { 2590 struct ohci_softc *sc = OHCI_BUS2SC(udev->bus); 2591 struct usb_xfer *xfer; 2592 const struct usb_pipe_methods *methods; 2593 ohci_ed_t *ed; 2594 2595 DPRINTF("\n"); 2596 2597 USB_BUS_LOCK(udev->bus); 2598 2599 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 2600 if (xfer->xroot->udev == udev) { 2601 methods = xfer->endpoint->methods; 2602 ed = xfer->qh_start[xfer->flags_int.curr_dma_set]; 2603 2604 if (methods == &ohci_device_bulk_methods) { 2605 OHCI_REMOVE_QH(ed, sc->sc_bulk_p_last); 2606 } 2607 if (methods == &ohci_device_ctrl_methods) { 2608 OHCI_REMOVE_QH(ed, sc->sc_ctrl_p_last); 2609 } 2610 if (methods == &ohci_device_intr_methods) { 2611 OHCI_REMOVE_QH(ed, sc->sc_intr_p_last[xfer->qh_pos]); 2612 } 2613 } 2614 } 2615 2616 USB_BUS_UNLOCK(udev->bus); 2617 2618 return; 2619 } 2620 2621 static void 2622 ohci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 2623 { 2624 struct ohci_softc *sc = OHCI_BUS2SC(bus); 2625 2626 switch (state) { 2627 case USB_HW_POWER_SUSPEND: 2628 case USB_HW_POWER_SHUTDOWN: 2629 ohci_suspend(sc); 2630 break; 2631 case USB_HW_POWER_RESUME: 2632 ohci_resume(sc); 2633 break; 2634 default: 2635 break; 2636 } 2637 } 2638 2639 static void 2640 ohci_set_hw_power(struct usb_bus *bus) 2641 { 2642 struct ohci_softc *sc = OHCI_BUS2SC(bus); 2643 uint32_t temp; 2644 uint32_t flags; 2645 2646 DPRINTF("\n"); 2647 2648 USB_BUS_LOCK(bus); 2649 2650 flags = bus->hw_power_state; 2651 2652 temp = OREAD4(sc, OHCI_CONTROL); 2653 temp &= ~(OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE); 2654 2655 if (flags & USB_HW_POWER_CONTROL) 2656 temp |= OHCI_CLE; 2657 2658 if (flags & USB_HW_POWER_BULK) 2659 temp |= OHCI_BLE; 2660 2661 if (flags & USB_HW_POWER_INTERRUPT) 2662 temp |= OHCI_PLE; 2663 2664 if (flags & USB_HW_POWER_ISOC) 2665 temp |= OHCI_IE | OHCI_PLE; 2666 2667 OWRITE4(sc, OHCI_CONTROL, temp); 2668 2669 USB_BUS_UNLOCK(bus); 2670 2671 return; 2672 } 2673 2674 static const struct usb_bus_methods ohci_bus_methods = 2675 { 2676 .endpoint_init = ohci_ep_init, 2677 .xfer_setup = ohci_xfer_setup, 2678 .xfer_unsetup = ohci_xfer_unsetup, 2679 .get_dma_delay = ohci_get_dma_delay, 2680 .device_resume = ohci_device_resume, 2681 .device_suspend = ohci_device_suspend, 2682 .set_hw_power = ohci_set_hw_power, 2683 .set_hw_power_sleep = ohci_set_hw_power_sleep, 2684 .roothub_exec = ohci_roothub_exec, 2685 .xfer_poll = ohci_do_poll, 2686 }; 2687