1 /* $FreeBSD$ */ 2 3 /*- 4 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 5 * 6 * Copyright (c) 2010 Hans Petter Selasky. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #ifndef _XHCI_H_ 31 #define _XHCI_H_ 32 33 #define XHCI_MAX_DEVICES MIN(USB_MAX_DEVICES, 128) 34 #define XHCI_MAX_ENDPOINTS 32 /* hardcoded - do not change */ 35 #define XHCI_MAX_SCRATCHPADS 256 /* theoretical max is 1023 */ 36 #define XHCI_MAX_EVENTS 232 37 #define XHCI_MAX_COMMANDS (16 * 1) 38 #define XHCI_MAX_RSEG 1 39 #define XHCI_MAX_TRANSFERS 4 40 #if USB_MAX_EP_STREAMS == 8 41 #define XHCI_MAX_STREAMS 8 42 #define XHCI_MAX_STREAMS_LOG 3 43 #elif USB_MAX_EP_STREAMS == 1 44 #define XHCI_MAX_STREAMS 1 45 #define XHCI_MAX_STREAMS_LOG 0 46 #else 47 #error "The USB_MAX_EP_STREAMS value is not supported." 48 #endif 49 #define XHCI_DEV_CTX_ADDR_ALIGN 64 /* bytes */ 50 #define XHCI_DEV_CTX_ALIGN 64 /* bytes */ 51 #define XHCI_INPUT_CTX_ALIGN 64 /* bytes */ 52 #define XHCI_SLOT_CTX_ALIGN 32 /* bytes */ 53 #define XHCI_ENDP_CTX_ALIGN 32 /* bytes */ 54 #define XHCI_STREAM_CTX_ALIGN 16 /* bytes */ 55 #define XHCI_TRANS_RING_SEG_ALIGN 16 /* bytes */ 56 #define XHCI_CMD_RING_SEG_ALIGN 64 /* bytes */ 57 #define XHCI_EVENT_RING_SEG_ALIGN 64 /* bytes */ 58 #define XHCI_SCRATCH_BUF_ARRAY_ALIGN 64 /* bytes */ 59 #define XHCI_SCRATCH_BUFFER_ALIGN USB_PAGE_SIZE 60 #define XHCI_TRB_ALIGN 16 /* bytes */ 61 #define XHCI_TD_ALIGN 64 /* bytes */ 62 #define XHCI_PAGE_SIZE 4096 /* bytes */ 63 64 struct xhci_dev_ctx_addr { 65 volatile uint64_t qwBaaDevCtxAddr[USB_MAX_DEVICES + 1]; 66 struct { 67 volatile uint64_t dummy; 68 } __aligned(64) padding; 69 volatile uint64_t qwSpBufPtr[XHCI_MAX_SCRATCHPADS]; 70 }; 71 72 #define XHCI_EPNO2EPID(x) \ 73 ((((x) & UE_DIR_IN) ? 1 : 0) | (2 * ((x) & UE_ADDR))) 74 75 struct xhci_slot_ctx { 76 volatile uint32_t dwSctx0; 77 #define XHCI_SCTX_0_ROUTE_SET(x) ((x) & 0xFFFFF) 78 #define XHCI_SCTX_0_ROUTE_GET(x) ((x) & 0xFFFFF) 79 #define XHCI_SCTX_0_SPEED_SET(x) (((x) & 0xF) << 20) 80 #define XHCI_SCTX_0_SPEED_GET(x) (((x) >> 20) & 0xF) 81 #define XHCI_SCTX_0_MTT_SET(x) (((x) & 0x1) << 25) 82 #define XHCI_SCTX_0_MTT_GET(x) (((x) >> 25) & 0x1) 83 #define XHCI_SCTX_0_HUB_SET(x) (((x) & 0x1) << 26) 84 #define XHCI_SCTX_0_HUB_GET(x) (((x) >> 26) & 0x1) 85 #define XHCI_SCTX_0_CTX_NUM_SET(x) (((x) & 0x1F) << 27) 86 #define XHCI_SCTX_0_CTX_NUM_GET(x) (((x) >> 27) & 0x1F) 87 volatile uint32_t dwSctx1; 88 #define XHCI_SCTX_1_MAX_EL_SET(x) ((x) & 0xFFFF) 89 #define XHCI_SCTX_1_MAX_EL_GET(x) ((x) & 0xFFFF) 90 #define XHCI_SCTX_1_RH_PORT_SET(x) (((x) & 0xFF) << 16) 91 #define XHCI_SCTX_1_RH_PORT_GET(x) (((x) >> 16) & 0xFF) 92 #define XHCI_SCTX_1_NUM_PORTS_SET(x) (((x) & 0xFF) << 24) 93 #define XHCI_SCTX_1_NUM_PORTS_GET(x) (((x) >> 24) & 0xFF) 94 volatile uint32_t dwSctx2; 95 #define XHCI_SCTX_2_TT_HUB_SID_SET(x) ((x) & 0xFF) 96 #define XHCI_SCTX_2_TT_HUB_SID_GET(x) ((x) & 0xFF) 97 #define XHCI_SCTX_2_TT_PORT_NUM_SET(x) (((x) & 0xFF) << 8) 98 #define XHCI_SCTX_2_TT_PORT_NUM_GET(x) (((x) >> 8) & 0xFF) 99 #define XHCI_SCTX_2_TT_THINK_TIME_SET(x) (((x) & 0x3) << 16) 100 #define XHCI_SCTX_2_TT_THINK_TIME_GET(x) (((x) >> 16) & 0x3) 101 #define XHCI_SCTX_2_IRQ_TARGET_SET(x) (((x) & 0x3FF) << 22) 102 #define XHCI_SCTX_2_IRQ_TARGET_GET(x) (((x) >> 22) & 0x3FF) 103 volatile uint32_t dwSctx3; 104 #define XHCI_SCTX_3_DEV_ADDR_SET(x) ((x) & 0xFF) 105 #define XHCI_SCTX_3_DEV_ADDR_GET(x) ((x) & 0xFF) 106 #define XHCI_SCTX_3_SLOT_STATE_SET(x) (((x) & 0x1F) << 27) 107 #define XHCI_SCTX_3_SLOT_STATE_GET(x) (((x) >> 27) & 0x1F) 108 volatile uint32_t dwSctx4; 109 volatile uint32_t dwSctx5; 110 volatile uint32_t dwSctx6; 111 volatile uint32_t dwSctx7; 112 }; 113 114 struct xhci_endp_ctx { 115 volatile uint32_t dwEpCtx0; 116 #define XHCI_EPCTX_0_EPSTATE_SET(x) ((x) & 0x7) 117 #define XHCI_EPCTX_0_EPSTATE_GET(x) ((x) & 0x7) 118 #define XHCI_EPCTX_0_EPSTATE_DISABLED 0 119 #define XHCI_EPCTX_0_EPSTATE_RUNNING 1 120 #define XHCI_EPCTX_0_EPSTATE_HALTED 2 121 #define XHCI_EPCTX_0_EPSTATE_STOPPED 3 122 #define XHCI_EPCTX_0_EPSTATE_ERROR 4 123 #define XHCI_EPCTX_0_EPSTATE_RESERVED_5 5 124 #define XHCI_EPCTX_0_EPSTATE_RESERVED_6 6 125 #define XHCI_EPCTX_0_EPSTATE_RESERVED_7 7 126 #define XHCI_EPCTX_0_MULT_SET(x) (((x) & 0x3) << 8) 127 #define XHCI_EPCTX_0_MULT_GET(x) (((x) >> 8) & 0x3) 128 #define XHCI_EPCTX_0_MAXP_STREAMS_SET(x) (((x) & 0x1F) << 10) 129 #define XHCI_EPCTX_0_MAXP_STREAMS_GET(x) (((x) >> 10) & 0x1F) 130 #define XHCI_EPCTX_0_LSA_SET(x) (((x) & 0x1) << 15) 131 #define XHCI_EPCTX_0_LSA_GET(x) (((x) >> 15) & 0x1) 132 #define XHCI_EPCTX_0_IVAL_SET(x) (((x) & 0xFF) << 16) 133 #define XHCI_EPCTX_0_IVAL_GET(x) (((x) >> 16) & 0xFF) 134 volatile uint32_t dwEpCtx1; 135 #define XHCI_EPCTX_1_CERR_SET(x) (((x) & 0x3) << 1) 136 #define XHCI_EPCTX_1_CERR_GET(x) (((x) >> 1) & 0x3) 137 #define XHCI_EPCTX_1_EPTYPE_SET(x) (((x) & 0x7) << 3) 138 #define XHCI_EPCTX_1_EPTYPE_GET(x) (((x) >> 3) & 0x7) 139 #define XHCI_EPCTX_1_HID_SET(x) (((x) & 0x1) << 7) 140 #define XHCI_EPCTX_1_HID_GET(x) (((x) >> 7) & 0x1) 141 #define XHCI_EPCTX_1_MAXB_SET(x) (((x) & 0xFF) << 8) 142 #define XHCI_EPCTX_1_MAXB_GET(x) (((x) >> 8) & 0xFF) 143 #define XHCI_EPCTX_1_MAXP_SIZE_SET(x) (((x) & 0xFFFF) << 16) 144 #define XHCI_EPCTX_1_MAXP_SIZE_GET(x) (((x) >> 16) & 0xFFFF) 145 volatile uint64_t qwEpCtx2; 146 #define XHCI_EPCTX_2_DCS_SET(x) ((x) & 0x1) 147 #define XHCI_EPCTX_2_DCS_GET(x) ((x) & 0x1) 148 #define XHCI_EPCTX_2_TR_DQ_PTR_MASK 0xFFFFFFFFFFFFFFF0U 149 volatile uint32_t dwEpCtx4; 150 #define XHCI_EPCTX_4_AVG_TRB_LEN_SET(x) ((x) & 0xFFFF) 151 #define XHCI_EPCTX_4_AVG_TRB_LEN_GET(x) ((x) & 0xFFFF) 152 #define XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(x) (((x) & 0xFFFF) << 16) 153 #define XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_GET(x) (((x) >> 16) & 0xFFFF) 154 volatile uint32_t dwEpCtx5; 155 volatile uint32_t dwEpCtx6; 156 volatile uint32_t dwEpCtx7; 157 }; 158 159 struct xhci_input_ctx { 160 #define XHCI_INCTX_NON_CTRL_MASK 0xFFFFFFFCU 161 volatile uint32_t dwInCtx0; 162 #define XHCI_INCTX_0_DROP_MASK(n) (1U << (n)) 163 volatile uint32_t dwInCtx1; 164 #define XHCI_INCTX_1_ADD_MASK(n) (1U << (n)) 165 volatile uint32_t dwInCtx2; 166 volatile uint32_t dwInCtx3; 167 volatile uint32_t dwInCtx4; 168 volatile uint32_t dwInCtx5; 169 volatile uint32_t dwInCtx6; 170 volatile uint32_t dwInCtx7; 171 }; 172 173 struct xhci_input_dev_ctx { 174 struct xhci_input_ctx ctx_input; 175 struct xhci_slot_ctx ctx_slot; 176 struct xhci_endp_ctx ctx_ep[XHCI_MAX_ENDPOINTS - 1]; 177 }; 178 179 struct xhci_dev_ctx { 180 struct xhci_slot_ctx ctx_slot; 181 struct xhci_endp_ctx ctx_ep[XHCI_MAX_ENDPOINTS - 1]; 182 } __aligned(XHCI_DEV_CTX_ALIGN); 183 184 struct xhci_stream_ctx { 185 volatile uint64_t qwSctx0; 186 #define XHCI_SCTX_0_DCS_GET(x) ((x) & 0x1) 187 #define XHCI_SCTX_0_DCS_SET(x) ((x) & 0x1) 188 #define XHCI_SCTX_0_SCT_SET(x) (((x) & 0x7) << 1) 189 #define XHCI_SCTX_0_SCT_GET(x) (((x) >> 1) & 0x7) 190 #define XHCI_SCTX_0_SCT_SEC_TR_RING 0x0 191 #define XHCI_SCTX_0_SCT_PRIM_TR_RING 0x1 192 #define XHCI_SCTX_0_SCT_PRIM_SSA_8 0x2 193 #define XHCI_SCTX_0_SCT_PRIM_SSA_16 0x3 194 #define XHCI_SCTX_0_SCT_PRIM_SSA_32 0x4 195 #define XHCI_SCTX_0_SCT_PRIM_SSA_64 0x5 196 #define XHCI_SCTX_0_SCT_PRIM_SSA_128 0x6 197 #define XHCI_SCTX_0_SCT_PRIM_SSA_256 0x7 198 #define XHCI_SCTX_0_TR_DQ_PTR_MASK 0xFFFFFFFFFFFFFFF0U 199 volatile uint32_t dwSctx2; 200 volatile uint32_t dwSctx3; 201 }; 202 203 struct xhci_trb { 204 volatile uint64_t qwTrb0; 205 #define XHCI_TRB_0_DIR_IN_MASK (0x80ULL << 0) 206 #define XHCI_TRB_0_WLENGTH_MASK (0xFFFFULL << 48) 207 volatile uint32_t dwTrb2; 208 #define XHCI_TRB_2_ERROR_GET(x) (((x) >> 24) & 0xFF) 209 #define XHCI_TRB_2_ERROR_SET(x) (((x) & 0xFF) << 24) 210 #define XHCI_TRB_2_TDSZ_GET(x) (((x) >> 17) & 0x1F) 211 #define XHCI_TRB_2_TDSZ_SET(x) (((x) & 0x1F) << 17) 212 #define XHCI_TRB_2_REM_GET(x) ((x) & 0xFFFFFF) 213 #define XHCI_TRB_2_REM_SET(x) ((x) & 0xFFFFFF) 214 #define XHCI_TRB_2_BYTES_GET(x) ((x) & 0x1FFFF) 215 #define XHCI_TRB_2_BYTES_SET(x) ((x) & 0x1FFFF) 216 #define XHCI_TRB_2_IRQ_GET(x) (((x) >> 22) & 0x3FF) 217 #define XHCI_TRB_2_IRQ_SET(x) (((x) & 0x3FF) << 22) 218 #define XHCI_TRB_2_STREAM_GET(x) (((x) >> 16) & 0xFFFF) 219 #define XHCI_TRB_2_STREAM_SET(x) (((x) & 0xFFFF) << 16) 220 221 volatile uint32_t dwTrb3; 222 #define XHCI_TRB_3_TYPE_GET(x) (((x) >> 10) & 0x3F) 223 #define XHCI_TRB_3_TYPE_SET(x) (((x) & 0x3F) << 10) 224 #define XHCI_TRB_3_CYCLE_BIT (1U << 0) 225 #define XHCI_TRB_3_TC_BIT (1U << 1) /* command ring only */ 226 #define XHCI_TRB_3_ENT_BIT (1U << 1) /* transfer ring only */ 227 #define XHCI_TRB_3_ISP_BIT (1U << 2) 228 #define XHCI_TRB_3_NSNOOP_BIT (1U << 3) 229 #define XHCI_TRB_3_CHAIN_BIT (1U << 4) 230 #define XHCI_TRB_3_IOC_BIT (1U << 5) 231 #define XHCI_TRB_3_IDT_BIT (1U << 6) 232 #define XHCI_TRB_3_TBC_GET(x) (((x) >> 7) & 3) 233 #define XHCI_TRB_3_TBC_SET(x) (((x) & 3) << 7) 234 #define XHCI_TRB_3_BEI_BIT (1U << 9) 235 #define XHCI_TRB_3_DCEP_BIT (1U << 9) 236 #define XHCI_TRB_3_PRSV_BIT (1U << 9) 237 #define XHCI_TRB_3_BSR_BIT (1U << 9) 238 #define XHCI_TRB_3_TRT_MASK (3U << 16) 239 #define XHCI_TRB_3_TRT_NONE (0U << 16) 240 #define XHCI_TRB_3_TRT_OUT (2U << 16) 241 #define XHCI_TRB_3_TRT_IN (3U << 16) 242 #define XHCI_TRB_3_DIR_IN (1U << 16) 243 #define XHCI_TRB_3_TLBPC_GET(x) (((x) >> 16) & 0xF) 244 #define XHCI_TRB_3_TLBPC_SET(x) (((x) & 0xF) << 16) 245 #define XHCI_TRB_3_EP_GET(x) (((x) >> 16) & 0x1F) 246 #define XHCI_TRB_3_EP_SET(x) (((x) & 0x1F) << 16) 247 #define XHCI_TRB_3_FRID_GET(x) (((x) >> 20) & 0x7FF) 248 #define XHCI_TRB_3_FRID_SET(x) (((x) & 0x7FF) << 20) 249 #define XHCI_TRB_3_ISO_SIA_BIT (1U << 31) 250 #define XHCI_TRB_3_SUSP_EP_BIT (1U << 23) 251 #define XHCI_TRB_3_SLOT_GET(x) (((x) >> 24) & 0xFF) 252 #define XHCI_TRB_3_SLOT_SET(x) (((x) & 0xFF) << 24) 253 254 /* Commands */ 255 #define XHCI_TRB_TYPE_RESERVED 0x00 256 #define XHCI_TRB_TYPE_NORMAL 0x01 257 #define XHCI_TRB_TYPE_SETUP_STAGE 0x02 258 #define XHCI_TRB_TYPE_DATA_STAGE 0x03 259 #define XHCI_TRB_TYPE_STATUS_STAGE 0x04 260 #define XHCI_TRB_TYPE_ISOCH 0x05 261 #define XHCI_TRB_TYPE_LINK 0x06 262 #define XHCI_TRB_TYPE_EVENT_DATA 0x07 263 #define XHCI_TRB_TYPE_NOOP 0x08 264 #define XHCI_TRB_TYPE_ENABLE_SLOT 0x09 265 #define XHCI_TRB_TYPE_DISABLE_SLOT 0x0A 266 #define XHCI_TRB_TYPE_ADDRESS_DEVICE 0x0B 267 #define XHCI_TRB_TYPE_CONFIGURE_EP 0x0C 268 #define XHCI_TRB_TYPE_EVALUATE_CTX 0x0D 269 #define XHCI_TRB_TYPE_RESET_EP 0x0E 270 #define XHCI_TRB_TYPE_STOP_EP 0x0F 271 #define XHCI_TRB_TYPE_SET_TR_DEQUEUE 0x10 272 #define XHCI_TRB_TYPE_RESET_DEVICE 0x11 273 #define XHCI_TRB_TYPE_FORCE_EVENT 0x12 274 #define XHCI_TRB_TYPE_NEGOTIATE_BW 0x13 275 #define XHCI_TRB_TYPE_SET_LATENCY_TOL 0x14 276 #define XHCI_TRB_TYPE_GET_PORT_BW 0x15 277 #define XHCI_TRB_TYPE_FORCE_HEADER 0x16 278 #define XHCI_TRB_TYPE_NOOP_CMD 0x17 279 280 /* Events */ 281 #define XHCI_TRB_EVENT_TRANSFER 0x20 282 #define XHCI_TRB_EVENT_CMD_COMPLETE 0x21 283 #define XHCI_TRB_EVENT_PORT_STS_CHANGE 0x22 284 #define XHCI_TRB_EVENT_BW_REQUEST 0x23 285 #define XHCI_TRB_EVENT_DOORBELL 0x24 286 #define XHCI_TRB_EVENT_HOST_CTRL 0x25 287 #define XHCI_TRB_EVENT_DEVICE_NOTIFY 0x26 288 #define XHCI_TRB_EVENT_MFINDEX_WRAP 0x27 289 290 /* Error codes */ 291 #define XHCI_TRB_ERROR_INVALID 0x00 292 #define XHCI_TRB_ERROR_SUCCESS 0x01 293 #define XHCI_TRB_ERROR_DATA_BUF 0x02 294 #define XHCI_TRB_ERROR_BABBLE 0x03 295 #define XHCI_TRB_ERROR_XACT 0x04 296 #define XHCI_TRB_ERROR_TRB 0x05 297 #define XHCI_TRB_ERROR_STALL 0x06 298 #define XHCI_TRB_ERROR_RESOURCE 0x07 299 #define XHCI_TRB_ERROR_BANDWIDTH 0x08 300 #define XHCI_TRB_ERROR_NO_SLOTS 0x09 301 #define XHCI_TRB_ERROR_STREAM_TYPE 0x0A 302 #define XHCI_TRB_ERROR_SLOT_NOT_ON 0x0B 303 #define XHCI_TRB_ERROR_ENDP_NOT_ON 0x0C 304 #define XHCI_TRB_ERROR_SHORT_PKT 0x0D 305 #define XHCI_TRB_ERROR_RING_UNDERRUN 0x0E 306 #define XHCI_TRB_ERROR_RING_OVERRUN 0x0F 307 #define XHCI_TRB_ERROR_VF_RING_FULL 0x10 308 #define XHCI_TRB_ERROR_PARAMETER 0x11 309 #define XHCI_TRB_ERROR_BW_OVERRUN 0x12 310 #define XHCI_TRB_ERROR_CONTEXT_STATE 0x13 311 #define XHCI_TRB_ERROR_NO_PING_RESP 0x14 312 #define XHCI_TRB_ERROR_EV_RING_FULL 0x15 313 #define XHCI_TRB_ERROR_INCOMPAT_DEV 0x16 314 #define XHCI_TRB_ERROR_MISSED_SERVICE 0x17 315 #define XHCI_TRB_ERROR_CMD_RING_STOP 0x18 316 #define XHCI_TRB_ERROR_CMD_ABORTED 0x19 317 #define XHCI_TRB_ERROR_STOPPED 0x1A 318 #define XHCI_TRB_ERROR_LENGTH 0x1B 319 #define XHCI_TRB_ERROR_BAD_MELAT 0x1D 320 #define XHCI_TRB_ERROR_ISOC_OVERRUN 0x1F 321 #define XHCI_TRB_ERROR_EVENT_LOST 0x20 322 #define XHCI_TRB_ERROR_UNDEFINED 0x21 323 #define XHCI_TRB_ERROR_INVALID_SID 0x22 324 #define XHCI_TRB_ERROR_SEC_BW 0x23 325 #define XHCI_TRB_ERROR_SPLIT_XACT 0x24 326 } __aligned(4); 327 328 struct xhci_dev_endpoint_trbs { 329 struct xhci_trb trb[(XHCI_MAX_STREAMS * 330 XHCI_MAX_TRANSFERS) + XHCI_MAX_STREAMS]; 331 }; 332 333 #if (USB_PAGE_SIZE < 4096) 334 #error "The XHCI driver needs a pagesize above or equal to 4K" 335 #endif 336 337 /* Define the maximum payload which we will handle in a single TRB */ 338 #define XHCI_TD_PAYLOAD_MAX 65536 /* bytes */ 339 340 /* Define the maximum payload of a single scatter-gather list element */ 341 #define XHCI_TD_PAGE_SIZE \ 342 ((USB_PAGE_SIZE < XHCI_TD_PAYLOAD_MAX) ? USB_PAGE_SIZE : XHCI_TD_PAYLOAD_MAX) 343 344 /* Define the maximum length of the scatter-gather list */ 345 #define XHCI_TD_PAGE_NBUF \ 346 (((XHCI_TD_PAYLOAD_MAX + XHCI_TD_PAGE_SIZE - 1) / XHCI_TD_PAGE_SIZE) + 1) 347 348 struct xhci_td { 349 /* one LINK TRB has been added to the TRB array */ 350 struct xhci_trb td_trb[XHCI_TD_PAGE_NBUF + 1]; 351 352 /* 353 * Extra information needed: 354 */ 355 uint64_t td_self; 356 struct xhci_td *next; 357 struct xhci_td *alt_next; 358 struct xhci_td *obj_next; 359 struct usb_page_cache *page_cache; 360 uint32_t len; 361 uint32_t remainder; 362 uint8_t ntrb; 363 uint8_t status; 364 } __aligned(XHCI_TRB_ALIGN); 365 366 struct xhci_command { 367 struct xhci_trb trb; 368 TAILQ_ENTRY(xhci_command) entry; 369 }; 370 371 struct xhci_event_ring_seg { 372 volatile uint64_t qwEvrsTablePtr; 373 volatile uint32_t dwEvrsTableSize; 374 volatile uint32_t dwEvrsReserved; 375 }; 376 377 struct xhci_hw_root { 378 struct xhci_event_ring_seg hwr_ring_seg[XHCI_MAX_RSEG]; 379 struct { 380 volatile uint64_t dummy; 381 } __aligned(64) padding; 382 struct xhci_trb hwr_events[XHCI_MAX_EVENTS]; 383 struct xhci_trb hwr_commands[XHCI_MAX_COMMANDS]; 384 }; 385 386 CTASSERT(sizeof(struct xhci_hw_root) == XHCI_PAGE_SIZE); 387 388 struct xhci_endpoint_ext { 389 struct xhci_trb *trb; 390 struct usb_xfer *xfer[XHCI_MAX_TRANSFERS * XHCI_MAX_STREAMS]; 391 struct usb_page_cache *page_cache; 392 uint64_t physaddr; 393 uint8_t trb_used[XHCI_MAX_STREAMS]; 394 uint8_t trb_index[XHCI_MAX_STREAMS]; 395 uint8_t trb_halted; 396 uint8_t trb_running; 397 uint8_t trb_ep_mode; 398 uint8_t trb_ep_maxp; 399 }; 400 401 enum { 402 XHCI_ST_DISABLED, 403 XHCI_ST_ENABLED, 404 XHCI_ST_DEFAULT, 405 XHCI_ST_ADDRESSED, 406 XHCI_ST_CONFIGURED, 407 XHCI_ST_MAX 408 }; 409 410 struct xhci_hw_dev { 411 struct usb_page_cache device_pc; 412 struct usb_page_cache input_pc; 413 struct usb_page_cache endpoint_pc[XHCI_MAX_ENDPOINTS]; 414 415 struct usb_page device_pg; 416 struct usb_page input_pg; 417 struct usb_page endpoint_pg[XHCI_MAX_ENDPOINTS]; 418 419 struct xhci_endpoint_ext endp[XHCI_MAX_ENDPOINTS]; 420 421 uint32_t ep_configured; 422 423 uint8_t state; 424 uint8_t nports; 425 uint8_t tt; 426 uint8_t context_num; 427 }; 428 429 struct xhci_hw_softc { 430 struct usb_page_cache root_pc; 431 struct usb_page_cache ctx_pc; 432 struct usb_page_cache scratch_pc[XHCI_MAX_SCRATCHPADS]; 433 434 struct usb_page root_pg; 435 struct usb_page ctx_pg; 436 struct usb_page scratch_pg[XHCI_MAX_SCRATCHPADS]; 437 438 struct xhci_hw_dev devs[XHCI_MAX_DEVICES + 1]; 439 }; 440 441 struct xhci_config_desc { 442 struct usb_config_descriptor confd; 443 struct usb_interface_descriptor ifcd; 444 struct usb_endpoint_descriptor endpd; 445 struct usb_endpoint_ss_comp_descriptor endpcd; 446 } __packed; 447 448 struct xhci_bos_desc { 449 struct usb_bos_descriptor bosd; 450 struct usb_devcap_usb2ext_descriptor usb2extd; 451 struct usb_devcap_ss_descriptor usbdcd; 452 struct usb_devcap_container_id_descriptor cidd; 453 } __packed; 454 455 union xhci_hub_desc { 456 struct usb_status stat; 457 struct usb_port_status ps; 458 struct usb_hub_ss_descriptor hubd; 459 uint8_t temp[128]; 460 }; 461 462 typedef int (xhci_port_route_t)(device_t, uint32_t, uint32_t); 463 464 struct xhci_softc { 465 struct xhci_hw_softc sc_hw; 466 /* base device */ 467 struct usb_bus sc_bus; 468 /* configure message */ 469 struct usb_bus_msg sc_config_msg[2]; 470 471 struct usb_callout sc_callout; 472 473 xhci_port_route_t *sc_port_route; 474 475 union xhci_hub_desc sc_hub_desc; 476 477 struct cv sc_cmd_cv; 478 struct sx sc_cmd_sx; 479 480 struct usb_device *sc_devices[XHCI_MAX_DEVICES]; 481 struct resource *sc_io_res; 482 struct resource *sc_irq_res; 483 struct resource *sc_msix_res; 484 485 void *sc_intr_hdl; 486 bus_size_t sc_io_size; 487 bus_space_tag_t sc_io_tag; 488 bus_space_handle_t sc_io_hdl; 489 /* last pending command address */ 490 uint64_t sc_cmd_addr; 491 /* result of command */ 492 uint32_t sc_cmd_result[2]; 493 /* copy of cmd register */ 494 uint32_t sc_cmd; 495 /* worst case exit latency */ 496 uint32_t sc_exit_lat_max; 497 498 /* offset to operational registers */ 499 uint32_t sc_oper_off; 500 /* offset to capability registers */ 501 uint32_t sc_capa_off; 502 /* offset to runtime registers */ 503 uint32_t sc_runt_off; 504 /* offset to doorbell registers */ 505 uint32_t sc_door_off; 506 507 /* chip specific */ 508 uint16_t sc_erst_max; 509 uint16_t sc_event_idx; 510 uint16_t sc_command_idx; 511 uint16_t sc_imod_default; 512 513 /* number of scratch pages */ 514 uint16_t sc_noscratch; 515 516 uint8_t sc_event_ccs; 517 uint8_t sc_command_ccs; 518 /* number of XHCI device slots */ 519 uint8_t sc_noslot; 520 /* number of ports on root HUB */ 521 uint8_t sc_noport; 522 /* root HUB device configuration */ 523 uint8_t sc_conf; 524 /* step status stage of all control transfers */ 525 uint8_t sc_ctlstep; 526 /* root HUB port event bitmap, max 256 ports */ 527 uint8_t sc_hub_idata[32]; 528 529 /* size of context */ 530 uint8_t sc_ctx_is_64_byte; 531 532 /* Isochronous Scheduling Threshold */ 533 uint8_t sc_ist; 534 535 /* vendor string for root HUB */ 536 char sc_vendor[16]; 537 }; 538 539 #define XHCI_CMD_LOCK(sc) sx_xlock(&(sc)->sc_cmd_sx) 540 #define XHCI_CMD_UNLOCK(sc) sx_xunlock(&(sc)->sc_cmd_sx) 541 #define XHCI_CMD_ASSERT_LOCKED(sc) sx_assert(&(sc)->sc_cmd_sx, SA_LOCKED) 542 543 /* prototypes */ 544 545 uint8_t xhci_use_polling(void); 546 usb_error_t xhci_halt_controller(struct xhci_softc *); 547 usb_error_t xhci_reset_controller(struct xhci_softc *); 548 usb_error_t xhci_init(struct xhci_softc *, device_t, uint8_t); 549 usb_error_t xhci_start_controller(struct xhci_softc *); 550 void xhci_interrupt(struct xhci_softc *); 551 void xhci_uninit(struct xhci_softc *); 552 int xhci_pci_attach(device_t); 553 554 DECLARE_CLASS(xhci_pci_driver); 555 556 #endif /* _XHCI_H_ */ 557