1 /*- 2 * Copyright (c) 2010 Hans Petter Selasky. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 */ 25 26 #include <sys/cdefs.h> 27 __FBSDID("$FreeBSD$"); 28 29 #include <sys/stdint.h> 30 #include <sys/stddef.h> 31 #include <sys/param.h> 32 #include <sys/queue.h> 33 #include <sys/types.h> 34 #include <sys/systm.h> 35 #include <sys/kernel.h> 36 #include <sys/bus.h> 37 #include <sys/module.h> 38 #include <sys/lock.h> 39 #include <sys/mutex.h> 40 #include <sys/condvar.h> 41 #include <sys/sysctl.h> 42 #include <sys/sx.h> 43 #include <sys/unistd.h> 44 #include <sys/callout.h> 45 #include <sys/malloc.h> 46 #include <sys/priv.h> 47 48 #include <dev/usb/usb.h> 49 #include <dev/usb/usbdi.h> 50 51 #include <dev/usb/usb_core.h> 52 #include <dev/usb/usb_busdma.h> 53 #include <dev/usb/usb_process.h> 54 #include <dev/usb/usb_util.h> 55 56 #include <dev/usb/usb_controller.h> 57 #include <dev/usb/usb_bus.h> 58 #include <dev/usb/usb_pci.h> 59 #include <dev/usb/controller/xhci.h> 60 #include <dev/usb/controller/xhcireg.h> 61 #include "usb_if.h" 62 63 static device_probe_t xhci_pci_probe; 64 static device_attach_t xhci_pci_attach; 65 static device_detach_t xhci_pci_detach; 66 static usb_take_controller_t xhci_pci_take_controller; 67 68 static device_method_t xhci_device_methods[] = { 69 /* device interface */ 70 DEVMETHOD(device_probe, xhci_pci_probe), 71 DEVMETHOD(device_attach, xhci_pci_attach), 72 DEVMETHOD(device_detach, xhci_pci_detach), 73 DEVMETHOD(device_suspend, bus_generic_suspend), 74 DEVMETHOD(device_resume, bus_generic_resume), 75 DEVMETHOD(device_shutdown, bus_generic_shutdown), 76 DEVMETHOD(usb_take_controller, xhci_pci_take_controller), 77 78 DEVMETHOD_END 79 }; 80 81 static driver_t xhci_driver = { 82 .name = "xhci", 83 .methods = xhci_device_methods, 84 .size = sizeof(struct xhci_softc), 85 }; 86 87 static devclass_t xhci_devclass; 88 89 DRIVER_MODULE(xhci, pci, xhci_driver, xhci_devclass, 0, 0); 90 MODULE_DEPEND(xhci, usb, 1, 1, 1); 91 92 93 static const char * 94 xhci_pci_match(device_t self) 95 { 96 uint32_t device_id = pci_get_devid(self); 97 98 switch (device_id) { 99 case 0x01941033: 100 return ("NEC uPD720200 USB 3.0 controller"); 101 102 case 0x10421b21: 103 return ("ASMedia ASM1042 USB 3.0 controller"); 104 105 case 0x0f358086: 106 return ("Intel Intel BayTrail USB 3.0 controller"); 107 case 0x9c318086: 108 case 0x1e318086: 109 return ("Intel Panther Point USB 3.0 controller"); 110 case 0x8c318086: 111 return ("Intel Lynx Point USB 3.0 controller"); 112 case 0x8cb18086: 113 return ("Intel Wildcat Point USB 3.0 controller"); 114 115 default: 116 break; 117 } 118 119 if ((pci_get_class(self) == PCIC_SERIALBUS) 120 && (pci_get_subclass(self) == PCIS_SERIALBUS_USB) 121 && (pci_get_progif(self) == PCIP_SERIALBUS_USB_XHCI)) { 122 return ("XHCI (generic) USB 3.0 controller"); 123 } 124 return (NULL); /* dunno */ 125 } 126 127 static int 128 xhci_pci_probe(device_t self) 129 { 130 const char *desc = xhci_pci_match(self); 131 132 if (desc) { 133 device_set_desc(self, desc); 134 return (BUS_PROBE_DEFAULT); 135 } else { 136 return (ENXIO); 137 } 138 } 139 140 static int xhci_use_msi = 1; 141 TUNABLE_INT("hw.usb.xhci.msi", &xhci_use_msi); 142 143 static void 144 xhci_interrupt_poll(void *_sc) 145 { 146 struct xhci_softc *sc = _sc; 147 USB_BUS_UNLOCK(&sc->sc_bus); 148 xhci_interrupt(sc); 149 USB_BUS_LOCK(&sc->sc_bus); 150 usb_callout_reset(&sc->sc_callout, 1, (void *)&xhci_interrupt_poll, sc); 151 } 152 153 static int 154 xhci_pci_port_route(device_t self, uint32_t set, uint32_t clear) 155 { 156 uint32_t temp; 157 uint32_t usb3_mask; 158 uint32_t usb2_mask; 159 160 temp = pci_read_config(self, PCI_XHCI_INTEL_USB3_PSSEN, 4) | 161 pci_read_config(self, PCI_XHCI_INTEL_XUSB2PR, 4); 162 163 temp |= set; 164 temp &= ~clear; 165 166 /* Don't set bits which the hardware doesn't support */ 167 usb3_mask = pci_read_config(self, PCI_XHCI_INTEL_USB3PRM, 4); 168 usb2_mask = pci_read_config(self, PCI_XHCI_INTEL_USB2PRM, 4); 169 170 pci_write_config(self, PCI_XHCI_INTEL_USB3_PSSEN, temp & usb3_mask, 4); 171 pci_write_config(self, PCI_XHCI_INTEL_XUSB2PR, temp & usb2_mask, 4); 172 173 device_printf(self, "Port routing mask set to 0x%08x\n", temp); 174 175 return (0); 176 } 177 178 static int 179 xhci_pci_attach(device_t self) 180 { 181 struct xhci_softc *sc = device_get_softc(self); 182 int count, err, rid; 183 uint8_t usedma32; 184 185 rid = PCI_XHCI_CBMEM; 186 sc->sc_io_res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, 187 RF_ACTIVE); 188 if (!sc->sc_io_res) { 189 device_printf(self, "Could not map memory\n"); 190 return (ENOMEM); 191 } 192 sc->sc_io_tag = rman_get_bustag(sc->sc_io_res); 193 sc->sc_io_hdl = rman_get_bushandle(sc->sc_io_res); 194 sc->sc_io_size = rman_get_size(sc->sc_io_res); 195 196 /* check for USB 3.0 controllers which don't support 64-bit DMA */ 197 switch (pci_get_devid(self)) { 198 case 0x01941033: /* NEC uPD720200 USB 3.0 controller */ 199 usedma32 = 1; 200 break; 201 default: 202 usedma32 = 0; 203 break; 204 } 205 206 if (xhci_init(sc, self, usedma32)) { 207 device_printf(self, "Could not initialize softc\n"); 208 bus_release_resource(self, SYS_RES_MEMORY, PCI_XHCI_CBMEM, 209 sc->sc_io_res); 210 return (ENXIO); 211 } 212 213 pci_enable_busmaster(self); 214 215 usb_callout_init_mtx(&sc->sc_callout, &sc->sc_bus.bus_mtx, 0); 216 217 rid = 0; 218 if (xhci_use_msi) { 219 count = 1; 220 if (pci_alloc_msi(self, &count) == 0) { 221 if (bootverbose) 222 device_printf(self, "MSI enabled\n"); 223 rid = 1; 224 } 225 } 226 sc->sc_irq_res = bus_alloc_resource_any(self, SYS_RES_IRQ, &rid, 227 RF_ACTIVE | (rid != 0 ? 0 : RF_SHAREABLE)); 228 if (sc->sc_irq_res == NULL) { 229 pci_release_msi(self); 230 device_printf(self, "Could not allocate IRQ\n"); 231 /* goto error; FALLTHROUGH - use polling */ 232 } 233 sc->sc_bus.bdev = device_add_child(self, "usbus", -1); 234 if (sc->sc_bus.bdev == NULL) { 235 device_printf(self, "Could not add USB device\n"); 236 goto error; 237 } 238 device_set_ivars(sc->sc_bus.bdev, &sc->sc_bus); 239 240 sprintf(sc->sc_vendor, "0x%04x", pci_get_vendor(self)); 241 242 if (sc->sc_irq_res != NULL) { 243 err = bus_setup_intr(self, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE, 244 NULL, (driver_intr_t *)xhci_interrupt, sc, &sc->sc_intr_hdl); 245 if (err != 0) { 246 bus_release_resource(self, SYS_RES_IRQ, 247 rman_get_rid(sc->sc_irq_res), sc->sc_irq_res); 248 sc->sc_irq_res = NULL; 249 pci_release_msi(self); 250 device_printf(self, "Could not setup IRQ, err=%d\n", err); 251 sc->sc_intr_hdl = NULL; 252 } 253 } 254 if (sc->sc_irq_res == NULL || sc->sc_intr_hdl == NULL) { 255 if (xhci_use_polling() != 0) { 256 device_printf(self, "Interrupt polling at %dHz\n", hz); 257 USB_BUS_LOCK(&sc->sc_bus); 258 xhci_interrupt_poll(sc); 259 USB_BUS_UNLOCK(&sc->sc_bus); 260 } else 261 goto error; 262 } 263 264 /* On Intel chipsets reroute ports from EHCI to XHCI controller. */ 265 switch (pci_get_devid(self)) { 266 case 0x0f358086: /* BayTrail */ 267 case 0x9c318086: /* Panther Point */ 268 case 0x1e318086: /* Panther Point */ 269 case 0x8c318086: /* Lynx Point */ 270 case 0x8cb18086: /* Wildcat Point */ 271 sc->sc_port_route = &xhci_pci_port_route; 272 sc->sc_imod_default = XHCI_IMOD_DEFAULT_LP; 273 break; 274 default: 275 break; 276 } 277 278 xhci_pci_take_controller(self); 279 280 err = xhci_halt_controller(sc); 281 282 if (err == 0) 283 err = xhci_start_controller(sc); 284 285 if (err == 0) 286 err = device_probe_and_attach(sc->sc_bus.bdev); 287 288 if (err) { 289 device_printf(self, "XHCI halt/start/probe failed err=%d\n", err); 290 goto error; 291 } 292 return (0); 293 294 error: 295 xhci_pci_detach(self); 296 return (ENXIO); 297 } 298 299 static int 300 xhci_pci_detach(device_t self) 301 { 302 struct xhci_softc *sc = device_get_softc(self); 303 device_t bdev; 304 305 if (sc->sc_bus.bdev != NULL) { 306 bdev = sc->sc_bus.bdev; 307 device_detach(bdev); 308 device_delete_child(self, bdev); 309 } 310 /* during module unload there are lots of children leftover */ 311 device_delete_children(self); 312 313 usb_callout_drain(&sc->sc_callout); 314 xhci_halt_controller(sc); 315 316 pci_disable_busmaster(self); 317 318 if (sc->sc_irq_res && sc->sc_intr_hdl) { 319 bus_teardown_intr(self, sc->sc_irq_res, sc->sc_intr_hdl); 320 sc->sc_intr_hdl = NULL; 321 } 322 if (sc->sc_irq_res) { 323 bus_release_resource(self, SYS_RES_IRQ, 324 rman_get_rid(sc->sc_irq_res), sc->sc_irq_res); 325 sc->sc_irq_res = NULL; 326 pci_release_msi(self); 327 } 328 if (sc->sc_io_res) { 329 bus_release_resource(self, SYS_RES_MEMORY, PCI_XHCI_CBMEM, 330 sc->sc_io_res); 331 sc->sc_io_res = NULL; 332 } 333 334 xhci_uninit(sc); 335 336 return (0); 337 } 338 339 static int 340 xhci_pci_take_controller(device_t self) 341 { 342 struct xhci_softc *sc = device_get_softc(self); 343 uint32_t cparams; 344 uint32_t eecp; 345 uint32_t eec; 346 uint16_t to; 347 uint8_t bios_sem; 348 349 cparams = XREAD4(sc, capa, XHCI_HCSPARAMS0); 350 351 eec = -1; 352 353 /* Synchronise with the BIOS if it owns the controller. */ 354 for (eecp = XHCI_HCS0_XECP(cparams) << 2; eecp != 0 && XHCI_XECP_NEXT(eec); 355 eecp += XHCI_XECP_NEXT(eec) << 2) { 356 eec = XREAD4(sc, capa, eecp); 357 358 if (XHCI_XECP_ID(eec) != XHCI_ID_USB_LEGACY) 359 continue; 360 bios_sem = XREAD1(sc, capa, eecp + 361 XHCI_XECP_BIOS_SEM); 362 if (bios_sem == 0) 363 continue; 364 device_printf(sc->sc_bus.bdev, "waiting for BIOS " 365 "to give up control\n"); 366 XWRITE1(sc, capa, eecp + 367 XHCI_XECP_OS_SEM, 1); 368 to = 500; 369 while (1) { 370 bios_sem = XREAD1(sc, capa, eecp + 371 XHCI_XECP_BIOS_SEM); 372 if (bios_sem == 0) 373 break; 374 375 if (--to == 0) { 376 device_printf(sc->sc_bus.bdev, 377 "timed out waiting for BIOS\n"); 378 break; 379 } 380 usb_pause_mtx(NULL, hz / 100); /* wait 10ms */ 381 } 382 } 383 return (0); 384 } 385