113540260SHans Petter Selasky 213540260SHans Petter Selasky /*- 34d846d26SWarner Losh * SPDX-License-Identifier: BSD-2-Clause 4718cf2ccSPedro F. Giffuni * 513540260SHans Petter Selasky * Copyright (c) 2010 Hans Petter Selasky. All rights reserved. 613540260SHans Petter Selasky * 713540260SHans Petter Selasky * Redistribution and use in source and binary forms, with or without 813540260SHans Petter Selasky * modification, are permitted provided that the following conditions 913540260SHans Petter Selasky * are met: 1013540260SHans Petter Selasky * 1. Redistributions of source code must retain the above copyright 1113540260SHans Petter Selasky * notice, this list of conditions and the following disclaimer. 1213540260SHans Petter Selasky * 2. Redistributions in binary form must reproduce the above copyright 1313540260SHans Petter Selasky * notice, this list of conditions and the following disclaimer in the 1413540260SHans Petter Selasky * documentation and/or other materials provided with the distribution. 1513540260SHans Petter Selasky * 1613540260SHans Petter Selasky * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 1713540260SHans Petter Selasky * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1813540260SHans Petter Selasky * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 1913540260SHans Petter Selasky * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 2013540260SHans Petter Selasky * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 2113540260SHans Petter Selasky * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2213540260SHans Petter Selasky * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2313540260SHans Petter Selasky * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2413540260SHans Petter Selasky * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2513540260SHans Petter Selasky * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2613540260SHans Petter Selasky * SUCH DAMAGE. 2713540260SHans Petter Selasky */ 2813540260SHans Petter Selasky 2913540260SHans Petter Selasky #ifndef _XHCIREG_H_ 3013540260SHans Petter Selasky #define _XHCIREG_H_ 3113540260SHans Petter Selasky 3213540260SHans Petter Selasky /* XHCI PCI config registers */ 3313540260SHans Petter Selasky #define PCI_XHCI_CBMEM 0x10 /* configuration base MEM */ 3413540260SHans Petter Selasky #define PCI_XHCI_USBREV 0x60 /* RO USB protocol revision */ 3513540260SHans Petter Selasky #define PCI_USB_REV_3_0 0x30 /* USB 3.0 */ 3613540260SHans Petter Selasky #define PCI_XHCI_FLADJ 0x61 /* RW frame length adjust */ 3713540260SHans Petter Selasky 38f4f6d5e0SAlexander Motin #define PCI_XHCI_INTEL_XUSB2PR 0xD0 /* Intel USB2 Port Routing */ 3988e0a639SHans Petter Selasky #define PCI_XHCI_INTEL_USB2PRM 0xD4 /* Intel USB2 Port Routing Mask */ 40f4f6d5e0SAlexander Motin #define PCI_XHCI_INTEL_USB3_PSSEN 0xD8 /* Intel USB3 Port SuperSpeed Enable */ 4188e0a639SHans Petter Selasky #define PCI_XHCI_INTEL_USB3PRM 0xDC /* Intel USB3 Port Routing Mask */ 42f4f6d5e0SAlexander Motin 4313540260SHans Petter Selasky /* XHCI capability registers */ 4413540260SHans Petter Selasky #define XHCI_CAPLENGTH 0x00 /* RO capability */ 4513540260SHans Petter Selasky #define XHCI_RESERVED 0x01 /* Reserved */ 4613540260SHans Petter Selasky #define XHCI_HCIVERSION 0x02 /* RO Interface version number */ 4713540260SHans Petter Selasky #define XHCI_HCIVERSION_0_9 0x0090 /* xHCI version 0.9 */ 4813540260SHans Petter Selasky #define XHCI_HCIVERSION_1_0 0x0100 /* xHCI version 1.0 */ 4920733245SPedro F. Giffuni #define XHCI_HCSPARAMS1 0x04 /* RO structural parameters 1 */ 5013540260SHans Petter Selasky #define XHCI_HCS1_DEVSLOT_MAX(x)((x) & 0xFF) 5113540260SHans Petter Selasky #define XHCI_HCS1_IRQ_MAX(x) (((x) >> 8) & 0x3FF) 5213540260SHans Petter Selasky #define XHCI_HCS1_N_PORTS(x) (((x) >> 24) & 0xFF) 5320733245SPedro F. Giffuni #define XHCI_HCSPARAMS2 0x08 /* RO structural parameters 2 */ 5413540260SHans Petter Selasky #define XHCI_HCS2_IST(x) ((x) & 0xF) 5513540260SHans Petter Selasky #define XHCI_HCS2_ERST_MAX(x) (((x) >> 4) & 0xF) 56bbd41717SHans Petter Selasky #define XHCI_HCS2_SPR(x) (((x) >> 26) & 0x1) 57bbd41717SHans Petter Selasky #define XHCI_HCS2_SPB_MAX(x) ((((x) >> 16) & 0x3E0) | (((x) >> 27) & 0x1F)) 5820733245SPedro F. Giffuni #define XHCI_HCSPARAMS3 0x0C /* RO structural parameters 3 */ 5913540260SHans Petter Selasky #define XHCI_HCS3_U1_DEL(x) ((x) & 0xFF) 6013540260SHans Petter Selasky #define XHCI_HCS3_U2_DEL(x) (((x) >> 16) & 0xFFFF) 6113540260SHans Petter Selasky #define XHCI_HCSPARAMS0 0x10 /* RO capability parameters */ 6213540260SHans Petter Selasky #define XHCI_HCS0_AC64(x) ((x) & 0x1) /* 64-bit capable */ 6313540260SHans Petter Selasky #define XHCI_HCS0_BNC(x) (((x) >> 1) & 0x1) /* BW negotiation */ 6413540260SHans Petter Selasky #define XHCI_HCS0_CSZ(x) (((x) >> 2) & 0x1) /* context size */ 6513540260SHans Petter Selasky #define XHCI_HCS0_PPC(x) (((x) >> 3) & 0x1) /* port power control */ 6613540260SHans Petter Selasky #define XHCI_HCS0_PIND(x) (((x) >> 4) & 0x1) /* port indicators */ 6713540260SHans Petter Selasky #define XHCI_HCS0_LHRC(x) (((x) >> 5) & 0x1) /* light HC reset */ 6813540260SHans Petter Selasky #define XHCI_HCS0_LTC(x) (((x) >> 6) & 0x1) /* latency tolerance msg */ 6913540260SHans Petter Selasky #define XHCI_HCS0_NSS(x) (((x) >> 7) & 0x1) /* no secondary sid */ 7013540260SHans Petter Selasky #define XHCI_HCS0_PSA_SZ_MAX(x) (((x) >> 12) & 0xF) /* max pri. stream array size */ 7113540260SHans Petter Selasky #define XHCI_HCS0_XECP(x) (((x) >> 16) & 0xFFFF) /* extended capabilities pointer */ 7213540260SHans Petter Selasky #define XHCI_DBOFF 0x14 /* RO doorbell offset */ 7313540260SHans Petter Selasky #define XHCI_RTSOFF 0x18 /* RO runtime register space offset */ 7413540260SHans Petter Selasky 7513540260SHans Petter Selasky /* XHCI operational registers. Offset given by XHCI_CAPLENGTH register */ 7613540260SHans Petter Selasky #define XHCI_USBCMD 0x00 /* XHCI command */ 7713540260SHans Petter Selasky #define XHCI_CMD_RS 0x00000001 /* RW Run/Stop */ 7813540260SHans Petter Selasky #define XHCI_CMD_HCRST 0x00000002 /* RW Host Controller Reset */ 7913540260SHans Petter Selasky #define XHCI_CMD_INTE 0x00000004 /* RW Interrupter Enable */ 8013540260SHans Petter Selasky #define XHCI_CMD_HSEE 0x00000008 /* RW Host System Error Enable */ 8113540260SHans Petter Selasky #define XHCI_CMD_LHCRST 0x00000080 /* RO/RW Light Host Controller Reset */ 8213540260SHans Petter Selasky #define XHCI_CMD_CSS 0x00000100 /* RW Controller Save State */ 8313540260SHans Petter Selasky #define XHCI_CMD_CRS 0x00000200 /* RW Controller Restore State */ 8413540260SHans Petter Selasky #define XHCI_CMD_EWE 0x00000400 /* RW Enable Wrap Event */ 8513540260SHans Petter Selasky #define XHCI_CMD_EU3S 0x00000800 /* RW Enable U3 MFINDEX Stop */ 8613540260SHans Petter Selasky #define XHCI_USBSTS 0x04 /* XHCI status */ 8713540260SHans Petter Selasky #define XHCI_STS_HCH 0x00000001 /* RO - Host Controller Halted */ 8813540260SHans Petter Selasky #define XHCI_STS_HSE 0x00000004 /* RW - Host System Error */ 8913540260SHans Petter Selasky #define XHCI_STS_EINT 0x00000008 /* RW - Event Interrupt */ 9013540260SHans Petter Selasky #define XHCI_STS_PCD 0x00000010 /* RW - Port Change Detect */ 9113540260SHans Petter Selasky #define XHCI_STS_SSS 0x00000100 /* RO - Save State Status */ 9213540260SHans Petter Selasky #define XHCI_STS_RSS 0x00000200 /* RO - Restore State Status */ 9313540260SHans Petter Selasky #define XHCI_STS_SRE 0x00000400 /* RW - Save/Restore Error */ 9413540260SHans Petter Selasky #define XHCI_STS_CNR 0x00000800 /* RO - Controller Not Ready */ 9513540260SHans Petter Selasky #define XHCI_STS_HCE 0x00001000 /* RO - Host Controller Error */ 9613540260SHans Petter Selasky #define XHCI_PAGESIZE 0x08 /* XHCI page size mask */ 9713540260SHans Petter Selasky #define XHCI_PAGESIZE_4K 0x00000001 /* 4K Page Size */ 9813540260SHans Petter Selasky #define XHCI_PAGESIZE_8K 0x00000002 /* 8K Page Size */ 9913540260SHans Petter Selasky #define XHCI_PAGESIZE_16K 0x00000004 /* 16K Page Size */ 10013540260SHans Petter Selasky #define XHCI_PAGESIZE_32K 0x00000008 /* 32K Page Size */ 10113540260SHans Petter Selasky #define XHCI_PAGESIZE_64K 0x00000010 /* 64K Page Size */ 10213540260SHans Petter Selasky #define XHCI_DNCTRL 0x14 /* XHCI device notification control */ 10313540260SHans Petter Selasky #define XHCI_DNCTRL_MASK(n) (1U << (n)) 10413540260SHans Petter Selasky #define XHCI_CRCR_LO 0x18 /* XHCI command ring control */ 10513540260SHans Petter Selasky #define XHCI_CRCR_LO_RCS 0x00000001 /* RW - consumer cycle state */ 10613540260SHans Petter Selasky #define XHCI_CRCR_LO_CS 0x00000002 /* RW - command stop */ 10713540260SHans Petter Selasky #define XHCI_CRCR_LO_CA 0x00000004 /* RW - command abort */ 10813540260SHans Petter Selasky #define XHCI_CRCR_LO_CRR 0x00000008 /* RW - command ring running */ 10913540260SHans Petter Selasky #define XHCI_CRCR_LO_MASK 0x0000000F 11013540260SHans Petter Selasky #define XHCI_CRCR_HI 0x1C /* XHCI command ring control */ 11113540260SHans Petter Selasky #define XHCI_DCBAAP_LO 0x30 /* XHCI dev context BA pointer */ 11213540260SHans Petter Selasky #define XHCI_DCBAAP_HI 0x34 /* XHCI dev context BA pointer */ 11313540260SHans Petter Selasky #define XHCI_CONFIG 0x38 11413540260SHans Petter Selasky #define XHCI_CONFIG_SLOTS_MASK 0x000000FF /* RW - number of device slots enabled */ 11513540260SHans Petter Selasky 11613540260SHans Petter Selasky /* XHCI port status registers */ 11713540260SHans Petter Selasky #define XHCI_PORTSC(n) (0x3F0 + (0x10 * (n))) /* XHCI port status */ 11813540260SHans Petter Selasky #define XHCI_PS_CCS 0x00000001 /* RO - current connect status */ 11913540260SHans Petter Selasky #define XHCI_PS_PED 0x00000002 /* RW - port enabled / disabled */ 12013540260SHans Petter Selasky #define XHCI_PS_OCA 0x00000008 /* RO - over current active */ 12113540260SHans Petter Selasky #define XHCI_PS_PR 0x00000010 /* RW - port reset */ 12213540260SHans Petter Selasky #define XHCI_PS_PLS_GET(x) (((x) >> 5) & 0xF) /* RW - port link state */ 12313540260SHans Petter Selasky #define XHCI_PS_PLS_SET(x) (((x) & 0xF) << 5) /* RW - port link state */ 1245f63a5d2SHans Petter Selasky #define XHCI_PS_PP 0x00000200 /* RW - port power */ 12513540260SHans Petter Selasky #define XHCI_PS_SPEED_GET(x) (((x) >> 10) & 0xF) /* RO - port speed */ 126d730333cSHans Petter Selasky #define XHCI_PS_SPEED_FULL 0x1 /* Full Speed USB */ 127d730333cSHans Petter Selasky #define XHCI_PS_SPEED_LOW 0x2 /* Low Speed USB */ 128d730333cSHans Petter Selasky #define XHCI_PS_SPEED_HIGH 0x3 /* High Speed USB */ 129d730333cSHans Petter Selasky #define XHCI_PS_SPEED_SS 0x4 /* Super Speed USB */ 13013540260SHans Petter Selasky #define XHCI_PS_PIC_GET(x) (((x) >> 14) & 0x3) /* RW - port indicator */ 13113540260SHans Petter Selasky #define XHCI_PS_PIC_SET(x) (((x) & 0x3) << 14) /* RW - port indicator */ 13213540260SHans Petter Selasky #define XHCI_PS_LWS 0x00010000 /* RW - port link state write strobe */ 13313540260SHans Petter Selasky #define XHCI_PS_CSC 0x00020000 /* RW - connect status change */ 13413540260SHans Petter Selasky #define XHCI_PS_PEC 0x00040000 /* RW - port enable/disable change */ 13513540260SHans Petter Selasky #define XHCI_PS_WRC 0x00080000 /* RW - warm port reset change */ 13613540260SHans Petter Selasky #define XHCI_PS_OCC 0x00100000 /* RW - over-current change */ 13713540260SHans Petter Selasky #define XHCI_PS_PRC 0x00200000 /* RW - port reset change */ 13813540260SHans Petter Selasky #define XHCI_PS_PLC 0x00400000 /* RW - port link state change */ 13913540260SHans Petter Selasky #define XHCI_PS_CEC 0x00800000 /* RW - config error change */ 14013540260SHans Petter Selasky #define XHCI_PS_CAS 0x01000000 /* RO - cold attach status */ 14113540260SHans Petter Selasky #define XHCI_PS_WCE 0x02000000 /* RW - wake on connect enable */ 14213540260SHans Petter Selasky #define XHCI_PS_WDE 0x04000000 /* RW - wake on disconnect enable */ 14313540260SHans Petter Selasky #define XHCI_PS_WOE 0x08000000 /* RW - wake on over-current enable */ 14413540260SHans Petter Selasky #define XHCI_PS_DR 0x40000000 /* RO - device removable */ 14513540260SHans Petter Selasky #define XHCI_PS_WPR 0x80000000U /* RW - warm port reset */ 1463d09c7b3SHans Petter Selasky #define XHCI_PS_CLEAR 0x80FF01FFU /* command bits */ 14713540260SHans Petter Selasky 14813540260SHans Petter Selasky #define XHCI_PORTPMSC(n) (0x3F4 + (0x10 * (n))) /* XHCI status and control */ 14913540260SHans Petter Selasky #define XHCI_PM3_U1TO_GET(x) (((x) >> 0) & 0xFF) /* RW - U1 timeout */ 15013540260SHans Petter Selasky #define XHCI_PM3_U1TO_SET(x) (((x) & 0xFF) << 0) /* RW - U1 timeout */ 15113540260SHans Petter Selasky #define XHCI_PM3_U2TO_GET(x) (((x) >> 8) & 0xFF) /* RW - U2 timeout */ 15213540260SHans Petter Selasky #define XHCI_PM3_U2TO_SET(x) (((x) & 0xFF) << 8) /* RW - U2 timeout */ 15313540260SHans Petter Selasky #define XHCI_PM3_FLA 0x00010000 /* RW - Force Link PM Accept */ 15413540260SHans Petter Selasky #define XHCI_PM2_L1S_GET(x) (((x) >> 0) & 0x7) /* RO - L1 status */ 15513540260SHans Petter Selasky #define XHCI_PM2_RWE 0x00000008 /* RW - remote wakup enable */ 15613540260SHans Petter Selasky #define XHCI_PM2_HIRD_GET(x) (((x) >> 4) & 0xF) /* RW - host initiated resume duration */ 15713540260SHans Petter Selasky #define XHCI_PM2_HIRD_SET(x) (((x) & 0xF) << 4) /* RW - host initiated resume duration */ 15813540260SHans Petter Selasky #define XHCI_PM2_L1SLOT_GET(x) (((x) >> 8) & 0xFF) /* RW - L1 device slot */ 15913540260SHans Petter Selasky #define XHCI_PM2_L1SLOT_SET(x) (((x) & 0xFF) << 8) /* RW - L1 device slot */ 16013540260SHans Petter Selasky #define XHCI_PM2_HLE 0x00010000 /* RW - hardware LPM enable */ 16113540260SHans Petter Selasky #define XHCI_PORTLI(n) (0x3F8 + (0x10 * (n))) /* XHCI port link info */ 16213540260SHans Petter Selasky #define XHCI_PLI3_ERR_GET(x) (((x) >> 0) & 0xFFFF) /* RO - port link errors */ 16313540260SHans Petter Selasky #define XHCI_PORTRSV(n) (0x3FC + (0x10 * (n))) /* XHCI port reserved */ 16413540260SHans Petter Selasky 16513540260SHans Petter Selasky /* XHCI runtime registers. Offset given by XHCI_CAPLENGTH + XHCI_RTSOFF registers */ 16613540260SHans Petter Selasky #define XHCI_MFINDEX 0x0000 /* RO - microframe index */ 16713540260SHans Petter Selasky #define XHCI_MFINDEX_GET(x) ((x) & 0x3FFF) 16813540260SHans Petter Selasky #define XHCI_IMAN(n) (0x0020 + (0x20 * (n))) /* XHCI interrupt management */ 16913540260SHans Petter Selasky #define XHCI_IMAN_INTR_PEND 0x00000001 /* RW - interrupt pending */ 17013540260SHans Petter Selasky #define XHCI_IMAN_INTR_ENA 0x00000002 /* RW - interrupt enable */ 17113540260SHans Petter Selasky #define XHCI_IMOD(n) (0x0024 + (0x20 * (n))) /* XHCI interrupt moderation */ 17213540260SHans Petter Selasky #define XHCI_IMOD_IVAL_GET(x) (((x) >> 0) & 0xFFFF) /* 250ns unit */ 17313540260SHans Petter Selasky #define XHCI_IMOD_IVAL_SET(x) (((x) & 0xFFFF) << 0) /* 250ns unit */ 17413540260SHans Petter Selasky #define XHCI_IMOD_ICNT_GET(x) (((x) >> 16) & 0xFFFF) /* 250ns unit */ 17513540260SHans Petter Selasky #define XHCI_IMOD_ICNT_SET(x) (((x) & 0xFFFF) << 16) /* 250ns unit */ 1768237c62bSHans Petter Selasky #define XHCI_IMOD_DEFAULT 0x000001F4U /* 8000 IRQs/second */ 1778237c62bSHans Petter Selasky #define XHCI_IMOD_DEFAULT_LP 0x000003F8U /* 4000 IRQs/second - LynxPoint */ 17813540260SHans Petter Selasky #define XHCI_ERSTSZ(n) (0x0028 + (0x20 * (n))) /* XHCI event ring segment table size */ 17913540260SHans Petter Selasky #define XHCI_ERSTS_GET(x) ((x) & 0xFFFF) 18013540260SHans Petter Selasky #define XHCI_ERSTS_SET(x) ((x) & 0xFFFF) 18113540260SHans Petter Selasky #define XHCI_ERSTBA_LO(n) (0x0030 + (0x20 * (n))) /* XHCI event ring segment table BA */ 18213540260SHans Petter Selasky #define XHCI_ERSTBA_HI(n) (0x0034 + (0x20 * (n))) /* XHCI event ring segment table BA */ 18313540260SHans Petter Selasky #define XHCI_ERDP_LO(n) (0x0038 + (0x20 * (n))) /* XHCI event ring dequeue pointer */ 18413540260SHans Petter Selasky #define XHCI_ERDP_LO_SINDEX(x) ((x) & 0x7) /* RO - dequeue segment index */ 18513540260SHans Petter Selasky #define XHCI_ERDP_LO_BUSY 0x00000008 /* RW - event handler busy */ 18613540260SHans Petter Selasky #define XHCI_ERDP_HI(n) (0x003C + (0x20 * (n))) /* XHCI event ring dequeue pointer */ 18713540260SHans Petter Selasky 18813540260SHans Petter Selasky /* XHCI doorbell registers. Offset given by XHCI_CAPLENGTH + XHCI_DBOFF registers */ 18913540260SHans Petter Selasky #define XHCI_DOORBELL(n) (0x0000 + (4 * (n))) 19013540260SHans Petter Selasky #define XHCI_DB_TARGET_GET(x) ((x) & 0xFF) /* RW - doorbell target */ 19113540260SHans Petter Selasky #define XHCI_DB_TARGET_SET(x) ((x) & 0xFF) /* RW - doorbell target */ 19213540260SHans Petter Selasky #define XHCI_DB_SID_GET(x) (((x) >> 16) & 0xFFFF) /* RW - doorbell stream ID */ 19313540260SHans Petter Selasky #define XHCI_DB_SID_SET(x) (((x) & 0xFFFF) << 16) /* RW - doorbell stream ID */ 19413540260SHans Petter Selasky 19513540260SHans Petter Selasky /* XHCI legacy support */ 19613540260SHans Petter Selasky #define XHCI_XECP_ID(x) ((x) & 0xFF) 19713540260SHans Petter Selasky #define XHCI_XECP_NEXT(x) (((x) >> 8) & 0xFF) 19813540260SHans Petter Selasky #define XHCI_XECP_BIOS_SEM 0x0002 19913540260SHans Petter Selasky #define XHCI_XECP_OS_SEM 0x0003 20013540260SHans Petter Selasky 20113540260SHans Petter Selasky /* XHCI capability ID's */ 20213540260SHans Petter Selasky #define XHCI_ID_USB_LEGACY 0x0001 20313540260SHans Petter Selasky #define XHCI_ID_PROTOCOLS 0x0002 20413540260SHans Petter Selasky #define XHCI_ID_POWER_MGMT 0x0003 20513540260SHans Petter Selasky #define XHCI_ID_VIRTUALIZATION 0x0004 20613540260SHans Petter Selasky #define XHCI_ID_MSG_IRQ 0x0005 20713540260SHans Petter Selasky #define XHCI_ID_USB_LOCAL_MEM 0x0006 20813540260SHans Petter Selasky 20913540260SHans Petter Selasky /* XHCI register R/W wrappers */ 21013540260SHans Petter Selasky #define XREAD1(sc, what, a) \ 21113540260SHans Petter Selasky bus_space_read_1((sc)->sc_io_tag, (sc)->sc_io_hdl, \ 21213540260SHans Petter Selasky (a) + (sc)->sc_##what##_off) 21313540260SHans Petter Selasky #define XREAD2(sc, what, a) \ 21413540260SHans Petter Selasky bus_space_read_2((sc)->sc_io_tag, (sc)->sc_io_hdl, \ 21513540260SHans Petter Selasky (a) + (sc)->sc_##what##_off) 21613540260SHans Petter Selasky #define XREAD4(sc, what, a) \ 21713540260SHans Petter Selasky bus_space_read_4((sc)->sc_io_tag, (sc)->sc_io_hdl, \ 21813540260SHans Petter Selasky (a) + (sc)->sc_##what##_off) 21913540260SHans Petter Selasky #define XWRITE1(sc, what, a, x) \ 22013540260SHans Petter Selasky bus_space_write_1((sc)->sc_io_tag, (sc)->sc_io_hdl, \ 22113540260SHans Petter Selasky (a) + (sc)->sc_##what##_off, (x)) 22213540260SHans Petter Selasky #define XWRITE2(sc, what, a, x) \ 22313540260SHans Petter Selasky bus_space_write_2((sc)->sc_io_tag, (sc)->sc_io_hdl, \ 22413540260SHans Petter Selasky (a) + (sc)->sc_##what##_off, (x)) 22513540260SHans Petter Selasky #define XWRITE4(sc, what, a, x) \ 22613540260SHans Petter Selasky bus_space_write_4((sc)->sc_io_tag, (sc)->sc_io_hdl, \ 22713540260SHans Petter Selasky (a) + (sc)->sc_##what##_off, (x)) 22813540260SHans Petter Selasky 22913540260SHans Petter Selasky #endif /* _XHCIREG_H_ */ 230