xref: /freebsd/sys/dev/usb/net/if_axe.c (revision 2b833162)
1 /*-
2  * SPDX-License-Identifier: BSD-4-Clause
3  *
4  * Copyright (c) 1997, 1998, 1999, 2000-2003
5  *	Bill Paul <wpaul@windriver.com>.  All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  * 3. All advertising materials mentioning features or use of this software
16  *    must display the following acknowledgement:
17  *	This product includes software developed by Bill Paul.
18  * 4. Neither the name of the author nor the names of any co-contributors
19  *    may be used to endorse or promote products derived from this software
20  *    without specific prior written permission.
21  *
22  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
23  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
26  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
32  * THE POSSIBILITY OF SUCH DAMAGE.
33  */
34 
35 #include <sys/cdefs.h>
36 __FBSDID("$FreeBSD$");
37 
38 /*
39  * ASIX Electronics AX88172/AX88178/AX88778 USB 2.0 ethernet driver.
40  * Used in the LinkSys USB200M and various other adapters.
41  *
42  * Manuals available from:
43  * http://www.asix.com.tw/datasheet/mac/Ax88172.PDF
44  * Note: you need the manual for the AX88170 chip (USB 1.x ethernet
45  * controller) to find the definitions for the RX control register.
46  * http://www.asix.com.tw/datasheet/mac/Ax88170.PDF
47  *
48  * Written by Bill Paul <wpaul@windriver.com>
49  * Senior Engineer
50  * Wind River Systems
51  */
52 
53 /*
54  * The AX88172 provides USB ethernet supports at 10 and 100Mbps.
55  * It uses an external PHY (reference designs use a RealTek chip),
56  * and has a 64-bit multicast hash filter. There is some information
57  * missing from the manual which one needs to know in order to make
58  * the chip function:
59  *
60  * - You must set bit 7 in the RX control register, otherwise the
61  *   chip won't receive any packets.
62  * - You must initialize all 3 IPG registers, or you won't be able
63  *   to send any packets.
64  *
65  * Note that this device appears to only support loading the station
66  * address via autload from the EEPROM (i.e. there's no way to manually
67  * set it).
68  *
69  * (Adam Weinberger wanted me to name this driver if_gir.c.)
70  */
71 
72 /*
73  * Ax88178 and Ax88772 support backported from the OpenBSD driver.
74  * 2007/02/12, J.R. Oldroyd, fbsd@opal.com
75  *
76  * Manual here:
77  * http://www.asix.com.tw/FrootAttach/datasheet/AX88178_datasheet_Rev10.pdf
78  * http://www.asix.com.tw/FrootAttach/datasheet/AX88772_datasheet_Rev10.pdf
79  */
80 
81 #include <sys/param.h>
82 #include <sys/systm.h>
83 #include <sys/bus.h>
84 #include <sys/condvar.h>
85 #include <sys/endian.h>
86 #include <sys/kernel.h>
87 #include <sys/lock.h>
88 #include <sys/malloc.h>
89 #include <sys/mbuf.h>
90 #include <sys/module.h>
91 #include <sys/mutex.h>
92 #include <sys/socket.h>
93 #include <sys/sockio.h>
94 #include <sys/sysctl.h>
95 #include <sys/sx.h>
96 
97 #include <net/if.h>
98 #include <net/if_var.h>
99 #include <net/ethernet.h>
100 #include <net/if_types.h>
101 #include <net/if_media.h>
102 #include <net/if_vlan_var.h>
103 
104 #include <dev/mii/mii.h>
105 #include <dev/mii/miivar.h>
106 
107 #include <dev/usb/usb.h>
108 #include <dev/usb/usbdi.h>
109 #include <dev/usb/usbdi_util.h>
110 #include "usbdevs.h"
111 
112 #define	USB_DEBUG_VAR axe_debug
113 #include <dev/usb/usb_debug.h>
114 #include <dev/usb/usb_process.h>
115 
116 #include <dev/usb/net/usb_ethernet.h>
117 #include <dev/usb/net/if_axereg.h>
118 
119 #include "miibus_if.h"
120 
121 /*
122  * AXE_178_MAX_FRAME_BURST
123  * max frame burst size for Ax88178 and Ax88772
124  *	0	2048 bytes
125  *	1	4096 bytes
126  *	2	8192 bytes
127  *	3	16384 bytes
128  * use the largest your system can handle without USB stalling.
129  *
130  * NB: 88772 parts appear to generate lots of input errors with
131  * a 2K rx buffer and 8K is only slightly faster than 4K on an
132  * EHCI port on a T42 so change at your own risk.
133  */
134 #define AXE_178_MAX_FRAME_BURST	1
135 
136 #define	AXE_CSUM_FEATURES	(CSUM_IP | CSUM_TCP | CSUM_UDP)
137 
138 #ifdef USB_DEBUG
139 static int axe_debug = 0;
140 
141 static SYSCTL_NODE(_hw_usb, OID_AUTO, axe, CTLFLAG_RW | CTLFLAG_MPSAFE, 0,
142     "USB axe");
143 SYSCTL_INT(_hw_usb_axe, OID_AUTO, debug, CTLFLAG_RWTUN, &axe_debug, 0,
144     "Debug level");
145 #endif
146 
147 /*
148  * Various supported device vendors/products.
149  */
150 static const STRUCT_USB_HOST_ID axe_devs[] = {
151 #define	AXE_DEV(v,p,i) { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, i) }
152 	AXE_DEV(ABOCOM, UF200, 0),
153 	AXE_DEV(ACERCM, EP1427X2, 0),
154 	AXE_DEV(APPLE, ETHERNET, AXE_FLAG_772),
155 	AXE_DEV(ASIX, AX88172, 0),
156 	AXE_DEV(ASIX, AX88178, AXE_FLAG_178),
157 	AXE_DEV(ASIX, AX88772, AXE_FLAG_772),
158 	AXE_DEV(ASIX, AX88772A, AXE_FLAG_772A),
159 	AXE_DEV(ASIX, AX88772B, AXE_FLAG_772B),
160 	AXE_DEV(ASIX, AX88772B_1, AXE_FLAG_772B),
161 	AXE_DEV(ATEN, UC210T, 0),
162 	AXE_DEV(BELKIN, F5D5055, AXE_FLAG_178),
163 	AXE_DEV(BILLIONTON, USB2AR, 0),
164 	AXE_DEV(CISCOLINKSYS, USB200MV2, AXE_FLAG_772A),
165 	AXE_DEV(COREGA, FETHER_USB2_TX, 0),
166 	AXE_DEV(DLINK, DUBE100, 0),
167 	AXE_DEV(DLINK, DUBE100B1, AXE_FLAG_772),
168 	AXE_DEV(DLINK, DUBE100C1, AXE_FLAG_772B),
169 	AXE_DEV(GOODWAY, GWUSB2E, 0),
170 	AXE_DEV(IODATA, ETGUS2, AXE_FLAG_178),
171 	AXE_DEV(JVC, MP_PRX1, 0),
172 	AXE_DEV(LENOVO, ETHERNET, AXE_FLAG_772B),
173 	AXE_DEV(LINKSYS2, USB200M, 0),
174 	AXE_DEV(LINKSYS4, USB1000, AXE_FLAG_178),
175 	AXE_DEV(LOGITEC, LAN_GTJU2A, AXE_FLAG_178),
176 	AXE_DEV(MELCO, LUAU2KTX, 0),
177 	AXE_DEV(MELCO, LUA3U2AGT, AXE_FLAG_178),
178 	AXE_DEV(NETGEAR, FA120, 0),
179 	AXE_DEV(OQO, ETHER01PLUS, AXE_FLAG_772),
180 	AXE_DEV(PLANEX3, GU1000T, AXE_FLAG_178),
181 	AXE_DEV(SITECOM, LN029, 0),
182 	AXE_DEV(SITECOMEU, LN028, AXE_FLAG_178),
183 	AXE_DEV(SITECOMEU, LN031, AXE_FLAG_178),
184 	AXE_DEV(SYSTEMTALKS, SGCX2UL, 0),
185 #undef AXE_DEV
186 };
187 
188 static device_probe_t axe_probe;
189 static device_attach_t axe_attach;
190 static device_detach_t axe_detach;
191 
192 static usb_callback_t axe_bulk_read_callback;
193 static usb_callback_t axe_bulk_write_callback;
194 
195 static miibus_readreg_t axe_miibus_readreg;
196 static miibus_writereg_t axe_miibus_writereg;
197 static miibus_statchg_t axe_miibus_statchg;
198 
199 static uether_fn_t axe_attach_post;
200 static uether_fn_t axe_init;
201 static uether_fn_t axe_stop;
202 static uether_fn_t axe_start;
203 static uether_fn_t axe_tick;
204 static uether_fn_t axe_setmulti;
205 static uether_fn_t axe_setpromisc;
206 
207 static int	axe_attach_post_sub(struct usb_ether *);
208 static int	axe_ifmedia_upd(if_t);
209 static void	axe_ifmedia_sts(if_t, struct ifmediareq *);
210 static int	axe_cmd(struct axe_softc *, int, int, int, void *);
211 static void	axe_ax88178_init(struct axe_softc *);
212 static void	axe_ax88772_init(struct axe_softc *);
213 static void	axe_ax88772_phywake(struct axe_softc *);
214 static void	axe_ax88772a_init(struct axe_softc *);
215 static void	axe_ax88772b_init(struct axe_softc *);
216 static int	axe_get_phyno(struct axe_softc *, int);
217 static int	axe_ioctl(if_t, u_long, caddr_t);
218 static int	axe_rx_frame(struct usb_ether *, struct usb_page_cache *, int);
219 static int	axe_rxeof(struct usb_ether *, struct usb_page_cache *,
220 		    unsigned offset, unsigned, struct axe_csum_hdr *);
221 static void	axe_csum_cfg(struct usb_ether *);
222 
223 static const struct usb_config axe_config[AXE_N_TRANSFER] = {
224 	[AXE_BULK_DT_WR] = {
225 		.type = UE_BULK,
226 		.endpoint = UE_ADDR_ANY,
227 		.direction = UE_DIR_OUT,
228 		.frames = 16,
229 		.bufsize = 16 * MCLBYTES,
230 		.flags = {.pipe_bof = 1,.force_short_xfer = 1,},
231 		.callback = axe_bulk_write_callback,
232 		.timeout = 10000,	/* 10 seconds */
233 	},
234 
235 	[AXE_BULK_DT_RD] = {
236 		.type = UE_BULK,
237 		.endpoint = UE_ADDR_ANY,
238 		.direction = UE_DIR_IN,
239 		.bufsize = 16384,	/* bytes */
240 		.flags = {.pipe_bof = 1,.short_xfer_ok = 1,},
241 		.callback = axe_bulk_read_callback,
242 		.timeout = 0,	/* no timeout */
243 	},
244 };
245 
246 static const struct ax88772b_mfb ax88772b_mfb_table[] = {
247 	{ 0x8000, 0x8001, 2048 },
248 	{ 0x8100, 0x8147, 4096},
249 	{ 0x8200, 0x81EB, 6144},
250 	{ 0x8300, 0x83D7, 8192},
251 	{ 0x8400, 0x851E, 16384},
252 	{ 0x8500, 0x8666, 20480},
253 	{ 0x8600, 0x87AE, 24576},
254 	{ 0x8700, 0x8A3D, 32768}
255 };
256 
257 static device_method_t axe_methods[] = {
258 	/* Device interface */
259 	DEVMETHOD(device_probe, axe_probe),
260 	DEVMETHOD(device_attach, axe_attach),
261 	DEVMETHOD(device_detach, axe_detach),
262 
263 	/* MII interface */
264 	DEVMETHOD(miibus_readreg, axe_miibus_readreg),
265 	DEVMETHOD(miibus_writereg, axe_miibus_writereg),
266 	DEVMETHOD(miibus_statchg, axe_miibus_statchg),
267 
268 	DEVMETHOD_END
269 };
270 
271 static driver_t axe_driver = {
272 	.name = "axe",
273 	.methods = axe_methods,
274 	.size = sizeof(struct axe_softc),
275 };
276 
277 DRIVER_MODULE(axe, uhub, axe_driver, NULL, NULL);
278 DRIVER_MODULE(miibus, axe, miibus_driver, 0, 0);
279 MODULE_DEPEND(axe, uether, 1, 1, 1);
280 MODULE_DEPEND(axe, usb, 1, 1, 1);
281 MODULE_DEPEND(axe, ether, 1, 1, 1);
282 MODULE_DEPEND(axe, miibus, 1, 1, 1);
283 MODULE_VERSION(axe, 1);
284 USB_PNP_HOST_INFO(axe_devs);
285 
286 static const struct usb_ether_methods axe_ue_methods = {
287 	.ue_attach_post = axe_attach_post,
288 	.ue_attach_post_sub = axe_attach_post_sub,
289 	.ue_start = axe_start,
290 	.ue_init = axe_init,
291 	.ue_stop = axe_stop,
292 	.ue_tick = axe_tick,
293 	.ue_setmulti = axe_setmulti,
294 	.ue_setpromisc = axe_setpromisc,
295 	.ue_mii_upd = axe_ifmedia_upd,
296 	.ue_mii_sts = axe_ifmedia_sts,
297 };
298 
299 static int
300 axe_cmd(struct axe_softc *sc, int cmd, int index, int val, void *buf)
301 {
302 	struct usb_device_request req;
303 	usb_error_t err;
304 
305 	AXE_LOCK_ASSERT(sc, MA_OWNED);
306 
307 	req.bmRequestType = (AXE_CMD_IS_WRITE(cmd) ?
308 	    UT_WRITE_VENDOR_DEVICE :
309 	    UT_READ_VENDOR_DEVICE);
310 	req.bRequest = AXE_CMD_CMD(cmd);
311 	USETW(req.wValue, val);
312 	USETW(req.wIndex, index);
313 	USETW(req.wLength, AXE_CMD_LEN(cmd));
314 
315 	err = uether_do_request(&sc->sc_ue, &req, buf, 1000);
316 
317 	return (err);
318 }
319 
320 static int
321 axe_miibus_readreg(device_t dev, int phy, int reg)
322 {
323 	struct axe_softc *sc = device_get_softc(dev);
324 	uint16_t val;
325 	int locked;
326 
327 	locked = mtx_owned(&sc->sc_mtx);
328 	if (!locked)
329 		AXE_LOCK(sc);
330 
331 	axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL);
332 	axe_cmd(sc, AXE_CMD_MII_READ_REG, reg, phy, &val);
333 	axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL);
334 
335 	val = le16toh(val);
336 	if (AXE_IS_772(sc) && reg == MII_BMSR) {
337 		/*
338 		 * BMSR of AX88772 indicates that it supports extended
339 		 * capability but the extended status register is
340 		 * revered for embedded ethernet PHY. So clear the
341 		 * extended capability bit of BMSR.
342 		 */
343 		val &= ~BMSR_EXTCAP;
344 	}
345 
346 	if (!locked)
347 		AXE_UNLOCK(sc);
348 	return (val);
349 }
350 
351 static int
352 axe_miibus_writereg(device_t dev, int phy, int reg, int val)
353 {
354 	struct axe_softc *sc = device_get_softc(dev);
355 	int locked;
356 
357 	val = htole32(val);
358 	locked = mtx_owned(&sc->sc_mtx);
359 	if (!locked)
360 		AXE_LOCK(sc);
361 
362 	axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL);
363 	axe_cmd(sc, AXE_CMD_MII_WRITE_REG, reg, phy, &val);
364 	axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL);
365 
366 	if (!locked)
367 		AXE_UNLOCK(sc);
368 	return (0);
369 }
370 
371 static void
372 axe_miibus_statchg(device_t dev)
373 {
374 	struct axe_softc *sc = device_get_softc(dev);
375 	struct mii_data *mii = GET_MII(sc);
376 	if_t ifp;
377 	uint16_t val;
378 	int err, locked;
379 
380 	locked = mtx_owned(&sc->sc_mtx);
381 	if (!locked)
382 		AXE_LOCK(sc);
383 
384 	ifp = uether_getifp(&sc->sc_ue);
385 	if (mii == NULL || ifp == NULL ||
386 	    (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0)
387 		goto done;
388 
389 	sc->sc_flags &= ~AXE_FLAG_LINK;
390 	if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
391 	    (IFM_ACTIVE | IFM_AVALID)) {
392 		switch (IFM_SUBTYPE(mii->mii_media_active)) {
393 		case IFM_10_T:
394 		case IFM_100_TX:
395 			sc->sc_flags |= AXE_FLAG_LINK;
396 			break;
397 		case IFM_1000_T:
398 			if ((sc->sc_flags & AXE_FLAG_178) == 0)
399 				break;
400 			sc->sc_flags |= AXE_FLAG_LINK;
401 			break;
402 		default:
403 			break;
404 		}
405 	}
406 
407 	/* Lost link, do nothing. */
408 	if ((sc->sc_flags & AXE_FLAG_LINK) == 0)
409 		goto done;
410 
411 	val = 0;
412 	if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
413 		val |= AXE_MEDIA_FULL_DUPLEX;
414 		if (AXE_IS_178_FAMILY(sc)) {
415 			if ((IFM_OPTIONS(mii->mii_media_active) &
416 			    IFM_ETH_TXPAUSE) != 0)
417 				val |= AXE_178_MEDIA_TXFLOW_CONTROL_EN;
418 			if ((IFM_OPTIONS(mii->mii_media_active) &
419 			    IFM_ETH_RXPAUSE) != 0)
420 				val |= AXE_178_MEDIA_RXFLOW_CONTROL_EN;
421 		}
422 	}
423 	if (AXE_IS_178_FAMILY(sc)) {
424 		val |= AXE_178_MEDIA_RX_EN | AXE_178_MEDIA_MAGIC;
425 		if ((sc->sc_flags & AXE_FLAG_178) != 0)
426 			val |= AXE_178_MEDIA_ENCK;
427 		switch (IFM_SUBTYPE(mii->mii_media_active)) {
428 		case IFM_1000_T:
429 			val |= AXE_178_MEDIA_GMII | AXE_178_MEDIA_ENCK;
430 			break;
431 		case IFM_100_TX:
432 			val |= AXE_178_MEDIA_100TX;
433 			break;
434 		case IFM_10_T:
435 			/* doesn't need to be handled */
436 			break;
437 		}
438 	}
439 	err = axe_cmd(sc, AXE_CMD_WRITE_MEDIA, 0, val, NULL);
440 	if (err)
441 		device_printf(dev, "media change failed, error %d\n", err);
442 done:
443 	if (!locked)
444 		AXE_UNLOCK(sc);
445 }
446 
447 /*
448  * Set media options.
449  */
450 static int
451 axe_ifmedia_upd(if_t ifp)
452 {
453 	struct axe_softc *sc = if_getsoftc(ifp);
454 	struct mii_data *mii = GET_MII(sc);
455 	struct mii_softc *miisc;
456 	int error;
457 
458 	AXE_LOCK_ASSERT(sc, MA_OWNED);
459 
460 	LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
461 		PHY_RESET(miisc);
462 	error = mii_mediachg(mii);
463 	return (error);
464 }
465 
466 /*
467  * Report current media status.
468  */
469 static void
470 axe_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr)
471 {
472 	struct axe_softc *sc = if_getsoftc(ifp);
473 	struct mii_data *mii = GET_MII(sc);
474 
475 	AXE_LOCK(sc);
476 	mii_pollstat(mii);
477 	ifmr->ifm_active = mii->mii_media_active;
478 	ifmr->ifm_status = mii->mii_media_status;
479 	AXE_UNLOCK(sc);
480 }
481 
482 static u_int
483 axe_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
484 {
485 	uint8_t *hashtbl = arg;
486 	uint32_t h;
487 
488 	h = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN) >> 26;
489 	hashtbl[h / 8] |= 1 << (h % 8);
490 
491 	return (1);
492 }
493 
494 static void
495 axe_setmulti(struct usb_ether *ue)
496 {
497 	struct axe_softc *sc = uether_getsc(ue);
498 	if_t ifp = uether_getifp(ue);
499 	uint16_t rxmode;
500 	uint8_t hashtbl[8] = { 0, 0, 0, 0, 0, 0, 0, 0 };
501 
502 	AXE_LOCK_ASSERT(sc, MA_OWNED);
503 
504 	axe_cmd(sc, AXE_CMD_RXCTL_READ, 0, 0, &rxmode);
505 	rxmode = le16toh(rxmode);
506 
507 	if (if_getflags(ifp) & (IFF_ALLMULTI | IFF_PROMISC)) {
508 		rxmode |= AXE_RXCMD_ALLMULTI;
509 		axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL);
510 		return;
511 	}
512 	rxmode &= ~AXE_RXCMD_ALLMULTI;
513 
514 	if_foreach_llmaddr(ifp, axe_hash_maddr, &hashtbl);
515 
516 	axe_cmd(sc, AXE_CMD_WRITE_MCAST, 0, 0, (void *)&hashtbl);
517 	axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL);
518 }
519 
520 static int
521 axe_get_phyno(struct axe_softc *sc, int sel)
522 {
523 	int phyno;
524 
525 	switch (AXE_PHY_TYPE(sc->sc_phyaddrs[sel])) {
526 	case PHY_TYPE_100_HOME:
527 	case PHY_TYPE_GIG:
528 		phyno = AXE_PHY_NO(sc->sc_phyaddrs[sel]);
529 		break;
530 	case PHY_TYPE_SPECIAL:
531 		/* FALLTHROUGH */
532 	case PHY_TYPE_RSVD:
533 		/* FALLTHROUGH */
534 	case PHY_TYPE_NON_SUP:
535 		/* FALLTHROUGH */
536 	default:
537 		phyno = -1;
538 		break;
539 	}
540 
541 	return (phyno);
542 }
543 
544 #define	AXE_GPIO_WRITE(x, y)	do {				\
545 	axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, (x), NULL);		\
546 	uether_pause(ue, (y));					\
547 } while (0)
548 
549 static void
550 axe_ax88178_init(struct axe_softc *sc)
551 {
552 	struct usb_ether *ue;
553 	int gpio0, ledmode, phymode;
554 	uint16_t eeprom, val;
555 
556 	ue = &sc->sc_ue;
557 	axe_cmd(sc, AXE_CMD_SROM_WR_ENABLE, 0, 0, NULL);
558 	/* XXX magic */
559 	axe_cmd(sc, AXE_CMD_SROM_READ, 0, 0x0017, &eeprom);
560 	eeprom = le16toh(eeprom);
561 	axe_cmd(sc, AXE_CMD_SROM_WR_DISABLE, 0, 0, NULL);
562 
563 	/* if EEPROM is invalid we have to use to GPIO0 */
564 	if (eeprom == 0xffff) {
565 		phymode = AXE_PHY_MODE_MARVELL;
566 		gpio0 = 1;
567 		ledmode = 0;
568 	} else {
569 		phymode = eeprom & 0x7f;
570 		gpio0 = (eeprom & 0x80) ? 0 : 1;
571 		ledmode = eeprom >> 8;
572 	}
573 
574 	if (bootverbose)
575 		device_printf(sc->sc_ue.ue_dev,
576 		    "EEPROM data : 0x%04x, phymode : 0x%02x\n", eeprom,
577 		    phymode);
578 	/* Program GPIOs depending on PHY hardware. */
579 	switch (phymode) {
580 	case AXE_PHY_MODE_MARVELL:
581 		if (gpio0 == 1) {
582 			AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO0_EN,
583 			    hz / 32);
584 			AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN,
585 			    hz / 32);
586 			AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2_EN, hz / 4);
587 			AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN,
588 			    hz / 32);
589 		} else {
590 			AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 |
591 			    AXE_GPIO1_EN, hz / 3);
592 			if (ledmode == 1) {
593 				AXE_GPIO_WRITE(AXE_GPIO1_EN, hz / 3);
594 				AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN,
595 				    hz / 3);
596 			} else {
597 				AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN |
598 				    AXE_GPIO2 | AXE_GPIO2_EN, hz / 32);
599 				AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN |
600 				    AXE_GPIO2_EN, hz / 4);
601 				AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN |
602 				    AXE_GPIO2 | AXE_GPIO2_EN, hz / 32);
603 			}
604 		}
605 		break;
606 	case AXE_PHY_MODE_CICADA:
607 	case AXE_PHY_MODE_CICADA_V2:
608 	case AXE_PHY_MODE_CICADA_V2_ASIX:
609 		if (gpio0 == 1)
610 			AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO0 |
611 			    AXE_GPIO0_EN, hz / 32);
612 		else
613 			AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 |
614 			    AXE_GPIO1_EN, hz / 32);
615 		break;
616 	case AXE_PHY_MODE_AGERE:
617 		AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 |
618 		    AXE_GPIO1_EN, hz / 32);
619 		AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 |
620 		    AXE_GPIO2_EN, hz / 32);
621 		AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2_EN, hz / 4);
622 		AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 |
623 		    AXE_GPIO2_EN, hz / 32);
624 		break;
625 	case AXE_PHY_MODE_REALTEK_8211CL:
626 	case AXE_PHY_MODE_REALTEK_8211BN:
627 	case AXE_PHY_MODE_REALTEK_8251CL:
628 		val = gpio0 == 1 ? AXE_GPIO0 | AXE_GPIO0_EN :
629 		    AXE_GPIO1 | AXE_GPIO1_EN;
630 		AXE_GPIO_WRITE(val, hz / 32);
631 		AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32);
632 		AXE_GPIO_WRITE(val | AXE_GPIO2_EN, hz / 4);
633 		AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32);
634 		if (phymode == AXE_PHY_MODE_REALTEK_8211CL) {
635 			axe_miibus_writereg(ue->ue_dev, sc->sc_phyno,
636 			    0x1F, 0x0005);
637 			axe_miibus_writereg(ue->ue_dev, sc->sc_phyno,
638 			    0x0C, 0x0000);
639 			val = axe_miibus_readreg(ue->ue_dev, sc->sc_phyno,
640 			    0x0001);
641 			axe_miibus_writereg(ue->ue_dev, sc->sc_phyno,
642 			    0x01, val | 0x0080);
643 			axe_miibus_writereg(ue->ue_dev, sc->sc_phyno,
644 			    0x1F, 0x0000);
645 		}
646 		break;
647 	default:
648 		/* Unknown PHY model or no need to program GPIOs. */
649 		break;
650 	}
651 
652 	/* soft reset */
653 	axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL);
654 	uether_pause(ue, hz / 4);
655 
656 	axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0,
657 	    AXE_SW_RESET_PRL | AXE_178_RESET_MAGIC, NULL);
658 	uether_pause(ue, hz / 4);
659 	/* Enable MII/GMII/RGMII interface to work with external PHY. */
660 	axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0, NULL);
661 	uether_pause(ue, hz / 4);
662 
663 	axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL);
664 }
665 
666 static void
667 axe_ax88772_init(struct axe_softc *sc)
668 {
669 	axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, 0x00b0, NULL);
670 	uether_pause(&sc->sc_ue, hz / 16);
671 
672 	if (sc->sc_phyno == AXE_772_PHY_NO_EPHY) {
673 		/* ask for the embedded PHY */
674 		axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0x01, NULL);
675 		uether_pause(&sc->sc_ue, hz / 64);
676 
677 		/* power down and reset state, pin reset state */
678 		axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0,
679 		    AXE_SW_RESET_CLEAR, NULL);
680 		uether_pause(&sc->sc_ue, hz / 16);
681 
682 		/* power down/reset state, pin operating state */
683 		axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0,
684 		    AXE_SW_RESET_IPPD | AXE_SW_RESET_PRL, NULL);
685 		uether_pause(&sc->sc_ue, hz / 4);
686 
687 		/* power up, reset */
688 		axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_PRL, NULL);
689 
690 		/* power up, operating */
691 		axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0,
692 		    AXE_SW_RESET_IPRL | AXE_SW_RESET_PRL, NULL);
693 	} else {
694 		/* ask for external PHY */
695 		axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0x00, NULL);
696 		uether_pause(&sc->sc_ue, hz / 64);
697 
698 		/* power down internal PHY */
699 		axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0,
700 		    AXE_SW_RESET_IPPD | AXE_SW_RESET_PRL, NULL);
701 	}
702 
703 	uether_pause(&sc->sc_ue, hz / 4);
704 	axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL);
705 }
706 
707 static void
708 axe_ax88772_phywake(struct axe_softc *sc)
709 {
710 	if (sc->sc_phyno == AXE_772_PHY_NO_EPHY) {
711 		/* Manually select internal(embedded) PHY - MAC mode. */
712 		axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, AXE_SW_PHY_SELECT_SS_ENB |
713 		    AXE_SW_PHY_SELECT_EMBEDDED | AXE_SW_PHY_SELECT_SS_MII,
714 		    NULL);
715 		uether_pause(&sc->sc_ue, hz / 32);
716 	} else {
717 		/*
718 		 * Manually select external PHY - MAC mode.
719 		 * Reverse MII/RMII is for AX88772A PHY mode.
720 		 */
721 		axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, AXE_SW_PHY_SELECT_SS_ENB |
722 		    AXE_SW_PHY_SELECT_EXT | AXE_SW_PHY_SELECT_SS_MII, NULL);
723 		uether_pause(&sc->sc_ue, hz / 32);
724 	}
725 	/* Take PHY out of power down. */
726 	axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPPD |
727 	    AXE_SW_RESET_IPRL, NULL);
728 	uether_pause(&sc->sc_ue, hz / 4);
729 	axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPRL, NULL);
730 	uether_pause(&sc->sc_ue, hz);
731 	axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL);
732 	uether_pause(&sc->sc_ue, hz / 32);
733 	axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPRL, NULL);
734 	uether_pause(&sc->sc_ue, hz / 32);
735 }
736 
737 static void
738 axe_ax88772a_init(struct axe_softc *sc)
739 {
740 	struct usb_ether *ue;
741 
742 	ue = &sc->sc_ue;
743 	/* Reload EEPROM. */
744 	AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM, hz / 32);
745 	axe_ax88772_phywake(sc);
746 	/* Stop MAC. */
747 	axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL);
748 }
749 
750 static void
751 axe_ax88772b_init(struct axe_softc *sc)
752 {
753 	struct usb_ether *ue;
754 	uint16_t eeprom;
755 	uint8_t *eaddr;
756 	int i;
757 
758 	ue = &sc->sc_ue;
759 	/* Reload EEPROM. */
760 	AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM, hz / 32);
761 	/*
762 	 * Save PHY power saving configuration(high byte) and
763 	 * clear EEPROM checksum value(low byte).
764 	 */
765 	axe_cmd(sc, AXE_CMD_SROM_READ, 0, AXE_EEPROM_772B_PHY_PWRCFG, &eeprom);
766 	sc->sc_pwrcfg = le16toh(eeprom) & 0xFF00;
767 
768 	/*
769 	 * Auto-loaded default station address from internal ROM is
770 	 * 00:00:00:00:00:00 such that an explicit access to EEPROM
771 	 * is required to get real station address.
772 	 */
773 	eaddr = ue->ue_eaddr;
774 	for (i = 0; i < ETHER_ADDR_LEN / 2; i++) {
775 		axe_cmd(sc, AXE_CMD_SROM_READ, 0, AXE_EEPROM_772B_NODE_ID + i,
776 		    &eeprom);
777 		eeprom = le16toh(eeprom);
778 		*eaddr++ = (uint8_t)(eeprom & 0xFF);
779 		*eaddr++ = (uint8_t)((eeprom >> 8) & 0xFF);
780 	}
781 	/* Wakeup PHY. */
782 	axe_ax88772_phywake(sc);
783 	/* Stop MAC. */
784 	axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL);
785 }
786 
787 #undef	AXE_GPIO_WRITE
788 
789 static void
790 axe_reset(struct axe_softc *sc)
791 {
792 	struct usb_config_descriptor *cd;
793 	usb_error_t err;
794 
795 	cd = usbd_get_config_descriptor(sc->sc_ue.ue_udev);
796 
797 	err = usbd_req_set_config(sc->sc_ue.ue_udev, &sc->sc_mtx,
798 	    cd->bConfigurationValue);
799 	if (err)
800 		DPRINTF("reset failed (ignored)\n");
801 
802 	/* Wait a little while for the chip to get its brains in order. */
803 	uether_pause(&sc->sc_ue, hz / 100);
804 
805 	/* Reinitialize controller to achieve full reset. */
806 	if (sc->sc_flags & AXE_FLAG_178)
807 		axe_ax88178_init(sc);
808 	else if (sc->sc_flags & AXE_FLAG_772)
809 		axe_ax88772_init(sc);
810 	else if (sc->sc_flags & AXE_FLAG_772A)
811 		axe_ax88772a_init(sc);
812 	else if (sc->sc_flags & AXE_FLAG_772B)
813 		axe_ax88772b_init(sc);
814 }
815 
816 static void
817 axe_attach_post(struct usb_ether *ue)
818 {
819 	struct axe_softc *sc = uether_getsc(ue);
820 
821 	/*
822 	 * Load PHY indexes first. Needed by axe_xxx_init().
823 	 */
824 	axe_cmd(sc, AXE_CMD_READ_PHYID, 0, 0, sc->sc_phyaddrs);
825 	if (bootverbose)
826 		device_printf(sc->sc_ue.ue_dev, "PHYADDR 0x%02x:0x%02x\n",
827 		    sc->sc_phyaddrs[0], sc->sc_phyaddrs[1]);
828 	sc->sc_phyno = axe_get_phyno(sc, AXE_PHY_SEL_PRI);
829 	if (sc->sc_phyno == -1)
830 		sc->sc_phyno = axe_get_phyno(sc, AXE_PHY_SEL_SEC);
831 	if (sc->sc_phyno == -1) {
832 		device_printf(sc->sc_ue.ue_dev,
833 		    "no valid PHY address found, assuming PHY address 0\n");
834 		sc->sc_phyno = 0;
835 	}
836 
837 	/* Initialize controller and get station address. */
838 	if (sc->sc_flags & AXE_FLAG_178) {
839 		axe_ax88178_init(sc);
840 		axe_cmd(sc, AXE_178_CMD_READ_NODEID, 0, 0, ue->ue_eaddr);
841 	} else if (sc->sc_flags & AXE_FLAG_772) {
842 		axe_ax88772_init(sc);
843 		axe_cmd(sc, AXE_178_CMD_READ_NODEID, 0, 0, ue->ue_eaddr);
844 	} else if (sc->sc_flags & AXE_FLAG_772A) {
845 		axe_ax88772a_init(sc);
846 		axe_cmd(sc, AXE_178_CMD_READ_NODEID, 0, 0, ue->ue_eaddr);
847 	} else if (sc->sc_flags & AXE_FLAG_772B) {
848 		axe_ax88772b_init(sc);
849 	} else
850 		axe_cmd(sc, AXE_172_CMD_READ_NODEID, 0, 0, ue->ue_eaddr);
851 
852 	/*
853 	 * Fetch IPG values.
854 	 */
855 	if (sc->sc_flags & (AXE_FLAG_772A | AXE_FLAG_772B)) {
856 		/* Set IPG values. */
857 		sc->sc_ipgs[0] = 0x15;
858 		sc->sc_ipgs[1] = 0x16;
859 		sc->sc_ipgs[2] = 0x1A;
860 	} else
861 		axe_cmd(sc, AXE_CMD_READ_IPG012, 0, 0, sc->sc_ipgs);
862 }
863 
864 static int
865 axe_attach_post_sub(struct usb_ether *ue)
866 {
867 	struct axe_softc *sc;
868 	if_t ifp;
869 	u_int adv_pause;
870 	int error;
871 
872 	sc = uether_getsc(ue);
873 	ifp = ue->ue_ifp;
874 	if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
875 	if_setstartfn(ifp, uether_start);
876 	if_setioctlfn(ifp, axe_ioctl);
877 	if_setinitfn(ifp, uether_init);
878 	if_setsendqlen(ifp, ifqmaxlen);
879 	if_setsendqready(ifp);
880 
881 	if (AXE_IS_178_FAMILY(sc))
882 		if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU, 0);
883 	if (sc->sc_flags & AXE_FLAG_772B) {
884 		if_setcapabilitiesbit(ifp, IFCAP_TXCSUM | IFCAP_RXCSUM, 0);
885 		if_sethwassist(ifp, AXE_CSUM_FEATURES);
886 		/*
887 		 * Checksum offloading of AX88772B also works with VLAN
888 		 * tagged frames but there is no way to take advantage
889 		 * of the feature because vlan(4) assumes
890 		 * IFCAP_VLAN_HWTAGGING is prerequisite condition to
891 		 * support checksum offloading with VLAN. VLAN hardware
892 		 * tagging support of AX88772B is very limited so it's
893 		 * not possible to announce IFCAP_VLAN_HWTAGGING.
894 		 */
895 	}
896 	if_setcapenable(ifp, if_getcapabilities(ifp));
897 	if (sc->sc_flags & (AXE_FLAG_772A | AXE_FLAG_772B | AXE_FLAG_178))
898 		adv_pause = MIIF_DOPAUSE;
899 	else
900 		adv_pause = 0;
901 	bus_topo_lock();
902 	error = mii_attach(ue->ue_dev, &ue->ue_miibus, ifp,
903 	    uether_ifmedia_upd, ue->ue_methods->ue_mii_sts,
904 	    BMSR_DEFCAPMASK, sc->sc_phyno, MII_OFFSET_ANY, adv_pause);
905 	bus_topo_unlock();
906 
907 	return (error);
908 }
909 
910 /*
911  * Probe for a AX88172 chip.
912  */
913 static int
914 axe_probe(device_t dev)
915 {
916 	struct usb_attach_arg *uaa = device_get_ivars(dev);
917 
918 	if (uaa->usb_mode != USB_MODE_HOST)
919 		return (ENXIO);
920 	if (uaa->info.bConfigIndex != AXE_CONFIG_IDX)
921 		return (ENXIO);
922 	if (uaa->info.bIfaceIndex != AXE_IFACE_IDX)
923 		return (ENXIO);
924 
925 	return (usbd_lookup_id_by_uaa(axe_devs, sizeof(axe_devs), uaa));
926 }
927 
928 /*
929  * Attach the interface. Allocate softc structures, do ifmedia
930  * setup and ethernet/BPF attach.
931  */
932 static int
933 axe_attach(device_t dev)
934 {
935 	struct usb_attach_arg *uaa = device_get_ivars(dev);
936 	struct axe_softc *sc = device_get_softc(dev);
937 	struct usb_ether *ue = &sc->sc_ue;
938 	uint8_t iface_index;
939 	int error;
940 
941 	sc->sc_flags = USB_GET_DRIVER_INFO(uaa);
942 
943 	device_set_usb_desc(dev);
944 
945 	mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_DEF);
946 
947 	iface_index = AXE_IFACE_IDX;
948 	error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer,
949 	    axe_config, AXE_N_TRANSFER, sc, &sc->sc_mtx);
950 	if (error) {
951 		device_printf(dev, "allocating USB transfers failed\n");
952 		goto detach;
953 	}
954 
955 	ue->ue_sc = sc;
956 	ue->ue_dev = dev;
957 	ue->ue_udev = uaa->device;
958 	ue->ue_mtx = &sc->sc_mtx;
959 	ue->ue_methods = &axe_ue_methods;
960 
961 	error = uether_ifattach(ue);
962 	if (error) {
963 		device_printf(dev, "could not attach interface\n");
964 		goto detach;
965 	}
966 	return (0);			/* success */
967 
968 detach:
969 	axe_detach(dev);
970 	return (ENXIO);			/* failure */
971 }
972 
973 static int
974 axe_detach(device_t dev)
975 {
976 	struct axe_softc *sc = device_get_softc(dev);
977 	struct usb_ether *ue = &sc->sc_ue;
978 
979 	usbd_transfer_unsetup(sc->sc_xfer, AXE_N_TRANSFER);
980 	uether_ifdetach(ue);
981 	mtx_destroy(&sc->sc_mtx);
982 
983 	return (0);
984 }
985 
986 #if (AXE_BULK_BUF_SIZE >= 0x10000)
987 #error "Please update axe_bulk_read_callback()!"
988 #endif
989 
990 static void
991 axe_bulk_read_callback(struct usb_xfer *xfer, usb_error_t error)
992 {
993 	struct axe_softc *sc = usbd_xfer_softc(xfer);
994 	struct usb_ether *ue = &sc->sc_ue;
995 	struct usb_page_cache *pc;
996 	int actlen;
997 
998 	usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL);
999 
1000 	switch (USB_GET_STATE(xfer)) {
1001 	case USB_ST_TRANSFERRED:
1002 		pc = usbd_xfer_get_frame(xfer, 0);
1003 		axe_rx_frame(ue, pc, actlen);
1004 
1005 		/* FALLTHROUGH */
1006 	case USB_ST_SETUP:
1007 tr_setup:
1008 		usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer));
1009 		usbd_transfer_submit(xfer);
1010 		uether_rxflush(ue);
1011 		return;
1012 
1013 	default:			/* Error */
1014 		DPRINTF("bulk read error, %s\n", usbd_errstr(error));
1015 
1016 		if (error != USB_ERR_CANCELLED) {
1017 			/* try to clear stall first */
1018 			usbd_xfer_set_stall(xfer);
1019 			goto tr_setup;
1020 		}
1021 		return;
1022 	}
1023 }
1024 
1025 static int
1026 axe_rx_frame(struct usb_ether *ue, struct usb_page_cache *pc, int actlen)
1027 {
1028 	struct axe_softc *sc;
1029 	struct axe_sframe_hdr hdr;
1030 	struct axe_csum_hdr csum_hdr;
1031 	int error, len, pos;
1032 
1033 	sc = uether_getsc(ue);
1034 	pos = 0;
1035 	len = 0;
1036 	error = 0;
1037 	if ((sc->sc_flags & AXE_FLAG_STD_FRAME) != 0) {
1038 		while (pos < actlen) {
1039 			if ((int)(pos + sizeof(hdr)) > actlen) {
1040 				/* too little data */
1041 				error = EINVAL;
1042 				break;
1043 			}
1044 			usbd_copy_out(pc, pos, &hdr, sizeof(hdr));
1045 
1046 			if ((hdr.len ^ hdr.ilen) != sc->sc_lenmask) {
1047 				/* we lost sync */
1048 				error = EINVAL;
1049 				break;
1050 			}
1051 			pos += sizeof(hdr);
1052 			len = le16toh(hdr.len);
1053 			if (pos + len > actlen) {
1054 				/* invalid length */
1055 				error = EINVAL;
1056 				break;
1057 			}
1058 			axe_rxeof(ue, pc, pos, len, NULL);
1059 			pos += len + (len % 2);
1060 		}
1061 	} else if ((sc->sc_flags & AXE_FLAG_CSUM_FRAME) != 0) {
1062 		while (pos < actlen) {
1063 			if ((int)(pos + sizeof(csum_hdr)) > actlen) {
1064 				/* too little data */
1065 				error = EINVAL;
1066 				break;
1067 			}
1068 			usbd_copy_out(pc, pos, &csum_hdr, sizeof(csum_hdr));
1069 
1070 			csum_hdr.len = le16toh(csum_hdr.len);
1071 			csum_hdr.ilen = le16toh(csum_hdr.ilen);
1072 			csum_hdr.cstatus = le16toh(csum_hdr.cstatus);
1073 			if ((AXE_CSUM_RXBYTES(csum_hdr.len) ^
1074 			    AXE_CSUM_RXBYTES(csum_hdr.ilen)) !=
1075 			    sc->sc_lenmask) {
1076 				/* we lost sync */
1077 				error = EINVAL;
1078 				break;
1079 			}
1080 			/*
1081 			 * Get total transferred frame length including
1082 			 * checksum header.  The length should be multiple
1083 			 * of 4.
1084 			 */
1085 			len = sizeof(csum_hdr) + AXE_CSUM_RXBYTES(csum_hdr.len);
1086 			len = (len + 3) & ~3;
1087 			if (pos + len > actlen) {
1088 				/* invalid length */
1089 				error = EINVAL;
1090 				break;
1091 			}
1092 			axe_rxeof(ue, pc, pos + sizeof(csum_hdr),
1093 			    AXE_CSUM_RXBYTES(csum_hdr.len), &csum_hdr);
1094 			pos += len;
1095 		}
1096 	} else
1097 		axe_rxeof(ue, pc, 0, actlen, NULL);
1098 
1099 	if (error != 0)
1100 		if_inc_counter(ue->ue_ifp, IFCOUNTER_IERRORS, 1);
1101 	return (error);
1102 }
1103 
1104 static int
1105 axe_rxeof(struct usb_ether *ue, struct usb_page_cache *pc, unsigned offset,
1106     unsigned len, struct axe_csum_hdr *csum_hdr)
1107 {
1108 	if_t ifp = ue->ue_ifp;
1109 	struct mbuf *m;
1110 
1111 	if (len < ETHER_HDR_LEN || len > MCLBYTES - ETHER_ALIGN) {
1112 		if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1113 		return (EINVAL);
1114 	}
1115 
1116 	m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
1117 	if (m == NULL) {
1118 		if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
1119 		return (ENOMEM);
1120 	}
1121 	m->m_len = m->m_pkthdr.len = MCLBYTES;
1122 	m_adj(m, ETHER_ALIGN);
1123 
1124 	usbd_copy_out(pc, offset, mtod(m, uint8_t *), len);
1125 
1126 	if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
1127 	m->m_pkthdr.rcvif = ifp;
1128 	m->m_pkthdr.len = m->m_len = len;
1129 
1130 	if (csum_hdr != NULL && csum_hdr->cstatus & AXE_CSUM_HDR_L3_TYPE_IPV4) {
1131 		if ((csum_hdr->cstatus & (AXE_CSUM_HDR_L4_CSUM_ERR |
1132 		    AXE_CSUM_HDR_L3_CSUM_ERR)) == 0) {
1133 			m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED |
1134 			    CSUM_IP_VALID;
1135 			if ((csum_hdr->cstatus & AXE_CSUM_HDR_L4_TYPE_MASK) ==
1136 			    AXE_CSUM_HDR_L4_TYPE_TCP ||
1137 			    (csum_hdr->cstatus & AXE_CSUM_HDR_L4_TYPE_MASK) ==
1138 			    AXE_CSUM_HDR_L4_TYPE_UDP) {
1139 				m->m_pkthdr.csum_flags |=
1140 				    CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
1141 				m->m_pkthdr.csum_data = 0xffff;
1142 			}
1143 		}
1144 	}
1145 
1146 	(void)mbufq_enqueue(&ue->ue_rxq, m);
1147 	return (0);
1148 }
1149 
1150 #if ((AXE_BULK_BUF_SIZE >= 0x10000) || (AXE_BULK_BUF_SIZE < (MCLBYTES+4)))
1151 #error "Please update axe_bulk_write_callback()!"
1152 #endif
1153 
1154 static void
1155 axe_bulk_write_callback(struct usb_xfer *xfer, usb_error_t error)
1156 {
1157 	struct axe_softc *sc = usbd_xfer_softc(xfer);
1158 	struct axe_sframe_hdr hdr;
1159 	if_t ifp = uether_getifp(&sc->sc_ue);
1160 	struct usb_page_cache *pc;
1161 	struct mbuf *m;
1162 	int nframes, pos;
1163 
1164 	switch (USB_GET_STATE(xfer)) {
1165 	case USB_ST_TRANSFERRED:
1166 		DPRINTFN(11, "transfer complete\n");
1167 		if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
1168 		/* FALLTHROUGH */
1169 	case USB_ST_SETUP:
1170 tr_setup:
1171 		if ((sc->sc_flags & AXE_FLAG_LINK) == 0 ||
1172 		    (if_getdrvflags(ifp) & IFF_DRV_OACTIVE) != 0) {
1173 			/*
1174 			 * Don't send anything if there is no link or
1175 			 * controller is busy.
1176 			 */
1177 			return;
1178 		}
1179 
1180 		for (nframes = 0; nframes < 16 &&
1181 		    !if_sendq_empty(ifp); nframes++) {
1182 			m = if_dequeue(ifp);
1183 			if (m == NULL)
1184 				break;
1185 			usbd_xfer_set_frame_offset(xfer, nframes * MCLBYTES,
1186 			    nframes);
1187 			pos = 0;
1188 			pc = usbd_xfer_get_frame(xfer, nframes);
1189 			if (AXE_IS_178_FAMILY(sc)) {
1190 				hdr.len = htole16(m->m_pkthdr.len);
1191 				hdr.ilen = ~hdr.len;
1192 				/*
1193 				 * If upper stack computed checksum, driver
1194 				 * should tell controller not to insert
1195 				 * computed checksum for checksum offloading
1196 				 * enabled controller.
1197 				 */
1198 				if (if_getcapabilities(ifp) & IFCAP_TXCSUM) {
1199 					if ((m->m_pkthdr.csum_flags &
1200 					    AXE_CSUM_FEATURES) != 0)
1201 						hdr.len |= htole16(
1202 						    AXE_TX_CSUM_PSEUDO_HDR);
1203 					else
1204 						hdr.len |= htole16(
1205 						    AXE_TX_CSUM_DIS);
1206 				}
1207 				usbd_copy_in(pc, pos, &hdr, sizeof(hdr));
1208 				pos += sizeof(hdr);
1209 				usbd_m_copy_in(pc, pos, m, 0, m->m_pkthdr.len);
1210 				pos += m->m_pkthdr.len;
1211 				if ((pos % 512) == 0) {
1212 					hdr.len = 0;
1213 					hdr.ilen = 0xffff;
1214 					usbd_copy_in(pc, pos, &hdr,
1215 					    sizeof(hdr));
1216 					pos += sizeof(hdr);
1217 				}
1218 			} else {
1219 				usbd_m_copy_in(pc, pos, m, 0, m->m_pkthdr.len);
1220 				pos += m->m_pkthdr.len;
1221 			}
1222 
1223 			/*
1224 			 * XXX
1225 			 * Update TX packet counter here. This is not
1226 			 * correct way but it seems that there is no way
1227 			 * to know how many packets are sent at the end
1228 			 * of transfer because controller combines
1229 			 * multiple writes into single one if there is
1230 			 * room in TX buffer of controller.
1231 			 */
1232 			if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
1233 
1234 			/*
1235 			 * if there's a BPF listener, bounce a copy
1236 			 * of this frame to him:
1237 			 */
1238 			BPF_MTAP(ifp, m);
1239 
1240 			m_freem(m);
1241 
1242 			/* Set frame length. */
1243 			usbd_xfer_set_frame_len(xfer, nframes, pos);
1244 		}
1245 		if (nframes != 0) {
1246 			usbd_xfer_set_frames(xfer, nframes);
1247 			usbd_transfer_submit(xfer);
1248 			if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0);
1249 		}
1250 		return;
1251 		/* NOTREACHED */
1252 	default:			/* Error */
1253 		DPRINTFN(11, "transfer error, %s\n",
1254 		    usbd_errstr(error));
1255 
1256 		if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1257 		if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
1258 
1259 		if (error != USB_ERR_CANCELLED) {
1260 			/* try to clear stall first */
1261 			usbd_xfer_set_stall(xfer);
1262 			goto tr_setup;
1263 		}
1264 		return;
1265 	}
1266 }
1267 
1268 static void
1269 axe_tick(struct usb_ether *ue)
1270 {
1271 	struct axe_softc *sc = uether_getsc(ue);
1272 	struct mii_data *mii = GET_MII(sc);
1273 
1274 	AXE_LOCK_ASSERT(sc, MA_OWNED);
1275 
1276 	mii_tick(mii);
1277 	if ((sc->sc_flags & AXE_FLAG_LINK) == 0) {
1278 		axe_miibus_statchg(ue->ue_dev);
1279 		if ((sc->sc_flags & AXE_FLAG_LINK) != 0)
1280 			axe_start(ue);
1281 	}
1282 }
1283 
1284 static void
1285 axe_start(struct usb_ether *ue)
1286 {
1287 	struct axe_softc *sc = uether_getsc(ue);
1288 
1289 	/*
1290 	 * start the USB transfers, if not already started:
1291 	 */
1292 	usbd_transfer_start(sc->sc_xfer[AXE_BULK_DT_RD]);
1293 	usbd_transfer_start(sc->sc_xfer[AXE_BULK_DT_WR]);
1294 }
1295 
1296 static void
1297 axe_csum_cfg(struct usb_ether *ue)
1298 {
1299 	struct axe_softc *sc;
1300 	if_t ifp;
1301 	uint16_t csum1, csum2;
1302 
1303 	sc = uether_getsc(ue);
1304 	AXE_LOCK_ASSERT(sc, MA_OWNED);
1305 
1306 	if ((sc->sc_flags & AXE_FLAG_772B) != 0) {
1307 		ifp = uether_getifp(ue);
1308 		csum1 = 0;
1309 		csum2 = 0;
1310 		if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0)
1311 			csum1 |= AXE_TXCSUM_IP | AXE_TXCSUM_TCP |
1312 			    AXE_TXCSUM_UDP;
1313 		axe_cmd(sc, AXE_772B_CMD_WRITE_TXCSUM, csum2, csum1, NULL);
1314 		csum1 = 0;
1315 		csum2 = 0;
1316 		if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0)
1317 			csum1 |= AXE_RXCSUM_IP | AXE_RXCSUM_IPVE |
1318 			    AXE_RXCSUM_TCP | AXE_RXCSUM_UDP | AXE_RXCSUM_ICMP |
1319 			    AXE_RXCSUM_IGMP;
1320 		axe_cmd(sc, AXE_772B_CMD_WRITE_RXCSUM, csum2, csum1, NULL);
1321 	}
1322 }
1323 
1324 static void
1325 axe_init(struct usb_ether *ue)
1326 {
1327 	struct axe_softc *sc = uether_getsc(ue);
1328 	if_t ifp = uether_getifp(ue);
1329 	uint16_t rxmode;
1330 
1331 	AXE_LOCK_ASSERT(sc, MA_OWNED);
1332 
1333 	if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0)
1334 		return;
1335 
1336 	/* Cancel pending I/O */
1337 	axe_stop(ue);
1338 
1339 	axe_reset(sc);
1340 
1341 	/* Set MAC address and transmitter IPG values. */
1342 	if (AXE_IS_178_FAMILY(sc)) {
1343 		axe_cmd(sc, AXE_178_CMD_WRITE_NODEID, 0, 0, if_getlladdr(ifp));
1344 		axe_cmd(sc, AXE_178_CMD_WRITE_IPG012, sc->sc_ipgs[2],
1345 		    (sc->sc_ipgs[1] << 8) | (sc->sc_ipgs[0]), NULL);
1346 	} else {
1347 		axe_cmd(sc, AXE_172_CMD_WRITE_NODEID, 0, 0, if_getlladdr(ifp));
1348 		axe_cmd(sc, AXE_172_CMD_WRITE_IPG0, 0, sc->sc_ipgs[0], NULL);
1349 		axe_cmd(sc, AXE_172_CMD_WRITE_IPG1, 0, sc->sc_ipgs[1], NULL);
1350 		axe_cmd(sc, AXE_172_CMD_WRITE_IPG2, 0, sc->sc_ipgs[2], NULL);
1351 	}
1352 
1353 	if (AXE_IS_178_FAMILY(sc)) {
1354 		sc->sc_flags &= ~(AXE_FLAG_STD_FRAME | AXE_FLAG_CSUM_FRAME);
1355 		if ((sc->sc_flags & AXE_FLAG_772B) != 0 &&
1356 		    (if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) {
1357 			sc->sc_lenmask = AXE_CSUM_HDR_LEN_MASK;
1358 			sc->sc_flags |= AXE_FLAG_CSUM_FRAME;
1359 		} else {
1360 			sc->sc_lenmask = AXE_HDR_LEN_MASK;
1361 			sc->sc_flags |= AXE_FLAG_STD_FRAME;
1362 		}
1363 	}
1364 
1365 	/* Configure TX/RX checksum offloading. */
1366 	axe_csum_cfg(ue);
1367 
1368 	if (sc->sc_flags & AXE_FLAG_772B) {
1369 		/* AX88772B uses different maximum frame burst configuration. */
1370 		axe_cmd(sc, AXE_772B_CMD_RXCTL_WRITE_CFG,
1371 		    ax88772b_mfb_table[AX88772B_MFB_16K].threshold,
1372 		    ax88772b_mfb_table[AX88772B_MFB_16K].byte_cnt, NULL);
1373 	}
1374 
1375 	/* Enable receiver, set RX mode. */
1376 	rxmode = (AXE_RXCMD_MULTICAST | AXE_RXCMD_ENABLE);
1377 	if (AXE_IS_178_FAMILY(sc)) {
1378 		if (sc->sc_flags & AXE_FLAG_772B) {
1379 			/*
1380 			 * Select RX header format type 1.  Aligning IP
1381 			 * header on 4 byte boundary is not needed when
1382 			 * checksum offloading feature is not used
1383 			 * because we always copy the received frame in
1384 			 * RX handler.  When RX checksum offloading is
1385 			 * active, aligning IP header is required to
1386 			 * reflect actual frame length including RX
1387 			 * header size.
1388 			 */
1389 			rxmode |= AXE_772B_RXCMD_HDR_TYPE_1;
1390 			if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0)
1391 				rxmode |= AXE_772B_RXCMD_IPHDR_ALIGN;
1392 		} else {
1393 			/*
1394 			 * Default Rx buffer size is too small to get
1395 			 * maximum performance.
1396 			 */
1397 			rxmode |= AXE_178_RXCMD_MFB_16384;
1398 		}
1399 	} else {
1400 		rxmode |= AXE_172_RXCMD_UNICAST;
1401 	}
1402 
1403 	/* If we want promiscuous mode, set the allframes bit. */
1404 	if (if_getflags(ifp) & IFF_PROMISC)
1405 		rxmode |= AXE_RXCMD_PROMISC;
1406 
1407 	if (if_getflags(ifp) & IFF_BROADCAST)
1408 		rxmode |= AXE_RXCMD_BROADCAST;
1409 
1410 	axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL);
1411 
1412 	/* Load the multicast filter. */
1413 	axe_setmulti(ue);
1414 
1415 	usbd_xfer_set_stall(sc->sc_xfer[AXE_BULK_DT_WR]);
1416 
1417 	if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0);
1418 	/* Switch to selected media. */
1419 	axe_ifmedia_upd(ifp);
1420 }
1421 
1422 static void
1423 axe_setpromisc(struct usb_ether *ue)
1424 {
1425 	struct axe_softc *sc = uether_getsc(ue);
1426 	if_t ifp = uether_getifp(ue);
1427 	uint16_t rxmode;
1428 
1429 	axe_cmd(sc, AXE_CMD_RXCTL_READ, 0, 0, &rxmode);
1430 
1431 	rxmode = le16toh(rxmode);
1432 
1433 	if (if_getflags(ifp) & IFF_PROMISC) {
1434 		rxmode |= AXE_RXCMD_PROMISC;
1435 	} else {
1436 		rxmode &= ~AXE_RXCMD_PROMISC;
1437 	}
1438 
1439 	axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL);
1440 
1441 	axe_setmulti(ue);
1442 }
1443 
1444 static void
1445 axe_stop(struct usb_ether *ue)
1446 {
1447 	struct axe_softc *sc = uether_getsc(ue);
1448 	if_t ifp = uether_getifp(ue);
1449 
1450 	AXE_LOCK_ASSERT(sc, MA_OWNED);
1451 
1452 	if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE));
1453 	sc->sc_flags &= ~AXE_FLAG_LINK;
1454 
1455 	/*
1456 	 * stop all the transfers, if not already stopped:
1457 	 */
1458 	usbd_transfer_stop(sc->sc_xfer[AXE_BULK_DT_WR]);
1459 	usbd_transfer_stop(sc->sc_xfer[AXE_BULK_DT_RD]);
1460 }
1461 
1462 static int
1463 axe_ioctl(if_t ifp, u_long cmd, caddr_t data)
1464 {
1465 	struct usb_ether *ue = if_getsoftc(ifp);
1466 	struct axe_softc *sc;
1467 	struct ifreq *ifr;
1468 	int error, mask, reinit;
1469 
1470 	sc = uether_getsc(ue);
1471 	ifr = (struct ifreq *)data;
1472 	error = 0;
1473 	reinit = 0;
1474 	if (cmd == SIOCSIFCAP) {
1475 		AXE_LOCK(sc);
1476 		mask = ifr->ifr_reqcap ^ if_getcapenable(ifp);
1477 		if ((mask & IFCAP_TXCSUM) != 0 &&
1478 		    (if_getcapabilities(ifp) & IFCAP_TXCSUM) != 0) {
1479 			if_togglecapenable(ifp, IFCAP_TXCSUM);
1480 			if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0)
1481 				if_sethwassistbits(ifp, AXE_CSUM_FEATURES, 0);
1482 			else
1483 				if_sethwassistbits(ifp, 0, AXE_CSUM_FEATURES);
1484 			reinit++;
1485 		}
1486 		if ((mask & IFCAP_RXCSUM) != 0 &&
1487 		    (if_getcapabilities(ifp) & IFCAP_RXCSUM) != 0) {
1488 			if_togglecapenable(ifp, IFCAP_RXCSUM);
1489 			reinit++;
1490 		}
1491 		if (reinit > 0 && if_getdrvflags(ifp) & IFF_DRV_RUNNING)
1492 			if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
1493 		else
1494 			reinit = 0;
1495 		AXE_UNLOCK(sc);
1496 		if (reinit > 0)
1497 			uether_init(ue);
1498 	} else
1499 		error = uether_ioctl(ifp, cmd, data);
1500 
1501 	return (error);
1502 }
1503