1 /*- 2 * Copyright (c) 1997, 1998, 1999, 2000-2003 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD$ 33 */ 34 35 /* 36 * Definitions for the ASIX Electronics AX88172, AX88178 37 * and AX88772 to ethernet controllers. 38 */ 39 40 /* 41 * Vendor specific commands. ASIX conveniently doesn't document the 'set 42 * NODEID' command in their datasheet (thanks a lot guys). 43 * To make handling these commands easier, I added some extra data which is 44 * decided by the axe_cmd() routine. Commands are encoded in 16 bits, with 45 * the format: LDCC. L and D are both nibbles in the high byte. L represents 46 * the data length (0 to 15) and D represents the direction (0 for vendor read, 47 * 1 for vendor write). CC is the command byte, as specified in the manual. 48 */ 49 50 #define AXE_CMD_IS_WRITE(x) (((x) & 0x0F00) >> 8) 51 #define AXE_CMD_LEN(x) (((x) & 0xF000) >> 12) 52 #define AXE_CMD_CMD(x) ((x) & 0x00FF) 53 54 #define AXE_172_CMD_READ_RXTX_SRAM 0x2002 55 #define AXE_182_CMD_READ_RXTX_SRAM 0x8002 56 #define AXE_172_CMD_WRITE_RX_SRAM 0x0103 57 #define AXE_182_CMD_WRITE_RXTX_SRAM 0x8103 58 #define AXE_172_CMD_WRITE_TX_SRAM 0x0104 59 #define AXE_CMD_MII_OPMODE_SW 0x0106 60 #define AXE_CMD_MII_READ_REG 0x2007 61 #define AXE_CMD_MII_WRITE_REG 0x2108 62 #define AXE_CMD_MII_READ_OPMODE 0x1009 63 #define AXE_CMD_MII_OPMODE_HW 0x010A 64 #define AXE_CMD_SROM_READ 0x200B 65 #define AXE_CMD_SROM_WRITE 0x010C 66 #define AXE_CMD_SROM_WR_ENABLE 0x010D 67 #define AXE_CMD_SROM_WR_DISABLE 0x010E 68 #define AXE_CMD_RXCTL_READ 0x200F 69 #define AXE_CMD_RXCTL_WRITE 0x0110 70 #define AXE_CMD_READ_IPG012 0x3011 71 #define AXE_172_CMD_WRITE_IPG0 0x0112 72 #define AXE_178_CMD_WRITE_IPG012 0x0112 73 #define AXE_172_CMD_WRITE_IPG1 0x0113 74 #define AXE_178_CMD_READ_NODEID 0x6013 75 #define AXE_172_CMD_WRITE_IPG2 0x0114 76 #define AXE_178_CMD_WRITE_NODEID 0x6114 77 #define AXE_CMD_READ_MCAST 0x8015 78 #define AXE_CMD_WRITE_MCAST 0x8116 79 #define AXE_172_CMD_READ_NODEID 0x6017 80 #define AXE_172_CMD_WRITE_NODEID 0x6118 81 82 #define AXE_CMD_READ_PHYID 0x2019 83 #define AXE_172_CMD_READ_MEDIA 0x101A 84 #define AXE_178_CMD_READ_MEDIA 0x201A 85 #define AXE_CMD_WRITE_MEDIA 0x011B 86 #define AXE_CMD_READ_MONITOR_MODE 0x101C 87 #define AXE_CMD_WRITE_MONITOR_MODE 0x011D 88 #define AXE_CMD_READ_GPIO 0x101E 89 #define AXE_CMD_WRITE_GPIO 0x011F 90 91 #define AXE_CMD_SW_RESET_REG 0x0120 92 #define AXE_CMD_SW_PHY_STATUS 0x0021 93 #define AXE_CMD_SW_PHY_SELECT 0x0122 94 95 #define AXE_SW_RESET_CLEAR 0x00 96 #define AXE_SW_RESET_RR 0x01 97 #define AXE_SW_RESET_RT 0x02 98 #define AXE_SW_RESET_PRTE 0x04 99 #define AXE_SW_RESET_PRL 0x08 100 #define AXE_SW_RESET_BZ 0x10 101 #define AXE_SW_RESET_IPRL 0x20 102 #define AXE_SW_RESET_IPPD 0x40 103 104 /* AX88178 documentation says to always write this bit... */ 105 #define AXE_178_RESET_MAGIC 0x40 106 107 #define AXE_178_MEDIA_GMII 0x0001 108 #define AXE_MEDIA_FULL_DUPLEX 0x0002 109 #define AXE_172_MEDIA_TX_ABORT_ALLOW 0x0004 110 111 /* AX88178/88772 documentation says to always write 1 to bit 2 */ 112 #define AXE_178_MEDIA_MAGIC 0x0004 113 /* AX88772 documentation says to always write 0 to bit 3 */ 114 #define AXE_178_MEDIA_ENCK 0x0008 115 #define AXE_172_MEDIA_FLOW_CONTROL_EN 0x0010 116 #define AXE_178_MEDIA_RXFLOW_CONTROL_EN 0x0010 117 #define AXE_178_MEDIA_TXFLOW_CONTROL_EN 0x0020 118 #define AXE_178_MEDIA_JUMBO_EN 0x0040 119 #define AXE_178_MEDIA_LTPF_ONLY 0x0080 120 #define AXE_178_MEDIA_RX_EN 0x0100 121 #define AXE_178_MEDIA_100TX 0x0200 122 #define AXE_178_MEDIA_SBP 0x0800 123 #define AXE_178_MEDIA_SUPERMAC 0x1000 124 125 #define AXE_RXCMD_PROMISC 0x0001 126 #define AXE_RXCMD_ALLMULTI 0x0002 127 #define AXE_172_RXCMD_UNICAST 0x0004 128 #define AXE_178_RXCMD_KEEP_INVALID_CRC 0x0004 129 #define AXE_RXCMD_BROADCAST 0x0008 130 #define AXE_RXCMD_MULTICAST 0x0010 131 #define AXE_RXCMD_ENABLE 0x0080 132 #define AXE_178_RXCMD_MFB_MASK 0x0300 133 #define AXE_178_RXCMD_MFB_2048 0x0000 134 #define AXE_178_RXCMD_MFB_4096 0x0100 135 #define AXE_178_RXCMD_MFB_8192 0x0200 136 #define AXE_178_RXCMD_MFB_16384 0x0300 137 138 #define AXE_PHY_SEL_PRI 1 139 #define AXE_PHY_SEL_SEC 0 140 #define AXE_PHY_TYPE_MASK 0xE0 141 #define AXE_PHY_TYPE_SHIFT 5 142 #define AXE_PHY_TYPE(x) \ 143 (((x) & AXE_PHY_TYPE_MASK) >> AXE_PHY_TYPE_SHIFT) 144 145 #define PHY_TYPE_100_HOME 0 /* 10/100 or 1M HOME PHY */ 146 #define PHY_TYPE_GIG 1 /* Gigabit PHY */ 147 #define PHY_TYPE_SPECIAL 4 /* Special case */ 148 #define PHY_TYPE_RSVD 5 /* Reserved */ 149 #define PHY_TYPE_NON_SUP 7 /* Non-supported PHY */ 150 151 #define AXE_PHY_NO_MASK 0x1F 152 #define AXE_PHY_NO(x) ((x) & AXE_PHY_NO_MASK) 153 154 #define AXE_772_PHY_NO_EPHY 0x10 /* Embedded 10/100 PHY of AX88772 */ 155 156 #define AXE_BULK_BUF_SIZE 16384 /* bytes */ 157 158 #define AXE_CTL_READ 0x01 159 #define AXE_CTL_WRITE 0x02 160 161 #define AXE_CONFIG_IDX 0 /* config number 1 */ 162 #define AXE_IFACE_IDX 0 163 164 struct axe_sframe_hdr { 165 uint16_t len; 166 uint16_t ilen; 167 } __packed; 168 169 #define GET_MII(sc) uether_getmii(&(sc)->sc_ue) 170 171 /* The interrupt endpoint is currently unused by the ASIX part. */ 172 enum { 173 AXE_BULK_DT_WR, 174 AXE_BULK_DT_RD, 175 AXE_INTR_DT_RD, 176 AXE_N_TRANSFER, 177 }; 178 179 struct axe_softc { 180 struct usb_ether sc_ue; 181 struct mtx sc_mtx; 182 struct usb_xfer *sc_xfer[AXE_N_TRANSFER]; 183 int sc_phyno; 184 185 int sc_flags; 186 #define AXE_FLAG_LINK 0x0001 187 #define AXE_FLAG_772 0x1000 /* AX88772 */ 188 #define AXE_FLAG_178 0x2000 /* AX88178 */ 189 190 uint8_t sc_ipgs[3]; 191 uint8_t sc_phyaddrs[2]; 192 }; 193 194 #define AXE_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 195 #define AXE_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 196 #define AXE_LOCK_ASSERT(_sc, t) mtx_assert(&(_sc)->sc_mtx, t) 197