1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2013-2014 Kevin Lo 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 /* 33 * ASIX Electronics AX88178A/AX88179 USB 2.0/3.0 gigabit ethernet driver. 34 */ 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/bus.h> 39 #include <sys/condvar.h> 40 #include <sys/endian.h> 41 #include <sys/kernel.h> 42 #include <sys/lock.h> 43 #include <sys/module.h> 44 #include <sys/mutex.h> 45 #include <sys/socket.h> 46 #include <sys/sysctl.h> 47 #include <sys/unistd.h> 48 49 #include <net/if.h> 50 #include <net/if_var.h> 51 #include <net/if_media.h> 52 53 #include <dev/mii/mii.h> 54 #include <dev/mii/miivar.h> 55 56 #include <dev/usb/usb.h> 57 #include <dev/usb/usbdi.h> 58 #include <dev/usb/usbdi_util.h> 59 #include "usbdevs.h" 60 61 #define USB_DEBUG_VAR axge_debug 62 #include <dev/usb/usb_debug.h> 63 #include <dev/usb/usb_process.h> 64 65 #include <dev/usb/net/usb_ethernet.h> 66 #include <dev/usb/net/if_axgereg.h> 67 68 #include "miibus_if.h" 69 70 /* 71 * Various supported device vendors/products. 72 */ 73 74 static const STRUCT_USB_HOST_ID axge_devs[] = { 75 #define AXGE_DEV(v,p) { USB_VP(USB_VENDOR_##v, USB_PRODUCT_##v##_##p) } 76 AXGE_DEV(ASIX, AX88178A), 77 AXGE_DEV(ASIX, AX88179), 78 AXGE_DEV(BELKIN, B2B128), 79 AXGE_DEV(DLINK, DUB1312), 80 AXGE_DEV(LENOVO, GIGALAN), 81 AXGE_DEV(SITECOMEU, LN032), 82 #undef AXGE_DEV 83 }; 84 85 static const struct { 86 uint8_t ctrl; 87 uint8_t timer_l; 88 uint8_t timer_h; 89 uint8_t size; 90 uint8_t ifg; 91 } __packed axge_bulk_size[] = { 92 { 7, 0x4f, 0x00, 0x12, 0xff }, 93 { 7, 0x20, 0x03, 0x16, 0xff }, 94 { 7, 0xae, 0x07, 0x18, 0xff }, 95 { 7, 0xcc, 0x4c, 0x18, 0x08 } 96 }; 97 98 /* prototypes */ 99 100 static device_probe_t axge_probe; 101 static device_attach_t axge_attach; 102 static device_detach_t axge_detach; 103 104 static usb_callback_t axge_bulk_read_callback; 105 static usb_callback_t axge_bulk_write_callback; 106 107 static miibus_readreg_t axge_miibus_readreg; 108 static miibus_writereg_t axge_miibus_writereg; 109 static miibus_statchg_t axge_miibus_statchg; 110 111 static uether_fn_t axge_attach_post; 112 static uether_fn_t axge_init; 113 static uether_fn_t axge_stop; 114 static uether_fn_t axge_start; 115 static uether_fn_t axge_tick; 116 static uether_fn_t axge_rxfilter; 117 118 static int axge_read_mem(struct axge_softc *, uint8_t, uint16_t, 119 uint16_t, void *, int); 120 static void axge_write_mem(struct axge_softc *, uint8_t, uint16_t, 121 uint16_t, void *, int); 122 static uint8_t axge_read_cmd_1(struct axge_softc *, uint8_t, uint16_t); 123 static uint16_t axge_read_cmd_2(struct axge_softc *, uint8_t, uint16_t, 124 uint16_t); 125 static void axge_write_cmd_1(struct axge_softc *, uint8_t, uint16_t, 126 uint8_t); 127 static void axge_write_cmd_2(struct axge_softc *, uint8_t, uint16_t, 128 uint16_t, uint16_t); 129 static void axge_chip_init(struct axge_softc *); 130 static void axge_reset(struct axge_softc *); 131 132 static int axge_attach_post_sub(struct usb_ether *); 133 static int axge_ifmedia_upd(if_t); 134 static void axge_ifmedia_sts(if_t, struct ifmediareq *); 135 static int axge_ioctl(if_t, u_long, caddr_t); 136 static void axge_rx_frame(struct usb_ether *, struct usb_page_cache *, int); 137 static void axge_rxeof(struct usb_ether *, struct usb_page_cache *, 138 unsigned, unsigned, uint32_t); 139 static void axge_csum_cfg(struct usb_ether *); 140 141 #define AXGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 142 143 #ifdef USB_DEBUG 144 static int axge_debug = 0; 145 146 static SYSCTL_NODE(_hw_usb, OID_AUTO, axge, CTLFLAG_RW | CTLFLAG_MPSAFE, 0, 147 "USB axge"); 148 SYSCTL_INT(_hw_usb_axge, OID_AUTO, debug, CTLFLAG_RWTUN, &axge_debug, 0, 149 "Debug level"); 150 #endif 151 152 static const struct usb_config axge_config[AXGE_N_TRANSFER] = { 153 [AXGE_BULK_DT_WR] = { 154 .type = UE_BULK, 155 .endpoint = UE_ADDR_ANY, 156 .direction = UE_DIR_OUT, 157 .frames = AXGE_N_FRAMES, 158 .bufsize = AXGE_N_FRAMES * MCLBYTES, 159 .flags = {.pipe_bof = 1,.force_short_xfer = 1,}, 160 .callback = axge_bulk_write_callback, 161 .timeout = 10000, /* 10 seconds */ 162 }, 163 [AXGE_BULK_DT_RD] = { 164 .type = UE_BULK, 165 .endpoint = UE_ADDR_ANY, 166 .direction = UE_DIR_IN, 167 .bufsize = 65536, 168 .flags = {.pipe_bof = 1,.short_xfer_ok = 1,}, 169 .callback = axge_bulk_read_callback, 170 .timeout = 0, /* no timeout */ 171 }, 172 }; 173 174 static device_method_t axge_methods[] = { 175 /* Device interface. */ 176 DEVMETHOD(device_probe, axge_probe), 177 DEVMETHOD(device_attach, axge_attach), 178 DEVMETHOD(device_detach, axge_detach), 179 180 /* MII interface. */ 181 DEVMETHOD(miibus_readreg, axge_miibus_readreg), 182 DEVMETHOD(miibus_writereg, axge_miibus_writereg), 183 DEVMETHOD(miibus_statchg, axge_miibus_statchg), 184 185 DEVMETHOD_END 186 }; 187 188 static driver_t axge_driver = { 189 .name = "axge", 190 .methods = axge_methods, 191 .size = sizeof(struct axge_softc), 192 }; 193 194 DRIVER_MODULE(axge, uhub, axge_driver, NULL, NULL); 195 DRIVER_MODULE(miibus, axge, miibus_driver, NULL, NULL); 196 MODULE_DEPEND(axge, uether, 1, 1, 1); 197 MODULE_DEPEND(axge, usb, 1, 1, 1); 198 MODULE_DEPEND(axge, ether, 1, 1, 1); 199 MODULE_DEPEND(axge, miibus, 1, 1, 1); 200 MODULE_VERSION(axge, 1); 201 USB_PNP_HOST_INFO(axge_devs); 202 203 static const struct usb_ether_methods axge_ue_methods = { 204 .ue_attach_post = axge_attach_post, 205 .ue_attach_post_sub = axge_attach_post_sub, 206 .ue_start = axge_start, 207 .ue_init = axge_init, 208 .ue_stop = axge_stop, 209 .ue_tick = axge_tick, 210 .ue_setmulti = axge_rxfilter, 211 .ue_setpromisc = axge_rxfilter, 212 .ue_mii_upd = axge_ifmedia_upd, 213 .ue_mii_sts = axge_ifmedia_sts, 214 }; 215 216 static int 217 axge_read_mem(struct axge_softc *sc, uint8_t cmd, uint16_t index, 218 uint16_t val, void *buf, int len) 219 { 220 struct usb_device_request req; 221 222 AXGE_LOCK_ASSERT(sc, MA_OWNED); 223 224 req.bmRequestType = UT_READ_VENDOR_DEVICE; 225 req.bRequest = cmd; 226 USETW(req.wValue, val); 227 USETW(req.wIndex, index); 228 USETW(req.wLength, len); 229 230 return (uether_do_request(&sc->sc_ue, &req, buf, 1000)); 231 } 232 233 static void 234 axge_write_mem(struct axge_softc *sc, uint8_t cmd, uint16_t index, 235 uint16_t val, void *buf, int len) 236 { 237 struct usb_device_request req; 238 239 AXGE_LOCK_ASSERT(sc, MA_OWNED); 240 241 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 242 req.bRequest = cmd; 243 USETW(req.wValue, val); 244 USETW(req.wIndex, index); 245 USETW(req.wLength, len); 246 247 if (uether_do_request(&sc->sc_ue, &req, buf, 1000)) { 248 /* Error ignored. */ 249 } 250 } 251 252 static uint8_t 253 axge_read_cmd_1(struct axge_softc *sc, uint8_t cmd, uint16_t reg) 254 { 255 uint8_t val; 256 257 axge_read_mem(sc, cmd, 1, reg, &val, 1); 258 return (val); 259 } 260 261 static uint16_t 262 axge_read_cmd_2(struct axge_softc *sc, uint8_t cmd, uint16_t index, 263 uint16_t reg) 264 { 265 uint8_t val[2]; 266 267 axge_read_mem(sc, cmd, index, reg, &val, 2); 268 return (UGETW(val)); 269 } 270 271 static void 272 axge_write_cmd_1(struct axge_softc *sc, uint8_t cmd, uint16_t reg, uint8_t val) 273 { 274 axge_write_mem(sc, cmd, 1, reg, &val, 1); 275 } 276 277 static void 278 axge_write_cmd_2(struct axge_softc *sc, uint8_t cmd, uint16_t index, 279 uint16_t reg, uint16_t val) 280 { 281 uint8_t temp[2]; 282 283 USETW(temp, val); 284 axge_write_mem(sc, cmd, index, reg, &temp, 2); 285 } 286 287 static int 288 axge_miibus_readreg(device_t dev, int phy, int reg) 289 { 290 struct axge_softc *sc; 291 uint16_t val; 292 int locked; 293 294 sc = device_get_softc(dev); 295 locked = mtx_owned(&sc->sc_mtx); 296 if (!locked) 297 AXGE_LOCK(sc); 298 299 val = axge_read_cmd_2(sc, AXGE_ACCESS_PHY, reg, phy); 300 301 if (!locked) 302 AXGE_UNLOCK(sc); 303 304 return (val); 305 } 306 307 static int 308 axge_miibus_writereg(device_t dev, int phy, int reg, int val) 309 { 310 struct axge_softc *sc; 311 int locked; 312 313 sc = device_get_softc(dev); 314 locked = mtx_owned(&sc->sc_mtx); 315 if (!locked) 316 AXGE_LOCK(sc); 317 318 axge_write_cmd_2(sc, AXGE_ACCESS_PHY, reg, phy, val); 319 320 if (!locked) 321 AXGE_UNLOCK(sc); 322 323 return (0); 324 } 325 326 static void 327 axge_miibus_statchg(device_t dev) 328 { 329 struct axge_softc *sc; 330 struct mii_data *mii; 331 if_t ifp; 332 uint8_t link_status, tmp[5]; 333 uint16_t val; 334 int locked; 335 336 sc = device_get_softc(dev); 337 mii = GET_MII(sc); 338 locked = mtx_owned(&sc->sc_mtx); 339 if (!locked) 340 AXGE_LOCK(sc); 341 342 ifp = uether_getifp(&sc->sc_ue); 343 if (mii == NULL || ifp == NULL || 344 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 345 goto done; 346 347 sc->sc_flags &= ~AXGE_FLAG_LINK; 348 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 349 (IFM_ACTIVE | IFM_AVALID)) { 350 switch (IFM_SUBTYPE(mii->mii_media_active)) { 351 case IFM_10_T: 352 case IFM_100_TX: 353 case IFM_1000_T: 354 sc->sc_flags |= AXGE_FLAG_LINK; 355 break; 356 default: 357 break; 358 } 359 } 360 361 /* Lost link, do nothing. */ 362 if ((sc->sc_flags & AXGE_FLAG_LINK) == 0) 363 goto done; 364 365 link_status = axge_read_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_PLSR); 366 367 val = 0; 368 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 369 val |= MSR_FD; 370 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 371 val |= MSR_TFC; 372 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 373 val |= MSR_RFC; 374 } 375 val |= MSR_RE; 376 switch (IFM_SUBTYPE(mii->mii_media_active)) { 377 case IFM_1000_T: 378 val |= MSR_GM | MSR_EN_125MHZ; 379 if (link_status & PLSR_USB_SS) 380 memcpy(tmp, &axge_bulk_size[0], 5); 381 else if (link_status & PLSR_USB_HS) 382 memcpy(tmp, &axge_bulk_size[1], 5); 383 else 384 memcpy(tmp, &axge_bulk_size[3], 5); 385 break; 386 case IFM_100_TX: 387 val |= MSR_PS; 388 if (link_status & (PLSR_USB_SS | PLSR_USB_HS)) 389 memcpy(tmp, &axge_bulk_size[2], 5); 390 else 391 memcpy(tmp, &axge_bulk_size[3], 5); 392 break; 393 case IFM_10_T: 394 memcpy(tmp, &axge_bulk_size[3], 5); 395 break; 396 } 397 /* Rx bulk configuration. */ 398 axge_write_mem(sc, AXGE_ACCESS_MAC, 5, AXGE_RX_BULKIN_QCTRL, tmp, 5); 399 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_MSR, val); 400 done: 401 if (!locked) 402 AXGE_UNLOCK(sc); 403 } 404 405 static void 406 axge_chip_init(struct axge_softc *sc) 407 { 408 /* Power up ethernet PHY. */ 409 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_EPPRCR, 0); 410 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_EPPRCR, EPPRCR_IPRL); 411 uether_pause(&sc->sc_ue, hz / 4); 412 axge_write_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_CLK_SELECT, 413 AXGE_CLK_SELECT_ACS | AXGE_CLK_SELECT_BCS); 414 uether_pause(&sc->sc_ue, hz / 10); 415 } 416 417 static void 418 axge_reset(struct axge_softc *sc) 419 { 420 struct usb_config_descriptor *cd; 421 usb_error_t err; 422 423 cd = usbd_get_config_descriptor(sc->sc_ue.ue_udev); 424 425 err = usbd_req_set_config(sc->sc_ue.ue_udev, &sc->sc_mtx, 426 cd->bConfigurationValue); 427 if (err) 428 DPRINTF("reset failed (ignored)\n"); 429 430 /* Wait a little while for the chip to get its brains in order. */ 431 uether_pause(&sc->sc_ue, hz / 100); 432 433 /* Reinitialize controller to achieve full reset. */ 434 axge_chip_init(sc); 435 } 436 437 static void 438 axge_attach_post(struct usb_ether *ue) 439 { 440 struct axge_softc *sc; 441 442 sc = uether_getsc(ue); 443 444 /* Initialize controller and get station address. */ 445 axge_chip_init(sc); 446 axge_read_mem(sc, AXGE_ACCESS_MAC, ETHER_ADDR_LEN, AXGE_NIDR, 447 ue->ue_eaddr, ETHER_ADDR_LEN); 448 } 449 450 static int 451 axge_attach_post_sub(struct usb_ether *ue) 452 { 453 if_t ifp; 454 int error; 455 456 ifp = ue->ue_ifp; 457 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 458 if_setstartfn(ifp, uether_start); 459 if_setioctlfn(ifp, axge_ioctl); 460 if_setinitfn(ifp, uether_init); 461 if_setsendqlen(ifp, ifqmaxlen); 462 if_setsendqready(ifp); 463 464 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU | IFCAP_TXCSUM | IFCAP_RXCSUM, 0); 465 if_sethwassist(ifp, AXGE_CSUM_FEATURES); 466 if_setcapenable(ifp, if_getcapabilities(ifp)); 467 468 bus_topo_lock(); 469 error = mii_attach(ue->ue_dev, &ue->ue_miibus, ifp, 470 uether_ifmedia_upd, ue->ue_methods->ue_mii_sts, 471 BMSR_DEFCAPMASK, AXGE_PHY_ADDR, MII_OFFSET_ANY, MIIF_DOPAUSE); 472 bus_topo_unlock(); 473 474 return (error); 475 } 476 477 /* 478 * Set media options. 479 */ 480 static int 481 axge_ifmedia_upd(if_t ifp) 482 { 483 struct axge_softc *sc; 484 struct mii_data *mii; 485 struct mii_softc *miisc; 486 int error; 487 488 sc = if_getsoftc(ifp); 489 mii = GET_MII(sc); 490 AXGE_LOCK_ASSERT(sc, MA_OWNED); 491 492 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 493 PHY_RESET(miisc); 494 error = mii_mediachg(mii); 495 496 return (error); 497 } 498 499 /* 500 * Report current media status. 501 */ 502 static void 503 axge_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr) 504 { 505 struct axge_softc *sc; 506 struct mii_data *mii; 507 508 sc = if_getsoftc(ifp); 509 mii = GET_MII(sc); 510 AXGE_LOCK(sc); 511 mii_pollstat(mii); 512 ifmr->ifm_active = mii->mii_media_active; 513 ifmr->ifm_status = mii->mii_media_status; 514 AXGE_UNLOCK(sc); 515 } 516 517 /* 518 * Probe for a AX88179 chip. 519 */ 520 static int 521 axge_probe(device_t dev) 522 { 523 struct usb_attach_arg *uaa; 524 525 uaa = device_get_ivars(dev); 526 if (uaa->usb_mode != USB_MODE_HOST) 527 return (ENXIO); 528 if (uaa->info.bConfigIndex != AXGE_CONFIG_IDX) 529 return (ENXIO); 530 if (uaa->info.bIfaceIndex != AXGE_IFACE_IDX) 531 return (ENXIO); 532 533 return (usbd_lookup_id_by_uaa(axge_devs, sizeof(axge_devs), uaa)); 534 } 535 536 /* 537 * Attach the interface. Allocate softc structures, do ifmedia 538 * setup and ethernet/BPF attach. 539 */ 540 static int 541 axge_attach(device_t dev) 542 { 543 struct usb_attach_arg *uaa; 544 struct axge_softc *sc; 545 struct usb_ether *ue; 546 uint8_t iface_index; 547 int error; 548 549 uaa = device_get_ivars(dev); 550 sc = device_get_softc(dev); 551 ue = &sc->sc_ue; 552 553 device_set_usb_desc(dev); 554 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_DEF); 555 556 iface_index = AXGE_IFACE_IDX; 557 error = usbd_transfer_setup(uaa->device, &iface_index, 558 sc->sc_xfer, axge_config, AXGE_N_TRANSFER, sc, &sc->sc_mtx); 559 if (error) { 560 device_printf(dev, "allocating USB transfers failed\n"); 561 mtx_destroy(&sc->sc_mtx); 562 return (ENXIO); 563 } 564 565 ue->ue_sc = sc; 566 ue->ue_dev = dev; 567 ue->ue_udev = uaa->device; 568 ue->ue_mtx = &sc->sc_mtx; 569 ue->ue_methods = &axge_ue_methods; 570 571 error = uether_ifattach(ue); 572 if (error) { 573 device_printf(dev, "could not attach interface\n"); 574 goto detach; 575 } 576 return (0); /* success */ 577 578 detach: 579 axge_detach(dev); 580 return (ENXIO); /* failure */ 581 } 582 583 static int 584 axge_detach(device_t dev) 585 { 586 struct axge_softc *sc; 587 struct usb_ether *ue; 588 uint16_t val; 589 590 sc = device_get_softc(dev); 591 ue = &sc->sc_ue; 592 if (device_is_attached(dev)) { 593 /* wait for any post attach or other command to complete */ 594 usb_proc_drain(&ue->ue_tq); 595 596 AXGE_LOCK(sc); 597 /* 598 * XXX 599 * ether_ifdetach(9) should be called first. 600 */ 601 axge_stop(ue); 602 /* Force bulk-in to return a zero-length USB packet. */ 603 val = axge_read_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_EPPRCR); 604 val |= EPPRCR_BZ | EPPRCR_IPRL; 605 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_EPPRCR, val); 606 /* Change clock. */ 607 axge_write_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_CLK_SELECT, 0); 608 /* Disable MAC. */ 609 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_RCR, 0); 610 AXGE_UNLOCK(sc); 611 } 612 usbd_transfer_unsetup(sc->sc_xfer, AXGE_N_TRANSFER); 613 uether_ifdetach(ue); 614 mtx_destroy(&sc->sc_mtx); 615 616 return (0); 617 } 618 619 static void 620 axge_bulk_read_callback(struct usb_xfer *xfer, usb_error_t error) 621 { 622 struct axge_softc *sc; 623 struct usb_ether *ue; 624 struct usb_page_cache *pc; 625 int actlen; 626 627 sc = usbd_xfer_softc(xfer); 628 ue = &sc->sc_ue; 629 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL); 630 631 switch (USB_GET_STATE(xfer)) { 632 case USB_ST_TRANSFERRED: 633 pc = usbd_xfer_get_frame(xfer, 0); 634 axge_rx_frame(ue, pc, actlen); 635 636 /* FALLTHROUGH */ 637 case USB_ST_SETUP: 638 tr_setup: 639 usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer)); 640 usbd_transfer_submit(xfer); 641 uether_rxflush(ue); 642 break; 643 644 default: 645 if (error != USB_ERR_CANCELLED) { 646 usbd_xfer_set_stall(xfer); 647 goto tr_setup; 648 } 649 break; 650 } 651 } 652 653 static void 654 axge_bulk_write_callback(struct usb_xfer *xfer, usb_error_t error) 655 { 656 struct axge_softc *sc; 657 if_t ifp; 658 struct usb_page_cache *pc; 659 struct mbuf *m; 660 struct axge_frame_txhdr txhdr; 661 int nframes, pos; 662 663 sc = usbd_xfer_softc(xfer); 664 ifp = uether_getifp(&sc->sc_ue); 665 666 switch (USB_GET_STATE(xfer)) { 667 case USB_ST_TRANSFERRED: 668 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 669 /* FALLTHROUGH */ 670 case USB_ST_SETUP: 671 tr_setup: 672 if ((sc->sc_flags & AXGE_FLAG_LINK) == 0 || 673 (if_getdrvflags(ifp) & IFF_DRV_OACTIVE) != 0) { 674 /* 675 * Don't send anything if there is no link or 676 * controller is busy. 677 */ 678 return; 679 } 680 681 for (nframes = 0; nframes < AXGE_N_FRAMES && 682 !if_sendq_empty(ifp); nframes++) { 683 m = if_dequeue(ifp); 684 if (m == NULL) 685 break; 686 usbd_xfer_set_frame_offset(xfer, nframes * MCLBYTES, 687 nframes); 688 pc = usbd_xfer_get_frame(xfer, nframes); 689 txhdr.mss = 0; 690 txhdr.len = htole32(AXGE_TXBYTES(m->m_pkthdr.len)); 691 if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0 && 692 (m->m_pkthdr.csum_flags & AXGE_CSUM_FEATURES) == 0) 693 txhdr.len |= htole32(AXGE_CSUM_DISABLE); 694 695 pos = 0; 696 usbd_copy_in(pc, pos, &txhdr, sizeof(txhdr)); 697 pos += sizeof(txhdr); 698 usbd_m_copy_in(pc, pos, m, 0, m->m_pkthdr.len); 699 pos += m->m_pkthdr.len; 700 701 /* 702 * if there's a BPF listener, bounce a copy 703 * of this frame to him: 704 */ 705 BPF_MTAP(ifp, m); 706 707 m_freem(m); 708 709 /* Set frame length. */ 710 usbd_xfer_set_frame_len(xfer, nframes, pos); 711 } 712 if (nframes != 0) { 713 /* 714 * XXX 715 * Update TX packet counter here. This is not 716 * correct way but it seems that there is no way 717 * to know how many packets are sent at the end 718 * of transfer because controller combines 719 * multiple writes into single one if there is 720 * room in TX buffer of controller. 721 */ 722 if_inc_counter(ifp, IFCOUNTER_OPACKETS, nframes); 723 usbd_xfer_set_frames(xfer, nframes); 724 usbd_transfer_submit(xfer); 725 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 726 } 727 return; 728 /* NOTREACHED */ 729 default: 730 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 731 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 732 733 if (error != USB_ERR_CANCELLED) { 734 usbd_xfer_set_stall(xfer); 735 goto tr_setup; 736 } 737 return; 738 } 739 } 740 741 static void 742 axge_tick(struct usb_ether *ue) 743 { 744 struct axge_softc *sc; 745 struct mii_data *mii; 746 747 sc = uether_getsc(ue); 748 mii = GET_MII(sc); 749 AXGE_LOCK_ASSERT(sc, MA_OWNED); 750 751 mii_tick(mii); 752 } 753 754 static u_int 755 axge_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 756 { 757 uint8_t *hashtbl = arg; 758 uint32_t h; 759 760 h = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN) >> 26; 761 hashtbl[h / 8] |= 1 << (h % 8); 762 763 return (1); 764 } 765 766 static void 767 axge_rxfilter(struct usb_ether *ue) 768 { 769 struct axge_softc *sc; 770 if_t ifp; 771 uint16_t rxmode; 772 uint8_t hashtbl[8] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 773 774 sc = uether_getsc(ue); 775 ifp = uether_getifp(ue); 776 AXGE_LOCK_ASSERT(sc, MA_OWNED); 777 778 /* 779 * Configure RX settings. 780 * Don't set RCR_IPE(IP header alignment on 32bit boundary) to disable 781 * inserting extra padding bytes. This wastes ethernet to USB host 782 * bandwidth as well as complicating RX handling logic. Current USB 783 * framework requires copying RX frames to mbufs so there is no need 784 * to worry about alignment. 785 */ 786 rxmode = RCR_DROP_CRCERR | RCR_START; 787 if (if_getflags(ifp) & IFF_BROADCAST) 788 rxmode |= RCR_ACPT_BCAST; 789 if (if_getflags(ifp) & (IFF_ALLMULTI | IFF_PROMISC)) { 790 if (if_getflags(ifp) & IFF_PROMISC) 791 rxmode |= RCR_PROMISC; 792 rxmode |= RCR_ACPT_ALL_MCAST; 793 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_RCR, rxmode); 794 return; 795 } 796 797 rxmode |= RCR_ACPT_MCAST; 798 if_foreach_llmaddr(ifp, axge_hash_maddr, &hashtbl); 799 800 axge_write_mem(sc, AXGE_ACCESS_MAC, 8, AXGE_MFA, (void *)&hashtbl, 8); 801 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_RCR, rxmode); 802 } 803 804 static void 805 axge_start(struct usb_ether *ue) 806 { 807 struct axge_softc *sc; 808 809 sc = uether_getsc(ue); 810 /* 811 * Start the USB transfers, if not already started. 812 */ 813 usbd_transfer_start(sc->sc_xfer[AXGE_BULK_DT_RD]); 814 usbd_transfer_start(sc->sc_xfer[AXGE_BULK_DT_WR]); 815 } 816 817 static void 818 axge_init(struct usb_ether *ue) 819 { 820 struct axge_softc *sc; 821 if_t ifp; 822 823 sc = uether_getsc(ue); 824 ifp = uether_getifp(ue); 825 AXGE_LOCK_ASSERT(sc, MA_OWNED); 826 827 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 828 return; 829 830 /* 831 * Cancel pending I/O and free all RX/TX buffers. 832 */ 833 axge_stop(ue); 834 835 axge_reset(sc); 836 837 /* Set MAC address. */ 838 axge_write_mem(sc, AXGE_ACCESS_MAC, ETHER_ADDR_LEN, AXGE_NIDR, 839 if_getlladdr(ifp), ETHER_ADDR_LEN); 840 841 axge_write_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_PWLLR, 0x34); 842 axge_write_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_PWLHR, 0x52); 843 844 /* Configure TX/RX checksum offloading. */ 845 axge_csum_cfg(ue); 846 847 /* Configure RX filters. */ 848 axge_rxfilter(ue); 849 850 /* 851 * XXX 852 * Controller supports wakeup on link change detection, 853 * magic packet and wakeup frame recpetion. But it seems 854 * there is no framework for USB ethernet suspend/wakeup. 855 * Disable all wakeup functions. 856 */ 857 axge_write_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_MMSR, 0); 858 (void)axge_read_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_MMSR); 859 860 /* Configure default medium type. */ 861 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_MSR, MSR_GM | MSR_FD | 862 MSR_RFC | MSR_TFC | MSR_RE); 863 864 usbd_xfer_set_stall(sc->sc_xfer[AXGE_BULK_DT_WR]); 865 866 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 867 /* Switch to selected media. */ 868 axge_ifmedia_upd(ifp); 869 } 870 871 static void 872 axge_stop(struct usb_ether *ue) 873 { 874 struct axge_softc *sc; 875 if_t ifp; 876 uint16_t val; 877 878 sc = uether_getsc(ue); 879 ifp = uether_getifp(ue); 880 881 AXGE_LOCK_ASSERT(sc, MA_OWNED); 882 883 val = axge_read_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_MSR); 884 val &= ~MSR_RE; 885 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_MSR, val); 886 887 if (ifp != NULL) 888 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)); 889 sc->sc_flags &= ~AXGE_FLAG_LINK; 890 891 /* 892 * Stop all the transfers, if not already stopped: 893 */ 894 usbd_transfer_stop(sc->sc_xfer[AXGE_BULK_DT_WR]); 895 usbd_transfer_stop(sc->sc_xfer[AXGE_BULK_DT_RD]); 896 } 897 898 static int 899 axge_ioctl(if_t ifp, u_long cmd, caddr_t data) 900 { 901 struct usb_ether *ue; 902 struct axge_softc *sc; 903 struct ifreq *ifr; 904 int error, mask, reinit; 905 906 ue = if_getsoftc(ifp); 907 sc = uether_getsc(ue); 908 ifr = (struct ifreq *)data; 909 error = 0; 910 reinit = 0; 911 if (cmd == SIOCSIFCAP) { 912 AXGE_LOCK(sc); 913 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 914 if ((mask & IFCAP_TXCSUM) != 0 && 915 (if_getcapabilities(ifp) & IFCAP_TXCSUM) != 0) { 916 if_togglecapenable(ifp, IFCAP_TXCSUM); 917 if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0) 918 if_sethwassistbits(ifp, AXGE_CSUM_FEATURES, 0); 919 else 920 if_sethwassistbits(ifp, 0, AXGE_CSUM_FEATURES); 921 reinit++; 922 } 923 if ((mask & IFCAP_RXCSUM) != 0 && 924 (if_getcapabilities(ifp) & IFCAP_RXCSUM) != 0) { 925 if_togglecapenable(ifp, IFCAP_RXCSUM); 926 reinit++; 927 } 928 if (reinit > 0 && if_getdrvflags(ifp) & IFF_DRV_RUNNING) 929 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 930 else 931 reinit = 0; 932 AXGE_UNLOCK(sc); 933 if (reinit > 0) 934 uether_init(ue); 935 } else 936 error = uether_ioctl(ifp, cmd, data); 937 938 return (error); 939 } 940 941 static void 942 axge_rx_frame(struct usb_ether *ue, struct usb_page_cache *pc, int actlen) 943 { 944 struct axge_frame_rxhdr pkt_hdr; 945 uint32_t rxhdr; 946 uint32_t pos; 947 uint32_t pkt_cnt, pkt_end; 948 uint32_t hdr_off; 949 uint32_t pktlen; 950 951 /* verify we have enough data */ 952 if (actlen < (int)sizeof(rxhdr)) 953 return; 954 955 pos = 0; 956 957 usbd_copy_out(pc, actlen - sizeof(rxhdr), &rxhdr, sizeof(rxhdr)); 958 rxhdr = le32toh(rxhdr); 959 960 pkt_cnt = rxhdr & 0xFFFF; 961 hdr_off = pkt_end = (rxhdr >> 16) & 0xFFFF; 962 963 /* 964 * <----------------------- actlen ------------------------> 965 * [frame #0]...[frame #N][pkt_hdr #0]...[pkt_hdr #N][rxhdr] 966 * Each RX frame would be aligned on 8 bytes boundary. If 967 * RCR_IPE bit is set in AXGE_RCR register, there would be 2 968 * padding bytes and 6 dummy bytes(as the padding also should 969 * be aligned on 8 bytes boundary) for each RX frame to align 970 * IP header on 32bits boundary. Driver don't set RCR_IPE bit 971 * of AXGE_RCR register, so there should be no padding bytes 972 * which simplifies RX logic a lot. 973 */ 974 while (pkt_cnt--) { 975 /* verify the header offset */ 976 if ((int)(hdr_off + sizeof(pkt_hdr)) > actlen) { 977 DPRINTF("End of packet headers\n"); 978 break; 979 } 980 usbd_copy_out(pc, hdr_off, &pkt_hdr, sizeof(pkt_hdr)); 981 pkt_hdr.status = le32toh(pkt_hdr.status); 982 pktlen = AXGE_RXBYTES(pkt_hdr.status); 983 if (pos + pktlen > pkt_end) { 984 DPRINTF("Data position reached end\n"); 985 break; 986 } 987 988 if (AXGE_RX_ERR(pkt_hdr.status) != 0) { 989 DPRINTF("Dropped a packet\n"); 990 if_inc_counter(ue->ue_ifp, IFCOUNTER_IERRORS, 1); 991 } else 992 axge_rxeof(ue, pc, pos, pktlen, pkt_hdr.status); 993 pos += (pktlen + 7) & ~7; 994 hdr_off += sizeof(pkt_hdr); 995 } 996 } 997 998 static void 999 axge_rxeof(struct usb_ether *ue, struct usb_page_cache *pc, unsigned offset, 1000 unsigned len, uint32_t status) 1001 { 1002 if_t ifp; 1003 struct mbuf *m; 1004 1005 ifp = ue->ue_ifp; 1006 if (len < ETHER_HDR_LEN || len > MCLBYTES - ETHER_ALIGN) { 1007 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 1008 return; 1009 } 1010 1011 if (len > MHLEN - ETHER_ALIGN) 1012 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1013 else 1014 m = m_gethdr(M_NOWAIT, MT_DATA); 1015 if (m == NULL) { 1016 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 1017 return; 1018 } 1019 m->m_pkthdr.rcvif = ifp; 1020 m->m_len = m->m_pkthdr.len = len; 1021 m->m_data += ETHER_ALIGN; 1022 1023 usbd_copy_out(pc, offset, mtod(m, uint8_t *), len); 1024 1025 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) { 1026 if ((status & AXGE_RX_L3_CSUM_ERR) == 0 && 1027 (status & AXGE_RX_L3_TYPE_MASK) == AXGE_RX_L3_TYPE_IPV4) 1028 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | 1029 CSUM_IP_VALID; 1030 if ((status & AXGE_RX_L4_CSUM_ERR) == 0 && 1031 ((status & AXGE_RX_L4_TYPE_MASK) == AXGE_RX_L4_TYPE_UDP || 1032 (status & AXGE_RX_L4_TYPE_MASK) == AXGE_RX_L4_TYPE_TCP)) { 1033 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 1034 CSUM_PSEUDO_HDR; 1035 m->m_pkthdr.csum_data = 0xffff; 1036 } 1037 } 1038 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 1039 1040 (void)mbufq_enqueue(&ue->ue_rxq, m); 1041 } 1042 1043 static void 1044 axge_csum_cfg(struct usb_ether *ue) 1045 { 1046 struct axge_softc *sc; 1047 if_t ifp; 1048 uint8_t csum; 1049 1050 sc = uether_getsc(ue); 1051 AXGE_LOCK_ASSERT(sc, MA_OWNED); 1052 ifp = uether_getifp(ue); 1053 1054 csum = 0; 1055 if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0) 1056 csum |= CTCR_IP | CTCR_TCP | CTCR_UDP; 1057 axge_write_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_CTCR, csum); 1058 1059 csum = 0; 1060 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) 1061 csum |= CRCR_IP | CRCR_TCP | CRCR_UDP; 1062 axge_write_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_CRCR, csum); 1063 } 1064