1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2013-2014 Kevin Lo 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 /* 33 * ASIX Electronics AX88178A/AX88179 USB 2.0/3.0 gigabit ethernet driver. 34 */ 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/bus.h> 39 #include <sys/condvar.h> 40 #include <sys/endian.h> 41 #include <sys/kernel.h> 42 #include <sys/lock.h> 43 #include <sys/module.h> 44 #include <sys/mutex.h> 45 #include <sys/socket.h> 46 #include <sys/sysctl.h> 47 #include <sys/unistd.h> 48 49 #include <net/if.h> 50 #include <net/if_var.h> 51 #include <net/if_media.h> 52 53 #include <dev/mii/mii.h> 54 #include <dev/mii/miivar.h> 55 56 #include <dev/usb/usb.h> 57 #include <dev/usb/usbdi.h> 58 #include <dev/usb/usbdi_util.h> 59 #include "usbdevs.h" 60 61 #define USB_DEBUG_VAR axge_debug 62 #include <dev/usb/usb_debug.h> 63 #include <dev/usb/usb_process.h> 64 65 #include <dev/usb/net/usb_ethernet.h> 66 #include <dev/usb/net/if_axgereg.h> 67 68 #include "miibus_if.h" 69 70 /* 71 * Various supported device vendors/products. 72 */ 73 74 static const STRUCT_USB_HOST_ID axge_devs[] = { 75 #define AXGE_DEV(v,p) { USB_VP(USB_VENDOR_##v, USB_PRODUCT_##v##_##p) } 76 AXGE_DEV(ASIX, AX88178A), 77 AXGE_DEV(ASIX, AX88179), 78 AXGE_DEV(BELKIN, B2B128), 79 AXGE_DEV(DLINK, DUB1312), 80 AXGE_DEV(LENOVO, GIGALAN), 81 AXGE_DEV(SITECOMEU, LN032), 82 #undef AXGE_DEV 83 }; 84 85 static const struct { 86 uint8_t ctrl; 87 uint8_t timer_l; 88 uint8_t timer_h; 89 uint8_t size; 90 uint8_t ifg; 91 } __packed axge_bulk_size[] = { 92 { 7, 0x4f, 0x00, 0x12, 0xff }, 93 { 7, 0x20, 0x03, 0x16, 0xff }, 94 { 7, 0xae, 0x07, 0x18, 0xff }, 95 { 7, 0xcc, 0x4c, 0x18, 0x08 } 96 }; 97 98 /* prototypes */ 99 100 static device_probe_t axge_probe; 101 static device_attach_t axge_attach; 102 static device_detach_t axge_detach; 103 104 static usb_callback_t axge_bulk_read_callback; 105 static usb_callback_t axge_bulk_write_callback; 106 107 static miibus_readreg_t axge_miibus_readreg; 108 static miibus_writereg_t axge_miibus_writereg; 109 static miibus_statchg_t axge_miibus_statchg; 110 111 static uether_fn_t axge_attach_post; 112 static uether_fn_t axge_init; 113 static uether_fn_t axge_stop; 114 static uether_fn_t axge_start; 115 static uether_fn_t axge_tick; 116 static uether_fn_t axge_rxfilter; 117 118 static int axge_read_mem(struct axge_softc *, uint8_t, uint16_t, 119 uint16_t, void *, int); 120 static void axge_write_mem(struct axge_softc *, uint8_t, uint16_t, 121 uint16_t, void *, int); 122 static uint8_t axge_read_cmd_1(struct axge_softc *, uint8_t, uint16_t); 123 static uint16_t axge_read_cmd_2(struct axge_softc *, uint8_t, uint16_t, 124 uint16_t); 125 static void axge_write_cmd_1(struct axge_softc *, uint8_t, uint16_t, 126 uint8_t); 127 static void axge_write_cmd_2(struct axge_softc *, uint8_t, uint16_t, 128 uint16_t, uint16_t); 129 static void axge_chip_init(struct axge_softc *); 130 static void axge_reset(struct axge_softc *); 131 132 static int axge_attach_post_sub(struct usb_ether *); 133 static int axge_ifmedia_upd(struct ifnet *); 134 static void axge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 135 static int axge_ioctl(struct ifnet *, u_long, caddr_t); 136 static void axge_rx_frame(struct usb_ether *, struct usb_page_cache *, int); 137 static void axge_rxeof(struct usb_ether *, struct usb_page_cache *, 138 unsigned int, unsigned int, uint32_t); 139 static void axge_csum_cfg(struct usb_ether *); 140 141 #define AXGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 142 143 #ifdef USB_DEBUG 144 static int axge_debug = 0; 145 146 static SYSCTL_NODE(_hw_usb, OID_AUTO, axge, CTLFLAG_RW | CTLFLAG_MPSAFE, 0, 147 "USB axge"); 148 SYSCTL_INT(_hw_usb_axge, OID_AUTO, debug, CTLFLAG_RWTUN, &axge_debug, 0, 149 "Debug level"); 150 #endif 151 152 static const struct usb_config axge_config[AXGE_N_TRANSFER] = { 153 [AXGE_BULK_DT_WR] = { 154 .type = UE_BULK, 155 .endpoint = UE_ADDR_ANY, 156 .direction = UE_DIR_OUT, 157 .frames = AXGE_N_FRAMES, 158 .bufsize = AXGE_N_FRAMES * MCLBYTES, 159 .flags = {.pipe_bof = 1,.force_short_xfer = 1,}, 160 .callback = axge_bulk_write_callback, 161 .timeout = 10000, /* 10 seconds */ 162 }, 163 [AXGE_BULK_DT_RD] = { 164 .type = UE_BULK, 165 .endpoint = UE_ADDR_ANY, 166 .direction = UE_DIR_IN, 167 .bufsize = 65536, 168 .flags = {.pipe_bof = 1,.short_xfer_ok = 1,}, 169 .callback = axge_bulk_read_callback, 170 .timeout = 0, /* no timeout */ 171 }, 172 }; 173 174 static device_method_t axge_methods[] = { 175 /* Device interface. */ 176 DEVMETHOD(device_probe, axge_probe), 177 DEVMETHOD(device_attach, axge_attach), 178 DEVMETHOD(device_detach, axge_detach), 179 180 /* MII interface. */ 181 DEVMETHOD(miibus_readreg, axge_miibus_readreg), 182 DEVMETHOD(miibus_writereg, axge_miibus_writereg), 183 DEVMETHOD(miibus_statchg, axge_miibus_statchg), 184 185 DEVMETHOD_END 186 }; 187 188 static driver_t axge_driver = { 189 .name = "axge", 190 .methods = axge_methods, 191 .size = sizeof(struct axge_softc), 192 }; 193 194 DRIVER_MODULE(axge, uhub, axge_driver, NULL, NULL); 195 DRIVER_MODULE(miibus, axge, miibus_driver, NULL, NULL); 196 MODULE_DEPEND(axge, uether, 1, 1, 1); 197 MODULE_DEPEND(axge, usb, 1, 1, 1); 198 MODULE_DEPEND(axge, ether, 1, 1, 1); 199 MODULE_DEPEND(axge, miibus, 1, 1, 1); 200 MODULE_VERSION(axge, 1); 201 USB_PNP_HOST_INFO(axge_devs); 202 203 static const struct usb_ether_methods axge_ue_methods = { 204 .ue_attach_post = axge_attach_post, 205 .ue_attach_post_sub = axge_attach_post_sub, 206 .ue_start = axge_start, 207 .ue_init = axge_init, 208 .ue_stop = axge_stop, 209 .ue_tick = axge_tick, 210 .ue_setmulti = axge_rxfilter, 211 .ue_setpromisc = axge_rxfilter, 212 .ue_mii_upd = axge_ifmedia_upd, 213 .ue_mii_sts = axge_ifmedia_sts, 214 }; 215 216 static int 217 axge_read_mem(struct axge_softc *sc, uint8_t cmd, uint16_t index, 218 uint16_t val, void *buf, int len) 219 { 220 struct usb_device_request req; 221 222 AXGE_LOCK_ASSERT(sc, MA_OWNED); 223 224 req.bmRequestType = UT_READ_VENDOR_DEVICE; 225 req.bRequest = cmd; 226 USETW(req.wValue, val); 227 USETW(req.wIndex, index); 228 USETW(req.wLength, len); 229 230 return (uether_do_request(&sc->sc_ue, &req, buf, 1000)); 231 } 232 233 static void 234 axge_write_mem(struct axge_softc *sc, uint8_t cmd, uint16_t index, 235 uint16_t val, void *buf, int len) 236 { 237 struct usb_device_request req; 238 239 AXGE_LOCK_ASSERT(sc, MA_OWNED); 240 241 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 242 req.bRequest = cmd; 243 USETW(req.wValue, val); 244 USETW(req.wIndex, index); 245 USETW(req.wLength, len); 246 247 if (uether_do_request(&sc->sc_ue, &req, buf, 1000)) { 248 /* Error ignored. */ 249 } 250 } 251 252 static uint8_t 253 axge_read_cmd_1(struct axge_softc *sc, uint8_t cmd, uint16_t reg) 254 { 255 uint8_t val; 256 257 axge_read_mem(sc, cmd, 1, reg, &val, 1); 258 return (val); 259 } 260 261 static uint16_t 262 axge_read_cmd_2(struct axge_softc *sc, uint8_t cmd, uint16_t index, 263 uint16_t reg) 264 { 265 uint8_t val[2]; 266 267 axge_read_mem(sc, cmd, index, reg, &val, 2); 268 return (UGETW(val)); 269 } 270 271 static void 272 axge_write_cmd_1(struct axge_softc *sc, uint8_t cmd, uint16_t reg, uint8_t val) 273 { 274 axge_write_mem(sc, cmd, 1, reg, &val, 1); 275 } 276 277 static void 278 axge_write_cmd_2(struct axge_softc *sc, uint8_t cmd, uint16_t index, 279 uint16_t reg, uint16_t val) 280 { 281 uint8_t temp[2]; 282 283 USETW(temp, val); 284 axge_write_mem(sc, cmd, index, reg, &temp, 2); 285 } 286 287 static int 288 axge_miibus_readreg(device_t dev, int phy, int reg) 289 { 290 struct axge_softc *sc; 291 uint16_t val; 292 int locked; 293 294 sc = device_get_softc(dev); 295 locked = mtx_owned(&sc->sc_mtx); 296 if (!locked) 297 AXGE_LOCK(sc); 298 299 val = axge_read_cmd_2(sc, AXGE_ACCESS_PHY, reg, phy); 300 301 if (!locked) 302 AXGE_UNLOCK(sc); 303 304 return (val); 305 } 306 307 static int 308 axge_miibus_writereg(device_t dev, int phy, int reg, int val) 309 { 310 struct axge_softc *sc; 311 int locked; 312 313 sc = device_get_softc(dev); 314 locked = mtx_owned(&sc->sc_mtx); 315 if (!locked) 316 AXGE_LOCK(sc); 317 318 axge_write_cmd_2(sc, AXGE_ACCESS_PHY, reg, phy, val); 319 320 if (!locked) 321 AXGE_UNLOCK(sc); 322 323 return (0); 324 } 325 326 static void 327 axge_miibus_statchg(device_t dev) 328 { 329 struct axge_softc *sc; 330 struct mii_data *mii; 331 struct ifnet *ifp; 332 uint8_t link_status, tmp[5]; 333 uint16_t val; 334 int locked; 335 336 sc = device_get_softc(dev); 337 mii = GET_MII(sc); 338 locked = mtx_owned(&sc->sc_mtx); 339 if (!locked) 340 AXGE_LOCK(sc); 341 342 ifp = uether_getifp(&sc->sc_ue); 343 if (mii == NULL || ifp == NULL || 344 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 345 goto done; 346 347 sc->sc_flags &= ~AXGE_FLAG_LINK; 348 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 349 (IFM_ACTIVE | IFM_AVALID)) { 350 switch (IFM_SUBTYPE(mii->mii_media_active)) { 351 case IFM_10_T: 352 case IFM_100_TX: 353 case IFM_1000_T: 354 sc->sc_flags |= AXGE_FLAG_LINK; 355 break; 356 default: 357 break; 358 } 359 } 360 361 /* Lost link, do nothing. */ 362 if ((sc->sc_flags & AXGE_FLAG_LINK) == 0) 363 goto done; 364 365 link_status = axge_read_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_PLSR); 366 367 val = 0; 368 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 369 val |= MSR_FD; 370 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 371 val |= MSR_TFC; 372 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 373 val |= MSR_RFC; 374 } 375 val |= MSR_RE; 376 switch (IFM_SUBTYPE(mii->mii_media_active)) { 377 case IFM_1000_T: 378 val |= MSR_GM | MSR_EN_125MHZ; 379 if (link_status & PLSR_USB_SS) 380 memcpy(tmp, &axge_bulk_size[0], 5); 381 else if (link_status & PLSR_USB_HS) 382 memcpy(tmp, &axge_bulk_size[1], 5); 383 else 384 memcpy(tmp, &axge_bulk_size[3], 5); 385 break; 386 case IFM_100_TX: 387 val |= MSR_PS; 388 if (link_status & (PLSR_USB_SS | PLSR_USB_HS)) 389 memcpy(tmp, &axge_bulk_size[2], 5); 390 else 391 memcpy(tmp, &axge_bulk_size[3], 5); 392 break; 393 case IFM_10_T: 394 memcpy(tmp, &axge_bulk_size[3], 5); 395 break; 396 } 397 /* Rx bulk configuration. */ 398 axge_write_mem(sc, AXGE_ACCESS_MAC, 5, AXGE_RX_BULKIN_QCTRL, tmp, 5); 399 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_MSR, val); 400 done: 401 if (!locked) 402 AXGE_UNLOCK(sc); 403 } 404 405 static void 406 axge_chip_init(struct axge_softc *sc) 407 { 408 /* Power up ethernet PHY. */ 409 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_EPPRCR, 0); 410 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_EPPRCR, EPPRCR_IPRL); 411 uether_pause(&sc->sc_ue, hz / 4); 412 axge_write_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_CLK_SELECT, 413 AXGE_CLK_SELECT_ACS | AXGE_CLK_SELECT_BCS); 414 uether_pause(&sc->sc_ue, hz / 10); 415 } 416 417 static void 418 axge_reset(struct axge_softc *sc) 419 { 420 struct usb_config_descriptor *cd; 421 usb_error_t err; 422 423 cd = usbd_get_config_descriptor(sc->sc_ue.ue_udev); 424 425 err = usbd_req_set_config(sc->sc_ue.ue_udev, &sc->sc_mtx, 426 cd->bConfigurationValue); 427 if (err) 428 DPRINTF("reset failed (ignored)\n"); 429 430 /* Wait a little while for the chip to get its brains in order. */ 431 uether_pause(&sc->sc_ue, hz / 100); 432 433 /* Reinitialize controller to achieve full reset. */ 434 axge_chip_init(sc); 435 } 436 437 static void 438 axge_attach_post(struct usb_ether *ue) 439 { 440 struct axge_softc *sc; 441 442 sc = uether_getsc(ue); 443 444 /* Initialize controller and get station address. */ 445 axge_chip_init(sc); 446 axge_read_mem(sc, AXGE_ACCESS_MAC, ETHER_ADDR_LEN, AXGE_NIDR, 447 ue->ue_eaddr, ETHER_ADDR_LEN); 448 } 449 450 static int 451 axge_attach_post_sub(struct usb_ether *ue) 452 { 453 struct ifnet *ifp; 454 int error; 455 456 ifp = ue->ue_ifp; 457 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 458 ifp->if_start = uether_start; 459 ifp->if_ioctl = axge_ioctl; 460 ifp->if_init = uether_init; 461 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen); 462 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen; 463 IFQ_SET_READY(&ifp->if_snd); 464 465 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_TXCSUM | IFCAP_RXCSUM; 466 ifp->if_hwassist = AXGE_CSUM_FEATURES; 467 ifp->if_capenable = ifp->if_capabilities; 468 469 bus_topo_lock(); 470 error = mii_attach(ue->ue_dev, &ue->ue_miibus, ifp, 471 uether_ifmedia_upd, ue->ue_methods->ue_mii_sts, 472 BMSR_DEFCAPMASK, AXGE_PHY_ADDR, MII_OFFSET_ANY, MIIF_DOPAUSE); 473 bus_topo_unlock(); 474 475 return (error); 476 } 477 478 /* 479 * Set media options. 480 */ 481 static int 482 axge_ifmedia_upd(struct ifnet *ifp) 483 { 484 struct axge_softc *sc; 485 struct mii_data *mii; 486 struct mii_softc *miisc; 487 int error; 488 489 sc = ifp->if_softc; 490 mii = GET_MII(sc); 491 AXGE_LOCK_ASSERT(sc, MA_OWNED); 492 493 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 494 PHY_RESET(miisc); 495 error = mii_mediachg(mii); 496 497 return (error); 498 } 499 500 /* 501 * Report current media status. 502 */ 503 static void 504 axge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 505 { 506 struct axge_softc *sc; 507 struct mii_data *mii; 508 509 sc = ifp->if_softc; 510 mii = GET_MII(sc); 511 AXGE_LOCK(sc); 512 mii_pollstat(mii); 513 ifmr->ifm_active = mii->mii_media_active; 514 ifmr->ifm_status = mii->mii_media_status; 515 AXGE_UNLOCK(sc); 516 } 517 518 /* 519 * Probe for a AX88179 chip. 520 */ 521 static int 522 axge_probe(device_t dev) 523 { 524 struct usb_attach_arg *uaa; 525 526 uaa = device_get_ivars(dev); 527 if (uaa->usb_mode != USB_MODE_HOST) 528 return (ENXIO); 529 if (uaa->info.bConfigIndex != AXGE_CONFIG_IDX) 530 return (ENXIO); 531 if (uaa->info.bIfaceIndex != AXGE_IFACE_IDX) 532 return (ENXIO); 533 534 return (usbd_lookup_id_by_uaa(axge_devs, sizeof(axge_devs), uaa)); 535 } 536 537 /* 538 * Attach the interface. Allocate softc structures, do ifmedia 539 * setup and ethernet/BPF attach. 540 */ 541 static int 542 axge_attach(device_t dev) 543 { 544 struct usb_attach_arg *uaa; 545 struct axge_softc *sc; 546 struct usb_ether *ue; 547 uint8_t iface_index; 548 int error; 549 550 uaa = device_get_ivars(dev); 551 sc = device_get_softc(dev); 552 ue = &sc->sc_ue; 553 554 device_set_usb_desc(dev); 555 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_DEF); 556 557 iface_index = AXGE_IFACE_IDX; 558 error = usbd_transfer_setup(uaa->device, &iface_index, 559 sc->sc_xfer, axge_config, AXGE_N_TRANSFER, sc, &sc->sc_mtx); 560 if (error) { 561 device_printf(dev, "allocating USB transfers failed\n"); 562 mtx_destroy(&sc->sc_mtx); 563 return (ENXIO); 564 } 565 566 ue->ue_sc = sc; 567 ue->ue_dev = dev; 568 ue->ue_udev = uaa->device; 569 ue->ue_mtx = &sc->sc_mtx; 570 ue->ue_methods = &axge_ue_methods; 571 572 error = uether_ifattach(ue); 573 if (error) { 574 device_printf(dev, "could not attach interface\n"); 575 goto detach; 576 } 577 return (0); /* success */ 578 579 detach: 580 axge_detach(dev); 581 return (ENXIO); /* failure */ 582 } 583 584 static int 585 axge_detach(device_t dev) 586 { 587 struct axge_softc *sc; 588 struct usb_ether *ue; 589 uint16_t val; 590 591 sc = device_get_softc(dev); 592 ue = &sc->sc_ue; 593 if (device_is_attached(dev)) { 594 /* wait for any post attach or other command to complete */ 595 usb_proc_drain(&ue->ue_tq); 596 597 AXGE_LOCK(sc); 598 /* 599 * XXX 600 * ether_ifdetach(9) should be called first. 601 */ 602 axge_stop(ue); 603 /* Force bulk-in to return a zero-length USB packet. */ 604 val = axge_read_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_EPPRCR); 605 val |= EPPRCR_BZ | EPPRCR_IPRL; 606 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_EPPRCR, val); 607 /* Change clock. */ 608 axge_write_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_CLK_SELECT, 0); 609 /* Disable MAC. */ 610 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_RCR, 0); 611 AXGE_UNLOCK(sc); 612 } 613 usbd_transfer_unsetup(sc->sc_xfer, AXGE_N_TRANSFER); 614 uether_ifdetach(ue); 615 mtx_destroy(&sc->sc_mtx); 616 617 return (0); 618 } 619 620 static void 621 axge_bulk_read_callback(struct usb_xfer *xfer, usb_error_t error) 622 { 623 struct axge_softc *sc; 624 struct usb_ether *ue; 625 struct usb_page_cache *pc; 626 int actlen; 627 628 sc = usbd_xfer_softc(xfer); 629 ue = &sc->sc_ue; 630 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL); 631 632 switch (USB_GET_STATE(xfer)) { 633 case USB_ST_TRANSFERRED: 634 pc = usbd_xfer_get_frame(xfer, 0); 635 axge_rx_frame(ue, pc, actlen); 636 637 /* FALLTHROUGH */ 638 case USB_ST_SETUP: 639 tr_setup: 640 usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer)); 641 usbd_transfer_submit(xfer); 642 uether_rxflush(ue); 643 break; 644 645 default: 646 if (error != USB_ERR_CANCELLED) { 647 usbd_xfer_set_stall(xfer); 648 goto tr_setup; 649 } 650 break; 651 } 652 } 653 654 static void 655 axge_bulk_write_callback(struct usb_xfer *xfer, usb_error_t error) 656 { 657 struct axge_softc *sc; 658 struct ifnet *ifp; 659 struct usb_page_cache *pc; 660 struct mbuf *m; 661 struct axge_frame_txhdr txhdr; 662 int nframes, pos; 663 664 sc = usbd_xfer_softc(xfer); 665 ifp = uether_getifp(&sc->sc_ue); 666 667 switch (USB_GET_STATE(xfer)) { 668 case USB_ST_TRANSFERRED: 669 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 670 /* FALLTHROUGH */ 671 case USB_ST_SETUP: 672 tr_setup: 673 if ((sc->sc_flags & AXGE_FLAG_LINK) == 0 || 674 (ifp->if_drv_flags & IFF_DRV_OACTIVE) != 0) { 675 /* 676 * Don't send anything if there is no link or 677 * controller is busy. 678 */ 679 return; 680 } 681 682 for (nframes = 0; nframes < AXGE_N_FRAMES && 683 !IFQ_DRV_IS_EMPTY(&ifp->if_snd); nframes++) { 684 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 685 if (m == NULL) 686 break; 687 usbd_xfer_set_frame_offset(xfer, nframes * MCLBYTES, 688 nframes); 689 pc = usbd_xfer_get_frame(xfer, nframes); 690 txhdr.mss = 0; 691 txhdr.len = htole32(AXGE_TXBYTES(m->m_pkthdr.len)); 692 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0 && 693 (m->m_pkthdr.csum_flags & AXGE_CSUM_FEATURES) == 0) 694 txhdr.len |= htole32(AXGE_CSUM_DISABLE); 695 696 pos = 0; 697 usbd_copy_in(pc, pos, &txhdr, sizeof(txhdr)); 698 pos += sizeof(txhdr); 699 usbd_m_copy_in(pc, pos, m, 0, m->m_pkthdr.len); 700 pos += m->m_pkthdr.len; 701 702 /* 703 * if there's a BPF listener, bounce a copy 704 * of this frame to him: 705 */ 706 BPF_MTAP(ifp, m); 707 708 m_freem(m); 709 710 /* Set frame length. */ 711 usbd_xfer_set_frame_len(xfer, nframes, pos); 712 } 713 if (nframes != 0) { 714 /* 715 * XXX 716 * Update TX packet counter here. This is not 717 * correct way but it seems that there is no way 718 * to know how many packets are sent at the end 719 * of transfer because controller combines 720 * multiple writes into single one if there is 721 * room in TX buffer of controller. 722 */ 723 if_inc_counter(ifp, IFCOUNTER_OPACKETS, nframes); 724 usbd_xfer_set_frames(xfer, nframes); 725 usbd_transfer_submit(xfer); 726 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 727 } 728 return; 729 /* NOTREACHED */ 730 default: 731 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 732 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 733 734 if (error != USB_ERR_CANCELLED) { 735 usbd_xfer_set_stall(xfer); 736 goto tr_setup; 737 } 738 return; 739 } 740 } 741 742 static void 743 axge_tick(struct usb_ether *ue) 744 { 745 struct axge_softc *sc; 746 struct mii_data *mii; 747 748 sc = uether_getsc(ue); 749 mii = GET_MII(sc); 750 AXGE_LOCK_ASSERT(sc, MA_OWNED); 751 752 mii_tick(mii); 753 } 754 755 static u_int 756 axge_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 757 { 758 uint8_t *hashtbl = arg; 759 uint32_t h; 760 761 h = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN) >> 26; 762 hashtbl[h / 8] |= 1 << (h % 8); 763 764 return (1); 765 } 766 767 static void 768 axge_rxfilter(struct usb_ether *ue) 769 { 770 struct axge_softc *sc; 771 struct ifnet *ifp; 772 uint16_t rxmode; 773 uint8_t hashtbl[8] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 774 775 sc = uether_getsc(ue); 776 ifp = uether_getifp(ue); 777 AXGE_LOCK_ASSERT(sc, MA_OWNED); 778 779 /* 780 * Configure RX settings. 781 * Don't set RCR_IPE(IP header alignment on 32bit boundary) to disable 782 * inserting extra padding bytes. This wastes ethernet to USB host 783 * bandwidth as well as complicating RX handling logic. Current USB 784 * framework requires copying RX frames to mbufs so there is no need 785 * to worry about alignment. 786 */ 787 rxmode = RCR_DROP_CRCERR | RCR_START; 788 if (ifp->if_flags & IFF_BROADCAST) 789 rxmode |= RCR_ACPT_BCAST; 790 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) { 791 if (ifp->if_flags & IFF_PROMISC) 792 rxmode |= RCR_PROMISC; 793 rxmode |= RCR_ACPT_ALL_MCAST; 794 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_RCR, rxmode); 795 return; 796 } 797 798 rxmode |= RCR_ACPT_MCAST; 799 if_foreach_llmaddr(ifp, axge_hash_maddr, &hashtbl); 800 801 axge_write_mem(sc, AXGE_ACCESS_MAC, 8, AXGE_MFA, (void *)&hashtbl, 8); 802 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_RCR, rxmode); 803 } 804 805 static void 806 axge_start(struct usb_ether *ue) 807 { 808 struct axge_softc *sc; 809 810 sc = uether_getsc(ue); 811 /* 812 * Start the USB transfers, if not already started. 813 */ 814 usbd_transfer_start(sc->sc_xfer[AXGE_BULK_DT_RD]); 815 usbd_transfer_start(sc->sc_xfer[AXGE_BULK_DT_WR]); 816 } 817 818 static void 819 axge_init(struct usb_ether *ue) 820 { 821 struct axge_softc *sc; 822 struct ifnet *ifp; 823 824 sc = uether_getsc(ue); 825 ifp = uether_getifp(ue); 826 AXGE_LOCK_ASSERT(sc, MA_OWNED); 827 828 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 829 return; 830 831 /* 832 * Cancel pending I/O and free all RX/TX buffers. 833 */ 834 axge_stop(ue); 835 836 axge_reset(sc); 837 838 /* Set MAC address. */ 839 axge_write_mem(sc, AXGE_ACCESS_MAC, ETHER_ADDR_LEN, AXGE_NIDR, 840 IF_LLADDR(ifp), ETHER_ADDR_LEN); 841 842 axge_write_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_PWLLR, 0x34); 843 axge_write_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_PWLHR, 0x52); 844 845 /* Configure TX/RX checksum offloading. */ 846 axge_csum_cfg(ue); 847 848 /* Configure RX filters. */ 849 axge_rxfilter(ue); 850 851 /* 852 * XXX 853 * Controller supports wakeup on link change detection, 854 * magic packet and wakeup frame recpetion. But it seems 855 * there is no framework for USB ethernet suspend/wakeup. 856 * Disable all wakeup functions. 857 */ 858 axge_write_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_MMSR, 0); 859 (void)axge_read_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_MMSR); 860 861 /* Configure default medium type. */ 862 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_MSR, MSR_GM | MSR_FD | 863 MSR_RFC | MSR_TFC | MSR_RE); 864 865 usbd_xfer_set_stall(sc->sc_xfer[AXGE_BULK_DT_WR]); 866 867 ifp->if_drv_flags |= IFF_DRV_RUNNING; 868 /* Switch to selected media. */ 869 axge_ifmedia_upd(ifp); 870 } 871 872 static void 873 axge_stop(struct usb_ether *ue) 874 { 875 struct axge_softc *sc; 876 struct ifnet *ifp; 877 uint16_t val; 878 879 sc = uether_getsc(ue); 880 ifp = uether_getifp(ue); 881 882 AXGE_LOCK_ASSERT(sc, MA_OWNED); 883 884 val = axge_read_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_MSR); 885 val &= ~MSR_RE; 886 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_MSR, val); 887 888 if (ifp != NULL) 889 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 890 sc->sc_flags &= ~AXGE_FLAG_LINK; 891 892 /* 893 * Stop all the transfers, if not already stopped: 894 */ 895 usbd_transfer_stop(sc->sc_xfer[AXGE_BULK_DT_WR]); 896 usbd_transfer_stop(sc->sc_xfer[AXGE_BULK_DT_RD]); 897 } 898 899 static int 900 axge_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 901 { 902 struct usb_ether *ue; 903 struct axge_softc *sc; 904 struct ifreq *ifr; 905 int error, mask, reinit; 906 907 ue = ifp->if_softc; 908 sc = uether_getsc(ue); 909 ifr = (struct ifreq *)data; 910 error = 0; 911 reinit = 0; 912 if (cmd == SIOCSIFCAP) { 913 AXGE_LOCK(sc); 914 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 915 if ((mask & IFCAP_TXCSUM) != 0 && 916 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 917 ifp->if_capenable ^= IFCAP_TXCSUM; 918 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 919 ifp->if_hwassist |= AXGE_CSUM_FEATURES; 920 else 921 ifp->if_hwassist &= ~AXGE_CSUM_FEATURES; 922 reinit++; 923 } 924 if ((mask & IFCAP_RXCSUM) != 0 && 925 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) { 926 ifp->if_capenable ^= IFCAP_RXCSUM; 927 reinit++; 928 } 929 if (reinit > 0 && ifp->if_drv_flags & IFF_DRV_RUNNING) 930 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 931 else 932 reinit = 0; 933 AXGE_UNLOCK(sc); 934 if (reinit > 0) 935 uether_init(ue); 936 } else 937 error = uether_ioctl(ifp, cmd, data); 938 939 return (error); 940 } 941 942 static void 943 axge_rx_frame(struct usb_ether *ue, struct usb_page_cache *pc, int actlen) 944 { 945 struct axge_frame_rxhdr pkt_hdr; 946 uint32_t rxhdr; 947 uint32_t pos; 948 uint32_t pkt_cnt, pkt_end; 949 uint32_t hdr_off; 950 uint32_t pktlen; 951 952 /* verify we have enough data */ 953 if (actlen < (int)sizeof(rxhdr)) 954 return; 955 956 pos = 0; 957 958 usbd_copy_out(pc, actlen - sizeof(rxhdr), &rxhdr, sizeof(rxhdr)); 959 rxhdr = le32toh(rxhdr); 960 961 pkt_cnt = rxhdr & 0xFFFF; 962 hdr_off = pkt_end = (rxhdr >> 16) & 0xFFFF; 963 964 /* 965 * <----------------------- actlen ------------------------> 966 * [frame #0]...[frame #N][pkt_hdr #0]...[pkt_hdr #N][rxhdr] 967 * Each RX frame would be aligned on 8 bytes boundary. If 968 * RCR_IPE bit is set in AXGE_RCR register, there would be 2 969 * padding bytes and 6 dummy bytes(as the padding also should 970 * be aligned on 8 bytes boundary) for each RX frame to align 971 * IP header on 32bits boundary. Driver don't set RCR_IPE bit 972 * of AXGE_RCR register, so there should be no padding bytes 973 * which simplifies RX logic a lot. 974 */ 975 while (pkt_cnt--) { 976 /* verify the header offset */ 977 if ((int)(hdr_off + sizeof(pkt_hdr)) > actlen) { 978 DPRINTF("End of packet headers\n"); 979 break; 980 } 981 usbd_copy_out(pc, hdr_off, &pkt_hdr, sizeof(pkt_hdr)); 982 pkt_hdr.status = le32toh(pkt_hdr.status); 983 pktlen = AXGE_RXBYTES(pkt_hdr.status); 984 if (pos + pktlen > pkt_end) { 985 DPRINTF("Data position reached end\n"); 986 break; 987 } 988 989 if (AXGE_RX_ERR(pkt_hdr.status) != 0) { 990 DPRINTF("Dropped a packet\n"); 991 if_inc_counter(ue->ue_ifp, IFCOUNTER_IERRORS, 1); 992 } else 993 axge_rxeof(ue, pc, pos, pktlen, pkt_hdr.status); 994 pos += (pktlen + 7) & ~7; 995 hdr_off += sizeof(pkt_hdr); 996 } 997 } 998 999 static void 1000 axge_rxeof(struct usb_ether *ue, struct usb_page_cache *pc, unsigned int offset, 1001 unsigned int len, uint32_t status) 1002 { 1003 struct ifnet *ifp; 1004 struct mbuf *m; 1005 1006 ifp = ue->ue_ifp; 1007 if (len < ETHER_HDR_LEN || len > MCLBYTES - ETHER_ALIGN) { 1008 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 1009 return; 1010 } 1011 1012 if (len > MHLEN - ETHER_ALIGN) 1013 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1014 else 1015 m = m_gethdr(M_NOWAIT, MT_DATA); 1016 if (m == NULL) { 1017 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 1018 return; 1019 } 1020 m->m_pkthdr.rcvif = ifp; 1021 m->m_len = m->m_pkthdr.len = len; 1022 m->m_data += ETHER_ALIGN; 1023 1024 usbd_copy_out(pc, offset, mtod(m, uint8_t *), len); 1025 1026 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) { 1027 if ((status & AXGE_RX_L3_CSUM_ERR) == 0 && 1028 (status & AXGE_RX_L3_TYPE_MASK) == AXGE_RX_L3_TYPE_IPV4) 1029 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | 1030 CSUM_IP_VALID; 1031 if ((status & AXGE_RX_L4_CSUM_ERR) == 0 && 1032 ((status & AXGE_RX_L4_TYPE_MASK) == AXGE_RX_L4_TYPE_UDP || 1033 (status & AXGE_RX_L4_TYPE_MASK) == AXGE_RX_L4_TYPE_TCP)) { 1034 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 1035 CSUM_PSEUDO_HDR; 1036 m->m_pkthdr.csum_data = 0xffff; 1037 } 1038 } 1039 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 1040 1041 (void)mbufq_enqueue(&ue->ue_rxq, m); 1042 } 1043 1044 static void 1045 axge_csum_cfg(struct usb_ether *ue) 1046 { 1047 struct axge_softc *sc; 1048 struct ifnet *ifp; 1049 uint8_t csum; 1050 1051 sc = uether_getsc(ue); 1052 AXGE_LOCK_ASSERT(sc, MA_OWNED); 1053 ifp = uether_getifp(ue); 1054 1055 csum = 0; 1056 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 1057 csum |= CTCR_IP | CTCR_TCP | CTCR_UDP; 1058 axge_write_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_CTCR, csum); 1059 1060 csum = 0; 1061 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 1062 csum |= CRCR_IP | CRCR_TCP | CRCR_UDP; 1063 axge_write_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_CRCR, csum); 1064 } 1065