1 /*- 2 * Copyright (c) 2015-2016 Kevin Lo <kevlo@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/bus.h> 33 #include <sys/condvar.h> 34 #include <sys/kernel.h> 35 #include <sys/lock.h> 36 #include <sys/module.h> 37 #include <sys/mutex.h> 38 #include <sys/sbuf.h> 39 #include <sys/socket.h> 40 #include <sys/sysctl.h> 41 #include <sys/unistd.h> 42 43 #include <net/if.h> 44 #include <net/if_var.h> 45 #include <net/if_media.h> 46 47 /* needed for checksum offload */ 48 #include <netinet/in.h> 49 #include <netinet/ip.h> 50 51 #include <dev/mii/mii.h> 52 #include <dev/mii/miivar.h> 53 54 #include <dev/usb/usb.h> 55 #include <dev/usb/usbdi.h> 56 #include <dev/usb/usbdi_util.h> 57 #include "usbdevs.h" 58 59 #define USB_DEBUG_VAR ure_debug 60 #include <dev/usb/usb_debug.h> 61 #include <dev/usb/usb_process.h> 62 63 #include <dev/usb/net/usb_ethernet.h> 64 #include <dev/usb/net/if_urereg.h> 65 66 #include "miibus_if.h" 67 68 #include "opt_inet6.h" 69 70 #ifdef USB_DEBUG 71 static int ure_debug = 0; 72 73 static SYSCTL_NODE(_hw_usb, OID_AUTO, ure, CTLFLAG_RW | CTLFLAG_MPSAFE, 0, 74 "USB ure"); 75 SYSCTL_INT(_hw_usb_ure, OID_AUTO, debug, CTLFLAG_RWTUN, &ure_debug, 0, 76 "Debug level"); 77 #endif 78 79 #ifdef USB_DEBUG_VAR 80 #ifdef USB_DEBUG 81 #define DEVPRINTFN(n,dev,fmt,...) do { \ 82 if ((USB_DEBUG_VAR) >= (n)) { \ 83 device_printf((dev), "%s: " fmt, \ 84 __FUNCTION__ ,##__VA_ARGS__); \ 85 } \ 86 } while (0) 87 #define DEVPRINTF(...) DEVPRINTFN(1, __VA_ARGS__) 88 #else 89 #define DEVPRINTF(...) do { } while (0) 90 #define DEVPRINTFN(...) do { } while (0) 91 #endif 92 #endif 93 94 /* 95 * Various supported device vendors/products. 96 */ 97 static const STRUCT_USB_HOST_ID ure_devs[] = { 98 #define URE_DEV(v,p,i) { \ 99 USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, i), \ 100 USB_IFACE_CLASS(UICLASS_VENDOR), \ 101 USB_IFACE_SUBCLASS(UISUBCLASS_VENDOR) } 102 URE_DEV(LENOVO, RTL8153, URE_FLAG_8153), 103 URE_DEV(LENOVO, TBT3LAN, 0), 104 URE_DEV(LENOVO, TBT3LANGEN2, 0), 105 URE_DEV(LENOVO, ONELINK, 0), 106 URE_DEV(LENOVO, RTL8153_04, URE_FLAG_8153), 107 URE_DEV(LENOVO, USBCLAN, 0), 108 URE_DEV(LENOVO, USBCLANGEN2, 0), 109 URE_DEV(MICROSOFT, WINDEVETH, 0), 110 URE_DEV(NVIDIA, RTL8153, URE_FLAG_8153), 111 URE_DEV(REALTEK, RTL8152, URE_FLAG_8152), 112 URE_DEV(REALTEK, RTL8153, URE_FLAG_8153), 113 URE_DEV(TPLINK, RTL8153, URE_FLAG_8153), 114 URE_DEV(REALTEK, RTL8156, URE_FLAG_8156), 115 #undef URE_DEV 116 }; 117 118 static device_probe_t ure_probe; 119 static device_attach_t ure_attach; 120 static device_detach_t ure_detach; 121 122 static usb_callback_t ure_bulk_read_callback; 123 static usb_callback_t ure_bulk_write_callback; 124 125 static miibus_readreg_t ure_miibus_readreg; 126 static miibus_writereg_t ure_miibus_writereg; 127 static miibus_statchg_t ure_miibus_statchg; 128 129 static uether_fn_t ure_attach_post; 130 static uether_fn_t ure_init; 131 static uether_fn_t ure_stop; 132 static uether_fn_t ure_start; 133 static uether_fn_t ure_tick; 134 static uether_fn_t ure_rxfilter; 135 136 static int ure_ctl(struct ure_softc *, uint8_t, uint16_t, uint16_t, 137 void *, int); 138 static int ure_read_mem(struct ure_softc *, uint16_t, uint16_t, void *, 139 int); 140 static int ure_write_mem(struct ure_softc *, uint16_t, uint16_t, void *, 141 int); 142 static uint8_t ure_read_1(struct ure_softc *, uint16_t, uint16_t); 143 static uint16_t ure_read_2(struct ure_softc *, uint16_t, uint16_t); 144 static uint32_t ure_read_4(struct ure_softc *, uint16_t, uint16_t); 145 static int ure_write_1(struct ure_softc *, uint16_t, uint16_t, uint32_t); 146 static int ure_write_2(struct ure_softc *, uint16_t, uint16_t, uint32_t); 147 static int ure_write_4(struct ure_softc *, uint16_t, uint16_t, uint32_t); 148 static uint16_t ure_ocp_reg_read(struct ure_softc *, uint16_t); 149 static void ure_ocp_reg_write(struct ure_softc *, uint16_t, uint16_t); 150 static void ure_sram_write(struct ure_softc *, uint16_t, uint16_t); 151 152 static int ure_sysctl_chipver(SYSCTL_HANDLER_ARGS); 153 154 static void ure_read_chipver(struct ure_softc *); 155 static int ure_attach_post_sub(struct usb_ether *); 156 static void ure_reset(struct ure_softc *); 157 static int ure_ifmedia_upd(struct ifnet *); 158 static void ure_ifmedia_sts(struct ifnet *, struct ifmediareq *); 159 static void ure_add_media_types(struct ure_softc *); 160 static void ure_link_state(struct ure_softc *sc); 161 static int ure_get_link_status(struct ure_softc *); 162 static int ure_ioctl(struct ifnet *, u_long, caddr_t); 163 static void ure_rtl8152_init(struct ure_softc *); 164 static void ure_rtl8152_nic_reset(struct ure_softc *); 165 static void ure_rtl8153_init(struct ure_softc *); 166 static void ure_rtl8153b_init(struct ure_softc *); 167 static void ure_rtl8153b_nic_reset(struct ure_softc *); 168 static void ure_disable_teredo(struct ure_softc *); 169 static void ure_enable_aldps(struct ure_softc *, bool); 170 static uint16_t ure_phy_status(struct ure_softc *, uint16_t); 171 static void ure_rxcsum(int capenb, struct ure_rxpkt *rp, struct mbuf *m); 172 static int ure_txcsum(struct mbuf *m, int caps, uint32_t *regout); 173 174 static device_method_t ure_methods[] = { 175 /* Device interface. */ 176 DEVMETHOD(device_probe, ure_probe), 177 DEVMETHOD(device_attach, ure_attach), 178 DEVMETHOD(device_detach, ure_detach), 179 180 /* MII interface. */ 181 DEVMETHOD(miibus_readreg, ure_miibus_readreg), 182 DEVMETHOD(miibus_writereg, ure_miibus_writereg), 183 DEVMETHOD(miibus_statchg, ure_miibus_statchg), 184 185 DEVMETHOD_END 186 }; 187 188 static driver_t ure_driver = { 189 .name = "ure", 190 .methods = ure_methods, 191 .size = sizeof(struct ure_softc), 192 }; 193 194 DRIVER_MODULE(ure, uhub, ure_driver, NULL, NULL); 195 DRIVER_MODULE(miibus, ure, miibus_driver, NULL, NULL); 196 MODULE_DEPEND(ure, uether, 1, 1, 1); 197 MODULE_DEPEND(ure, usb, 1, 1, 1); 198 MODULE_DEPEND(ure, ether, 1, 1, 1); 199 MODULE_DEPEND(ure, miibus, 1, 1, 1); 200 MODULE_VERSION(ure, 1); 201 USB_PNP_HOST_INFO(ure_devs); 202 203 static const struct usb_ether_methods ure_ue_methods = { 204 .ue_attach_post = ure_attach_post, 205 .ue_attach_post_sub = ure_attach_post_sub, 206 .ue_start = ure_start, 207 .ue_init = ure_init, 208 .ue_stop = ure_stop, 209 .ue_tick = ure_tick, 210 .ue_setmulti = ure_rxfilter, 211 .ue_setpromisc = ure_rxfilter, 212 .ue_mii_upd = ure_ifmedia_upd, 213 .ue_mii_sts = ure_ifmedia_sts, 214 }; 215 216 #define URE_SETBIT_1(sc, reg, index, x) \ 217 ure_write_1(sc, reg, index, ure_read_1(sc, reg, index) | (x)) 218 #define URE_SETBIT_2(sc, reg, index, x) \ 219 ure_write_2(sc, reg, index, ure_read_2(sc, reg, index) | (x)) 220 #define URE_SETBIT_4(sc, reg, index, x) \ 221 ure_write_4(sc, reg, index, ure_read_4(sc, reg, index) | (x)) 222 223 #define URE_CLRBIT_1(sc, reg, index, x) \ 224 ure_write_1(sc, reg, index, ure_read_1(sc, reg, index) & ~(x)) 225 #define URE_CLRBIT_2(sc, reg, index, x) \ 226 ure_write_2(sc, reg, index, ure_read_2(sc, reg, index) & ~(x)) 227 #define URE_CLRBIT_4(sc, reg, index, x) \ 228 ure_write_4(sc, reg, index, ure_read_4(sc, reg, index) & ~(x)) 229 230 static int 231 ure_ctl(struct ure_softc *sc, uint8_t rw, uint16_t val, uint16_t index, 232 void *buf, int len) 233 { 234 struct usb_device_request req; 235 236 URE_LOCK_ASSERT(sc, MA_OWNED); 237 238 if (rw == URE_CTL_WRITE) 239 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 240 else 241 req.bmRequestType = UT_READ_VENDOR_DEVICE; 242 req.bRequest = UR_SET_ADDRESS; 243 USETW(req.wValue, val); 244 USETW(req.wIndex, index); 245 USETW(req.wLength, len); 246 247 return (uether_do_request(&sc->sc_ue, &req, buf, 1000)); 248 } 249 250 static int 251 ure_read_mem(struct ure_softc *sc, uint16_t addr, uint16_t index, 252 void *buf, int len) 253 { 254 255 return (ure_ctl(sc, URE_CTL_READ, addr, index, buf, len)); 256 } 257 258 static int 259 ure_write_mem(struct ure_softc *sc, uint16_t addr, uint16_t index, 260 void *buf, int len) 261 { 262 263 return (ure_ctl(sc, URE_CTL_WRITE, addr, index, buf, len)); 264 } 265 266 static uint8_t 267 ure_read_1(struct ure_softc *sc, uint16_t reg, uint16_t index) 268 { 269 uint32_t val; 270 uint8_t temp[4]; 271 uint8_t shift; 272 273 shift = (reg & 3) << 3; 274 reg &= ~3; 275 276 ure_read_mem(sc, reg, index, &temp, 4); 277 val = UGETDW(temp); 278 val >>= shift; 279 280 return (val & 0xff); 281 } 282 283 static uint16_t 284 ure_read_2(struct ure_softc *sc, uint16_t reg, uint16_t index) 285 { 286 uint32_t val; 287 uint8_t temp[4]; 288 uint8_t shift; 289 290 shift = (reg & 2) << 3; 291 reg &= ~3; 292 293 ure_read_mem(sc, reg, index, &temp, 4); 294 val = UGETDW(temp); 295 val >>= shift; 296 297 return (val & 0xffff); 298 } 299 300 static uint32_t 301 ure_read_4(struct ure_softc *sc, uint16_t reg, uint16_t index) 302 { 303 uint8_t temp[4]; 304 305 ure_read_mem(sc, reg, index, &temp, 4); 306 return (UGETDW(temp)); 307 } 308 309 static int 310 ure_write_1(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val) 311 { 312 uint16_t byen; 313 uint8_t temp[4]; 314 uint8_t shift; 315 316 byen = URE_BYTE_EN_BYTE; 317 shift = reg & 3; 318 val &= 0xff; 319 320 if (reg & 3) { 321 byen <<= shift; 322 val <<= (shift << 3); 323 reg &= ~3; 324 } 325 326 USETDW(temp, val); 327 return (ure_write_mem(sc, reg, index | byen, &temp, 4)); 328 } 329 330 static int 331 ure_write_2(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val) 332 { 333 uint16_t byen; 334 uint8_t temp[4]; 335 uint8_t shift; 336 337 byen = URE_BYTE_EN_WORD; 338 shift = reg & 2; 339 val &= 0xffff; 340 341 if (reg & 2) { 342 byen <<= shift; 343 val <<= (shift << 3); 344 reg &= ~3; 345 } 346 347 USETDW(temp, val); 348 return (ure_write_mem(sc, reg, index | byen, &temp, 4)); 349 } 350 351 static int 352 ure_write_4(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val) 353 { 354 uint8_t temp[4]; 355 356 USETDW(temp, val); 357 return (ure_write_mem(sc, reg, index | URE_BYTE_EN_DWORD, &temp, 4)); 358 } 359 360 static uint16_t 361 ure_ocp_reg_read(struct ure_softc *sc, uint16_t addr) 362 { 363 uint16_t reg; 364 365 ure_write_2(sc, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000); 366 reg = (addr & 0x0fff) | 0xb000; 367 368 return (ure_read_2(sc, reg, URE_MCU_TYPE_PLA)); 369 } 370 371 static void 372 ure_ocp_reg_write(struct ure_softc *sc, uint16_t addr, uint16_t data) 373 { 374 uint16_t reg; 375 376 ure_write_2(sc, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000); 377 reg = (addr & 0x0fff) | 0xb000; 378 379 ure_write_2(sc, reg, URE_MCU_TYPE_PLA, data); 380 } 381 382 static void 383 ure_sram_write(struct ure_softc *sc, uint16_t addr, uint16_t data) 384 { 385 ure_ocp_reg_write(sc, URE_OCP_SRAM_ADDR, addr); 386 ure_ocp_reg_write(sc, URE_OCP_SRAM_DATA, data); 387 } 388 389 static int 390 ure_miibus_readreg(device_t dev, int phy, int reg) 391 { 392 struct ure_softc *sc; 393 uint16_t val; 394 int locked; 395 396 sc = device_get_softc(dev); 397 locked = mtx_owned(&sc->sc_mtx); 398 if (!locked) 399 URE_LOCK(sc); 400 401 /* Let the rgephy driver read the URE_GMEDIASTAT register. */ 402 if (reg == URE_GMEDIASTAT) { 403 if (!locked) 404 URE_UNLOCK(sc); 405 return (ure_read_1(sc, URE_GMEDIASTAT, URE_MCU_TYPE_PLA)); 406 } 407 408 val = ure_ocp_reg_read(sc, URE_OCP_BASE_MII + reg * 2); 409 410 if (!locked) 411 URE_UNLOCK(sc); 412 return (val); 413 } 414 415 static int 416 ure_miibus_writereg(device_t dev, int phy, int reg, int val) 417 { 418 struct ure_softc *sc; 419 int locked; 420 421 sc = device_get_softc(dev); 422 if (sc->sc_phyno != phy) 423 return (0); 424 425 locked = mtx_owned(&sc->sc_mtx); 426 if (!locked) 427 URE_LOCK(sc); 428 429 ure_ocp_reg_write(sc, URE_OCP_BASE_MII + reg * 2, val); 430 431 if (!locked) 432 URE_UNLOCK(sc); 433 return (0); 434 } 435 436 static void 437 ure_miibus_statchg(device_t dev) 438 { 439 struct ure_softc *sc; 440 struct mii_data *mii; 441 struct ifnet *ifp; 442 int locked; 443 444 sc = device_get_softc(dev); 445 mii = GET_MII(sc); 446 locked = mtx_owned(&sc->sc_mtx); 447 if (!locked) 448 URE_LOCK(sc); 449 450 ifp = uether_getifp(&sc->sc_ue); 451 if (mii == NULL || ifp == NULL || 452 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 453 goto done; 454 455 sc->sc_flags &= ~URE_FLAG_LINK; 456 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 457 (IFM_ACTIVE | IFM_AVALID)) { 458 switch (IFM_SUBTYPE(mii->mii_media_active)) { 459 case IFM_10_T: 460 case IFM_100_TX: 461 sc->sc_flags |= URE_FLAG_LINK; 462 sc->sc_rxstarted = 0; 463 break; 464 case IFM_1000_T: 465 if ((sc->sc_flags & URE_FLAG_8152) != 0) 466 break; 467 sc->sc_flags |= URE_FLAG_LINK; 468 sc->sc_rxstarted = 0; 469 break; 470 default: 471 break; 472 } 473 } 474 475 /* Lost link, do nothing. */ 476 if ((sc->sc_flags & URE_FLAG_LINK) == 0) 477 goto done; 478 done: 479 if (!locked) 480 URE_UNLOCK(sc); 481 } 482 483 /* 484 * Probe for a RTL8152/RTL8153 chip. 485 */ 486 static int 487 ure_probe(device_t dev) 488 { 489 struct usb_attach_arg *uaa; 490 491 uaa = device_get_ivars(dev); 492 if (uaa->usb_mode != USB_MODE_HOST) 493 return (ENXIO); 494 if (uaa->info.bIfaceIndex != URE_IFACE_IDX) 495 return (ENXIO); 496 497 return (usbd_lookup_id_by_uaa(ure_devs, sizeof(ure_devs), uaa)); 498 } 499 500 /* 501 * Attach the interface. Allocate softc structures, do ifmedia 502 * setup and ethernet/BPF attach. 503 */ 504 static int 505 ure_attach(device_t dev) 506 { 507 struct usb_attach_arg *uaa = device_get_ivars(dev); 508 struct ure_softc *sc = device_get_softc(dev); 509 struct usb_ether *ue = &sc->sc_ue; 510 struct usb_config ure_config_rx[URE_MAX_RX]; 511 struct usb_config ure_config_tx[URE_MAX_TX]; 512 uint8_t iface_index; 513 int error; 514 int i; 515 516 sc->sc_flags = USB_GET_DRIVER_INFO(uaa); 517 device_set_usb_desc(dev); 518 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_DEF); 519 520 iface_index = URE_IFACE_IDX; 521 522 if (sc->sc_flags & (URE_FLAG_8153 | URE_FLAG_8153B)) 523 sc->sc_rxbufsz = URE_8153_RX_BUFSZ; 524 else if (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) 525 sc->sc_rxbufsz = URE_8156_RX_BUFSZ; 526 else 527 sc->sc_rxbufsz = URE_8152_RX_BUFSZ; 528 529 for (i = 0; i < URE_MAX_RX; i++) { 530 ure_config_rx[i] = (struct usb_config) { 531 .type = UE_BULK, 532 .endpoint = UE_ADDR_ANY, 533 .direction = UE_DIR_IN, 534 .bufsize = sc->sc_rxbufsz, 535 .flags = {.pipe_bof = 1,.short_xfer_ok = 1,}, 536 .callback = ure_bulk_read_callback, 537 .timeout = 0, /* no timeout */ 538 }; 539 } 540 error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_rx_xfer, 541 ure_config_rx, URE_MAX_RX, sc, &sc->sc_mtx); 542 if (error != 0) { 543 device_printf(dev, "allocating USB RX transfers failed\n"); 544 goto detach; 545 } 546 547 for (i = 0; i < URE_MAX_TX; i++) { 548 ure_config_tx[i] = (struct usb_config) { 549 .type = UE_BULK, 550 .endpoint = UE_ADDR_ANY, 551 .direction = UE_DIR_OUT, 552 .bufsize = URE_TX_BUFSZ, 553 .flags = {.pipe_bof = 1,.force_short_xfer = 1,}, 554 .callback = ure_bulk_write_callback, 555 .timeout = 10000, /* 10 seconds */ 556 }; 557 } 558 error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_tx_xfer, 559 ure_config_tx, URE_MAX_TX, sc, &sc->sc_mtx); 560 if (error != 0) { 561 usbd_transfer_unsetup(sc->sc_rx_xfer, URE_MAX_RX); 562 device_printf(dev, "allocating USB TX transfers failed\n"); 563 goto detach; 564 } 565 566 ue->ue_sc = sc; 567 ue->ue_dev = dev; 568 ue->ue_udev = uaa->device; 569 ue->ue_mtx = &sc->sc_mtx; 570 ue->ue_methods = &ure_ue_methods; 571 572 error = uether_ifattach(ue); 573 if (error != 0) { 574 device_printf(dev, "could not attach interface\n"); 575 goto detach; 576 } 577 return (0); /* success */ 578 579 detach: 580 ure_detach(dev); 581 return (ENXIO); /* failure */ 582 } 583 584 static int 585 ure_detach(device_t dev) 586 { 587 struct ure_softc *sc = device_get_softc(dev); 588 struct usb_ether *ue = &sc->sc_ue; 589 590 usbd_transfer_unsetup(sc->sc_tx_xfer, URE_MAX_TX); 591 usbd_transfer_unsetup(sc->sc_rx_xfer, URE_MAX_RX); 592 uether_ifdetach(ue); 593 mtx_destroy(&sc->sc_mtx); 594 595 return (0); 596 } 597 598 /* 599 * Copy from USB buffers to a new mbuf chain with pkt header. 600 * 601 * This will use m_getm2 to get a mbuf chain w/ properly sized mbuf 602 * clusters as necessary. 603 */ 604 static struct mbuf * 605 ure_makembuf(struct usb_page_cache *pc, usb_frlength_t offset, 606 usb_frlength_t len) 607 { 608 struct usb_page_search_res; 609 struct mbuf *m, *mb; 610 usb_frlength_t tlen; 611 612 m = m_getm2(NULL, len + ETHER_ALIGN, M_NOWAIT, MT_DATA, M_PKTHDR); 613 if (m == NULL) 614 return (m); 615 616 /* uether_newbuf does this. */ 617 m_adj(m, ETHER_ALIGN); 618 619 m->m_pkthdr.len = len; 620 621 for (mb = m; len > 0; mb = mb->m_next) { 622 tlen = MIN(len, M_TRAILINGSPACE(mb)); 623 624 usbd_copy_out(pc, offset, mtod(mb, uint8_t *), tlen); 625 mb->m_len = tlen; 626 627 offset += tlen; 628 len -= tlen; 629 } 630 631 return (m); 632 } 633 634 static void 635 ure_bulk_read_callback(struct usb_xfer *xfer, usb_error_t error) 636 { 637 struct ure_softc *sc = usbd_xfer_softc(xfer); 638 struct usb_ether *ue = &sc->sc_ue; 639 struct ifnet *ifp = uether_getifp(ue); 640 struct usb_page_cache *pc; 641 struct mbuf *m; 642 struct ure_rxpkt pkt; 643 int actlen, off, len; 644 int caps; 645 uint32_t pktcsum; 646 647 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL); 648 649 switch (USB_GET_STATE(xfer)) { 650 case USB_ST_TRANSFERRED: 651 off = 0; 652 pc = usbd_xfer_get_frame(xfer, 0); 653 caps = if_getcapenable(ifp); 654 DEVPRINTFN(13, sc->sc_ue.ue_dev, "rcb start\n"); 655 while (actlen > 0) { 656 if (actlen < (int)(sizeof(pkt))) { 657 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 658 goto tr_setup; 659 } 660 usbd_copy_out(pc, off, &pkt, sizeof(pkt)); 661 662 off += sizeof(pkt); 663 actlen -= sizeof(pkt); 664 665 len = le32toh(pkt.ure_pktlen) & URE_RXPKT_LEN_MASK; 666 667 DEVPRINTFN(13, sc->sc_ue.ue_dev, 668 "rxpkt: %#x, %#x, %#x, %#x, %#x, %#x\n", 669 pkt.ure_pktlen, pkt.ure_csum, pkt.ure_misc, 670 pkt.ure_rsvd2, pkt.ure_rsvd3, pkt.ure_rsvd4); 671 DEVPRINTFN(13, sc->sc_ue.ue_dev, "len: %d\n", len); 672 673 if (len >= URE_RXPKT_LEN_MASK) { 674 /* 675 * drop the rest of this segment. With out 676 * more information, we cannot know where next 677 * packet starts. Blindly continuing would 678 * cause a packet in packet attack, allowing 679 * one VLAN to inject packets w/o a VLAN tag, 680 * or injecting packets into other VLANs. 681 */ 682 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 683 goto tr_setup; 684 } 685 686 if (actlen < len) { 687 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 688 goto tr_setup; 689 } 690 691 if (len >= (ETHER_HDR_LEN + ETHER_CRC_LEN)) 692 m = ure_makembuf(pc, off, len - ETHER_CRC_LEN); 693 else 694 m = NULL; 695 if (m == NULL) { 696 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 697 } else { 698 /* make mbuf and queue */ 699 pktcsum = le32toh(pkt.ure_csum); 700 if (caps & IFCAP_VLAN_HWTAGGING && 701 pktcsum & URE_RXPKT_RX_VLAN_TAG) { 702 m->m_pkthdr.ether_vtag = 703 bswap16(pktcsum & 704 URE_RXPKT_VLAN_MASK); 705 m->m_flags |= M_VLANTAG; 706 } 707 708 /* set the necessary flags for rx checksum */ 709 ure_rxcsum(caps, &pkt, m); 710 711 uether_rxmbuf(ue, m, len - ETHER_CRC_LEN); 712 } 713 714 off += roundup(len, URE_RXPKT_ALIGN); 715 actlen -= roundup(len, URE_RXPKT_ALIGN); 716 } 717 DEVPRINTFN(13, sc->sc_ue.ue_dev, "rcb end\n"); 718 719 /* FALLTHROUGH */ 720 case USB_ST_SETUP: 721 tr_setup: 722 usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer)); 723 usbd_transfer_submit(xfer); 724 uether_rxflush(ue); 725 return; 726 727 default: /* Error */ 728 DPRINTF("bulk read error, %s\n", 729 usbd_errstr(error)); 730 731 if (error != USB_ERR_CANCELLED) { 732 /* try to clear stall first */ 733 usbd_xfer_set_stall(xfer); 734 goto tr_setup; 735 } 736 return; 737 } 738 } 739 740 static void 741 ure_bulk_write_callback(struct usb_xfer *xfer, usb_error_t error) 742 { 743 struct ure_softc *sc = usbd_xfer_softc(xfer); 744 struct ifnet *ifp = uether_getifp(&sc->sc_ue); 745 struct usb_page_cache *pc; 746 struct mbuf *m; 747 struct ure_txpkt txpkt; 748 uint32_t regtmp; 749 int len, pos; 750 int rem; 751 int caps; 752 753 switch (USB_GET_STATE(xfer)) { 754 case USB_ST_TRANSFERRED: 755 DPRINTFN(11, "transfer complete\n"); 756 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 757 758 /* FALLTHROUGH */ 759 case USB_ST_SETUP: 760 tr_setup: 761 if ((sc->sc_flags & URE_FLAG_LINK) == 0) { 762 /* don't send anything if there is no link! */ 763 break; 764 } 765 766 pc = usbd_xfer_get_frame(xfer, 0); 767 caps = if_getcapenable(ifp); 768 769 pos = 0; 770 rem = URE_TX_BUFSZ; 771 while (rem > sizeof(txpkt)) { 772 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 773 if (m == NULL) 774 break; 775 776 /* 777 * make sure we don't ever send too large of a 778 * packet 779 */ 780 len = m->m_pkthdr.len; 781 if ((len & URE_TXPKT_LEN_MASK) != len) { 782 device_printf(sc->sc_ue.ue_dev, 783 "pkt len too large: %#x", len); 784 pkterror: 785 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 786 m_freem(m); 787 continue; 788 } 789 790 if (sizeof(txpkt) + 791 roundup(len, URE_TXPKT_ALIGN) > rem) { 792 /* out of space */ 793 IFQ_DRV_PREPEND(&ifp->if_snd, m); 794 m = NULL; 795 break; 796 } 797 798 txpkt = (struct ure_txpkt){}; 799 txpkt.ure_pktlen = htole32((len & URE_TXPKT_LEN_MASK) | 800 URE_TKPKT_TX_FS | URE_TKPKT_TX_LS); 801 if (m->m_flags & M_VLANTAG) { 802 txpkt.ure_csum = htole32( 803 bswap16(m->m_pkthdr.ether_vtag & 804 URE_TXPKT_VLAN_MASK) | URE_TXPKT_VLAN); 805 } 806 if (ure_txcsum(m, caps, ®tmp)) { 807 device_printf(sc->sc_ue.ue_dev, 808 "pkt l4 off too large"); 809 goto pkterror; 810 } 811 txpkt.ure_csum |= htole32(regtmp); 812 813 DEVPRINTFN(13, sc->sc_ue.ue_dev, 814 "txpkt: mbflg: %#x, %#x, %#x\n", 815 m->m_pkthdr.csum_flags, le32toh(txpkt.ure_pktlen), 816 le32toh(txpkt.ure_csum)); 817 818 usbd_copy_in(pc, pos, &txpkt, sizeof(txpkt)); 819 820 pos += sizeof(txpkt); 821 rem -= sizeof(txpkt); 822 823 usbd_m_copy_in(pc, pos, m, 0, len); 824 825 pos += roundup(len, URE_TXPKT_ALIGN); 826 rem -= roundup(len, URE_TXPKT_ALIGN); 827 828 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 829 830 /* 831 * If there's a BPF listener, bounce a copy 832 * of this frame to him. 833 */ 834 BPF_MTAP(ifp, m); 835 836 m_freem(m); 837 } 838 839 /* no packets to send */ 840 if (pos == 0) 841 break; 842 843 /* Set frame length. */ 844 usbd_xfer_set_frame_len(xfer, 0, pos); 845 846 usbd_transfer_submit(xfer); 847 848 return; 849 850 default: /* Error */ 851 DPRINTFN(11, "transfer error, %s\n", 852 usbd_errstr(error)); 853 854 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 855 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 856 857 if (error == USB_ERR_TIMEOUT) { 858 DEVPRINTFN(12, sc->sc_ue.ue_dev, 859 "pkt tx timeout\n"); 860 } 861 862 if (error != USB_ERR_CANCELLED) { 863 /* try to clear stall first */ 864 usbd_xfer_set_stall(xfer); 865 goto tr_setup; 866 } 867 } 868 } 869 870 static void 871 ure_read_chipver(struct ure_softc *sc) 872 { 873 uint16_t ver; 874 875 ver = ure_read_2(sc, URE_PLA_TCR1, URE_MCU_TYPE_PLA) & URE_VERSION_MASK; 876 sc->sc_ver = ver; 877 switch (ver) { 878 case 0x4c00: 879 sc->sc_chip |= URE_CHIP_VER_4C00; 880 sc->sc_flags = URE_FLAG_8152; 881 break; 882 case 0x4c10: 883 sc->sc_chip |= URE_CHIP_VER_4C10; 884 sc->sc_flags = URE_FLAG_8152; 885 break; 886 case 0x5c00: 887 sc->sc_chip |= URE_CHIP_VER_5C00; 888 sc->sc_flags = URE_FLAG_8153; 889 break; 890 case 0x5c10: 891 sc->sc_chip |= URE_CHIP_VER_5C10; 892 sc->sc_flags = URE_FLAG_8153; 893 break; 894 case 0x5c20: 895 sc->sc_chip |= URE_CHIP_VER_5C20; 896 sc->sc_flags = URE_FLAG_8153; 897 break; 898 case 0x5c30: 899 sc->sc_chip |= URE_CHIP_VER_5C30; 900 sc->sc_flags = URE_FLAG_8153; 901 break; 902 case 0x6000: 903 sc->sc_flags = URE_FLAG_8153B; 904 sc->sc_chip |= URE_CHIP_VER_6000; 905 break; 906 case 0x6010: 907 sc->sc_flags = URE_FLAG_8153B; 908 sc->sc_chip |= URE_CHIP_VER_6010; 909 break; 910 case 0x7020: 911 sc->sc_flags = URE_FLAG_8156; 912 sc->sc_chip |= URE_CHIP_VER_7020; 913 break; 914 case 0x7030: 915 sc->sc_flags = URE_FLAG_8156; 916 sc->sc_chip |= URE_CHIP_VER_7030; 917 break; 918 case 0x7400: 919 sc->sc_flags = URE_FLAG_8156B; 920 sc->sc_chip |= URE_CHIP_VER_7400; 921 break; 922 case 0x7410: 923 sc->sc_flags = URE_FLAG_8156B; 924 sc->sc_chip |= URE_CHIP_VER_7410; 925 break; 926 default: 927 device_printf(sc->sc_ue.ue_dev, 928 "unknown version 0x%04x\n", ver); 929 break; 930 } 931 } 932 933 static int 934 ure_sysctl_chipver(SYSCTL_HANDLER_ARGS) 935 { 936 struct sbuf sb; 937 struct ure_softc *sc = arg1; 938 int error; 939 940 sbuf_new_for_sysctl(&sb, NULL, 0, req); 941 942 sbuf_printf(&sb, "%04x", sc->sc_ver); 943 944 error = sbuf_finish(&sb); 945 sbuf_delete(&sb); 946 947 return (error); 948 } 949 950 static void 951 ure_attach_post(struct usb_ether *ue) 952 { 953 struct ure_softc *sc = uether_getsc(ue); 954 955 sc->sc_rxstarted = 0; 956 sc->sc_phyno = 0; 957 958 /* Determine the chip version. */ 959 ure_read_chipver(sc); 960 961 /* Initialize controller and get station address. */ 962 if (sc->sc_flags & URE_FLAG_8152) 963 ure_rtl8152_init(sc); 964 else if (sc->sc_flags & (URE_FLAG_8153B | URE_FLAG_8156 | URE_FLAG_8156B)) 965 ure_rtl8153b_init(sc); 966 else 967 ure_rtl8153_init(sc); 968 969 if ((sc->sc_chip & URE_CHIP_VER_4C00) || 970 (sc->sc_chip & URE_CHIP_VER_4C10)) 971 ure_read_mem(sc, URE_PLA_IDR, URE_MCU_TYPE_PLA, 972 ue->ue_eaddr, 8); 973 else 974 ure_read_mem(sc, URE_PLA_BACKUP, URE_MCU_TYPE_PLA, 975 ue->ue_eaddr, 8); 976 977 if (ETHER_IS_ZERO(sc->sc_ue.ue_eaddr)) { 978 device_printf(sc->sc_ue.ue_dev, "MAC assigned randomly\n"); 979 arc4rand(sc->sc_ue.ue_eaddr, ETHER_ADDR_LEN, 0); 980 sc->sc_ue.ue_eaddr[0] &= ~0x01; /* unicast */ 981 sc->sc_ue.ue_eaddr[0] |= 0x02; /* locally administered */ 982 } 983 } 984 985 static int 986 ure_attach_post_sub(struct usb_ether *ue) 987 { 988 struct sysctl_ctx_list *sctx; 989 struct sysctl_oid *soid; 990 struct ure_softc *sc; 991 struct ifnet *ifp; 992 int error; 993 994 sc = uether_getsc(ue); 995 ifp = ue->ue_ifp; 996 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 997 ifp->if_start = uether_start; 998 ifp->if_ioctl = ure_ioctl; 999 ifp->if_init = uether_init; 1000 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen); 1001 /* 1002 * Try to keep two transfers full at a time. 1003 * ~(TRANSFER_SIZE / 80 bytes/pkt * 2 buffers in flight) 1004 */ 1005 ifp->if_snd.ifq_drv_maxlen = 512; 1006 IFQ_SET_READY(&ifp->if_snd); 1007 1008 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU, 0); 1009 if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWTAGGING, 0); 1010 if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWCSUM|IFCAP_HWCSUM, 0); 1011 if_sethwassist(ifp, CSUM_IP|CSUM_IP_UDP|CSUM_IP_TCP); 1012 #ifdef INET6 1013 if_setcapabilitiesbit(ifp, IFCAP_HWCSUM_IPV6, 0); 1014 #endif 1015 if_setcapenable(ifp, if_getcapabilities(ifp)); 1016 1017 if (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) { 1018 ifmedia_init(&sc->sc_ifmedia, IFM_IMASK, ure_ifmedia_upd, 1019 ure_ifmedia_sts); 1020 ure_add_media_types(sc); 1021 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 1022 ifmedia_set(&sc->sc_ifmedia, IFM_ETHER | IFM_AUTO); 1023 sc->sc_ifmedia.ifm_media = IFM_ETHER | IFM_AUTO; 1024 error = 0; 1025 } else { 1026 bus_topo_lock(); 1027 error = mii_attach(ue->ue_dev, &ue->ue_miibus, ifp, 1028 uether_ifmedia_upd, ue->ue_methods->ue_mii_sts, 1029 BMSR_DEFCAPMASK, sc->sc_phyno, MII_OFFSET_ANY, 0); 1030 bus_topo_unlock(); 1031 } 1032 1033 sctx = device_get_sysctl_ctx(sc->sc_ue.ue_dev); 1034 soid = device_get_sysctl_tree(sc->sc_ue.ue_dev); 1035 SYSCTL_ADD_PROC(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "chipver", 1036 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 1037 ure_sysctl_chipver, "A", 1038 "Return string with chip version."); 1039 1040 return (error); 1041 } 1042 1043 static void 1044 ure_init(struct usb_ether *ue) 1045 { 1046 struct ure_softc *sc = uether_getsc(ue); 1047 struct ifnet *ifp = uether_getifp(ue); 1048 uint16_t cpcr; 1049 uint32_t reg; 1050 1051 URE_LOCK_ASSERT(sc, MA_OWNED); 1052 1053 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1054 return; 1055 1056 /* Cancel pending I/O. */ 1057 ure_stop(ue); 1058 1059 if (sc->sc_flags & (URE_FLAG_8153B | URE_FLAG_8156 | URE_FLAG_8156B)) 1060 ure_rtl8153b_nic_reset(sc); 1061 else 1062 ure_reset(sc); 1063 1064 /* Set MAC address. */ 1065 ure_write_1(sc, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_CONFIG); 1066 ure_write_mem(sc, URE_PLA_IDR, URE_MCU_TYPE_PLA | URE_BYTE_EN_SIX_BYTES, 1067 IF_LLADDR(ifp), 8); 1068 ure_write_1(sc, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_NORAML); 1069 1070 /* Set RX EARLY timeout and size */ 1071 if (sc->sc_flags & URE_FLAG_8153) { 1072 switch (usbd_get_speed(sc->sc_ue.ue_udev)) { 1073 case USB_SPEED_SUPER: 1074 reg = URE_COALESCE_SUPER / 8; 1075 break; 1076 case USB_SPEED_HIGH: 1077 reg = URE_COALESCE_HIGH / 8; 1078 break; 1079 default: 1080 reg = URE_COALESCE_SLOW / 8; 1081 break; 1082 } 1083 ure_write_2(sc, URE_USB_RX_EARLY_AGG, URE_MCU_TYPE_USB, reg); 1084 reg = URE_8153_RX_BUFSZ - (URE_FRAMELEN(if_getmtu(ifp)) + 1085 sizeof(struct ure_rxpkt) + URE_RXPKT_ALIGN); 1086 ure_write_2(sc, URE_USB_RX_EARLY_SIZE, URE_MCU_TYPE_USB, reg / 4); 1087 } else if (sc->sc_flags & URE_FLAG_8153B) { 1088 ure_write_2(sc, URE_USB_RX_EARLY_AGG, URE_MCU_TYPE_USB, 158); 1089 ure_write_2(sc, URE_USB_RX_EXTRA_AGG_TMR, URE_MCU_TYPE_USB, 1875); 1090 reg = URE_8153_RX_BUFSZ - (URE_FRAMELEN(if_getmtu(ifp)) + 1091 sizeof(struct ure_rxpkt) + URE_RXPKT_ALIGN); 1092 ure_write_2(sc, URE_USB_RX_EARLY_SIZE, URE_MCU_TYPE_USB, reg / 8); 1093 ure_write_1(sc, URE_USB_UPT_RXDMA_OWN, URE_MCU_TYPE_USB, 1094 URE_OWN_UPDATE | URE_OWN_CLEAR); 1095 } else if (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) { 1096 ure_write_2(sc, URE_USB_RX_EARLY_AGG, URE_MCU_TYPE_USB, 80); 1097 ure_write_2(sc, URE_USB_RX_EXTRA_AGG_TMR, URE_MCU_TYPE_USB, 1875); 1098 reg = URE_8156_RX_BUFSZ - (URE_FRAMELEN(if_getmtu(ifp)) + 1099 sizeof(struct ure_rxpkt) + URE_RXPKT_ALIGN); 1100 ure_write_2(sc, URE_USB_RX_EARLY_SIZE, URE_MCU_TYPE_USB, reg / 8); 1101 ure_write_1(sc, URE_USB_UPT_RXDMA_OWN, URE_MCU_TYPE_USB, 1102 URE_OWN_UPDATE | URE_OWN_CLEAR); 1103 } 1104 1105 if (sc->sc_flags & URE_FLAG_8156B) { 1106 URE_CLRBIT_2(sc, URE_USB_FW_TASK, URE_MCU_TYPE_USB, URE_FC_PATCH_TASK); 1107 uether_pause(&sc->sc_ue, hz / 500); 1108 URE_SETBIT_2(sc, URE_USB_FW_TASK, URE_MCU_TYPE_USB, URE_FC_PATCH_TASK); 1109 } 1110 1111 /* Reset the packet filter. */ 1112 URE_CLRBIT_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA, URE_FMC_FCR_MCU_EN); 1113 URE_SETBIT_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA, URE_FMC_FCR_MCU_EN); 1114 1115 /* Enable RX VLANs if enabled */ 1116 cpcr = ure_read_2(sc, URE_PLA_CPCR, URE_MCU_TYPE_PLA); 1117 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) { 1118 DEVPRINTFN(12, sc->sc_ue.ue_dev, "enabled hw vlan tag\n"); 1119 cpcr |= URE_CPCR_RX_VLAN; 1120 } else { 1121 DEVPRINTFN(12, sc->sc_ue.ue_dev, "disabled hw vlan tag\n"); 1122 cpcr &= ~URE_CPCR_RX_VLAN; 1123 } 1124 ure_write_2(sc, URE_PLA_CPCR, URE_MCU_TYPE_PLA, cpcr); 1125 1126 /* Enable transmit and receive. */ 1127 URE_SETBIT_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, URE_CR_RE | URE_CR_TE); 1128 1129 URE_CLRBIT_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, URE_RXDY_GATED_EN); 1130 1131 /* Configure RX filters. */ 1132 ure_rxfilter(ue); 1133 1134 usbd_xfer_set_stall(sc->sc_tx_xfer[0]); 1135 1136 /* Indicate we are up and running. */ 1137 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1138 1139 /* Switch to selected media. */ 1140 ure_ifmedia_upd(ifp); 1141 } 1142 1143 static void 1144 ure_tick(struct usb_ether *ue) 1145 { 1146 struct ure_softc *sc = uether_getsc(ue); 1147 struct ifnet *ifp = uether_getifp(ue); 1148 struct mii_data *mii; 1149 1150 URE_LOCK_ASSERT(sc, MA_OWNED); 1151 1152 (void)ifp; 1153 for (int i = 0; i < URE_MAX_RX; i++) 1154 DEVPRINTFN(13, sc->sc_ue.ue_dev, 1155 "rx[%d] = %d\n", i, USB_GET_STATE(sc->sc_rx_xfer[i])); 1156 1157 for (int i = 0; i < URE_MAX_TX; i++) 1158 DEVPRINTFN(13, sc->sc_ue.ue_dev, 1159 "tx[%d] = %d\n", i, USB_GET_STATE(sc->sc_tx_xfer[i])); 1160 1161 if (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) { 1162 ure_link_state(sc); 1163 } else { 1164 mii = GET_MII(sc); 1165 mii_tick(mii); 1166 if ((sc->sc_flags & URE_FLAG_LINK) == 0 1167 && mii->mii_media_status & IFM_ACTIVE && 1168 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1169 sc->sc_flags |= URE_FLAG_LINK; 1170 sc->sc_rxstarted = 0; 1171 ure_start(ue); 1172 } 1173 } 1174 } 1175 1176 static u_int 1177 ure_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 1178 { 1179 uint32_t h, *hashes = arg; 1180 1181 h = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN) >> 26; 1182 if (h < 32) 1183 hashes[0] |= (1 << h); 1184 else 1185 hashes[1] |= (1 << (h - 32)); 1186 return (1); 1187 } 1188 1189 /* 1190 * Program the 64-bit multicast hash filter. 1191 */ 1192 static void 1193 ure_rxfilter(struct usb_ether *ue) 1194 { 1195 struct ure_softc *sc = uether_getsc(ue); 1196 struct ifnet *ifp = uether_getifp(ue); 1197 uint32_t rxmode; 1198 uint32_t h, hashes[2] = { 0, 0 }; 1199 1200 URE_LOCK_ASSERT(sc, MA_OWNED); 1201 1202 rxmode = ure_read_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA); 1203 rxmode &= ~(URE_RCR_AAP | URE_RCR_AM); 1204 rxmode |= URE_RCR_APM; /* accept physical match packets */ 1205 rxmode |= URE_RCR_AB; /* always accept broadcasts */ 1206 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) { 1207 if (ifp->if_flags & IFF_PROMISC) 1208 rxmode |= URE_RCR_AAP; 1209 rxmode |= URE_RCR_AM; 1210 hashes[0] = hashes[1] = 0xffffffff; 1211 goto done; 1212 } 1213 1214 /* calculate multicast masks */ 1215 if_foreach_llmaddr(ifp, ure_hash_maddr, &hashes); 1216 1217 h = bswap32(hashes[0]); 1218 hashes[0] = bswap32(hashes[1]); 1219 hashes[1] = h; 1220 rxmode |= URE_RCR_AM; /* accept multicast packets */ 1221 1222 done: 1223 DEVPRINTFN(14, ue->ue_dev, "rxfilt: RCR: %#x\n", 1224 ure_read_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA)); 1225 ure_write_4(sc, URE_PLA_MAR0, URE_MCU_TYPE_PLA, hashes[0]); 1226 ure_write_4(sc, URE_PLA_MAR4, URE_MCU_TYPE_PLA, hashes[1]); 1227 ure_write_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, rxmode); 1228 } 1229 1230 static void 1231 ure_start(struct usb_ether *ue) 1232 { 1233 struct ure_softc *sc = uether_getsc(ue); 1234 unsigned i; 1235 1236 URE_LOCK_ASSERT(sc, MA_OWNED); 1237 1238 if (!sc->sc_rxstarted) { 1239 sc->sc_rxstarted = 1; 1240 for (i = 0; i != URE_MAX_RX; i++) 1241 usbd_transfer_start(sc->sc_rx_xfer[i]); 1242 } 1243 1244 for (i = 0; i != URE_MAX_TX; i++) 1245 usbd_transfer_start(sc->sc_tx_xfer[i]); 1246 } 1247 1248 static void 1249 ure_reset(struct ure_softc *sc) 1250 { 1251 int i; 1252 1253 ure_write_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, URE_CR_RST); 1254 1255 for (i = 0; i < URE_TIMEOUT; i++) { 1256 if (!(ure_read_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA) & 1257 URE_CR_RST)) 1258 break; 1259 uether_pause(&sc->sc_ue, hz / 100); 1260 } 1261 if (i == URE_TIMEOUT) 1262 device_printf(sc->sc_ue.ue_dev, "reset never completed\n"); 1263 } 1264 1265 /* 1266 * Set media options. 1267 */ 1268 static int 1269 ure_ifmedia_upd(struct ifnet *ifp) 1270 { 1271 struct ure_softc *sc = ifp->if_softc; 1272 struct ifmedia *ifm; 1273 struct mii_data *mii; 1274 struct mii_softc *miisc; 1275 int gig; 1276 int reg; 1277 int anar; 1278 int locked; 1279 int error; 1280 1281 if (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) { 1282 ifm = &sc->sc_ifmedia; 1283 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1284 return (EINVAL); 1285 1286 locked = mtx_owned(&sc->sc_mtx); 1287 if (!locked) 1288 URE_LOCK(sc); 1289 reg = ure_ocp_reg_read(sc, 0xa5d4); 1290 reg &= ~URE_ADV_2500TFDX; 1291 1292 anar = gig = 0; 1293 switch (IFM_SUBTYPE(ifm->ifm_media)) { 1294 case IFM_AUTO: 1295 anar |= ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10; 1296 gig |= GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX; 1297 reg |= URE_ADV_2500TFDX; 1298 break; 1299 case IFM_2500_T: 1300 anar |= ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10; 1301 gig |= GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX; 1302 reg |= URE_ADV_2500TFDX; 1303 ifp->if_baudrate = IF_Mbps(2500); 1304 break; 1305 case IFM_1000_T: 1306 anar |= ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10; 1307 gig |= GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX; 1308 ifp->if_baudrate = IF_Gbps(1); 1309 break; 1310 case IFM_100_TX: 1311 anar |= ANAR_TX | ANAR_TX_FD; 1312 ifp->if_baudrate = IF_Mbps(100); 1313 break; 1314 case IFM_10_T: 1315 anar |= ANAR_10 | ANAR_10_FD; 1316 ifp->if_baudrate = IF_Mbps(10); 1317 break; 1318 default: 1319 device_printf(sc->sc_ue.ue_dev, "unsupported media type\n"); 1320 if (!locked) 1321 URE_UNLOCK(sc); 1322 return (EINVAL); 1323 } 1324 1325 ure_ocp_reg_write(sc, URE_OCP_BASE_MII + MII_ANAR * 2, 1326 anar | ANAR_PAUSE_ASYM | ANAR_FC); 1327 ure_ocp_reg_write(sc, URE_OCP_BASE_MII + MII_100T2CR * 2, gig); 1328 ure_ocp_reg_write(sc, 0xa5d4, reg); 1329 ure_ocp_reg_write(sc, URE_OCP_BASE_MII + MII_BMCR, 1330 BMCR_AUTOEN | BMCR_STARTNEG); 1331 if (!locked) 1332 URE_UNLOCK(sc); 1333 return (0); 1334 } 1335 1336 mii = GET_MII(sc); 1337 1338 URE_LOCK_ASSERT(sc, MA_OWNED); 1339 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1340 PHY_RESET(miisc); 1341 error = mii_mediachg(mii); 1342 return (error); 1343 } 1344 1345 /* 1346 * Report current media status. 1347 */ 1348 static void 1349 ure_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1350 { 1351 struct ure_softc *sc; 1352 struct mii_data *mii; 1353 uint16_t status; 1354 1355 sc = ifp->if_softc; 1356 if (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) { 1357 URE_LOCK(sc); 1358 ifmr->ifm_status = IFM_AVALID; 1359 if (ure_get_link_status(sc)) { 1360 ifmr->ifm_status |= IFM_ACTIVE; 1361 status = ure_read_2(sc, URE_PLA_PHYSTATUS, 1362 URE_MCU_TYPE_PLA); 1363 if ((status & URE_PHYSTATUS_FDX) || 1364 (status & URE_PHYSTATUS_2500MBPS)) 1365 ifmr->ifm_active |= IFM_FDX; 1366 else 1367 ifmr->ifm_active |= IFM_HDX; 1368 if (status & URE_PHYSTATUS_10MBPS) 1369 ifmr->ifm_active |= IFM_10_T; 1370 else if (status & URE_PHYSTATUS_100MBPS) 1371 ifmr->ifm_active |= IFM_100_TX; 1372 else if (status & URE_PHYSTATUS_1000MBPS) 1373 ifmr->ifm_active |= IFM_1000_T; 1374 else if (status & URE_PHYSTATUS_2500MBPS) 1375 ifmr->ifm_active |= IFM_2500_T; 1376 } 1377 URE_UNLOCK(sc); 1378 return; 1379 } 1380 1381 mii = GET_MII(sc); 1382 1383 URE_LOCK(sc); 1384 mii_pollstat(mii); 1385 ifmr->ifm_active = mii->mii_media_active; 1386 ifmr->ifm_status = mii->mii_media_status; 1387 URE_UNLOCK(sc); 1388 } 1389 1390 static void 1391 ure_add_media_types(struct ure_softc *sc) 1392 { 1393 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_10_T, 0, NULL); 1394 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL); 1395 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_100_TX, 0, NULL); 1396 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL); 1397 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 1398 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_2500_T | IFM_FDX, 0, NULL); 1399 } 1400 1401 static void 1402 ure_link_state(struct ure_softc *sc) 1403 { 1404 struct ifnet *ifp = uether_getifp(&sc->sc_ue); 1405 1406 if (ure_get_link_status(sc)) { 1407 if (ifp->if_link_state != LINK_STATE_UP) { 1408 if_link_state_change(ifp, LINK_STATE_UP); 1409 /* Enable transmit and receive. */ 1410 URE_SETBIT_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, URE_CR_RE | URE_CR_TE); 1411 1412 if (ure_read_2(sc, URE_PLA_PHYSTATUS, URE_MCU_TYPE_PLA) & 1413 URE_PHYSTATUS_2500MBPS) 1414 URE_CLRBIT_2(sc, URE_PLA_MAC_PWR_CTRL4, URE_MCU_TYPE_PLA, 0x40); 1415 else 1416 URE_SETBIT_2(sc, URE_PLA_MAC_PWR_CTRL4, URE_MCU_TYPE_PLA, 0x40); 1417 } 1418 } else { 1419 if (ifp->if_link_state != LINK_STATE_DOWN) { 1420 if_link_state_change(ifp, LINK_STATE_DOWN); 1421 } 1422 } 1423 } 1424 1425 static int 1426 ure_get_link_status(struct ure_softc *sc) 1427 { 1428 if (ure_read_2(sc, URE_PLA_PHYSTATUS, URE_MCU_TYPE_PLA) & 1429 URE_PHYSTATUS_LINK) { 1430 sc->sc_flags |= URE_FLAG_LINK; 1431 return (1); 1432 } else { 1433 sc->sc_flags &= ~URE_FLAG_LINK; 1434 return (0); 1435 } 1436 } 1437 1438 static int 1439 ure_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1440 { 1441 struct usb_ether *ue = ifp->if_softc; 1442 struct ure_softc *sc; 1443 struct ifreq *ifr; 1444 int error, mask, reinit; 1445 1446 sc = uether_getsc(ue); 1447 ifr = (struct ifreq *)data; 1448 error = 0; 1449 reinit = 0; 1450 switch (cmd) { 1451 case SIOCSIFCAP: 1452 URE_LOCK(sc); 1453 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1454 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 1455 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 1456 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 1457 reinit++; 1458 } 1459 if ((mask & IFCAP_TXCSUM) != 0 && 1460 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 1461 ifp->if_capenable ^= IFCAP_TXCSUM; 1462 } 1463 if ((mask & IFCAP_RXCSUM) != 0 && 1464 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) { 1465 ifp->if_capenable ^= IFCAP_RXCSUM; 1466 } 1467 if ((mask & IFCAP_TXCSUM_IPV6) != 0 && 1468 (ifp->if_capabilities & IFCAP_TXCSUM_IPV6) != 0) { 1469 ifp->if_capenable ^= IFCAP_TXCSUM_IPV6; 1470 } 1471 if ((mask & IFCAP_RXCSUM_IPV6) != 0 && 1472 (ifp->if_capabilities & IFCAP_RXCSUM_IPV6) != 0) { 1473 ifp->if_capenable ^= IFCAP_RXCSUM_IPV6; 1474 } 1475 if (reinit > 0 && ifp->if_drv_flags & IFF_DRV_RUNNING) 1476 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1477 else 1478 reinit = 0; 1479 URE_UNLOCK(sc); 1480 if (reinit > 0) 1481 uether_init(ue); 1482 break; 1483 1484 case SIOCSIFMTU: 1485 /* 1486 * in testing large MTUs "crashes" the device, it 1487 * leaves the device w/ a broken state where link 1488 * is in a bad state. 1489 */ 1490 if (ifr->ifr_mtu < ETHERMIN || 1491 ifr->ifr_mtu > (4096 - ETHER_HDR_LEN - 1492 ETHER_VLAN_ENCAP_LEN - ETHER_CRC_LEN)) { 1493 error = EINVAL; 1494 break; 1495 } 1496 URE_LOCK(sc); 1497 if (if_getmtu(ifp) != ifr->ifr_mtu) 1498 if_setmtu(ifp, ifr->ifr_mtu); 1499 URE_UNLOCK(sc); 1500 break; 1501 1502 case SIOCGIFMEDIA: 1503 case SIOCSIFMEDIA: 1504 if (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) 1505 error = ifmedia_ioctl(ifp, ifr, &sc->sc_ifmedia, cmd); 1506 else 1507 error = uether_ioctl(ifp, cmd, data); 1508 break; 1509 1510 default: 1511 error = uether_ioctl(ifp, cmd, data); 1512 break; 1513 } 1514 1515 return (error); 1516 } 1517 1518 static void 1519 ure_rtl8152_init(struct ure_softc *sc) 1520 { 1521 uint32_t pwrctrl; 1522 1523 ure_enable_aldps(sc, false); 1524 1525 if (sc->sc_chip & URE_CHIP_VER_4C00) { 1526 URE_CLRBIT_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA, URE_LED_MODE_MASK); 1527 } 1528 1529 URE_CLRBIT_2(sc, URE_USB_UPS_CTRL, URE_MCU_TYPE_USB, URE_POWER_CUT); 1530 1531 URE_CLRBIT_2(sc, URE_USB_PM_CTRL_STATUS, URE_MCU_TYPE_USB, URE_RESUME_INDICATE); 1532 1533 URE_SETBIT_2(sc, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA, URE_TX_10M_IDLE_EN | URE_PFM_PWM_SWITCH); 1534 1535 pwrctrl = ure_read_4(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA); 1536 pwrctrl &= ~URE_MCU_CLK_RATIO_MASK; 1537 pwrctrl |= URE_MCU_CLK_RATIO | URE_D3_CLK_GATED_EN; 1538 ure_write_4(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, pwrctrl); 1539 ure_write_2(sc, URE_PLA_GPHY_INTR_IMR, URE_MCU_TYPE_PLA, 1540 URE_GPHY_STS_MSK | URE_SPEED_DOWN_MSK | URE_SPDWN_RXDV_MSK | 1541 URE_SPDWN_LINKCHG_MSK); 1542 1543 /* Enable Rx aggregation. */ 1544 URE_CLRBIT_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, URE_RX_AGG_DISABLE | URE_RX_ZERO_EN); 1545 1546 ure_enable_aldps(sc, false); 1547 1548 ure_rtl8152_nic_reset(sc); 1549 1550 ure_write_1(sc, URE_USB_TX_AGG, URE_MCU_TYPE_USB, 1551 URE_TX_AGG_MAX_THRESHOLD); 1552 ure_write_4(sc, URE_USB_RX_BUF_TH, URE_MCU_TYPE_USB, URE_RX_THR_HIGH); 1553 ure_write_4(sc, URE_USB_TX_DMA, URE_MCU_TYPE_USB, 1554 URE_TEST_MODE_DISABLE | URE_TX_SIZE_ADJUST1); 1555 } 1556 1557 static void 1558 ure_rtl8153_init(struct ure_softc *sc) 1559 { 1560 uint16_t val; 1561 uint8_t u1u2[8]; 1562 int i; 1563 1564 ure_enable_aldps(sc, false); 1565 1566 memset(u1u2, 0x00, sizeof(u1u2)); 1567 ure_write_mem(sc, URE_USB_TOLERANCE, 1568 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 1569 1570 for (i = 0; i < URE_TIMEOUT; i++) { 1571 if (ure_read_2(sc, URE_PLA_BOOT_CTRL, URE_MCU_TYPE_PLA) & 1572 URE_AUTOLOAD_DONE) 1573 break; 1574 uether_pause(&sc->sc_ue, hz / 100); 1575 } 1576 if (i == URE_TIMEOUT) 1577 device_printf(sc->sc_ue.ue_dev, 1578 "timeout waiting for chip autoload\n"); 1579 1580 for (i = 0; i < URE_TIMEOUT; i++) { 1581 val = ure_ocp_reg_read(sc, URE_OCP_PHY_STATUS) & 1582 URE_PHY_STAT_MASK; 1583 if (val == URE_PHY_STAT_LAN_ON || val == URE_PHY_STAT_PWRDN) 1584 break; 1585 uether_pause(&sc->sc_ue, hz / 100); 1586 } 1587 if (i == URE_TIMEOUT) 1588 device_printf(sc->sc_ue.ue_dev, 1589 "timeout waiting for phy to stabilize\n"); 1590 1591 URE_CLRBIT_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, URE_U2P3_ENABLE); 1592 1593 if (sc->sc_chip & URE_CHIP_VER_5C10) { 1594 val = ure_read_2(sc, URE_USB_SSPHYLINK2, URE_MCU_TYPE_USB); 1595 val &= ~URE_PWD_DN_SCALE_MASK; 1596 val |= URE_PWD_DN_SCALE(96); 1597 ure_write_2(sc, URE_USB_SSPHYLINK2, URE_MCU_TYPE_USB, val); 1598 1599 URE_SETBIT_1(sc, URE_USB_USB2PHY, URE_MCU_TYPE_USB, URE_USB2PHY_L1 | URE_USB2PHY_SUSPEND); 1600 } else if (sc->sc_chip & URE_CHIP_VER_5C20) 1601 URE_CLRBIT_1(sc, URE_PLA_DMY_REG0, URE_MCU_TYPE_PLA, URE_ECM_ALDPS); 1602 1603 if (sc->sc_chip & (URE_CHIP_VER_5C20 | URE_CHIP_VER_5C30)) { 1604 val = ure_read_1(sc, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB); 1605 if (ure_read_2(sc, URE_USB_BURST_SIZE, URE_MCU_TYPE_USB) == 1606 0) 1607 val &= ~URE_DYNAMIC_BURST; 1608 else 1609 val |= URE_DYNAMIC_BURST; 1610 ure_write_1(sc, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB, val); 1611 } 1612 1613 URE_SETBIT_1(sc, URE_USB_CSR_DUMMY2, URE_MCU_TYPE_USB, URE_EP4_FULL_FC); 1614 1615 URE_CLRBIT_2(sc, URE_USB_WDT11_CTRL, URE_MCU_TYPE_USB, URE_TIMER11_EN); 1616 1617 URE_CLRBIT_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA, URE_LED_MODE_MASK); 1618 1619 if ((sc->sc_chip & URE_CHIP_VER_5C10) && 1620 usbd_get_speed(sc->sc_ue.ue_udev) != USB_SPEED_SUPER) 1621 val = URE_LPM_TIMER_500MS; 1622 else 1623 val = URE_LPM_TIMER_500US; 1624 ure_write_1(sc, URE_USB_LPM_CTRL, URE_MCU_TYPE_USB, 1625 val | URE_FIFO_EMPTY_1FB | URE_ROK_EXIT_LPM); 1626 1627 val = ure_read_2(sc, URE_USB_AFE_CTRL2, URE_MCU_TYPE_USB); 1628 val &= ~URE_SEN_VAL_MASK; 1629 val |= URE_SEN_VAL_NORMAL | URE_SEL_RXIDLE; 1630 ure_write_2(sc, URE_USB_AFE_CTRL2, URE_MCU_TYPE_USB, val); 1631 1632 ure_write_2(sc, URE_USB_CONNECT_TIMER, URE_MCU_TYPE_USB, 0x0001); 1633 1634 URE_CLRBIT_2(sc, URE_USB_POWER_CUT, URE_MCU_TYPE_USB, URE_PWR_EN | URE_PHASE2_EN); 1635 1636 URE_CLRBIT_2(sc, URE_USB_MISC_0, URE_MCU_TYPE_USB, URE_PCUT_STATUS); 1637 1638 memset(u1u2, 0xff, sizeof(u1u2)); 1639 ure_write_mem(sc, URE_USB_TOLERANCE, 1640 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 1641 1642 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, 1643 URE_ALDPS_SPDWN_RATIO); 1644 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_PLA, 1645 URE_EEE_SPDWN_RATIO); 1646 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL3, URE_MCU_TYPE_PLA, 1647 URE_PKT_AVAIL_SPDWN_EN | URE_SUSPEND_SPDWN_EN | 1648 URE_U1U2_SPDWN_EN | URE_L1_SPDWN_EN); 1649 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL4, URE_MCU_TYPE_PLA, 1650 URE_PWRSAVE_SPDWN_EN | URE_RXDV_SPDWN_EN | URE_TX10MIDLE_EN | 1651 URE_TP100_SPDWN_EN | URE_TP500_SPDWN_EN | URE_TP1000_SPDWN_EN | 1652 URE_EEE_SPDWN_EN); 1653 1654 val = ure_read_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB); 1655 if (!(sc->sc_chip & (URE_CHIP_VER_5C00 | URE_CHIP_VER_5C10))) 1656 val |= URE_U2P3_ENABLE; 1657 else 1658 val &= ~URE_U2P3_ENABLE; 1659 ure_write_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, val); 1660 1661 memset(u1u2, 0x00, sizeof(u1u2)); 1662 ure_write_mem(sc, URE_USB_TOLERANCE, 1663 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 1664 1665 ure_enable_aldps(sc, false); 1666 1667 if (sc->sc_chip & (URE_CHIP_VER_5C00 | URE_CHIP_VER_5C10 | 1668 URE_CHIP_VER_5C20)) { 1669 ure_ocp_reg_write(sc, URE_OCP_ADC_CFG, 1670 URE_CKADSEL_L | URE_ADC_EN | URE_EN_EMI_L); 1671 } 1672 if (sc->sc_chip & URE_CHIP_VER_5C00) { 1673 ure_ocp_reg_write(sc, URE_OCP_EEE_CFG, 1674 ure_ocp_reg_read(sc, URE_OCP_EEE_CFG) & 1675 ~URE_CTAP_SHORT_EN); 1676 } 1677 ure_ocp_reg_write(sc, URE_OCP_POWER_CFG, 1678 ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) | 1679 URE_EEE_CLKDIV_EN); 1680 ure_ocp_reg_write(sc, URE_OCP_DOWN_SPEED, 1681 ure_ocp_reg_read(sc, URE_OCP_DOWN_SPEED) | 1682 URE_EN_10M_BGOFF); 1683 ure_ocp_reg_write(sc, URE_OCP_POWER_CFG, 1684 ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) | 1685 URE_EN_10M_PLLOFF); 1686 ure_sram_write(sc, URE_SRAM_IMPEDANCE, 0x0b13); 1687 URE_SETBIT_2(sc, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA, URE_PFM_PWM_SWITCH); 1688 1689 /* Enable LPF corner auto tune. */ 1690 ure_sram_write(sc, URE_SRAM_LPF_CFG, 0xf70f); 1691 1692 /* Adjust 10M amplitude. */ 1693 ure_sram_write(sc, URE_SRAM_10M_AMP1, 0x00af); 1694 ure_sram_write(sc, URE_SRAM_10M_AMP2, 0x0208); 1695 1696 ure_rtl8152_nic_reset(sc); 1697 1698 /* Enable Rx aggregation. */ 1699 URE_CLRBIT_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, URE_RX_AGG_DISABLE | URE_RX_ZERO_EN); 1700 1701 val = ure_read_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB); 1702 if (!(sc->sc_chip & (URE_CHIP_VER_5C00 | URE_CHIP_VER_5C10))) 1703 val |= URE_U2P3_ENABLE; 1704 else 1705 val &= ~URE_U2P3_ENABLE; 1706 ure_write_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, val); 1707 1708 memset(u1u2, 0xff, sizeof(u1u2)); 1709 ure_write_mem(sc, URE_USB_TOLERANCE, 1710 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 1711 } 1712 1713 static void 1714 ure_rtl8153b_init(struct ure_softc *sc) 1715 { 1716 uint16_t val; 1717 int i; 1718 1719 if (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) { 1720 URE_CLRBIT_1(sc, 0xd26b, URE_MCU_TYPE_USB, 0x01); 1721 ure_write_2(sc, 0xd32a, URE_MCU_TYPE_USB, 0); 1722 URE_SETBIT_2(sc, 0xcfee, URE_MCU_TYPE_USB, 0x0020); 1723 } 1724 1725 if (sc->sc_flags & URE_FLAG_8156B) { 1726 URE_SETBIT_2(sc, 0xb460, URE_MCU_TYPE_USB, 0x08); 1727 } 1728 1729 ure_enable_aldps(sc, false); 1730 1731 /* Disable U1U2 */ 1732 URE_CLRBIT_2(sc, URE_USB_LPM_CONFIG, URE_MCU_TYPE_USB, URE_LPM_U1U2_EN); 1733 1734 /* Wait loading flash */ 1735 if (sc->sc_chip == URE_CHIP_VER_7410) { 1736 if ((ure_read_2(sc, 0xd3ae, URE_MCU_TYPE_PLA) & 0x0002) && 1737 !(ure_read_2(sc, 0xd284, URE_MCU_TYPE_USB) & 0x0020)) { 1738 for (i=0; i < 100; i++) { 1739 if (ure_read_2(sc, 0xd284, URE_MCU_TYPE_USB) & 0x0004) 1740 break; 1741 uether_pause(&sc->sc_ue, hz / 1000); 1742 } 1743 } 1744 } 1745 1746 for (i = 0; i < URE_TIMEOUT; i++) { 1747 if (ure_read_2(sc, URE_PLA_BOOT_CTRL, URE_MCU_TYPE_PLA) & 1748 URE_AUTOLOAD_DONE) 1749 break; 1750 uether_pause(&sc->sc_ue, hz / 100); 1751 } 1752 if (i == URE_TIMEOUT) 1753 device_printf(sc->sc_ue.ue_dev, 1754 "timeout waiting for chip autoload\n"); 1755 1756 val = ure_phy_status(sc, 0); 1757 if ((val == URE_PHY_STAT_EXT_INIT) & 1758 (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B))) { 1759 ure_ocp_reg_write(sc, 0xa468, 1760 ure_ocp_reg_read(sc, 0xa468) & ~0x0a); 1761 if (sc->sc_flags & URE_FLAG_8156B) 1762 ure_ocp_reg_write(sc, 0xa466, 1763 ure_ocp_reg_read(sc, 0xa466) & ~0x01); 1764 } 1765 1766 val = ure_ocp_reg_read(sc, URE_OCP_BASE_MII + MII_BMCR); 1767 if (val & BMCR_PDOWN) { 1768 val &= ~BMCR_PDOWN; 1769 ure_ocp_reg_write(sc, URE_OCP_BASE_MII + MII_BMCR, val); 1770 } 1771 1772 ure_phy_status(sc, URE_PHY_STAT_LAN_ON); 1773 1774 /* Disable U2P3 */ 1775 URE_CLRBIT_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, URE_U2P3_ENABLE); 1776 1777 /* MSC timer, 32760 ms. */ 1778 ure_write_2(sc, URE_USB_MSC_TIMER, URE_MCU_TYPE_USB, 0x0fff); 1779 1780 /* U1/U2/L1 idle timer, 500 us. */ 1781 ure_write_2(sc, URE_USB_U1U2_TIMER, URE_MCU_TYPE_USB, 500); 1782 1783 /* Disable power cut */ 1784 URE_CLRBIT_2(sc, URE_USB_POWER_CUT, URE_MCU_TYPE_USB, URE_PWR_EN); 1785 URE_CLRBIT_2(sc, URE_USB_MISC_0, URE_MCU_TYPE_USB, URE_PCUT_STATUS); 1786 1787 /* Disable ups */ 1788 URE_CLRBIT_1(sc, URE_USB_POWER_CUT, URE_MCU_TYPE_USB, URE_UPS_EN | URE_USP_PREWAKE); 1789 URE_CLRBIT_1(sc, 0xcfff, URE_MCU_TYPE_USB, 0x01); 1790 1791 /* Disable queue wake */ 1792 URE_CLRBIT_1(sc, URE_PLA_INDICATE_FALG, URE_MCU_TYPE_USB, URE_UPCOMING_RUNTIME_D3); 1793 URE_CLRBIT_1(sc, URE_PLA_SUSPEND_FLAG, URE_MCU_TYPE_USB, URE_LINK_CHG_EVENT); 1794 URE_CLRBIT_2(sc, URE_PLA_EXTRA_STATUS, URE_MCU_TYPE_USB, URE_LINK_CHANGE_FLAG); 1795 1796 /* Disable runtime suspend */ 1797 ure_write_1(sc, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_CONFIG); 1798 URE_CLRBIT_2(sc, URE_PLA_CONFIG34, URE_MCU_TYPE_USB, URE_LINK_OFF_WAKE_EN); 1799 ure_write_1(sc, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_NORAML); 1800 1801 /* Enable U1U2 */ 1802 if (usbd_get_speed(sc->sc_ue.ue_udev) == USB_SPEED_SUPER) 1803 URE_SETBIT_2(sc, URE_USB_LPM_CONFIG, URE_MCU_TYPE_USB, URE_LPM_U1U2_EN); 1804 1805 if (sc->sc_flags & URE_FLAG_8156B) { 1806 URE_CLRBIT_2(sc, 0xc010, URE_MCU_TYPE_PLA, 0x0800); 1807 URE_SETBIT_2(sc, 0xe854, URE_MCU_TYPE_PLA, 0x0001); 1808 1809 /* enable fc timer and set timer to 600 ms. */ 1810 ure_write_2(sc, URE_USB_FC_TIMER, URE_MCU_TYPE_USB, URE_CTRL_TIMER_EN | (600 / 8)); 1811 1812 if (!(ure_read_1(sc, 0xdc6b, URE_MCU_TYPE_PLA) & 0x80)) { 1813 val = ure_read_2(sc, URE_USB_FW_CTRL, URE_MCU_TYPE_USB); 1814 val |= URE_FLOW_CTRL_PATCH_OPT | 0x0100; 1815 val &= ~0x08; 1816 ure_write_2(sc, URE_USB_FW_CTRL, URE_MCU_TYPE_USB, val); 1817 } 1818 1819 URE_SETBIT_2(sc, URE_USB_FW_TASK, URE_MCU_TYPE_USB, URE_FC_PATCH_TASK); 1820 } 1821 1822 val = ure_read_2(sc, URE_PLA_EXTRA_STATUS, URE_MCU_TYPE_PLA); 1823 if (ure_get_link_status(sc)) 1824 val |= URE_CUR_LINK_OK; 1825 else 1826 val &= ~URE_CUR_LINK_OK; 1827 val |= URE_POLL_LINK_CHG; 1828 ure_write_2(sc, URE_PLA_EXTRA_STATUS, URE_MCU_TYPE_PLA, val); 1829 1830 /* MAC clock speed down */ 1831 if (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) { 1832 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, 0x0403); 1833 val = ure_read_2(sc, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_PLA); 1834 val &= ~0xff; 1835 val |= URE_MAC_CLK_SPDWN_EN | 0x03; 1836 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_PLA, val); 1837 } else { 1838 URE_SETBIT_2(sc, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_USB, URE_MAC_CLK_SPDWN_EN); 1839 } 1840 URE_CLRBIT_2(sc, URE_PLA_MAC_PWR_CTRL3, URE_MCU_TYPE_PLA, URE_PLA_MCU_SPDWN_EN); 1841 1842 /* Enable Rx aggregation. */ 1843 URE_CLRBIT_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, URE_RX_AGG_DISABLE | URE_RX_ZERO_EN); 1844 1845 if (sc->sc_flags & URE_FLAG_8156) 1846 URE_SETBIT_1(sc, 0xd4b4, URE_MCU_TYPE_USB, 0x02); 1847 1848 /* Reset tally */ 1849 URE_SETBIT_2(sc, URE_PLA_RSTTALLY, URE_MCU_TYPE_USB, URE_TALLY_RESET); 1850 } 1851 1852 static void 1853 ure_rtl8153b_nic_reset(struct ure_softc *sc) 1854 { 1855 struct ifnet *ifp = uether_getifp(&sc->sc_ue); 1856 uint16_t val; 1857 int i; 1858 1859 /* Disable U1U2 */ 1860 URE_CLRBIT_2(sc, URE_USB_LPM_CONFIG, URE_MCU_TYPE_USB, URE_LPM_U1U2_EN); 1861 1862 /* Disable U2P3 */ 1863 URE_CLRBIT_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, URE_U2P3_ENABLE); 1864 1865 ure_enable_aldps(sc, false); 1866 1867 /* Enable rxdy_gated */ 1868 URE_SETBIT_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, URE_RXDY_GATED_EN); 1869 1870 /* Disable teredo */ 1871 ure_disable_teredo(sc); 1872 1873 DEVPRINTFN(14, sc->sc_ue.ue_dev, "rtl8153b_nic_reset: RCR: %#x\n", ure_read_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA)); 1874 URE_CLRBIT_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, URE_RCR_ACPT_ALL); 1875 1876 ure_reset(sc); 1877 1878 /* Reset BMU */ 1879 URE_CLRBIT_1(sc, URE_USB_BMU_RESET, URE_MCU_TYPE_USB, URE_BMU_RESET_EP_IN | URE_BMU_RESET_EP_OUT); 1880 URE_SETBIT_1(sc, URE_USB_BMU_RESET, URE_MCU_TYPE_USB, URE_BMU_RESET_EP_IN | URE_BMU_RESET_EP_OUT); 1881 1882 URE_CLRBIT_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA, URE_NOW_IS_OOB); 1883 URE_CLRBIT_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, URE_MCU_BORW_EN); 1884 if (sc->sc_flags & URE_FLAG_8153B) { 1885 for (i = 0; i < URE_TIMEOUT; i++) { 1886 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 1887 URE_LINK_LIST_READY) 1888 break; 1889 uether_pause(&sc->sc_ue, hz / 100); 1890 } 1891 if (i == URE_TIMEOUT) 1892 device_printf(sc->sc_ue.ue_dev, 1893 "timeout waiting for OOB control\n"); 1894 1895 URE_SETBIT_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, URE_RE_INIT_LL); 1896 for (i = 0; i < URE_TIMEOUT; i++) { 1897 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 1898 URE_LINK_LIST_READY) 1899 break; 1900 uether_pause(&sc->sc_ue, hz / 100); 1901 } 1902 if (i == URE_TIMEOUT) 1903 device_printf(sc->sc_ue.ue_dev, 1904 "timeout waiting for OOB control\n"); 1905 } 1906 1907 /* Configure rxvlan */ 1908 val = ure_read_2(sc, 0xc012, URE_MCU_TYPE_PLA); 1909 val &= ~0x00c0; 1910 if (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) 1911 val |= 0x00c0; 1912 ure_write_2(sc, 0xc012, URE_MCU_TYPE_PLA, val); 1913 1914 val = if_getmtu(ifp); 1915 ure_write_2(sc, URE_PLA_RMS, URE_MCU_TYPE_PLA, URE_FRAMELEN(val)); 1916 ure_write_1(sc, URE_PLA_MTPS, URE_MCU_TYPE_PLA, URE_MTPS_JUMBO); 1917 1918 if (sc->sc_flags & URE_FLAG_8153B) { 1919 URE_SETBIT_2(sc, URE_PLA_TCR0, URE_MCU_TYPE_PLA, URE_TCR0_AUTO_FIFO); 1920 ure_reset(sc); 1921 } 1922 1923 /* Configure fc parameter */ 1924 if (sc->sc_flags & URE_FLAG_8156) { 1925 ure_write_2(sc, 0xc0a6, URE_MCU_TYPE_PLA, 0x0400); 1926 ure_write_2(sc, 0xc0aa, URE_MCU_TYPE_PLA, 0x0800); 1927 } else if (sc->sc_flags & URE_FLAG_8156B) { 1928 ure_write_2(sc, 0xc0a6, URE_MCU_TYPE_PLA, 0x0200); 1929 ure_write_2(sc, 0xc0aa, URE_MCU_TYPE_PLA, 0x0400); 1930 } 1931 1932 /* Configure Rx FIFO threshold. */ 1933 if (sc->sc_flags & URE_FLAG_8153B) { 1934 ure_write_4(sc, URE_PLA_RXFIFO_CTRL0, URE_MCU_TYPE_PLA, URE_RXFIFO_THR1_NORMAL); 1935 ure_write_2(sc, URE_PLA_RXFIFO_CTRL1, URE_MCU_TYPE_PLA, URE_RXFIFO_THR2_NORMAL); 1936 ure_write_2(sc, URE_PLA_RXFIFO_CTRL2, URE_MCU_TYPE_PLA, URE_RXFIFO_THR3_NORMAL); 1937 ure_write_4(sc, URE_USB_RX_BUF_TH, URE_MCU_TYPE_USB, URE_RX_THR_B); 1938 } else { 1939 ure_write_2(sc, 0xc0a2, URE_MCU_TYPE_PLA, 1940 (ure_read_2(sc, 0xc0a2, URE_MCU_TYPE_PLA) & ~0xfff) | 0x08); 1941 ure_write_4(sc, URE_USB_RX_BUF_TH, URE_MCU_TYPE_USB, 0x00600400); 1942 } 1943 1944 /* Configure Tx FIFO threshold. */ 1945 if (sc->sc_flags & URE_FLAG_8153B) { 1946 ure_write_4(sc, URE_PLA_TXFIFO_CTRL, URE_MCU_TYPE_PLA, URE_TXFIFO_THR_NORMAL2); 1947 } else if (sc->sc_flags & URE_FLAG_8156) { 1948 ure_write_2(sc, URE_PLA_TXFIFO_CTRL, URE_MCU_TYPE_PLA, URE_TXFIFO_THR_NORMAL2); 1949 URE_SETBIT_2(sc, 0xd4b4, URE_MCU_TYPE_USB, 0x0002); 1950 } else if (sc->sc_flags & URE_FLAG_8156B) { 1951 ure_write_2(sc, URE_PLA_TXFIFO_CTRL, URE_MCU_TYPE_PLA, 0x0008); 1952 ure_write_2(sc, 0xe61a, URE_MCU_TYPE_PLA, 1953 (URE_FRAMELEN(val) + 0x100) / 16 ); 1954 } 1955 1956 URE_CLRBIT_2(sc, URE_PLA_MAC_PWR_CTRL3, URE_MCU_TYPE_PLA, URE_PLA_MCU_SPDWN_EN); 1957 1958 if (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) 1959 URE_CLRBIT_2(sc, 0xd32a, URE_MCU_TYPE_USB, 0x300); 1960 1961 ure_enable_aldps(sc, true); 1962 1963 if (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) { 1964 /* Enable U2P3 */ 1965 URE_SETBIT_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, URE_U2P3_ENABLE); 1966 } 1967 1968 /* Enable U1U2 */ 1969 if (usbd_get_speed(sc->sc_ue.ue_udev) == USB_SPEED_SUPER) 1970 URE_SETBIT_2(sc, URE_USB_LPM_CONFIG, URE_MCU_TYPE_USB, URE_LPM_U1U2_EN); 1971 } 1972 1973 static void 1974 ure_stop(struct usb_ether *ue) 1975 { 1976 struct ure_softc *sc = uether_getsc(ue); 1977 struct ifnet *ifp = uether_getifp(ue); 1978 1979 URE_LOCK_ASSERT(sc, MA_OWNED); 1980 1981 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1982 sc->sc_flags &= ~URE_FLAG_LINK; 1983 sc->sc_rxstarted = 0; 1984 1985 /* 1986 * stop all the transfers, if not already stopped: 1987 */ 1988 for (int i = 0; i < URE_MAX_RX; i++) 1989 usbd_transfer_stop(sc->sc_rx_xfer[i]); 1990 for (int i = 0; i < URE_MAX_TX; i++) 1991 usbd_transfer_stop(sc->sc_tx_xfer[i]); 1992 } 1993 1994 static void 1995 ure_disable_teredo(struct ure_softc *sc) 1996 { 1997 1998 if (sc->sc_flags & (URE_FLAG_8153B | URE_FLAG_8156 | URE_FLAG_8156B)) 1999 ure_write_1(sc, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA, 0xff); 2000 else { 2001 URE_CLRBIT_2(sc, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA, 2002 (URE_TEREDO_SEL | URE_TEREDO_RS_EVENT_MASK | URE_OOB_TEREDO_EN)); 2003 } 2004 ure_write_2(sc, URE_PLA_WDT6_CTRL, URE_MCU_TYPE_PLA, URE_WDT6_SET_MODE); 2005 ure_write_2(sc, URE_PLA_REALWOW_TIMER, URE_MCU_TYPE_PLA, 0); 2006 ure_write_4(sc, URE_PLA_TEREDO_TIMER, URE_MCU_TYPE_PLA, 0); 2007 } 2008 2009 static void 2010 ure_enable_aldps(struct ure_softc *sc, bool enable) 2011 { 2012 int i; 2013 2014 if (enable) { 2015 ure_ocp_reg_write(sc, URE_OCP_POWER_CFG, 2016 ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) | URE_EN_ALDPS); 2017 } else { 2018 ure_ocp_reg_write(sc, URE_OCP_ALDPS_CONFIG, URE_ENPDNPS | URE_LINKENA | 2019 URE_DIS_SDSAVE); 2020 for (i = 0; i < 20; i++) { 2021 uether_pause(&sc->sc_ue, hz / 1000); 2022 if (ure_ocp_reg_read(sc, 0xe000) & 0x0100) 2023 break; 2024 } 2025 } 2026 } 2027 2028 static uint16_t 2029 ure_phy_status(struct ure_softc *sc, uint16_t desired) 2030 { 2031 uint16_t val; 2032 int i; 2033 2034 for (i = 0; i < URE_TIMEOUT; i++) { 2035 val = ure_ocp_reg_read(sc, URE_OCP_PHY_STATUS) & 2036 URE_PHY_STAT_MASK; 2037 if (desired) { 2038 if (val == desired) 2039 break; 2040 } else { 2041 if (val == URE_PHY_STAT_LAN_ON || 2042 val == URE_PHY_STAT_PWRDN || 2043 val == URE_PHY_STAT_EXT_INIT) 2044 break; 2045 } 2046 uether_pause(&sc->sc_ue, hz / 100); 2047 } 2048 if (i == URE_TIMEOUT) 2049 device_printf(sc->sc_ue.ue_dev, 2050 "timeout waiting for phy to stabilize\n"); 2051 2052 return (val); 2053 } 2054 2055 static void 2056 ure_rtl8152_nic_reset(struct ure_softc *sc) 2057 { 2058 uint32_t rx_fifo1, rx_fifo2; 2059 int i; 2060 2061 URE_SETBIT_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, URE_RXDY_GATED_EN); 2062 2063 ure_disable_teredo(sc); 2064 2065 DEVPRINTFN(14, sc->sc_ue.ue_dev, "rtl8152_nic_reset: RCR: %#x\n", ure_read_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA)); 2066 URE_CLRBIT_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, URE_RCR_ACPT_ALL); 2067 2068 ure_reset(sc); 2069 2070 ure_write_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, 0); 2071 2072 URE_CLRBIT_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA, URE_NOW_IS_OOB); 2073 2074 URE_CLRBIT_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, URE_MCU_BORW_EN); 2075 for (i = 0; i < URE_TIMEOUT; i++) { 2076 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 2077 URE_LINK_LIST_READY) 2078 break; 2079 uether_pause(&sc->sc_ue, hz / 100); 2080 } 2081 if (i == URE_TIMEOUT) 2082 device_printf(sc->sc_ue.ue_dev, 2083 "timeout waiting for OOB control\n"); 2084 URE_SETBIT_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, URE_RE_INIT_LL); 2085 for (i = 0; i < URE_TIMEOUT; i++) { 2086 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 2087 URE_LINK_LIST_READY) 2088 break; 2089 uether_pause(&sc->sc_ue, hz / 100); 2090 } 2091 if (i == URE_TIMEOUT) 2092 device_printf(sc->sc_ue.ue_dev, 2093 "timeout waiting for OOB control\n"); 2094 2095 URE_CLRBIT_2(sc, URE_PLA_CPCR, URE_MCU_TYPE_PLA, URE_CPCR_RX_VLAN); 2096 2097 URE_SETBIT_2(sc, URE_PLA_TCR0, URE_MCU_TYPE_PLA, URE_TCR0_AUTO_FIFO); 2098 2099 /* Configure Rx FIFO threshold. */ 2100 ure_write_4(sc, URE_PLA_RXFIFO_CTRL0, URE_MCU_TYPE_PLA, 2101 URE_RXFIFO_THR1_NORMAL); 2102 if (usbd_get_speed(sc->sc_ue.ue_udev) == USB_SPEED_FULL) { 2103 rx_fifo1 = URE_RXFIFO_THR2_FULL; 2104 rx_fifo2 = URE_RXFIFO_THR3_FULL; 2105 } else { 2106 rx_fifo1 = URE_RXFIFO_THR2_HIGH; 2107 rx_fifo2 = URE_RXFIFO_THR3_HIGH; 2108 } 2109 ure_write_4(sc, URE_PLA_RXFIFO_CTRL1, URE_MCU_TYPE_PLA, rx_fifo1); 2110 ure_write_4(sc, URE_PLA_RXFIFO_CTRL2, URE_MCU_TYPE_PLA, rx_fifo2); 2111 2112 /* Configure Tx FIFO threshold. */ 2113 ure_write_4(sc, URE_PLA_TXFIFO_CTRL, URE_MCU_TYPE_PLA, 2114 URE_TXFIFO_THR_NORMAL); 2115 } 2116 2117 /* 2118 * Update mbuf for rx checksum from hardware 2119 */ 2120 static void 2121 ure_rxcsum(int capenb, struct ure_rxpkt *rp, struct mbuf *m) 2122 { 2123 int flags; 2124 uint32_t csum, misc; 2125 int tcp, udp; 2126 2127 m->m_pkthdr.csum_flags = 0; 2128 2129 if (!(capenb & IFCAP_RXCSUM)) 2130 return; 2131 2132 csum = le32toh(rp->ure_csum); 2133 misc = le32toh(rp->ure_misc); 2134 2135 tcp = udp = 0; 2136 2137 flags = 0; 2138 if (csum & URE_RXPKT_IPV4_CS) 2139 flags |= CSUM_IP_CHECKED; 2140 else if (csum & URE_RXPKT_IPV6_CS) 2141 flags = 0; 2142 2143 tcp = rp->ure_csum & URE_RXPKT_TCP_CS; 2144 udp = rp->ure_csum & URE_RXPKT_UDP_CS; 2145 2146 if (__predict_true((flags & CSUM_IP_CHECKED) && 2147 !(misc & URE_RXPKT_IP_F))) { 2148 flags |= CSUM_IP_VALID; 2149 } 2150 if (__predict_true( 2151 (tcp && !(misc & URE_RXPKT_TCP_F)) || 2152 (udp && !(misc & URE_RXPKT_UDP_F)))) { 2153 flags |= CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 2154 m->m_pkthdr.csum_data = 0xFFFF; 2155 } 2156 2157 m->m_pkthdr.csum_flags = flags; 2158 } 2159 2160 /* 2161 * If the L4 checksum offset is larger than 0x7ff (2047), return failure. 2162 * We currently restrict MTU such that it can't happen, and even if we 2163 * did have a large enough MTU, only a very specially crafted IPv6 packet 2164 * with MANY headers could possibly come close. 2165 * 2166 * Returns 0 for success, and 1 if the packet cannot be checksummed and 2167 * should be dropped. 2168 */ 2169 static int 2170 ure_txcsum(struct mbuf *m, int caps, uint32_t *regout) 2171 { 2172 struct ip ip; 2173 struct ether_header *eh; 2174 int flags; 2175 uint32_t data; 2176 uint32_t reg; 2177 int l3off, l4off; 2178 uint16_t type; 2179 2180 *regout = 0; 2181 flags = m->m_pkthdr.csum_flags; 2182 if (flags == 0) 2183 return (0); 2184 2185 if (__predict_true(m->m_len >= (int)sizeof(*eh))) { 2186 eh = mtod(m, struct ether_header *); 2187 type = eh->ether_type; 2188 } else 2189 m_copydata(m, offsetof(struct ether_header, ether_type), 2190 sizeof(type), (caddr_t)&type); 2191 2192 switch (type = htons(type)) { 2193 case ETHERTYPE_IP: 2194 case ETHERTYPE_IPV6: 2195 l3off = ETHER_HDR_LEN; 2196 break; 2197 case ETHERTYPE_VLAN: 2198 /* XXX - what about QinQ? */ 2199 l3off = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 2200 break; 2201 default: 2202 return (0); 2203 } 2204 2205 reg = 0; 2206 2207 if (flags & CSUM_IP) 2208 reg |= URE_TXPKT_IPV4_CS; 2209 2210 data = m->m_pkthdr.csum_data; 2211 if (flags & (CSUM_IP_TCP | CSUM_IP_UDP)) { 2212 m_copydata(m, l3off, sizeof ip, (caddr_t)&ip); 2213 l4off = l3off + (ip.ip_hl << 2) + data; 2214 if (__predict_false(l4off > URE_L4_OFFSET_MAX)) 2215 return (1); 2216 2217 reg |= URE_TXPKT_IPV4_CS; 2218 if (flags & CSUM_IP_TCP) 2219 reg |= URE_TXPKT_TCP_CS; 2220 else if (flags & CSUM_IP_UDP) 2221 reg |= URE_TXPKT_UDP_CS; 2222 reg |= l4off << URE_L4_OFFSET_SHIFT; 2223 } 2224 #ifdef INET6 2225 else if (flags & (CSUM_IP6_TCP | CSUM_IP6_UDP)) { 2226 l4off = l3off + data; 2227 if (__predict_false(l4off > URE_L4_OFFSET_MAX)) 2228 return (1); 2229 2230 reg |= URE_TXPKT_IPV6_CS; 2231 if (flags & CSUM_IP6_TCP) 2232 reg |= URE_TXPKT_TCP_CS; 2233 else if (flags & CSUM_IP6_UDP) 2234 reg |= URE_TXPKT_UDP_CS; 2235 reg |= l4off << URE_L4_OFFSET_SHIFT; 2236 } 2237 #endif 2238 *regout = reg; 2239 return 0; 2240 } 2241