1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2010, Pyun YongHyeon <yongari@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* Driver for DM&P Electronics, Inc, Vortex86 RDC R6040 FastEthernet. */ 31 32 #include <sys/cdefs.h> 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 #include <sys/endian.h> 37 #include <sys/kernel.h> 38 #include <sys/lock.h> 39 #include <sys/malloc.h> 40 #include <sys/mbuf.h> 41 #include <sys/module.h> 42 #include <sys/mutex.h> 43 #include <sys/rman.h> 44 #include <sys/socket.h> 45 #include <sys/sockio.h> 46 #include <sys/sysctl.h> 47 48 #include <net/bpf.h> 49 #include <net/if.h> 50 #include <net/if_var.h> 51 #include <net/if_arp.h> 52 #include <net/ethernet.h> 53 #include <net/if_dl.h> 54 #include <net/if_llc.h> 55 #include <net/if_media.h> 56 #include <net/if_types.h> 57 #include <net/if_vlan_var.h> 58 59 #include <netinet/in.h> 60 #include <netinet/in_systm.h> 61 62 #include <dev/mii/mii.h> 63 #include <dev/mii/miivar.h> 64 65 #include <dev/pci/pcireg.h> 66 #include <dev/pci/pcivar.h> 67 68 #include <machine/bus.h> 69 70 #include <dev/vte/if_vtereg.h> 71 #include <dev/vte/if_vtevar.h> 72 73 /* "device miibus" required. See GENERIC if you get errors here. */ 74 #include "miibus_if.h" 75 76 MODULE_DEPEND(vte, pci, 1, 1, 1); 77 MODULE_DEPEND(vte, ether, 1, 1, 1); 78 MODULE_DEPEND(vte, miibus, 1, 1, 1); 79 80 /* Tunables. */ 81 static int tx_deep_copy = 1; 82 TUNABLE_INT("hw.vte.tx_deep_copy", &tx_deep_copy); 83 84 /* 85 * Devices supported by this driver. 86 */ 87 static const struct vte_ident vte_ident_table[] = { 88 { VENDORID_RDC, DEVICEID_RDC_R6040, "RDC R6040 FastEthernet"}, 89 { 0, 0, NULL} 90 }; 91 92 static int vte_attach(device_t); 93 static int vte_detach(device_t); 94 static int vte_dma_alloc(struct vte_softc *); 95 static void vte_dma_free(struct vte_softc *); 96 static void vte_dmamap_cb(void *, bus_dma_segment_t *, int, int); 97 static struct vte_txdesc * 98 vte_encap(struct vte_softc *, struct mbuf **); 99 static const struct vte_ident * 100 vte_find_ident(device_t); 101 #ifndef __NO_STRICT_ALIGNMENT 102 static struct mbuf * 103 vte_fixup_rx(if_t, struct mbuf *); 104 #endif 105 static void vte_get_macaddr(struct vte_softc *); 106 static void vte_init(void *); 107 static void vte_init_locked(struct vte_softc *); 108 static int vte_init_rx_ring(struct vte_softc *); 109 static int vte_init_tx_ring(struct vte_softc *); 110 static void vte_intr(void *); 111 static int vte_ioctl(if_t, u_long, caddr_t); 112 static uint64_t vte_get_counter(if_t, ift_counter); 113 static void vte_mac_config(struct vte_softc *); 114 static int vte_miibus_readreg(device_t, int, int); 115 static void vte_miibus_statchg(device_t); 116 static int vte_miibus_writereg(device_t, int, int, int); 117 static int vte_mediachange(if_t); 118 static int vte_mediachange_locked(if_t); 119 static void vte_mediastatus(if_t, struct ifmediareq *); 120 static int vte_newbuf(struct vte_softc *, struct vte_rxdesc *); 121 static int vte_probe(device_t); 122 static void vte_reset(struct vte_softc *); 123 static int vte_resume(device_t); 124 static void vte_rxeof(struct vte_softc *); 125 static void vte_rxfilter(struct vte_softc *); 126 static int vte_shutdown(device_t); 127 static void vte_start(if_t); 128 static void vte_start_locked(struct vte_softc *); 129 static void vte_start_mac(struct vte_softc *); 130 static void vte_stats_clear(struct vte_softc *); 131 static void vte_stats_update(struct vte_softc *); 132 static void vte_stop(struct vte_softc *); 133 static void vte_stop_mac(struct vte_softc *); 134 static int vte_suspend(device_t); 135 static void vte_sysctl_node(struct vte_softc *); 136 static void vte_tick(void *); 137 static void vte_txeof(struct vte_softc *); 138 static void vte_watchdog(struct vte_softc *); 139 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 140 static int sysctl_hw_vte_int_mod(SYSCTL_HANDLER_ARGS); 141 142 static device_method_t vte_methods[] = { 143 /* Device interface. */ 144 DEVMETHOD(device_probe, vte_probe), 145 DEVMETHOD(device_attach, vte_attach), 146 DEVMETHOD(device_detach, vte_detach), 147 DEVMETHOD(device_shutdown, vte_shutdown), 148 DEVMETHOD(device_suspend, vte_suspend), 149 DEVMETHOD(device_resume, vte_resume), 150 151 /* MII interface. */ 152 DEVMETHOD(miibus_readreg, vte_miibus_readreg), 153 DEVMETHOD(miibus_writereg, vte_miibus_writereg), 154 DEVMETHOD(miibus_statchg, vte_miibus_statchg), 155 156 DEVMETHOD_END 157 }; 158 159 static driver_t vte_driver = { 160 "vte", 161 vte_methods, 162 sizeof(struct vte_softc) 163 }; 164 165 DRIVER_MODULE(vte, pci, vte_driver, 0, 0); 166 DRIVER_MODULE(miibus, vte, miibus_driver, 0, 0); 167 168 static int 169 vte_miibus_readreg(device_t dev, int phy, int reg) 170 { 171 struct vte_softc *sc; 172 int i; 173 174 sc = device_get_softc(dev); 175 176 CSR_WRITE_2(sc, VTE_MMDIO, MMDIO_READ | 177 (phy << MMDIO_PHY_ADDR_SHIFT) | (reg << MMDIO_REG_ADDR_SHIFT)); 178 for (i = VTE_PHY_TIMEOUT; i > 0; i--) { 179 DELAY(5); 180 if ((CSR_READ_2(sc, VTE_MMDIO) & MMDIO_READ) == 0) 181 break; 182 } 183 184 if (i == 0) { 185 device_printf(sc->vte_dev, "phy read timeout : %d\n", reg); 186 return (0); 187 } 188 189 return (CSR_READ_2(sc, VTE_MMRD)); 190 } 191 192 static int 193 vte_miibus_writereg(device_t dev, int phy, int reg, int val) 194 { 195 struct vte_softc *sc; 196 int i; 197 198 sc = device_get_softc(dev); 199 200 CSR_WRITE_2(sc, VTE_MMWD, val); 201 CSR_WRITE_2(sc, VTE_MMDIO, MMDIO_WRITE | 202 (phy << MMDIO_PHY_ADDR_SHIFT) | (reg << MMDIO_REG_ADDR_SHIFT)); 203 for (i = VTE_PHY_TIMEOUT; i > 0; i--) { 204 DELAY(5); 205 if ((CSR_READ_2(sc, VTE_MMDIO) & MMDIO_WRITE) == 0) 206 break; 207 } 208 209 if (i == 0) 210 device_printf(sc->vte_dev, "phy write timeout : %d\n", reg); 211 212 return (0); 213 } 214 215 static void 216 vte_miibus_statchg(device_t dev) 217 { 218 struct vte_softc *sc; 219 struct mii_data *mii; 220 if_t ifp; 221 uint16_t val; 222 223 sc = device_get_softc(dev); 224 225 mii = device_get_softc(sc->vte_miibus); 226 ifp = sc->vte_ifp; 227 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 228 return; 229 230 sc->vte_flags &= ~VTE_FLAG_LINK; 231 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 232 (IFM_ACTIVE | IFM_AVALID)) { 233 switch (IFM_SUBTYPE(mii->mii_media_active)) { 234 case IFM_10_T: 235 case IFM_100_TX: 236 sc->vte_flags |= VTE_FLAG_LINK; 237 break; 238 default: 239 break; 240 } 241 } 242 243 /* Stop RX/TX MACs. */ 244 vte_stop_mac(sc); 245 /* Program MACs with resolved duplex and flow control. */ 246 if ((sc->vte_flags & VTE_FLAG_LINK) != 0) { 247 /* 248 * Timer waiting time : (63 + TIMER * 64) MII clock. 249 * MII clock : 25MHz(100Mbps) or 2.5MHz(10Mbps). 250 */ 251 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) 252 val = 18 << VTE_IM_TIMER_SHIFT; 253 else 254 val = 1 << VTE_IM_TIMER_SHIFT; 255 val |= sc->vte_int_rx_mod << VTE_IM_BUNDLE_SHIFT; 256 /* 48.6us for 100Mbps, 50.8us for 10Mbps */ 257 CSR_WRITE_2(sc, VTE_MRICR, val); 258 259 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) 260 val = 18 << VTE_IM_TIMER_SHIFT; 261 else 262 val = 1 << VTE_IM_TIMER_SHIFT; 263 val |= sc->vte_int_tx_mod << VTE_IM_BUNDLE_SHIFT; 264 /* 48.6us for 100Mbps, 50.8us for 10Mbps */ 265 CSR_WRITE_2(sc, VTE_MTICR, val); 266 267 vte_mac_config(sc); 268 vte_start_mac(sc); 269 } 270 } 271 272 static void 273 vte_mediastatus(if_t ifp, struct ifmediareq *ifmr) 274 { 275 struct vte_softc *sc; 276 struct mii_data *mii; 277 278 sc = if_getsoftc(ifp); 279 VTE_LOCK(sc); 280 if ((if_getflags(ifp) & IFF_UP) == 0) { 281 VTE_UNLOCK(sc); 282 return; 283 } 284 mii = device_get_softc(sc->vte_miibus); 285 286 mii_pollstat(mii); 287 ifmr->ifm_status = mii->mii_media_status; 288 ifmr->ifm_active = mii->mii_media_active; 289 VTE_UNLOCK(sc); 290 } 291 292 static int 293 vte_mediachange(if_t ifp) 294 { 295 struct vte_softc *sc; 296 int error; 297 298 sc = if_getsoftc(ifp); 299 VTE_LOCK(sc); 300 error = vte_mediachange_locked(ifp); 301 VTE_UNLOCK(sc); 302 return (error); 303 } 304 305 static int 306 vte_mediachange_locked(if_t ifp) 307 { 308 struct vte_softc *sc; 309 struct mii_data *mii; 310 struct mii_softc *miisc; 311 int error; 312 313 sc = if_getsoftc(ifp); 314 mii = device_get_softc(sc->vte_miibus); 315 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 316 PHY_RESET(miisc); 317 error = mii_mediachg(mii); 318 319 return (error); 320 } 321 322 static const struct vte_ident * 323 vte_find_ident(device_t dev) 324 { 325 const struct vte_ident *ident; 326 uint16_t vendor, devid; 327 328 vendor = pci_get_vendor(dev); 329 devid = pci_get_device(dev); 330 for (ident = vte_ident_table; ident->name != NULL; ident++) { 331 if (vendor == ident->vendorid && devid == ident->deviceid) 332 return (ident); 333 } 334 335 return (NULL); 336 } 337 338 static int 339 vte_probe(device_t dev) 340 { 341 const struct vte_ident *ident; 342 343 ident = vte_find_ident(dev); 344 if (ident != NULL) { 345 device_set_desc(dev, ident->name); 346 return (BUS_PROBE_DEFAULT); 347 } 348 349 return (ENXIO); 350 } 351 352 static void 353 vte_get_macaddr(struct vte_softc *sc) 354 { 355 uint16_t mid; 356 357 /* 358 * It seems there is no way to reload station address and 359 * it is supposed to be set by BIOS. 360 */ 361 mid = CSR_READ_2(sc, VTE_MID0L); 362 sc->vte_eaddr[0] = (mid >> 0) & 0xFF; 363 sc->vte_eaddr[1] = (mid >> 8) & 0xFF; 364 mid = CSR_READ_2(sc, VTE_MID0M); 365 sc->vte_eaddr[2] = (mid >> 0) & 0xFF; 366 sc->vte_eaddr[3] = (mid >> 8) & 0xFF; 367 mid = CSR_READ_2(sc, VTE_MID0H); 368 sc->vte_eaddr[4] = (mid >> 0) & 0xFF; 369 sc->vte_eaddr[5] = (mid >> 8) & 0xFF; 370 } 371 372 static int 373 vte_attach(device_t dev) 374 { 375 struct vte_softc *sc; 376 if_t ifp; 377 uint16_t macid; 378 int error, rid; 379 380 error = 0; 381 sc = device_get_softc(dev); 382 sc->vte_dev = dev; 383 384 mtx_init(&sc->vte_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 385 MTX_DEF); 386 callout_init_mtx(&sc->vte_tick_ch, &sc->vte_mtx, 0); 387 sc->vte_ident = vte_find_ident(dev); 388 389 /* Map the device. */ 390 pci_enable_busmaster(dev); 391 sc->vte_res_id = PCIR_BAR(1); 392 sc->vte_res_type = SYS_RES_MEMORY; 393 sc->vte_res = bus_alloc_resource_any(dev, sc->vte_res_type, 394 &sc->vte_res_id, RF_ACTIVE); 395 if (sc->vte_res == NULL) { 396 sc->vte_res_id = PCIR_BAR(0); 397 sc->vte_res_type = SYS_RES_IOPORT; 398 sc->vte_res = bus_alloc_resource_any(dev, sc->vte_res_type, 399 &sc->vte_res_id, RF_ACTIVE); 400 if (sc->vte_res == NULL) { 401 device_printf(dev, "cannot map memory/ports.\n"); 402 mtx_destroy(&sc->vte_mtx); 403 return (ENXIO); 404 } 405 } 406 if (bootverbose) { 407 device_printf(dev, "using %s space register mapping\n", 408 sc->vte_res_type == SYS_RES_MEMORY ? "memory" : "I/O"); 409 device_printf(dev, "MAC Identifier : 0x%04x\n", 410 CSR_READ_2(sc, VTE_MACID)); 411 macid = CSR_READ_2(sc, VTE_MACID_REV); 412 device_printf(dev, "MAC Id. 0x%02x, Rev. 0x%02x\n", 413 (macid & VTE_MACID_MASK) >> VTE_MACID_SHIFT, 414 (macid & VTE_MACID_REV_MASK) >> VTE_MACID_REV_SHIFT); 415 } 416 417 rid = 0; 418 sc->vte_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 419 RF_SHAREABLE | RF_ACTIVE); 420 if (sc->vte_irq == NULL) { 421 device_printf(dev, "cannot allocate IRQ resources.\n"); 422 error = ENXIO; 423 goto fail; 424 } 425 426 /* Reset the ethernet controller. */ 427 vte_reset(sc); 428 429 if ((error = vte_dma_alloc(sc)) != 0) 430 goto fail; 431 432 /* Create device sysctl node. */ 433 vte_sysctl_node(sc); 434 435 /* Load station address. */ 436 vte_get_macaddr(sc); 437 438 ifp = sc->vte_ifp = if_alloc(IFT_ETHER); 439 if (ifp == NULL) { 440 device_printf(dev, "cannot allocate ifnet structure.\n"); 441 error = ENXIO; 442 goto fail; 443 } 444 445 if_setsoftc(ifp, sc); 446 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 447 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 448 if_setioctlfn(ifp, vte_ioctl); 449 if_setstartfn(ifp, vte_start); 450 if_setinitfn(ifp, vte_init); 451 if_setgetcounterfn(ifp, vte_get_counter); 452 if_setsendqlen(ifp, VTE_TX_RING_CNT - 1); 453 if_setsendqready(ifp); 454 455 /* 456 * Set up MII bus. 457 * BIOS would have initialized VTE_MPSCCR to catch PHY 458 * status changes so driver may be able to extract 459 * configured PHY address. Since it's common to see BIOS 460 * fails to initialize the register(including the sample 461 * board I have), let mii(4) probe it. This is more 462 * reliable than relying on BIOS's initialization. 463 * 464 * Advertising flow control capability to mii(4) was 465 * intentionally disabled due to severe problems in TX 466 * pause frame generation. See vte_rxeof() for more 467 * details. 468 */ 469 error = mii_attach(dev, &sc->vte_miibus, ifp, vte_mediachange, 470 vte_mediastatus, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0); 471 if (error != 0) { 472 device_printf(dev, "attaching PHYs failed\n"); 473 goto fail; 474 } 475 476 ether_ifattach(ifp, sc->vte_eaddr); 477 478 /* VLAN capability setup. */ 479 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU, 0); 480 if_setcapenable(ifp, if_getcapabilities(ifp)); 481 /* Tell the upper layer we support VLAN over-sized frames. */ 482 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 483 484 error = bus_setup_intr(dev, sc->vte_irq, INTR_TYPE_NET | INTR_MPSAFE, 485 NULL, vte_intr, sc, &sc->vte_intrhand); 486 if (error != 0) { 487 device_printf(dev, "could not set up interrupt handler.\n"); 488 ether_ifdetach(ifp); 489 goto fail; 490 } 491 492 fail: 493 if (error != 0) 494 vte_detach(dev); 495 496 return (error); 497 } 498 499 static int 500 vte_detach(device_t dev) 501 { 502 struct vte_softc *sc; 503 if_t ifp; 504 505 sc = device_get_softc(dev); 506 507 ifp = sc->vte_ifp; 508 if (device_is_attached(dev)) { 509 VTE_LOCK(sc); 510 vte_stop(sc); 511 VTE_UNLOCK(sc); 512 callout_drain(&sc->vte_tick_ch); 513 ether_ifdetach(ifp); 514 } 515 516 if (sc->vte_miibus != NULL) { 517 device_delete_child(dev, sc->vte_miibus); 518 sc->vte_miibus = NULL; 519 } 520 bus_generic_detach(dev); 521 522 if (sc->vte_intrhand != NULL) { 523 bus_teardown_intr(dev, sc->vte_irq, sc->vte_intrhand); 524 sc->vte_intrhand = NULL; 525 } 526 if (sc->vte_irq != NULL) { 527 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vte_irq); 528 sc->vte_irq = NULL; 529 } 530 if (sc->vte_res != NULL) { 531 bus_release_resource(dev, sc->vte_res_type, sc->vte_res_id, 532 sc->vte_res); 533 sc->vte_res = NULL; 534 } 535 if (ifp != NULL) { 536 if_free(ifp); 537 sc->vte_ifp = NULL; 538 } 539 vte_dma_free(sc); 540 mtx_destroy(&sc->vte_mtx); 541 542 return (0); 543 } 544 545 #define VTE_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 546 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 547 548 static void 549 vte_sysctl_node(struct vte_softc *sc) 550 { 551 struct sysctl_ctx_list *ctx; 552 struct sysctl_oid_list *child, *parent; 553 struct sysctl_oid *tree; 554 struct vte_hw_stats *stats; 555 int error; 556 557 stats = &sc->vte_stats; 558 ctx = device_get_sysctl_ctx(sc->vte_dev); 559 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->vte_dev)); 560 561 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_rx_mod", 562 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 563 &sc->vte_int_rx_mod, 0, sysctl_hw_vte_int_mod, "I", 564 "vte RX interrupt moderation"); 565 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_tx_mod", 566 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 567 &sc->vte_int_tx_mod, 0, sysctl_hw_vte_int_mod, "I", 568 "vte TX interrupt moderation"); 569 /* Pull in device tunables. */ 570 sc->vte_int_rx_mod = VTE_IM_RX_BUNDLE_DEFAULT; 571 error = resource_int_value(device_get_name(sc->vte_dev), 572 device_get_unit(sc->vte_dev), "int_rx_mod", &sc->vte_int_rx_mod); 573 if (error == 0) { 574 if (sc->vte_int_rx_mod < VTE_IM_BUNDLE_MIN || 575 sc->vte_int_rx_mod > VTE_IM_BUNDLE_MAX) { 576 device_printf(sc->vte_dev, "int_rx_mod value out of " 577 "range; using default: %d\n", 578 VTE_IM_RX_BUNDLE_DEFAULT); 579 sc->vte_int_rx_mod = VTE_IM_RX_BUNDLE_DEFAULT; 580 } 581 } 582 583 sc->vte_int_tx_mod = VTE_IM_TX_BUNDLE_DEFAULT; 584 error = resource_int_value(device_get_name(sc->vte_dev), 585 device_get_unit(sc->vte_dev), "int_tx_mod", &sc->vte_int_tx_mod); 586 if (error == 0) { 587 if (sc->vte_int_tx_mod < VTE_IM_BUNDLE_MIN || 588 sc->vte_int_tx_mod > VTE_IM_BUNDLE_MAX) { 589 device_printf(sc->vte_dev, "int_tx_mod value out of " 590 "range; using default: %d\n", 591 VTE_IM_TX_BUNDLE_DEFAULT); 592 sc->vte_int_tx_mod = VTE_IM_TX_BUNDLE_DEFAULT; 593 } 594 } 595 596 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", 597 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "VTE statistics"); 598 parent = SYSCTL_CHILDREN(tree); 599 600 /* RX statistics. */ 601 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", 602 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "RX MAC statistics"); 603 child = SYSCTL_CHILDREN(tree); 604 VTE_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 605 &stats->rx_frames, "Good frames"); 606 VTE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 607 &stats->rx_bcast_frames, "Good broadcast frames"); 608 VTE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 609 &stats->rx_mcast_frames, "Good multicast frames"); 610 VTE_SYSCTL_STAT_ADD32(ctx, child, "runt", 611 &stats->rx_runts, "Too short frames"); 612 VTE_SYSCTL_STAT_ADD32(ctx, child, "crc_errs", 613 &stats->rx_crcerrs, "CRC errors"); 614 VTE_SYSCTL_STAT_ADD32(ctx, child, "long_frames", 615 &stats->rx_long_frames, 616 "Frames that have longer length than maximum packet length"); 617 VTE_SYSCTL_STAT_ADD32(ctx, child, "fifo_full", 618 &stats->rx_fifo_full, "FIFO full"); 619 VTE_SYSCTL_STAT_ADD32(ctx, child, "desc_unavail", 620 &stats->rx_desc_unavail, "Descriptor unavailable frames"); 621 VTE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 622 &stats->rx_pause_frames, "Pause control frames"); 623 624 /* TX statistics. */ 625 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", 626 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TX MAC statistics"); 627 child = SYSCTL_CHILDREN(tree); 628 VTE_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 629 &stats->tx_frames, "Good frames"); 630 VTE_SYSCTL_STAT_ADD32(ctx, child, "underruns", 631 &stats->tx_underruns, "FIFO underruns"); 632 VTE_SYSCTL_STAT_ADD32(ctx, child, "late_colls", 633 &stats->tx_late_colls, "Late collisions"); 634 VTE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 635 &stats->tx_pause_frames, "Pause control frames"); 636 } 637 638 #undef VTE_SYSCTL_STAT_ADD32 639 640 struct vte_dmamap_arg { 641 bus_addr_t vte_busaddr; 642 }; 643 644 static void 645 vte_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 646 { 647 struct vte_dmamap_arg *ctx; 648 649 if (error != 0) 650 return; 651 652 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 653 654 ctx = (struct vte_dmamap_arg *)arg; 655 ctx->vte_busaddr = segs[0].ds_addr; 656 } 657 658 static int 659 vte_dma_alloc(struct vte_softc *sc) 660 { 661 struct vte_txdesc *txd; 662 struct vte_rxdesc *rxd; 663 struct vte_dmamap_arg ctx; 664 int error, i; 665 666 /* Create parent DMA tag. */ 667 error = bus_dma_tag_create( 668 bus_get_dma_tag(sc->vte_dev), /* parent */ 669 1, 0, /* alignment, boundary */ 670 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 671 BUS_SPACE_MAXADDR, /* highaddr */ 672 NULL, NULL, /* filter, filterarg */ 673 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 674 0, /* nsegments */ 675 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 676 0, /* flags */ 677 NULL, NULL, /* lockfunc, lockarg */ 678 &sc->vte_cdata.vte_parent_tag); 679 if (error != 0) { 680 device_printf(sc->vte_dev, 681 "could not create parent DMA tag.\n"); 682 goto fail; 683 } 684 685 /* Create DMA tag for TX descriptor ring. */ 686 error = bus_dma_tag_create( 687 sc->vte_cdata.vte_parent_tag, /* parent */ 688 VTE_TX_RING_ALIGN, 0, /* alignment, boundary */ 689 BUS_SPACE_MAXADDR, /* lowaddr */ 690 BUS_SPACE_MAXADDR, /* highaddr */ 691 NULL, NULL, /* filter, filterarg */ 692 VTE_TX_RING_SZ, /* maxsize */ 693 1, /* nsegments */ 694 VTE_TX_RING_SZ, /* maxsegsize */ 695 0, /* flags */ 696 NULL, NULL, /* lockfunc, lockarg */ 697 &sc->vte_cdata.vte_tx_ring_tag); 698 if (error != 0) { 699 device_printf(sc->vte_dev, 700 "could not create TX ring DMA tag.\n"); 701 goto fail; 702 } 703 704 /* Create DMA tag for RX free descriptor ring. */ 705 error = bus_dma_tag_create( 706 sc->vte_cdata.vte_parent_tag, /* parent */ 707 VTE_RX_RING_ALIGN, 0, /* alignment, boundary */ 708 BUS_SPACE_MAXADDR, /* lowaddr */ 709 BUS_SPACE_MAXADDR, /* highaddr */ 710 NULL, NULL, /* filter, filterarg */ 711 VTE_RX_RING_SZ, /* maxsize */ 712 1, /* nsegments */ 713 VTE_RX_RING_SZ, /* maxsegsize */ 714 0, /* flags */ 715 NULL, NULL, /* lockfunc, lockarg */ 716 &sc->vte_cdata.vte_rx_ring_tag); 717 if (error != 0) { 718 device_printf(sc->vte_dev, 719 "could not create RX ring DMA tag.\n"); 720 goto fail; 721 } 722 723 /* Allocate DMA'able memory and load the DMA map for TX ring. */ 724 error = bus_dmamem_alloc(sc->vte_cdata.vte_tx_ring_tag, 725 (void **)&sc->vte_cdata.vte_tx_ring, 726 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 727 &sc->vte_cdata.vte_tx_ring_map); 728 if (error != 0) { 729 device_printf(sc->vte_dev, 730 "could not allocate DMA'able memory for TX ring.\n"); 731 goto fail; 732 } 733 ctx.vte_busaddr = 0; 734 error = bus_dmamap_load(sc->vte_cdata.vte_tx_ring_tag, 735 sc->vte_cdata.vte_tx_ring_map, sc->vte_cdata.vte_tx_ring, 736 VTE_TX_RING_SZ, vte_dmamap_cb, &ctx, 0); 737 if (error != 0 || ctx.vte_busaddr == 0) { 738 device_printf(sc->vte_dev, 739 "could not load DMA'able memory for TX ring.\n"); 740 goto fail; 741 } 742 sc->vte_cdata.vte_tx_ring_paddr = ctx.vte_busaddr; 743 744 /* Allocate DMA'able memory and load the DMA map for RX ring. */ 745 error = bus_dmamem_alloc(sc->vte_cdata.vte_rx_ring_tag, 746 (void **)&sc->vte_cdata.vte_rx_ring, 747 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 748 &sc->vte_cdata.vte_rx_ring_map); 749 if (error != 0) { 750 device_printf(sc->vte_dev, 751 "could not allocate DMA'able memory for RX ring.\n"); 752 goto fail; 753 } 754 ctx.vte_busaddr = 0; 755 error = bus_dmamap_load(sc->vte_cdata.vte_rx_ring_tag, 756 sc->vte_cdata.vte_rx_ring_map, sc->vte_cdata.vte_rx_ring, 757 VTE_RX_RING_SZ, vte_dmamap_cb, &ctx, 0); 758 if (error != 0 || ctx.vte_busaddr == 0) { 759 device_printf(sc->vte_dev, 760 "could not load DMA'able memory for RX ring.\n"); 761 goto fail; 762 } 763 sc->vte_cdata.vte_rx_ring_paddr = ctx.vte_busaddr; 764 765 /* Create TX buffer parent tag. */ 766 error = bus_dma_tag_create( 767 bus_get_dma_tag(sc->vte_dev), /* parent */ 768 1, 0, /* alignment, boundary */ 769 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 770 BUS_SPACE_MAXADDR, /* highaddr */ 771 NULL, NULL, /* filter, filterarg */ 772 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 773 0, /* nsegments */ 774 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 775 0, /* flags */ 776 NULL, NULL, /* lockfunc, lockarg */ 777 &sc->vte_cdata.vte_buffer_tag); 778 if (error != 0) { 779 device_printf(sc->vte_dev, 780 "could not create parent buffer DMA tag.\n"); 781 goto fail; 782 } 783 784 /* Create DMA tag for TX buffers. */ 785 error = bus_dma_tag_create( 786 sc->vte_cdata.vte_buffer_tag, /* parent */ 787 1, 0, /* alignment, boundary */ 788 BUS_SPACE_MAXADDR, /* lowaddr */ 789 BUS_SPACE_MAXADDR, /* highaddr */ 790 NULL, NULL, /* filter, filterarg */ 791 MCLBYTES, /* maxsize */ 792 1, /* nsegments */ 793 MCLBYTES, /* maxsegsize */ 794 0, /* flags */ 795 NULL, NULL, /* lockfunc, lockarg */ 796 &sc->vte_cdata.vte_tx_tag); 797 if (error != 0) { 798 device_printf(sc->vte_dev, "could not create TX DMA tag.\n"); 799 goto fail; 800 } 801 802 /* Create DMA tag for RX buffers. */ 803 error = bus_dma_tag_create( 804 sc->vte_cdata.vte_buffer_tag, /* parent */ 805 VTE_RX_BUF_ALIGN, 0, /* alignment, boundary */ 806 BUS_SPACE_MAXADDR, /* lowaddr */ 807 BUS_SPACE_MAXADDR, /* highaddr */ 808 NULL, NULL, /* filter, filterarg */ 809 MCLBYTES, /* maxsize */ 810 1, /* nsegments */ 811 MCLBYTES, /* maxsegsize */ 812 0, /* flags */ 813 NULL, NULL, /* lockfunc, lockarg */ 814 &sc->vte_cdata.vte_rx_tag); 815 if (error != 0) { 816 device_printf(sc->vte_dev, "could not create RX DMA tag.\n"); 817 goto fail; 818 } 819 /* Create DMA maps for TX buffers. */ 820 for (i = 0; i < VTE_TX_RING_CNT; i++) { 821 txd = &sc->vte_cdata.vte_txdesc[i]; 822 txd->tx_m = NULL; 823 txd->tx_dmamap = NULL; 824 error = bus_dmamap_create(sc->vte_cdata.vte_tx_tag, 0, 825 &txd->tx_dmamap); 826 if (error != 0) { 827 device_printf(sc->vte_dev, 828 "could not create TX dmamap.\n"); 829 goto fail; 830 } 831 } 832 /* Create DMA maps for RX buffers. */ 833 if ((error = bus_dmamap_create(sc->vte_cdata.vte_rx_tag, 0, 834 &sc->vte_cdata.vte_rx_sparemap)) != 0) { 835 device_printf(sc->vte_dev, 836 "could not create spare RX dmamap.\n"); 837 goto fail; 838 } 839 for (i = 0; i < VTE_RX_RING_CNT; i++) { 840 rxd = &sc->vte_cdata.vte_rxdesc[i]; 841 rxd->rx_m = NULL; 842 rxd->rx_dmamap = NULL; 843 error = bus_dmamap_create(sc->vte_cdata.vte_rx_tag, 0, 844 &rxd->rx_dmamap); 845 if (error != 0) { 846 device_printf(sc->vte_dev, 847 "could not create RX dmamap.\n"); 848 goto fail; 849 } 850 } 851 852 fail: 853 return (error); 854 } 855 856 static void 857 vte_dma_free(struct vte_softc *sc) 858 { 859 struct vte_txdesc *txd; 860 struct vte_rxdesc *rxd; 861 int i; 862 863 /* TX buffers. */ 864 if (sc->vte_cdata.vte_tx_tag != NULL) { 865 for (i = 0; i < VTE_TX_RING_CNT; i++) { 866 txd = &sc->vte_cdata.vte_txdesc[i]; 867 if (txd->tx_dmamap != NULL) { 868 bus_dmamap_destroy(sc->vte_cdata.vte_tx_tag, 869 txd->tx_dmamap); 870 txd->tx_dmamap = NULL; 871 } 872 } 873 bus_dma_tag_destroy(sc->vte_cdata.vte_tx_tag); 874 sc->vte_cdata.vte_tx_tag = NULL; 875 } 876 /* RX buffers */ 877 if (sc->vte_cdata.vte_rx_tag != NULL) { 878 for (i = 0; i < VTE_RX_RING_CNT; i++) { 879 rxd = &sc->vte_cdata.vte_rxdesc[i]; 880 if (rxd->rx_dmamap != NULL) { 881 bus_dmamap_destroy(sc->vte_cdata.vte_rx_tag, 882 rxd->rx_dmamap); 883 rxd->rx_dmamap = NULL; 884 } 885 } 886 if (sc->vte_cdata.vte_rx_sparemap != NULL) { 887 bus_dmamap_destroy(sc->vte_cdata.vte_rx_tag, 888 sc->vte_cdata.vte_rx_sparemap); 889 sc->vte_cdata.vte_rx_sparemap = NULL; 890 } 891 bus_dma_tag_destroy(sc->vte_cdata.vte_rx_tag); 892 sc->vte_cdata.vte_rx_tag = NULL; 893 } 894 /* TX descriptor ring. */ 895 if (sc->vte_cdata.vte_tx_ring_tag != NULL) { 896 if (sc->vte_cdata.vte_tx_ring_paddr != 0) 897 bus_dmamap_unload(sc->vte_cdata.vte_tx_ring_tag, 898 sc->vte_cdata.vte_tx_ring_map); 899 if (sc->vte_cdata.vte_tx_ring != NULL) 900 bus_dmamem_free(sc->vte_cdata.vte_tx_ring_tag, 901 sc->vte_cdata.vte_tx_ring, 902 sc->vte_cdata.vte_tx_ring_map); 903 sc->vte_cdata.vte_tx_ring = NULL; 904 sc->vte_cdata.vte_tx_ring_paddr = 0; 905 bus_dma_tag_destroy(sc->vte_cdata.vte_tx_ring_tag); 906 sc->vte_cdata.vte_tx_ring_tag = NULL; 907 } 908 /* RX ring. */ 909 if (sc->vte_cdata.vte_rx_ring_tag != NULL) { 910 if (sc->vte_cdata.vte_rx_ring_paddr != 0) 911 bus_dmamap_unload(sc->vte_cdata.vte_rx_ring_tag, 912 sc->vte_cdata.vte_rx_ring_map); 913 if (sc->vte_cdata.vte_rx_ring != NULL) 914 bus_dmamem_free(sc->vte_cdata.vte_rx_ring_tag, 915 sc->vte_cdata.vte_rx_ring, 916 sc->vte_cdata.vte_rx_ring_map); 917 sc->vte_cdata.vte_rx_ring = NULL; 918 sc->vte_cdata.vte_rx_ring_paddr = 0; 919 bus_dma_tag_destroy(sc->vte_cdata.vte_rx_ring_tag); 920 sc->vte_cdata.vte_rx_ring_tag = NULL; 921 } 922 if (sc->vte_cdata.vte_buffer_tag != NULL) { 923 bus_dma_tag_destroy(sc->vte_cdata.vte_buffer_tag); 924 sc->vte_cdata.vte_buffer_tag = NULL; 925 } 926 if (sc->vte_cdata.vte_parent_tag != NULL) { 927 bus_dma_tag_destroy(sc->vte_cdata.vte_parent_tag); 928 sc->vte_cdata.vte_parent_tag = NULL; 929 } 930 } 931 932 static int 933 vte_shutdown(device_t dev) 934 { 935 936 return (vte_suspend(dev)); 937 } 938 939 static int 940 vte_suspend(device_t dev) 941 { 942 struct vte_softc *sc; 943 if_t ifp; 944 945 sc = device_get_softc(dev); 946 947 VTE_LOCK(sc); 948 ifp = sc->vte_ifp; 949 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 950 vte_stop(sc); 951 VTE_UNLOCK(sc); 952 953 return (0); 954 } 955 956 static int 957 vte_resume(device_t dev) 958 { 959 struct vte_softc *sc; 960 if_t ifp; 961 962 sc = device_get_softc(dev); 963 964 VTE_LOCK(sc); 965 ifp = sc->vte_ifp; 966 if ((if_getflags(ifp) & IFF_UP) != 0) { 967 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 968 vte_init_locked(sc); 969 } 970 VTE_UNLOCK(sc); 971 972 return (0); 973 } 974 975 static struct vte_txdesc * 976 vte_encap(struct vte_softc *sc, struct mbuf **m_head) 977 { 978 struct vte_txdesc *txd; 979 struct mbuf *m, *n; 980 bus_dma_segment_t txsegs[1]; 981 int copy, error, nsegs, padlen; 982 983 VTE_LOCK_ASSERT(sc); 984 985 M_ASSERTPKTHDR((*m_head)); 986 987 txd = &sc->vte_cdata.vte_txdesc[sc->vte_cdata.vte_tx_prod]; 988 m = *m_head; 989 /* 990 * Controller doesn't auto-pad, so we have to make sure pad 991 * short frames out to the minimum frame length. 992 */ 993 if (m->m_pkthdr.len < VTE_MIN_FRAMELEN) 994 padlen = VTE_MIN_FRAMELEN - m->m_pkthdr.len; 995 else 996 padlen = 0; 997 998 /* 999 * Controller does not support multi-fragmented TX buffers. 1000 * Controller spends most of its TX processing time in 1001 * de-fragmenting TX buffers. Either faster CPU or more 1002 * advanced controller DMA engine is required to speed up 1003 * TX path processing. 1004 * To mitigate the de-fragmenting issue, perform deep copy 1005 * from fragmented mbuf chains to a pre-allocated mbuf 1006 * cluster with extra cost of kernel memory. For frames 1007 * that is composed of single TX buffer, the deep copy is 1008 * bypassed. 1009 */ 1010 if (tx_deep_copy != 0) { 1011 copy = 0; 1012 if (m->m_next != NULL) 1013 copy++; 1014 if (padlen > 0 && (M_WRITABLE(m) == 0 || 1015 padlen > M_TRAILINGSPACE(m))) 1016 copy++; 1017 if (copy != 0) { 1018 /* Avoid expensive m_defrag(9) and do deep copy. */ 1019 n = sc->vte_cdata.vte_txmbufs[sc->vte_cdata.vte_tx_prod]; 1020 m_copydata(m, 0, m->m_pkthdr.len, mtod(n, char *)); 1021 n->m_pkthdr.len = m->m_pkthdr.len; 1022 n->m_len = m->m_pkthdr.len; 1023 m = n; 1024 txd->tx_flags |= VTE_TXMBUF; 1025 } 1026 1027 if (padlen > 0) { 1028 /* Zero out the bytes in the pad area. */ 1029 bzero(mtod(m, char *) + m->m_pkthdr.len, padlen); 1030 m->m_pkthdr.len += padlen; 1031 m->m_len = m->m_pkthdr.len; 1032 } 1033 } else { 1034 if (M_WRITABLE(m) == 0) { 1035 if (m->m_next != NULL || padlen > 0) { 1036 /* Get a writable copy. */ 1037 m = m_dup(*m_head, M_NOWAIT); 1038 /* Release original mbuf chains. */ 1039 m_freem(*m_head); 1040 if (m == NULL) { 1041 *m_head = NULL; 1042 return (NULL); 1043 } 1044 *m_head = m; 1045 } 1046 } 1047 1048 if (m->m_next != NULL) { 1049 m = m_defrag(*m_head, M_NOWAIT); 1050 if (m == NULL) { 1051 m_freem(*m_head); 1052 *m_head = NULL; 1053 return (NULL); 1054 } 1055 *m_head = m; 1056 } 1057 1058 if (padlen > 0) { 1059 if (M_TRAILINGSPACE(m) < padlen) { 1060 m = m_defrag(*m_head, M_NOWAIT); 1061 if (m == NULL) { 1062 m_freem(*m_head); 1063 *m_head = NULL; 1064 return (NULL); 1065 } 1066 *m_head = m; 1067 } 1068 /* Zero out the bytes in the pad area. */ 1069 bzero(mtod(m, char *) + m->m_pkthdr.len, padlen); 1070 m->m_pkthdr.len += padlen; 1071 m->m_len = m->m_pkthdr.len; 1072 } 1073 } 1074 1075 error = bus_dmamap_load_mbuf_sg(sc->vte_cdata.vte_tx_tag, 1076 txd->tx_dmamap, m, txsegs, &nsegs, 0); 1077 if (error != 0) { 1078 txd->tx_flags &= ~VTE_TXMBUF; 1079 return (NULL); 1080 } 1081 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1082 bus_dmamap_sync(sc->vte_cdata.vte_tx_tag, txd->tx_dmamap, 1083 BUS_DMASYNC_PREWRITE); 1084 1085 txd->tx_desc->dtlen = htole16(VTE_TX_LEN(txsegs[0].ds_len)); 1086 txd->tx_desc->dtbp = htole32(txsegs[0].ds_addr); 1087 sc->vte_cdata.vte_tx_cnt++; 1088 /* Update producer index. */ 1089 VTE_DESC_INC(sc->vte_cdata.vte_tx_prod, VTE_TX_RING_CNT); 1090 1091 /* Finally hand over ownership to controller. */ 1092 txd->tx_desc->dtst = htole16(VTE_DTST_TX_OWN); 1093 txd->tx_m = m; 1094 1095 return (txd); 1096 } 1097 1098 static void 1099 vte_start(if_t ifp) 1100 { 1101 struct vte_softc *sc; 1102 1103 sc = if_getsoftc(ifp); 1104 VTE_LOCK(sc); 1105 vte_start_locked(sc); 1106 VTE_UNLOCK(sc); 1107 } 1108 1109 static void 1110 vte_start_locked(struct vte_softc *sc) 1111 { 1112 if_t ifp; 1113 struct vte_txdesc *txd; 1114 struct mbuf *m_head; 1115 int enq; 1116 1117 ifp = sc->vte_ifp; 1118 1119 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1120 IFF_DRV_RUNNING || (sc->vte_flags & VTE_FLAG_LINK) == 0) 1121 return; 1122 1123 for (enq = 0; !if_sendq_empty(ifp); ) { 1124 /* Reserve one free TX descriptor. */ 1125 if (sc->vte_cdata.vte_tx_cnt >= VTE_TX_RING_CNT - 1) { 1126 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 1127 break; 1128 } 1129 m_head = if_dequeue(ifp); 1130 if (m_head == NULL) 1131 break; 1132 /* 1133 * Pack the data into the transmit ring. If we 1134 * don't have room, set the OACTIVE flag and wait 1135 * for the NIC to drain the ring. 1136 */ 1137 if ((txd = vte_encap(sc, &m_head)) == NULL) { 1138 if (m_head != NULL) 1139 if_sendq_prepend(ifp, m_head); 1140 break; 1141 } 1142 1143 enq++; 1144 /* 1145 * If there's a BPF listener, bounce a copy of this frame 1146 * to him. 1147 */ 1148 ETHER_BPF_MTAP(ifp, m_head); 1149 /* Free consumed TX frame. */ 1150 if ((txd->tx_flags & VTE_TXMBUF) != 0) 1151 m_freem(m_head); 1152 } 1153 1154 if (enq > 0) { 1155 bus_dmamap_sync(sc->vte_cdata.vte_tx_ring_tag, 1156 sc->vte_cdata.vte_tx_ring_map, BUS_DMASYNC_PREREAD | 1157 BUS_DMASYNC_PREWRITE); 1158 CSR_WRITE_2(sc, VTE_TX_POLL, TX_POLL_START); 1159 sc->vte_watchdog_timer = VTE_TX_TIMEOUT; 1160 } 1161 } 1162 1163 static void 1164 vte_watchdog(struct vte_softc *sc) 1165 { 1166 if_t ifp; 1167 1168 VTE_LOCK_ASSERT(sc); 1169 1170 if (sc->vte_watchdog_timer == 0 || --sc->vte_watchdog_timer) 1171 return; 1172 1173 ifp = sc->vte_ifp; 1174 if_printf(sc->vte_ifp, "watchdog timeout -- resetting\n"); 1175 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1176 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1177 vte_init_locked(sc); 1178 if (!if_sendq_empty(ifp)) 1179 vte_start_locked(sc); 1180 } 1181 1182 static int 1183 vte_ioctl(if_t ifp, u_long cmd, caddr_t data) 1184 { 1185 struct vte_softc *sc; 1186 struct ifreq *ifr; 1187 struct mii_data *mii; 1188 int error; 1189 1190 sc = if_getsoftc(ifp); 1191 ifr = (struct ifreq *)data; 1192 error = 0; 1193 switch (cmd) { 1194 case SIOCSIFFLAGS: 1195 VTE_LOCK(sc); 1196 if ((if_getflags(ifp) & IFF_UP) != 0) { 1197 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0 && 1198 ((if_getflags(ifp) ^ sc->vte_if_flags) & 1199 (IFF_PROMISC | IFF_ALLMULTI)) != 0) 1200 vte_rxfilter(sc); 1201 else 1202 vte_init_locked(sc); 1203 } else if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 1204 vte_stop(sc); 1205 sc->vte_if_flags = if_getflags(ifp); 1206 VTE_UNLOCK(sc); 1207 break; 1208 case SIOCADDMULTI: 1209 case SIOCDELMULTI: 1210 VTE_LOCK(sc); 1211 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 1212 vte_rxfilter(sc); 1213 VTE_UNLOCK(sc); 1214 break; 1215 case SIOCSIFMEDIA: 1216 case SIOCGIFMEDIA: 1217 mii = device_get_softc(sc->vte_miibus); 1218 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1219 break; 1220 default: 1221 error = ether_ioctl(ifp, cmd, data); 1222 break; 1223 } 1224 1225 return (error); 1226 } 1227 1228 static void 1229 vte_mac_config(struct vte_softc *sc) 1230 { 1231 struct mii_data *mii; 1232 uint16_t mcr; 1233 1234 VTE_LOCK_ASSERT(sc); 1235 1236 mii = device_get_softc(sc->vte_miibus); 1237 mcr = CSR_READ_2(sc, VTE_MCR0); 1238 mcr &= ~(MCR0_FC_ENB | MCR0_FULL_DUPLEX); 1239 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 1240 mcr |= MCR0_FULL_DUPLEX; 1241 #ifdef notyet 1242 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 1243 mcr |= MCR0_FC_ENB; 1244 /* 1245 * The data sheet is not clear whether the controller 1246 * honors received pause frames or not. The is no 1247 * separate control bit for RX pause frame so just 1248 * enable MCR0_FC_ENB bit. 1249 */ 1250 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 1251 mcr |= MCR0_FC_ENB; 1252 #endif 1253 } 1254 CSR_WRITE_2(sc, VTE_MCR0, mcr); 1255 } 1256 1257 static void 1258 vte_stats_clear(struct vte_softc *sc) 1259 { 1260 1261 /* Reading counter registers clears its contents. */ 1262 CSR_READ_2(sc, VTE_CNT_RX_DONE); 1263 CSR_READ_2(sc, VTE_CNT_MECNT0); 1264 CSR_READ_2(sc, VTE_CNT_MECNT1); 1265 CSR_READ_2(sc, VTE_CNT_MECNT2); 1266 CSR_READ_2(sc, VTE_CNT_MECNT3); 1267 CSR_READ_2(sc, VTE_CNT_TX_DONE); 1268 CSR_READ_2(sc, VTE_CNT_MECNT4); 1269 CSR_READ_2(sc, VTE_CNT_PAUSE); 1270 } 1271 1272 static void 1273 vte_stats_update(struct vte_softc *sc) 1274 { 1275 struct vte_hw_stats *stat; 1276 uint16_t value; 1277 1278 VTE_LOCK_ASSERT(sc); 1279 1280 stat = &sc->vte_stats; 1281 1282 CSR_READ_2(sc, VTE_MECISR); 1283 /* RX stats. */ 1284 stat->rx_frames += CSR_READ_2(sc, VTE_CNT_RX_DONE); 1285 value = CSR_READ_2(sc, VTE_CNT_MECNT0); 1286 stat->rx_bcast_frames += (value >> 8); 1287 stat->rx_mcast_frames += (value & 0xFF); 1288 value = CSR_READ_2(sc, VTE_CNT_MECNT1); 1289 stat->rx_runts += (value >> 8); 1290 stat->rx_crcerrs += (value & 0xFF); 1291 value = CSR_READ_2(sc, VTE_CNT_MECNT2); 1292 stat->rx_long_frames += (value & 0xFF); 1293 value = CSR_READ_2(sc, VTE_CNT_MECNT3); 1294 stat->rx_fifo_full += (value >> 8); 1295 stat->rx_desc_unavail += (value & 0xFF); 1296 1297 /* TX stats. */ 1298 stat->tx_frames += CSR_READ_2(sc, VTE_CNT_TX_DONE); 1299 value = CSR_READ_2(sc, VTE_CNT_MECNT4); 1300 stat->tx_underruns += (value >> 8); 1301 stat->tx_late_colls += (value & 0xFF); 1302 1303 value = CSR_READ_2(sc, VTE_CNT_PAUSE); 1304 stat->tx_pause_frames += (value >> 8); 1305 stat->rx_pause_frames += (value & 0xFF); 1306 } 1307 1308 static uint64_t 1309 vte_get_counter(if_t ifp, ift_counter cnt) 1310 { 1311 struct vte_softc *sc; 1312 struct vte_hw_stats *stat; 1313 1314 sc = if_getsoftc(ifp); 1315 stat = &sc->vte_stats; 1316 1317 switch (cnt) { 1318 case IFCOUNTER_OPACKETS: 1319 return (stat->tx_frames); 1320 case IFCOUNTER_COLLISIONS: 1321 return (stat->tx_late_colls); 1322 case IFCOUNTER_OERRORS: 1323 return (stat->tx_late_colls + stat->tx_underruns); 1324 case IFCOUNTER_IPACKETS: 1325 return (stat->rx_frames); 1326 case IFCOUNTER_IERRORS: 1327 return (stat->rx_crcerrs + stat->rx_runts + 1328 stat->rx_long_frames + stat->rx_fifo_full); 1329 default: 1330 return (if_get_counter_default(ifp, cnt)); 1331 } 1332 } 1333 1334 static void 1335 vte_intr(void *arg) 1336 { 1337 struct vte_softc *sc; 1338 if_t ifp; 1339 uint16_t status; 1340 int n; 1341 1342 sc = (struct vte_softc *)arg; 1343 VTE_LOCK(sc); 1344 1345 ifp = sc->vte_ifp; 1346 /* Reading VTE_MISR acknowledges interrupts. */ 1347 status = CSR_READ_2(sc, VTE_MISR); 1348 if ((status & VTE_INTRS) == 0) { 1349 /* Not ours. */ 1350 VTE_UNLOCK(sc); 1351 return; 1352 } 1353 1354 /* Disable interrupts. */ 1355 CSR_WRITE_2(sc, VTE_MIER, 0); 1356 for (n = 8; (status & VTE_INTRS) != 0;) { 1357 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 1358 break; 1359 if ((status & (MISR_RX_DONE | MISR_RX_DESC_UNAVAIL | 1360 MISR_RX_FIFO_FULL)) != 0) 1361 vte_rxeof(sc); 1362 if ((status & MISR_TX_DONE) != 0) 1363 vte_txeof(sc); 1364 if ((status & MISR_EVENT_CNT_OFLOW) != 0) 1365 vte_stats_update(sc); 1366 if (!if_sendq_empty(ifp)) 1367 vte_start_locked(sc); 1368 if (--n > 0) 1369 status = CSR_READ_2(sc, VTE_MISR); 1370 else 1371 break; 1372 } 1373 1374 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 1375 /* Re-enable interrupts. */ 1376 CSR_WRITE_2(sc, VTE_MIER, VTE_INTRS); 1377 } 1378 VTE_UNLOCK(sc); 1379 } 1380 1381 static void 1382 vte_txeof(struct vte_softc *sc) 1383 { 1384 if_t ifp; 1385 struct vte_txdesc *txd; 1386 uint16_t status; 1387 int cons, prog; 1388 1389 VTE_LOCK_ASSERT(sc); 1390 1391 ifp = sc->vte_ifp; 1392 1393 if (sc->vte_cdata.vte_tx_cnt == 0) 1394 return; 1395 bus_dmamap_sync(sc->vte_cdata.vte_tx_ring_tag, 1396 sc->vte_cdata.vte_tx_ring_map, BUS_DMASYNC_POSTREAD | 1397 BUS_DMASYNC_POSTWRITE); 1398 cons = sc->vte_cdata.vte_tx_cons; 1399 /* 1400 * Go through our TX list and free mbufs for those 1401 * frames which have been transmitted. 1402 */ 1403 for (prog = 0; sc->vte_cdata.vte_tx_cnt > 0; prog++) { 1404 txd = &sc->vte_cdata.vte_txdesc[cons]; 1405 status = le16toh(txd->tx_desc->dtst); 1406 if ((status & VTE_DTST_TX_OWN) != 0) 1407 break; 1408 sc->vte_cdata.vte_tx_cnt--; 1409 /* Reclaim transmitted mbufs. */ 1410 bus_dmamap_sync(sc->vte_cdata.vte_tx_tag, txd->tx_dmamap, 1411 BUS_DMASYNC_POSTWRITE); 1412 bus_dmamap_unload(sc->vte_cdata.vte_tx_tag, txd->tx_dmamap); 1413 if ((txd->tx_flags & VTE_TXMBUF) == 0) 1414 m_freem(txd->tx_m); 1415 txd->tx_flags &= ~VTE_TXMBUF; 1416 txd->tx_m = NULL; 1417 prog++; 1418 VTE_DESC_INC(cons, VTE_TX_RING_CNT); 1419 } 1420 1421 if (prog > 0) { 1422 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 1423 sc->vte_cdata.vte_tx_cons = cons; 1424 /* 1425 * Unarm watchdog timer only when there is no pending 1426 * frames in TX queue. 1427 */ 1428 if (sc->vte_cdata.vte_tx_cnt == 0) 1429 sc->vte_watchdog_timer = 0; 1430 } 1431 } 1432 1433 static int 1434 vte_newbuf(struct vte_softc *sc, struct vte_rxdesc *rxd) 1435 { 1436 struct mbuf *m; 1437 bus_dma_segment_t segs[1]; 1438 bus_dmamap_t map; 1439 int nsegs; 1440 1441 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1442 if (m == NULL) 1443 return (ENOBUFS); 1444 m->m_len = m->m_pkthdr.len = MCLBYTES; 1445 m_adj(m, sizeof(uint32_t)); 1446 1447 if (bus_dmamap_load_mbuf_sg(sc->vte_cdata.vte_rx_tag, 1448 sc->vte_cdata.vte_rx_sparemap, m, segs, &nsegs, 0) != 0) { 1449 m_freem(m); 1450 return (ENOBUFS); 1451 } 1452 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1453 1454 if (rxd->rx_m != NULL) { 1455 bus_dmamap_sync(sc->vte_cdata.vte_rx_tag, rxd->rx_dmamap, 1456 BUS_DMASYNC_POSTREAD); 1457 bus_dmamap_unload(sc->vte_cdata.vte_rx_tag, rxd->rx_dmamap); 1458 } 1459 map = rxd->rx_dmamap; 1460 rxd->rx_dmamap = sc->vte_cdata.vte_rx_sparemap; 1461 sc->vte_cdata.vte_rx_sparemap = map; 1462 bus_dmamap_sync(sc->vte_cdata.vte_rx_tag, rxd->rx_dmamap, 1463 BUS_DMASYNC_PREREAD); 1464 rxd->rx_m = m; 1465 rxd->rx_desc->drbp = htole32(segs[0].ds_addr); 1466 rxd->rx_desc->drlen = htole16(VTE_RX_LEN(segs[0].ds_len)); 1467 rxd->rx_desc->drst = htole16(VTE_DRST_RX_OWN); 1468 1469 return (0); 1470 } 1471 1472 /* 1473 * It's not supposed to see this controller on strict-alignment 1474 * architectures but make it work for completeness. 1475 */ 1476 #ifndef __NO_STRICT_ALIGNMENT 1477 static struct mbuf * 1478 vte_fixup_rx(if_t ifp, struct mbuf *m) 1479 { 1480 uint16_t *src, *dst; 1481 int i; 1482 1483 src = mtod(m, uint16_t *); 1484 dst = src - 1; 1485 1486 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1487 *dst++ = *src++; 1488 m->m_data -= ETHER_ALIGN; 1489 return (m); 1490 } 1491 #endif 1492 1493 static void 1494 vte_rxeof(struct vte_softc *sc) 1495 { 1496 if_t ifp; 1497 struct vte_rxdesc *rxd; 1498 struct mbuf *m; 1499 uint16_t status, total_len; 1500 int cons, prog; 1501 1502 bus_dmamap_sync(sc->vte_cdata.vte_rx_ring_tag, 1503 sc->vte_cdata.vte_rx_ring_map, BUS_DMASYNC_POSTREAD | 1504 BUS_DMASYNC_POSTWRITE); 1505 cons = sc->vte_cdata.vte_rx_cons; 1506 ifp = sc->vte_ifp; 1507 for (prog = 0; (if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0; prog++, 1508 VTE_DESC_INC(cons, VTE_RX_RING_CNT)) { 1509 rxd = &sc->vte_cdata.vte_rxdesc[cons]; 1510 status = le16toh(rxd->rx_desc->drst); 1511 if ((status & VTE_DRST_RX_OWN) != 0) 1512 break; 1513 total_len = VTE_RX_LEN(le16toh(rxd->rx_desc->drlen)); 1514 m = rxd->rx_m; 1515 if ((status & VTE_DRST_RX_OK) == 0) { 1516 /* Discard errored frame. */ 1517 rxd->rx_desc->drlen = 1518 htole16(MCLBYTES - sizeof(uint32_t)); 1519 rxd->rx_desc->drst = htole16(VTE_DRST_RX_OWN); 1520 continue; 1521 } 1522 if (vte_newbuf(sc, rxd) != 0) { 1523 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 1524 rxd->rx_desc->drlen = 1525 htole16(MCLBYTES - sizeof(uint32_t)); 1526 rxd->rx_desc->drst = htole16(VTE_DRST_RX_OWN); 1527 continue; 1528 } 1529 1530 /* 1531 * It seems there is no way to strip FCS bytes. 1532 */ 1533 m->m_pkthdr.len = m->m_len = total_len - ETHER_CRC_LEN; 1534 m->m_pkthdr.rcvif = ifp; 1535 #ifndef __NO_STRICT_ALIGNMENT 1536 vte_fixup_rx(ifp, m); 1537 #endif 1538 VTE_UNLOCK(sc); 1539 if_input(ifp, m); 1540 VTE_LOCK(sc); 1541 } 1542 1543 if (prog > 0) { 1544 /* Update the consumer index. */ 1545 sc->vte_cdata.vte_rx_cons = cons; 1546 /* 1547 * Sync updated RX descriptors such that controller see 1548 * modified RX buffer addresses. 1549 */ 1550 bus_dmamap_sync(sc->vte_cdata.vte_rx_ring_tag, 1551 sc->vte_cdata.vte_rx_ring_map, 1552 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1553 #ifdef notyet 1554 /* 1555 * Update residue counter. Controller does not 1556 * keep track of number of available RX descriptors 1557 * such that driver should have to update VTE_MRDCR 1558 * to make controller know how many free RX 1559 * descriptors were added to controller. This is 1560 * a similar mechanism used in VIA velocity 1561 * controllers and it indicates controller just 1562 * polls OWN bit of current RX descriptor pointer. 1563 * A couple of severe issues were seen on sample 1564 * board where the controller continuously emits TX 1565 * pause frames once RX pause threshold crossed. 1566 * Once triggered it never recovered form that 1567 * state, I couldn't find a way to make it back to 1568 * work at least. This issue effectively 1569 * disconnected the system from network. Also, the 1570 * controller used 00:00:00:00:00:00 as source 1571 * station address of TX pause frame. Probably this 1572 * is one of reason why vendor recommends not to 1573 * enable flow control on R6040 controller. 1574 */ 1575 CSR_WRITE_2(sc, VTE_MRDCR, prog | 1576 (((VTE_RX_RING_CNT * 2) / 10) << 1577 VTE_MRDCR_RX_PAUSE_THRESH_SHIFT)); 1578 #endif 1579 } 1580 } 1581 1582 static void 1583 vte_tick(void *arg) 1584 { 1585 struct vte_softc *sc; 1586 struct mii_data *mii; 1587 1588 sc = (struct vte_softc *)arg; 1589 1590 VTE_LOCK_ASSERT(sc); 1591 1592 mii = device_get_softc(sc->vte_miibus); 1593 mii_tick(mii); 1594 vte_stats_update(sc); 1595 vte_txeof(sc); 1596 vte_watchdog(sc); 1597 callout_reset(&sc->vte_tick_ch, hz, vte_tick, sc); 1598 } 1599 1600 static void 1601 vte_reset(struct vte_softc *sc) 1602 { 1603 uint16_t mcr, mdcsc; 1604 int i; 1605 1606 mdcsc = CSR_READ_2(sc, VTE_MDCSC); 1607 mcr = CSR_READ_2(sc, VTE_MCR1); 1608 CSR_WRITE_2(sc, VTE_MCR1, mcr | MCR1_MAC_RESET); 1609 for (i = VTE_RESET_TIMEOUT; i > 0; i--) { 1610 DELAY(10); 1611 if ((CSR_READ_2(sc, VTE_MCR1) & MCR1_MAC_RESET) == 0) 1612 break; 1613 } 1614 if (i == 0) 1615 device_printf(sc->vte_dev, "reset timeout(0x%04x)!\n", mcr); 1616 /* 1617 * Follow the guide of vendor recommended way to reset MAC. 1618 * Vendor confirms relying on MCR1_MAC_RESET of VTE_MCR1 is 1619 * not reliable so manually reset internal state machine. 1620 */ 1621 CSR_WRITE_2(sc, VTE_MACSM, 0x0002); 1622 CSR_WRITE_2(sc, VTE_MACSM, 0); 1623 DELAY(5000); 1624 1625 /* 1626 * On some SoCs (like Vortex86DX3) MDC speed control register value 1627 * needs to be restored to original value instead of default one, 1628 * otherwise some PHY registers may fail to be read. 1629 */ 1630 if (mdcsc != MDCSC_DEFAULT) 1631 CSR_WRITE_2(sc, VTE_MDCSC, mdcsc); 1632 } 1633 1634 static void 1635 vte_init(void *xsc) 1636 { 1637 struct vte_softc *sc; 1638 1639 sc = (struct vte_softc *)xsc; 1640 VTE_LOCK(sc); 1641 vte_init_locked(sc); 1642 VTE_UNLOCK(sc); 1643 } 1644 1645 static void 1646 vte_init_locked(struct vte_softc *sc) 1647 { 1648 if_t ifp; 1649 bus_addr_t paddr; 1650 uint8_t *eaddr; 1651 1652 VTE_LOCK_ASSERT(sc); 1653 1654 ifp = sc->vte_ifp; 1655 1656 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 1657 return; 1658 /* 1659 * Cancel any pending I/O. 1660 */ 1661 vte_stop(sc); 1662 /* 1663 * Reset the chip to a known state. 1664 */ 1665 vte_reset(sc); 1666 1667 /* Initialize RX descriptors. */ 1668 if (vte_init_rx_ring(sc) != 0) { 1669 device_printf(sc->vte_dev, "no memory for RX buffers.\n"); 1670 vte_stop(sc); 1671 return; 1672 } 1673 if (vte_init_tx_ring(sc) != 0) { 1674 device_printf(sc->vte_dev, "no memory for TX buffers.\n"); 1675 vte_stop(sc); 1676 return; 1677 } 1678 1679 /* 1680 * Reprogram the station address. Controller supports up 1681 * to 4 different station addresses so driver programs the 1682 * first station address as its own ethernet address and 1683 * configure the remaining three addresses as perfect 1684 * multicast addresses. 1685 */ 1686 eaddr = if_getlladdr(sc->vte_ifp); 1687 CSR_WRITE_2(sc, VTE_MID0L, eaddr[1] << 8 | eaddr[0]); 1688 CSR_WRITE_2(sc, VTE_MID0M, eaddr[3] << 8 | eaddr[2]); 1689 CSR_WRITE_2(sc, VTE_MID0H, eaddr[5] << 8 | eaddr[4]); 1690 1691 /* Set TX descriptor base addresses. */ 1692 paddr = sc->vte_cdata.vte_tx_ring_paddr; 1693 CSR_WRITE_2(sc, VTE_MTDSA1, paddr >> 16); 1694 CSR_WRITE_2(sc, VTE_MTDSA0, paddr & 0xFFFF); 1695 /* Set RX descriptor base addresses. */ 1696 paddr = sc->vte_cdata.vte_rx_ring_paddr; 1697 CSR_WRITE_2(sc, VTE_MRDSA1, paddr >> 16); 1698 CSR_WRITE_2(sc, VTE_MRDSA0, paddr & 0xFFFF); 1699 /* 1700 * Initialize RX descriptor residue counter and set RX 1701 * pause threshold to 20% of available RX descriptors. 1702 * See comments on vte_rxeof() for details on flow control 1703 * issues. 1704 */ 1705 CSR_WRITE_2(sc, VTE_MRDCR, (VTE_RX_RING_CNT & VTE_MRDCR_RESIDUE_MASK) | 1706 (((VTE_RX_RING_CNT * 2) / 10) << VTE_MRDCR_RX_PAUSE_THRESH_SHIFT)); 1707 1708 /* 1709 * Always use maximum frame size that controller can 1710 * support. Otherwise received frames that has longer 1711 * frame length than vte(4) MTU would be silently dropped 1712 * in controller. This would break path-MTU discovery as 1713 * sender wouldn't get any responses from receiver. The 1714 * RX buffer size should be multiple of 4. 1715 * Note, jumbo frames are silently ignored by controller 1716 * and even MAC counters do not detect them. 1717 */ 1718 CSR_WRITE_2(sc, VTE_MRBSR, VTE_RX_BUF_SIZE_MAX); 1719 1720 /* Configure FIFO. */ 1721 CSR_WRITE_2(sc, VTE_MBCR, MBCR_FIFO_XFER_LENGTH_16 | 1722 MBCR_TX_FIFO_THRESH_64 | MBCR_RX_FIFO_THRESH_16 | 1723 MBCR_SDRAM_BUS_REQ_TIMER_DEFAULT); 1724 1725 /* 1726 * Configure TX/RX MACs. Actual resolved duplex and flow 1727 * control configuration is done after detecting a valid 1728 * link. Note, we don't generate early interrupt here 1729 * as well since FreeBSD does not have interrupt latency 1730 * problems like Windows. 1731 */ 1732 CSR_WRITE_2(sc, VTE_MCR0, MCR0_ACCPT_LONG_PKT); 1733 /* 1734 * We manually keep track of PHY status changes to 1735 * configure resolved duplex and flow control since only 1736 * duplex configuration can be automatically reflected to 1737 * MCR0. 1738 */ 1739 CSR_WRITE_2(sc, VTE_MCR1, MCR1_PKT_LENGTH_1537 | 1740 MCR1_EXCESS_COL_RETRY_16); 1741 1742 /* Initialize RX filter. */ 1743 vte_rxfilter(sc); 1744 1745 /* Disable TX/RX interrupt moderation control. */ 1746 CSR_WRITE_2(sc, VTE_MRICR, 0); 1747 CSR_WRITE_2(sc, VTE_MTICR, 0); 1748 1749 /* Enable MAC event counter interrupts. */ 1750 CSR_WRITE_2(sc, VTE_MECIER, VTE_MECIER_INTRS); 1751 /* Clear MAC statistics. */ 1752 vte_stats_clear(sc); 1753 1754 /* Acknowledge all pending interrupts and clear it. */ 1755 CSR_WRITE_2(sc, VTE_MIER, VTE_INTRS); 1756 CSR_WRITE_2(sc, VTE_MISR, 0); 1757 1758 sc->vte_flags &= ~VTE_FLAG_LINK; 1759 /* Switch to the current media. */ 1760 vte_mediachange_locked(ifp); 1761 1762 callout_reset(&sc->vte_tick_ch, hz, vte_tick, sc); 1763 1764 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 1765 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 1766 } 1767 1768 static void 1769 vte_stop(struct vte_softc *sc) 1770 { 1771 if_t ifp; 1772 struct vte_txdesc *txd; 1773 struct vte_rxdesc *rxd; 1774 int i; 1775 1776 VTE_LOCK_ASSERT(sc); 1777 /* 1778 * Mark the interface down and cancel the watchdog timer. 1779 */ 1780 ifp = sc->vte_ifp; 1781 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)); 1782 sc->vte_flags &= ~VTE_FLAG_LINK; 1783 callout_stop(&sc->vte_tick_ch); 1784 sc->vte_watchdog_timer = 0; 1785 vte_stats_update(sc); 1786 /* Disable interrupts. */ 1787 CSR_WRITE_2(sc, VTE_MIER, 0); 1788 CSR_WRITE_2(sc, VTE_MECIER, 0); 1789 /* Stop RX/TX MACs. */ 1790 vte_stop_mac(sc); 1791 /* Clear interrupts. */ 1792 CSR_READ_2(sc, VTE_MISR); 1793 /* 1794 * Free TX/RX mbufs still in the queues. 1795 */ 1796 for (i = 0; i < VTE_RX_RING_CNT; i++) { 1797 rxd = &sc->vte_cdata.vte_rxdesc[i]; 1798 if (rxd->rx_m != NULL) { 1799 bus_dmamap_sync(sc->vte_cdata.vte_rx_tag, 1800 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 1801 bus_dmamap_unload(sc->vte_cdata.vte_rx_tag, 1802 rxd->rx_dmamap); 1803 m_freem(rxd->rx_m); 1804 rxd->rx_m = NULL; 1805 } 1806 } 1807 for (i = 0; i < VTE_TX_RING_CNT; i++) { 1808 txd = &sc->vte_cdata.vte_txdesc[i]; 1809 if (txd->tx_m != NULL) { 1810 bus_dmamap_sync(sc->vte_cdata.vte_tx_tag, 1811 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 1812 bus_dmamap_unload(sc->vte_cdata.vte_tx_tag, 1813 txd->tx_dmamap); 1814 if ((txd->tx_flags & VTE_TXMBUF) == 0) 1815 m_freem(txd->tx_m); 1816 txd->tx_m = NULL; 1817 txd->tx_flags &= ~VTE_TXMBUF; 1818 } 1819 } 1820 /* Free TX mbuf pools used for deep copy. */ 1821 for (i = 0; i < VTE_TX_RING_CNT; i++) { 1822 if (sc->vte_cdata.vte_txmbufs[i] != NULL) { 1823 m_freem(sc->vte_cdata.vte_txmbufs[i]); 1824 sc->vte_cdata.vte_txmbufs[i] = NULL; 1825 } 1826 } 1827 } 1828 1829 static void 1830 vte_start_mac(struct vte_softc *sc) 1831 { 1832 uint16_t mcr; 1833 int i; 1834 1835 VTE_LOCK_ASSERT(sc); 1836 1837 /* Enable RX/TX MACs. */ 1838 mcr = CSR_READ_2(sc, VTE_MCR0); 1839 if ((mcr & (MCR0_RX_ENB | MCR0_TX_ENB)) != 1840 (MCR0_RX_ENB | MCR0_TX_ENB)) { 1841 mcr |= MCR0_RX_ENB | MCR0_TX_ENB; 1842 CSR_WRITE_2(sc, VTE_MCR0, mcr); 1843 for (i = VTE_TIMEOUT; i > 0; i--) { 1844 mcr = CSR_READ_2(sc, VTE_MCR0); 1845 if ((mcr & (MCR0_RX_ENB | MCR0_TX_ENB)) == 1846 (MCR0_RX_ENB | MCR0_TX_ENB)) 1847 break; 1848 DELAY(10); 1849 } 1850 if (i == 0) 1851 device_printf(sc->vte_dev, 1852 "could not enable RX/TX MAC(0x%04x)!\n", mcr); 1853 } 1854 } 1855 1856 static void 1857 vte_stop_mac(struct vte_softc *sc) 1858 { 1859 uint16_t mcr; 1860 int i; 1861 1862 VTE_LOCK_ASSERT(sc); 1863 1864 /* Disable RX/TX MACs. */ 1865 mcr = CSR_READ_2(sc, VTE_MCR0); 1866 if ((mcr & (MCR0_RX_ENB | MCR0_TX_ENB)) != 0) { 1867 mcr &= ~(MCR0_RX_ENB | MCR0_TX_ENB); 1868 CSR_WRITE_2(sc, VTE_MCR0, mcr); 1869 for (i = VTE_TIMEOUT; i > 0; i--) { 1870 mcr = CSR_READ_2(sc, VTE_MCR0); 1871 if ((mcr & (MCR0_RX_ENB | MCR0_TX_ENB)) == 0) 1872 break; 1873 DELAY(10); 1874 } 1875 if (i == 0) 1876 device_printf(sc->vte_dev, 1877 "could not disable RX/TX MAC(0x%04x)!\n", mcr); 1878 } 1879 } 1880 1881 static int 1882 vte_init_tx_ring(struct vte_softc *sc) 1883 { 1884 struct vte_tx_desc *desc; 1885 struct vte_txdesc *txd; 1886 bus_addr_t addr; 1887 int i; 1888 1889 VTE_LOCK_ASSERT(sc); 1890 1891 sc->vte_cdata.vte_tx_prod = 0; 1892 sc->vte_cdata.vte_tx_cons = 0; 1893 sc->vte_cdata.vte_tx_cnt = 0; 1894 1895 /* Pre-allocate TX mbufs for deep copy. */ 1896 if (tx_deep_copy != 0) { 1897 for (i = 0; i < VTE_TX_RING_CNT; i++) { 1898 sc->vte_cdata.vte_txmbufs[i] = m_getcl(M_NOWAIT, 1899 MT_DATA, M_PKTHDR); 1900 if (sc->vte_cdata.vte_txmbufs[i] == NULL) 1901 return (ENOBUFS); 1902 sc->vte_cdata.vte_txmbufs[i]->m_pkthdr.len = MCLBYTES; 1903 sc->vte_cdata.vte_txmbufs[i]->m_len = MCLBYTES; 1904 } 1905 } 1906 desc = sc->vte_cdata.vte_tx_ring; 1907 bzero(desc, VTE_TX_RING_SZ); 1908 for (i = 0; i < VTE_TX_RING_CNT; i++) { 1909 txd = &sc->vte_cdata.vte_txdesc[i]; 1910 txd->tx_m = NULL; 1911 if (i != VTE_TX_RING_CNT - 1) 1912 addr = sc->vte_cdata.vte_tx_ring_paddr + 1913 sizeof(struct vte_tx_desc) * (i + 1); 1914 else 1915 addr = sc->vte_cdata.vte_tx_ring_paddr + 1916 sizeof(struct vte_tx_desc) * 0; 1917 desc = &sc->vte_cdata.vte_tx_ring[i]; 1918 desc->dtnp = htole32(addr); 1919 txd->tx_desc = desc; 1920 } 1921 1922 bus_dmamap_sync(sc->vte_cdata.vte_tx_ring_tag, 1923 sc->vte_cdata.vte_tx_ring_map, BUS_DMASYNC_PREREAD | 1924 BUS_DMASYNC_PREWRITE); 1925 return (0); 1926 } 1927 1928 static int 1929 vte_init_rx_ring(struct vte_softc *sc) 1930 { 1931 struct vte_rx_desc *desc; 1932 struct vte_rxdesc *rxd; 1933 bus_addr_t addr; 1934 int i; 1935 1936 VTE_LOCK_ASSERT(sc); 1937 1938 sc->vte_cdata.vte_rx_cons = 0; 1939 desc = sc->vte_cdata.vte_rx_ring; 1940 bzero(desc, VTE_RX_RING_SZ); 1941 for (i = 0; i < VTE_RX_RING_CNT; i++) { 1942 rxd = &sc->vte_cdata.vte_rxdesc[i]; 1943 rxd->rx_m = NULL; 1944 if (i != VTE_RX_RING_CNT - 1) 1945 addr = sc->vte_cdata.vte_rx_ring_paddr + 1946 sizeof(struct vte_rx_desc) * (i + 1); 1947 else 1948 addr = sc->vte_cdata.vte_rx_ring_paddr + 1949 sizeof(struct vte_rx_desc) * 0; 1950 desc = &sc->vte_cdata.vte_rx_ring[i]; 1951 desc->drnp = htole32(addr); 1952 rxd->rx_desc = desc; 1953 if (vte_newbuf(sc, rxd) != 0) 1954 return (ENOBUFS); 1955 } 1956 1957 bus_dmamap_sync(sc->vte_cdata.vte_rx_ring_tag, 1958 sc->vte_cdata.vte_rx_ring_map, BUS_DMASYNC_PREREAD | 1959 BUS_DMASYNC_PREWRITE); 1960 1961 return (0); 1962 } 1963 1964 struct vte_maddr_ctx { 1965 uint16_t rxfilt_perf[VTE_RXFILT_PERFECT_CNT][3]; 1966 uint16_t mchash[4]; 1967 u_int nperf; 1968 }; 1969 1970 static u_int 1971 vte_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 1972 { 1973 struct vte_maddr_ctx *ctx = arg; 1974 uint8_t *eaddr; 1975 uint32_t crc; 1976 1977 /* 1978 * Program the first 3 multicast groups into the perfect filter. 1979 * For all others, use the hash table. 1980 */ 1981 if (ctx->nperf < VTE_RXFILT_PERFECT_CNT) { 1982 eaddr = LLADDR(sdl); 1983 ctx->rxfilt_perf[ctx->nperf][0] = eaddr[1] << 8 | eaddr[0]; 1984 ctx->rxfilt_perf[ctx->nperf][1] = eaddr[3] << 8 | eaddr[2]; 1985 ctx->rxfilt_perf[ctx->nperf][2] = eaddr[5] << 8 | eaddr[4]; 1986 ctx->nperf++; 1987 1988 return (1); 1989 } 1990 crc = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN); 1991 ctx->mchash[crc >> 30] |= 1 << ((crc >> 26) & 0x0F); 1992 1993 return (1); 1994 } 1995 1996 static void 1997 vte_rxfilter(struct vte_softc *sc) 1998 { 1999 if_t ifp; 2000 struct vte_maddr_ctx ctx; 2001 uint16_t mcr; 2002 int i; 2003 2004 VTE_LOCK_ASSERT(sc); 2005 2006 ifp = sc->vte_ifp; 2007 2008 bzero(ctx.mchash, sizeof(ctx.mchash)); 2009 for (i = 0; i < VTE_RXFILT_PERFECT_CNT; i++) { 2010 ctx.rxfilt_perf[i][0] = 0xFFFF; 2011 ctx.rxfilt_perf[i][1] = 0xFFFF; 2012 ctx.rxfilt_perf[i][2] = 0xFFFF; 2013 } 2014 ctx.nperf = 0; 2015 2016 mcr = CSR_READ_2(sc, VTE_MCR0); 2017 mcr &= ~(MCR0_PROMISC | MCR0_MULTICAST); 2018 mcr |= MCR0_BROADCAST_DIS; 2019 if ((if_getflags(ifp) & IFF_BROADCAST) != 0) 2020 mcr &= ~MCR0_BROADCAST_DIS; 2021 if ((if_getflags(ifp) & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 2022 if ((if_getflags(ifp) & IFF_PROMISC) != 0) 2023 mcr |= MCR0_PROMISC; 2024 if ((if_getflags(ifp) & IFF_ALLMULTI) != 0) 2025 mcr |= MCR0_MULTICAST; 2026 ctx.mchash[0] = 0xFFFF; 2027 ctx.mchash[1] = 0xFFFF; 2028 ctx.mchash[2] = 0xFFFF; 2029 ctx.mchash[3] = 0xFFFF; 2030 goto chipit; 2031 } 2032 2033 if_foreach_llmaddr(ifp, vte_hash_maddr, &ctx); 2034 if (ctx.mchash[0] != 0 || ctx.mchash[1] != 0 || 2035 ctx.mchash[2] != 0 || ctx.mchash[3] != 0) 2036 mcr |= MCR0_MULTICAST; 2037 2038 chipit: 2039 /* Program multicast hash table. */ 2040 CSR_WRITE_2(sc, VTE_MAR0, ctx.mchash[0]); 2041 CSR_WRITE_2(sc, VTE_MAR1, ctx.mchash[1]); 2042 CSR_WRITE_2(sc, VTE_MAR2, ctx.mchash[2]); 2043 CSR_WRITE_2(sc, VTE_MAR3, ctx.mchash[3]); 2044 /* Program perfect filter table. */ 2045 for (i = 0; i < VTE_RXFILT_PERFECT_CNT; i++) { 2046 CSR_WRITE_2(sc, VTE_RXFILTER_PEEFECT_BASE + 8 * i + 0, 2047 ctx.rxfilt_perf[i][0]); 2048 CSR_WRITE_2(sc, VTE_RXFILTER_PEEFECT_BASE + 8 * i + 2, 2049 ctx.rxfilt_perf[i][1]); 2050 CSR_WRITE_2(sc, VTE_RXFILTER_PEEFECT_BASE + 8 * i + 4, 2051 ctx.rxfilt_perf[i][2]); 2052 } 2053 CSR_WRITE_2(sc, VTE_MCR0, mcr); 2054 CSR_READ_2(sc, VTE_MCR0); 2055 } 2056 2057 static int 2058 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 2059 { 2060 int error, value; 2061 2062 if (arg1 == NULL) 2063 return (EINVAL); 2064 value = *(int *)arg1; 2065 error = sysctl_handle_int(oidp, &value, 0, req); 2066 if (error || req->newptr == NULL) 2067 return (error); 2068 if (value < low || value > high) 2069 return (EINVAL); 2070 *(int *)arg1 = value; 2071 2072 return (0); 2073 } 2074 2075 static int 2076 sysctl_hw_vte_int_mod(SYSCTL_HANDLER_ARGS) 2077 { 2078 2079 return (sysctl_int_range(oidp, arg1, arg2, req, 2080 VTE_IM_BUNDLE_MIN, VTE_IM_BUNDLE_MAX)); 2081 } 2082