1 /*- 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * 3Com 3c90x Etherlink XL PCI NIC driver 38 * 39 * Supports the 3Com "boomerang", "cyclone" and "hurricane" PCI 40 * bus-master chips (3c90x cards and embedded controllers) including 41 * the following: 42 * 43 * 3Com 3c900-TPO 10Mbps/RJ-45 44 * 3Com 3c900-COMBO 10Mbps/RJ-45,AUI,BNC 45 * 3Com 3c905-TX 10/100Mbps/RJ-45 46 * 3Com 3c905-T4 10/100Mbps/RJ-45 47 * 3Com 3c900B-TPO 10Mbps/RJ-45 48 * 3Com 3c900B-COMBO 10Mbps/RJ-45,AUI,BNC 49 * 3Com 3c900B-TPC 10Mbps/RJ-45,BNC 50 * 3Com 3c900B-FL 10Mbps/Fiber-optic 51 * 3Com 3c905B-COMBO 10/100Mbps/RJ-45,AUI,BNC 52 * 3Com 3c905B-TX 10/100Mbps/RJ-45 53 * 3Com 3c905B-FL/FX 10/100Mbps/Fiber-optic 54 * 3Com 3c905C-TX 10/100Mbps/RJ-45 (Tornado ASIC) 55 * 3Com 3c980-TX 10/100Mbps server adapter (Hurricane ASIC) 56 * 3Com 3c980C-TX 10/100Mbps server adapter (Tornado ASIC) 57 * 3Com 3cSOHO100-TX 10/100Mbps/RJ-45 (Hurricane ASIC) 58 * 3Com 3c450-TX 10/100Mbps/RJ-45 (Tornado ASIC) 59 * 3Com 3c555 10/100Mbps/RJ-45 (MiniPCI, Laptop Hurricane) 60 * 3Com 3c556 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC) 61 * 3Com 3c556B 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC) 62 * 3Com 3c575TX 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 63 * 3Com 3c575B 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 64 * 3Com 3c575C 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 65 * 3Com 3cxfem656 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 66 * 3Com 3cxfem656b 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 67 * 3Com 3cxfem656c 10/100Mbps/RJ-45 (Cardbus, Tornado ASIC) 68 * Dell Optiplex GX1 on-board 3c918 10/100Mbps/RJ-45 69 * Dell on-board 3c920 10/100Mbps/RJ-45 70 * Dell Precision on-board 3c905B 10/100Mbps/RJ-45 71 * Dell Latitude laptop docking station embedded 3c905-TX 72 * 73 * Written by Bill Paul <wpaul@ctr.columbia.edu> 74 * Electrical Engineering Department 75 * Columbia University, New York City 76 */ 77 /* 78 * The 3c90x series chips use a bus-master DMA interface for transfering 79 * packets to and from the controller chip. Some of the "vortex" cards 80 * (3c59x) also supported a bus master mode, however for those chips 81 * you could only DMA packets to/from a contiguous memory buffer. For 82 * transmission this would mean copying the contents of the queued mbuf 83 * chain into an mbuf cluster and then DMAing the cluster. This extra 84 * copy would sort of defeat the purpose of the bus master support for 85 * any packet that doesn't fit into a single mbuf. 86 * 87 * By contrast, the 3c90x cards support a fragment-based bus master 88 * mode where mbuf chains can be encapsulated using TX descriptors. 89 * This is similar to other PCI chips such as the Texas Instruments 90 * ThunderLAN and the Intel 82557/82558. 91 * 92 * The "vortex" driver (if_vx.c) happens to work for the "boomerang" 93 * bus master chips because they maintain the old PIO interface for 94 * backwards compatibility, but starting with the 3c905B and the 95 * "cyclone" chips, the compatibility interface has been dropped. 96 * Since using bus master DMA is a big win, we use this driver to 97 * support the PCI "boomerang" chips even though they work with the 98 * "vortex" driver in order to obtain better performance. 99 */ 100 101 #ifdef HAVE_KERNEL_OPTION_HEADERS 102 #include "opt_device_polling.h" 103 #endif 104 105 #include <sys/param.h> 106 #include <sys/systm.h> 107 #include <sys/sockio.h> 108 #include <sys/endian.h> 109 #include <sys/mbuf.h> 110 #include <sys/kernel.h> 111 #include <sys/module.h> 112 #include <sys/socket.h> 113 #include <sys/taskqueue.h> 114 115 #include <net/if.h> 116 #include <net/if_arp.h> 117 #include <net/ethernet.h> 118 #include <net/if_dl.h> 119 #include <net/if_media.h> 120 #include <net/if_types.h> 121 122 #include <net/bpf.h> 123 124 #include <machine/bus.h> 125 #include <machine/resource.h> 126 #include <sys/bus.h> 127 #include <sys/rman.h> 128 129 #include <dev/mii/mii.h> 130 #include <dev/mii/miivar.h> 131 132 #include <dev/pci/pcireg.h> 133 #include <dev/pci/pcivar.h> 134 135 MODULE_DEPEND(xl, pci, 1, 1, 1); 136 MODULE_DEPEND(xl, ether, 1, 1, 1); 137 MODULE_DEPEND(xl, miibus, 1, 1, 1); 138 139 /* "device miibus" required. See GENERIC if you get errors here. */ 140 #include "miibus_if.h" 141 142 #include <dev/xl/if_xlreg.h> 143 144 /* 145 * TX Checksumming is disabled by default for two reasons: 146 * - TX Checksumming will occasionally produce corrupt packets 147 * - TX Checksumming seems to reduce performance 148 * 149 * Only 905B/C cards were reported to have this problem, it is possible 150 * that later chips _may_ be immune. 151 */ 152 #define XL905B_TXCSUM_BROKEN 1 153 154 #ifdef XL905B_TXCSUM_BROKEN 155 #define XL905B_CSUM_FEATURES 0 156 #else 157 #define XL905B_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 158 #endif 159 160 /* 161 * Various supported device vendors/types and their names. 162 */ 163 static const struct xl_type xl_devs[] = { 164 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT, 165 "3Com 3c900-TPO Etherlink XL" }, 166 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT_COMBO, 167 "3Com 3c900-COMBO Etherlink XL" }, 168 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10_100BT, 169 "3Com 3c905-TX Fast Etherlink XL" }, 170 { TC_VENDORID, TC_DEVICEID_BOOMERANG_100BT4, 171 "3Com 3c905-T4 Fast Etherlink XL" }, 172 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT, 173 "3Com 3c900B-TPO Etherlink XL" }, 174 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_COMBO, 175 "3Com 3c900B-COMBO Etherlink XL" }, 176 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_TPC, 177 "3Com 3c900B-TPC Etherlink XL" }, 178 { TC_VENDORID, TC_DEVICEID_CYCLONE_10FL, 179 "3Com 3c900B-FL Etherlink XL" }, 180 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT, 181 "3Com 3c905B-TX Fast Etherlink XL" }, 182 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100BT4, 183 "3Com 3c905B-T4 Fast Etherlink XL" }, 184 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100FX, 185 "3Com 3c905B-FX/SC Fast Etherlink XL" }, 186 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100_COMBO, 187 "3Com 3c905B-COMBO Fast Etherlink XL" }, 188 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT, 189 "3Com 3c905C-TX Fast Etherlink XL" }, 190 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_920B, 191 "3Com 3c920B-EMB Integrated Fast Etherlink XL" }, 192 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_920B_WNM, 193 "3Com 3c920B-EMB-WNM Integrated Fast Etherlink XL" }, 194 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT_SERV, 195 "3Com 3c980 Fast Etherlink XL" }, 196 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_SERV, 197 "3Com 3c980C Fast Etherlink XL" }, 198 { TC_VENDORID, TC_DEVICEID_HURRICANE_SOHO100TX, 199 "3Com 3cSOHO100-TX OfficeConnect" }, 200 { TC_VENDORID, TC_DEVICEID_TORNADO_HOMECONNECT, 201 "3Com 3c450-TX HomeConnect" }, 202 { TC_VENDORID, TC_DEVICEID_HURRICANE_555, 203 "3Com 3c555 Fast Etherlink XL" }, 204 { TC_VENDORID, TC_DEVICEID_HURRICANE_556, 205 "3Com 3c556 Fast Etherlink XL" }, 206 { TC_VENDORID, TC_DEVICEID_HURRICANE_556B, 207 "3Com 3c556B Fast Etherlink XL" }, 208 { TC_VENDORID, TC_DEVICEID_HURRICANE_575A, 209 "3Com 3c575TX Fast Etherlink XL" }, 210 { TC_VENDORID, TC_DEVICEID_HURRICANE_575B, 211 "3Com 3c575B Fast Etherlink XL" }, 212 { TC_VENDORID, TC_DEVICEID_HURRICANE_575C, 213 "3Com 3c575C Fast Etherlink XL" }, 214 { TC_VENDORID, TC_DEVICEID_HURRICANE_656, 215 "3Com 3c656 Fast Etherlink XL" }, 216 { TC_VENDORID, TC_DEVICEID_HURRICANE_656B, 217 "3Com 3c656B Fast Etherlink XL" }, 218 { TC_VENDORID, TC_DEVICEID_TORNADO_656C, 219 "3Com 3c656C Fast Etherlink XL" }, 220 { 0, 0, NULL } 221 }; 222 223 static int xl_probe(device_t); 224 static int xl_attach(device_t); 225 static int xl_detach(device_t); 226 227 static int xl_newbuf(struct xl_softc *, struct xl_chain_onefrag *); 228 static void xl_stats_update(void *); 229 static void xl_stats_update_locked(struct xl_softc *); 230 static int xl_encap(struct xl_softc *, struct xl_chain *, struct mbuf **); 231 static int xl_rxeof(struct xl_softc *); 232 static void xl_rxeof_task(void *, int); 233 static int xl_rx_resync(struct xl_softc *); 234 static void xl_txeof(struct xl_softc *); 235 static void xl_txeof_90xB(struct xl_softc *); 236 static void xl_txeoc(struct xl_softc *); 237 static void xl_intr(void *); 238 static void xl_start(struct ifnet *); 239 static void xl_start_locked(struct ifnet *); 240 static void xl_start_90xB_locked(struct ifnet *); 241 static int xl_ioctl(struct ifnet *, u_long, caddr_t); 242 static void xl_init(void *); 243 static void xl_init_locked(struct xl_softc *); 244 static void xl_stop(struct xl_softc *); 245 static int xl_watchdog(struct xl_softc *); 246 static int xl_shutdown(device_t); 247 static int xl_suspend(device_t); 248 static int xl_resume(device_t); 249 250 #ifdef DEVICE_POLLING 251 static int xl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count); 252 static int xl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count); 253 #endif 254 255 static int xl_ifmedia_upd(struct ifnet *); 256 static void xl_ifmedia_sts(struct ifnet *, struct ifmediareq *); 257 258 static int xl_eeprom_wait(struct xl_softc *); 259 static int xl_read_eeprom(struct xl_softc *, caddr_t, int, int, int); 260 static void xl_mii_sync(struct xl_softc *); 261 static void xl_mii_send(struct xl_softc *, u_int32_t, int); 262 static int xl_mii_readreg(struct xl_softc *, struct xl_mii_frame *); 263 static int xl_mii_writereg(struct xl_softc *, struct xl_mii_frame *); 264 265 static void xl_setcfg(struct xl_softc *); 266 static void xl_setmode(struct xl_softc *, int); 267 static void xl_setmulti(struct xl_softc *); 268 static void xl_setmulti_hash(struct xl_softc *); 269 static void xl_reset(struct xl_softc *); 270 static int xl_list_rx_init(struct xl_softc *); 271 static int xl_list_tx_init(struct xl_softc *); 272 static int xl_list_tx_init_90xB(struct xl_softc *); 273 static void xl_wait(struct xl_softc *); 274 static void xl_mediacheck(struct xl_softc *); 275 static void xl_choose_media(struct xl_softc *sc, int *media); 276 static void xl_choose_xcvr(struct xl_softc *, int); 277 static void xl_dma_map_addr(void *, bus_dma_segment_t *, int, int); 278 #ifdef notdef 279 static void xl_testpacket(struct xl_softc *); 280 #endif 281 282 static int xl_miibus_readreg(device_t, int, int); 283 static int xl_miibus_writereg(device_t, int, int, int); 284 static void xl_miibus_statchg(device_t); 285 static void xl_miibus_mediainit(device_t); 286 287 static device_method_t xl_methods[] = { 288 /* Device interface */ 289 DEVMETHOD(device_probe, xl_probe), 290 DEVMETHOD(device_attach, xl_attach), 291 DEVMETHOD(device_detach, xl_detach), 292 DEVMETHOD(device_shutdown, xl_shutdown), 293 DEVMETHOD(device_suspend, xl_suspend), 294 DEVMETHOD(device_resume, xl_resume), 295 296 /* bus interface */ 297 DEVMETHOD(bus_print_child, bus_generic_print_child), 298 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 299 300 /* MII interface */ 301 DEVMETHOD(miibus_readreg, xl_miibus_readreg), 302 DEVMETHOD(miibus_writereg, xl_miibus_writereg), 303 DEVMETHOD(miibus_statchg, xl_miibus_statchg), 304 DEVMETHOD(miibus_mediainit, xl_miibus_mediainit), 305 306 { 0, 0 } 307 }; 308 309 static driver_t xl_driver = { 310 "xl", 311 xl_methods, 312 sizeof(struct xl_softc) 313 }; 314 315 static devclass_t xl_devclass; 316 317 DRIVER_MODULE(xl, pci, xl_driver, xl_devclass, 0, 0); 318 DRIVER_MODULE(miibus, xl, miibus_driver, miibus_devclass, 0, 0); 319 320 static void 321 xl_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 322 { 323 u_int32_t *paddr; 324 325 paddr = arg; 326 *paddr = segs->ds_addr; 327 } 328 329 /* 330 * Murphy's law says that it's possible the chip can wedge and 331 * the 'command in progress' bit may never clear. Hence, we wait 332 * only a finite amount of time to avoid getting caught in an 333 * infinite loop. Normally this delay routine would be a macro, 334 * but it isn't called during normal operation so we can afford 335 * to make it a function. 336 */ 337 static void 338 xl_wait(struct xl_softc *sc) 339 { 340 register int i; 341 342 for (i = 0; i < XL_TIMEOUT; i++) { 343 if ((CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY) == 0) 344 break; 345 } 346 347 if (i == XL_TIMEOUT) 348 device_printf(sc->xl_dev, "command never completed!\n"); 349 } 350 351 /* 352 * MII access routines are provided for adapters with external 353 * PHYs (3c905-TX, 3c905-T4, 3c905B-T4) and those with built-in 354 * autoneg logic that's faked up to look like a PHY (3c905B-TX). 355 * Note: if you don't perform the MDIO operations just right, 356 * it's possible to end up with code that works correctly with 357 * some chips/CPUs/processor speeds/bus speeds/etc but not 358 * with others. 359 */ 360 #define MII_SET(x) \ 361 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \ 362 CSR_READ_2(sc, XL_W4_PHY_MGMT) | (x)) 363 364 #define MII_CLR(x) \ 365 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \ 366 CSR_READ_2(sc, XL_W4_PHY_MGMT) & ~(x)) 367 368 /* 369 * Sync the PHYs by setting data bit and strobing the clock 32 times. 370 */ 371 static void 372 xl_mii_sync(struct xl_softc *sc) 373 { 374 register int i; 375 376 XL_SEL_WIN(4); 377 MII_SET(XL_MII_DIR|XL_MII_DATA); 378 379 for (i = 0; i < 32; i++) { 380 MII_SET(XL_MII_CLK); 381 MII_SET(XL_MII_DATA); 382 MII_SET(XL_MII_DATA); 383 MII_CLR(XL_MII_CLK); 384 MII_SET(XL_MII_DATA); 385 MII_SET(XL_MII_DATA); 386 } 387 } 388 389 /* 390 * Clock a series of bits through the MII. 391 */ 392 static void 393 xl_mii_send(struct xl_softc *sc, u_int32_t bits, int cnt) 394 { 395 int i; 396 397 XL_SEL_WIN(4); 398 MII_CLR(XL_MII_CLK); 399 400 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 401 if (bits & i) { 402 MII_SET(XL_MII_DATA); 403 } else { 404 MII_CLR(XL_MII_DATA); 405 } 406 MII_CLR(XL_MII_CLK); 407 MII_SET(XL_MII_CLK); 408 } 409 } 410 411 /* 412 * Read an PHY register through the MII. 413 */ 414 static int 415 xl_mii_readreg(struct xl_softc *sc, struct xl_mii_frame *frame) 416 { 417 int i, ack; 418 419 /* Set up frame for RX. */ 420 frame->mii_stdelim = XL_MII_STARTDELIM; 421 frame->mii_opcode = XL_MII_READOP; 422 frame->mii_turnaround = 0; 423 frame->mii_data = 0; 424 425 /* Select register window 4. */ 426 XL_SEL_WIN(4); 427 428 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, 0); 429 /* Turn on data xmit. */ 430 MII_SET(XL_MII_DIR); 431 432 xl_mii_sync(sc); 433 434 /* Send command/address info. */ 435 xl_mii_send(sc, frame->mii_stdelim, 2); 436 xl_mii_send(sc, frame->mii_opcode, 2); 437 xl_mii_send(sc, frame->mii_phyaddr, 5); 438 xl_mii_send(sc, frame->mii_regaddr, 5); 439 440 /* Idle bit */ 441 MII_CLR((XL_MII_CLK|XL_MII_DATA)); 442 MII_SET(XL_MII_CLK); 443 444 /* Turn off xmit. */ 445 MII_CLR(XL_MII_DIR); 446 447 /* Check for ack */ 448 MII_CLR(XL_MII_CLK); 449 ack = CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA; 450 MII_SET(XL_MII_CLK); 451 452 /* 453 * Now try reading data bits. If the ack failed, we still 454 * need to clock through 16 cycles to keep the PHY(s) in sync. 455 */ 456 if (ack) { 457 for (i = 0; i < 16; i++) { 458 MII_CLR(XL_MII_CLK); 459 MII_SET(XL_MII_CLK); 460 } 461 goto fail; 462 } 463 464 for (i = 0x8000; i; i >>= 1) { 465 MII_CLR(XL_MII_CLK); 466 if (!ack) { 467 if (CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA) 468 frame->mii_data |= i; 469 } 470 MII_SET(XL_MII_CLK); 471 } 472 473 fail: 474 MII_CLR(XL_MII_CLK); 475 MII_SET(XL_MII_CLK); 476 477 return (ack ? 1 : 0); 478 } 479 480 /* 481 * Write to a PHY register through the MII. 482 */ 483 static int 484 xl_mii_writereg(struct xl_softc *sc, struct xl_mii_frame *frame) 485 { 486 487 /* Set up frame for TX. */ 488 frame->mii_stdelim = XL_MII_STARTDELIM; 489 frame->mii_opcode = XL_MII_WRITEOP; 490 frame->mii_turnaround = XL_MII_TURNAROUND; 491 492 /* Select the window 4. */ 493 XL_SEL_WIN(4); 494 495 /* Turn on data output. */ 496 MII_SET(XL_MII_DIR); 497 498 xl_mii_sync(sc); 499 500 xl_mii_send(sc, frame->mii_stdelim, 2); 501 xl_mii_send(sc, frame->mii_opcode, 2); 502 xl_mii_send(sc, frame->mii_phyaddr, 5); 503 xl_mii_send(sc, frame->mii_regaddr, 5); 504 xl_mii_send(sc, frame->mii_turnaround, 2); 505 xl_mii_send(sc, frame->mii_data, 16); 506 507 /* Idle bit. */ 508 MII_SET(XL_MII_CLK); 509 MII_CLR(XL_MII_CLK); 510 511 /* Turn off xmit. */ 512 MII_CLR(XL_MII_DIR); 513 514 return (0); 515 } 516 517 static int 518 xl_miibus_readreg(device_t dev, int phy, int reg) 519 { 520 struct xl_softc *sc; 521 struct xl_mii_frame frame; 522 523 sc = device_get_softc(dev); 524 525 /* 526 * Pretend that PHYs are only available at MII address 24. 527 * This is to guard against problems with certain 3Com ASIC 528 * revisions that incorrectly map the internal transceiver 529 * control registers at all MII addresses. This can cause 530 * the miibus code to attach the same PHY several times over. 531 */ 532 if ((sc->xl_flags & XL_FLAG_PHYOK) == 0 && phy != 24) 533 return (0); 534 535 bzero((char *)&frame, sizeof(frame)); 536 frame.mii_phyaddr = phy; 537 frame.mii_regaddr = reg; 538 539 xl_mii_readreg(sc, &frame); 540 541 return (frame.mii_data); 542 } 543 544 static int 545 xl_miibus_writereg(device_t dev, int phy, int reg, int data) 546 { 547 struct xl_softc *sc; 548 struct xl_mii_frame frame; 549 550 sc = device_get_softc(dev); 551 552 if ((sc->xl_flags & XL_FLAG_PHYOK) == 0 && phy != 24) 553 return (0); 554 555 bzero((char *)&frame, sizeof(frame)); 556 frame.mii_phyaddr = phy; 557 frame.mii_regaddr = reg; 558 frame.mii_data = data; 559 560 xl_mii_writereg(sc, &frame); 561 562 return (0); 563 } 564 565 static void 566 xl_miibus_statchg(device_t dev) 567 { 568 struct xl_softc *sc; 569 struct mii_data *mii; 570 571 sc = device_get_softc(dev); 572 mii = device_get_softc(sc->xl_miibus); 573 574 xl_setcfg(sc); 575 576 /* Set ASIC's duplex mode to match the PHY. */ 577 XL_SEL_WIN(3); 578 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 579 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX); 580 else 581 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, 582 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX)); 583 } 584 585 /* 586 * Special support for the 3c905B-COMBO. This card has 10/100 support 587 * plus BNC and AUI ports. This means we will have both an miibus attached 588 * plus some non-MII media settings. In order to allow this, we have to 589 * add the extra media to the miibus's ifmedia struct, but we can't do 590 * that during xl_attach() because the miibus hasn't been attached yet. 591 * So instead, we wait until the miibus probe/attach is done, at which 592 * point we will get a callback telling is that it's safe to add our 593 * extra media. 594 */ 595 static void 596 xl_miibus_mediainit(device_t dev) 597 { 598 struct xl_softc *sc; 599 struct mii_data *mii; 600 struct ifmedia *ifm; 601 602 sc = device_get_softc(dev); 603 mii = device_get_softc(sc->xl_miibus); 604 ifm = &mii->mii_media; 605 606 if (sc->xl_media & (XL_MEDIAOPT_AUI | XL_MEDIAOPT_10FL)) { 607 /* 608 * Check for a 10baseFL board in disguise. 609 */ 610 if (sc->xl_type == XL_TYPE_905B && 611 sc->xl_media == XL_MEDIAOPT_10FL) { 612 if (bootverbose) 613 device_printf(sc->xl_dev, "found 10baseFL\n"); 614 ifmedia_add(ifm, IFM_ETHER | IFM_10_FL, 0, NULL); 615 ifmedia_add(ifm, IFM_ETHER | IFM_10_FL|IFM_HDX, 0, 616 NULL); 617 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 618 ifmedia_add(ifm, 619 IFM_ETHER | IFM_10_FL | IFM_FDX, 0, NULL); 620 } else { 621 if (bootverbose) 622 device_printf(sc->xl_dev, "found AUI\n"); 623 ifmedia_add(ifm, IFM_ETHER | IFM_10_5, 0, NULL); 624 } 625 } 626 627 if (sc->xl_media & XL_MEDIAOPT_BNC) { 628 if (bootverbose) 629 device_printf(sc->xl_dev, "found BNC\n"); 630 ifmedia_add(ifm, IFM_ETHER | IFM_10_2, 0, NULL); 631 } 632 } 633 634 /* 635 * The EEPROM is slow: give it time to come ready after issuing 636 * it a command. 637 */ 638 static int 639 xl_eeprom_wait(struct xl_softc *sc) 640 { 641 int i; 642 643 for (i = 0; i < 100; i++) { 644 if (CSR_READ_2(sc, XL_W0_EE_CMD) & XL_EE_BUSY) 645 DELAY(162); 646 else 647 break; 648 } 649 650 if (i == 100) { 651 device_printf(sc->xl_dev, "eeprom failed to come ready\n"); 652 return (1); 653 } 654 655 return (0); 656 } 657 658 /* 659 * Read a sequence of words from the EEPROM. Note that ethernet address 660 * data is stored in the EEPROM in network byte order. 661 */ 662 static int 663 xl_read_eeprom(struct xl_softc *sc, caddr_t dest, int off, int cnt, int swap) 664 { 665 int err = 0, i; 666 u_int16_t word = 0, *ptr; 667 668 #define EEPROM_5BIT_OFFSET(A) ((((A) << 2) & 0x7F00) | ((A) & 0x003F)) 669 #define EEPROM_8BIT_OFFSET(A) ((A) & 0x003F) 670 /* 671 * XXX: WARNING! DANGER! 672 * It's easy to accidentally overwrite the rom content! 673 * Note: the 3c575 uses 8bit EEPROM offsets. 674 */ 675 XL_SEL_WIN(0); 676 677 if (xl_eeprom_wait(sc)) 678 return (1); 679 680 if (sc->xl_flags & XL_FLAG_EEPROM_OFFSET_30) 681 off += 0x30; 682 683 for (i = 0; i < cnt; i++) { 684 if (sc->xl_flags & XL_FLAG_8BITROM) 685 CSR_WRITE_2(sc, XL_W0_EE_CMD, 686 XL_EE_8BIT_READ | EEPROM_8BIT_OFFSET(off + i)); 687 else 688 CSR_WRITE_2(sc, XL_W0_EE_CMD, 689 XL_EE_READ | EEPROM_5BIT_OFFSET(off + i)); 690 err = xl_eeprom_wait(sc); 691 if (err) 692 break; 693 word = CSR_READ_2(sc, XL_W0_EE_DATA); 694 ptr = (u_int16_t *)(dest + (i * 2)); 695 if (swap) 696 *ptr = ntohs(word); 697 else 698 *ptr = word; 699 } 700 701 return (err ? 1 : 0); 702 } 703 704 /* 705 * NICs older than the 3c905B have only one multicast option, which 706 * is to enable reception of all multicast frames. 707 */ 708 static void 709 xl_setmulti(struct xl_softc *sc) 710 { 711 struct ifnet *ifp = sc->xl_ifp; 712 struct ifmultiaddr *ifma; 713 u_int8_t rxfilt; 714 int mcnt = 0; 715 716 XL_LOCK_ASSERT(sc); 717 718 XL_SEL_WIN(5); 719 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 720 721 if (ifp->if_flags & IFF_ALLMULTI) { 722 rxfilt |= XL_RXFILTER_ALLMULTI; 723 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 724 return; 725 } 726 727 if_maddr_rlock(ifp); 728 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) 729 mcnt++; 730 if_maddr_runlock(ifp); 731 732 if (mcnt) 733 rxfilt |= XL_RXFILTER_ALLMULTI; 734 else 735 rxfilt &= ~XL_RXFILTER_ALLMULTI; 736 737 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 738 } 739 740 /* 741 * 3c905B adapters have a hash filter that we can program. 742 */ 743 static void 744 xl_setmulti_hash(struct xl_softc *sc) 745 { 746 struct ifnet *ifp = sc->xl_ifp; 747 int h = 0, i; 748 struct ifmultiaddr *ifma; 749 u_int8_t rxfilt; 750 int mcnt = 0; 751 752 XL_LOCK_ASSERT(sc); 753 754 XL_SEL_WIN(5); 755 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 756 757 if (ifp->if_flags & IFF_ALLMULTI) { 758 rxfilt |= XL_RXFILTER_ALLMULTI; 759 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 760 return; 761 } else 762 rxfilt &= ~XL_RXFILTER_ALLMULTI; 763 764 /* first, zot all the existing hash bits */ 765 for (i = 0; i < XL_HASHFILT_SIZE; i++) 766 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH|i); 767 768 /* now program new ones */ 769 if_maddr_rlock(ifp); 770 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 771 if (ifma->ifma_addr->sa_family != AF_LINK) 772 continue; 773 /* 774 * Note: the 3c905B currently only supports a 64-bit hash 775 * table, which means we really only need 6 bits, but the 776 * manual indicates that future chip revisions will have a 777 * 256-bit hash table, hence the routine is set up to 778 * calculate 8 bits of position info in case we need it some 779 * day. 780 * Note II, The Sequel: _CURRENT_ versions of the 3c905B have 781 * a 256 bit hash table. This means we have to use all 8 bits 782 * regardless. On older cards, the upper 2 bits will be 783 * ignored. Grrrr.... 784 */ 785 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 786 ifma->ifma_addr), ETHER_ADDR_LEN) & 0xFF; 787 CSR_WRITE_2(sc, XL_COMMAND, 788 h | XL_CMD_RX_SET_HASH | XL_HASH_SET); 789 mcnt++; 790 } 791 if_maddr_runlock(ifp); 792 793 if (mcnt) 794 rxfilt |= XL_RXFILTER_MULTIHASH; 795 else 796 rxfilt &= ~XL_RXFILTER_MULTIHASH; 797 798 CSR_WRITE_2(sc, XL_COMMAND, rxfilt | XL_CMD_RX_SET_FILT); 799 } 800 801 static void 802 xl_setcfg(struct xl_softc *sc) 803 { 804 u_int32_t icfg; 805 806 /*XL_LOCK_ASSERT(sc);*/ 807 808 XL_SEL_WIN(3); 809 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG); 810 icfg &= ~XL_ICFG_CONNECTOR_MASK; 811 if (sc->xl_media & XL_MEDIAOPT_MII || 812 sc->xl_media & XL_MEDIAOPT_BT4) 813 icfg |= (XL_XCVR_MII << XL_ICFG_CONNECTOR_BITS); 814 if (sc->xl_media & XL_MEDIAOPT_BTX) 815 icfg |= (XL_XCVR_AUTO << XL_ICFG_CONNECTOR_BITS); 816 817 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg); 818 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 819 } 820 821 static void 822 xl_setmode(struct xl_softc *sc, int media) 823 { 824 u_int32_t icfg; 825 u_int16_t mediastat; 826 char *pmsg = "", *dmsg = ""; 827 828 XL_LOCK_ASSERT(sc); 829 830 XL_SEL_WIN(4); 831 mediastat = CSR_READ_2(sc, XL_W4_MEDIA_STATUS); 832 XL_SEL_WIN(3); 833 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG); 834 835 if (sc->xl_media & XL_MEDIAOPT_BT) { 836 if (IFM_SUBTYPE(media) == IFM_10_T) { 837 pmsg = "10baseT transceiver"; 838 sc->xl_xcvr = XL_XCVR_10BT; 839 icfg &= ~XL_ICFG_CONNECTOR_MASK; 840 icfg |= (XL_XCVR_10BT << XL_ICFG_CONNECTOR_BITS); 841 mediastat |= XL_MEDIASTAT_LINKBEAT | 842 XL_MEDIASTAT_JABGUARD; 843 mediastat &= ~XL_MEDIASTAT_SQEENB; 844 } 845 } 846 847 if (sc->xl_media & XL_MEDIAOPT_BFX) { 848 if (IFM_SUBTYPE(media) == IFM_100_FX) { 849 pmsg = "100baseFX port"; 850 sc->xl_xcvr = XL_XCVR_100BFX; 851 icfg &= ~XL_ICFG_CONNECTOR_MASK; 852 icfg |= (XL_XCVR_100BFX << XL_ICFG_CONNECTOR_BITS); 853 mediastat |= XL_MEDIASTAT_LINKBEAT; 854 mediastat &= ~XL_MEDIASTAT_SQEENB; 855 } 856 } 857 858 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) { 859 if (IFM_SUBTYPE(media) == IFM_10_5) { 860 pmsg = "AUI port"; 861 sc->xl_xcvr = XL_XCVR_AUI; 862 icfg &= ~XL_ICFG_CONNECTOR_MASK; 863 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS); 864 mediastat &= ~(XL_MEDIASTAT_LINKBEAT | 865 XL_MEDIASTAT_JABGUARD); 866 mediastat |= ~XL_MEDIASTAT_SQEENB; 867 } 868 if (IFM_SUBTYPE(media) == IFM_10_FL) { 869 pmsg = "10baseFL transceiver"; 870 sc->xl_xcvr = XL_XCVR_AUI; 871 icfg &= ~XL_ICFG_CONNECTOR_MASK; 872 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS); 873 mediastat &= ~(XL_MEDIASTAT_LINKBEAT | 874 XL_MEDIASTAT_JABGUARD); 875 mediastat |= ~XL_MEDIASTAT_SQEENB; 876 } 877 } 878 879 if (sc->xl_media & XL_MEDIAOPT_BNC) { 880 if (IFM_SUBTYPE(media) == IFM_10_2) { 881 pmsg = "AUI port"; 882 sc->xl_xcvr = XL_XCVR_COAX; 883 icfg &= ~XL_ICFG_CONNECTOR_MASK; 884 icfg |= (XL_XCVR_COAX << XL_ICFG_CONNECTOR_BITS); 885 mediastat &= ~(XL_MEDIASTAT_LINKBEAT | 886 XL_MEDIASTAT_JABGUARD | XL_MEDIASTAT_SQEENB); 887 } 888 } 889 890 if ((media & IFM_GMASK) == IFM_FDX || 891 IFM_SUBTYPE(media) == IFM_100_FX) { 892 dmsg = "full"; 893 XL_SEL_WIN(3); 894 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX); 895 } else { 896 dmsg = "half"; 897 XL_SEL_WIN(3); 898 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, 899 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX)); 900 } 901 902 if (IFM_SUBTYPE(media) == IFM_10_2) 903 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START); 904 else 905 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 906 907 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg); 908 XL_SEL_WIN(4); 909 CSR_WRITE_2(sc, XL_W4_MEDIA_STATUS, mediastat); 910 911 DELAY(800); 912 XL_SEL_WIN(7); 913 914 device_printf(sc->xl_dev, "selecting %s, %s duplex\n", pmsg, dmsg); 915 } 916 917 static void 918 xl_reset(struct xl_softc *sc) 919 { 920 register int i; 921 922 XL_LOCK_ASSERT(sc); 923 924 XL_SEL_WIN(0); 925 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RESET | 926 ((sc->xl_flags & XL_FLAG_WEIRDRESET) ? 927 XL_RESETOPT_DISADVFD:0)); 928 929 /* 930 * If we're using memory mapped register mode, pause briefly 931 * after issuing the reset command before trying to access any 932 * other registers. With my 3c575C CardBus card, failing to do 933 * this results in the system locking up while trying to poll 934 * the command busy bit in the status register. 935 */ 936 if (sc->xl_flags & XL_FLAG_USE_MMIO) 937 DELAY(100000); 938 939 for (i = 0; i < XL_TIMEOUT; i++) { 940 DELAY(10); 941 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY)) 942 break; 943 } 944 945 if (i == XL_TIMEOUT) 946 device_printf(sc->xl_dev, "reset didn't complete\n"); 947 948 /* Reset TX and RX. */ 949 /* Note: the RX reset takes an absurd amount of time 950 * on newer versions of the Tornado chips such as those 951 * on the 3c905CX and newer 3c908C cards. We wait an 952 * extra amount of time so that xl_wait() doesn't complain 953 * and annoy the users. 954 */ 955 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 956 DELAY(100000); 957 xl_wait(sc); 958 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 959 xl_wait(sc); 960 961 if (sc->xl_flags & XL_FLAG_INVERT_LED_PWR || 962 sc->xl_flags & XL_FLAG_INVERT_MII_PWR) { 963 XL_SEL_WIN(2); 964 CSR_WRITE_2(sc, XL_W2_RESET_OPTIONS, 965 CSR_READ_2(sc, XL_W2_RESET_OPTIONS) | 966 ((sc->xl_flags & XL_FLAG_INVERT_LED_PWR) ? 967 XL_RESETOPT_INVERT_LED : 0) | 968 ((sc->xl_flags & XL_FLAG_INVERT_MII_PWR) ? 969 XL_RESETOPT_INVERT_MII : 0)); 970 } 971 972 /* Wait a little while for the chip to get its brains in order. */ 973 DELAY(100000); 974 } 975 976 /* 977 * Probe for a 3Com Etherlink XL chip. Check the PCI vendor and device 978 * IDs against our list and return a device name if we find a match. 979 */ 980 static int 981 xl_probe(device_t dev) 982 { 983 const struct xl_type *t; 984 985 t = xl_devs; 986 987 while (t->xl_name != NULL) { 988 if ((pci_get_vendor(dev) == t->xl_vid) && 989 (pci_get_device(dev) == t->xl_did)) { 990 device_set_desc(dev, t->xl_name); 991 return (BUS_PROBE_DEFAULT); 992 } 993 t++; 994 } 995 996 return (ENXIO); 997 } 998 999 /* 1000 * This routine is a kludge to work around possible hardware faults 1001 * or manufacturing defects that can cause the media options register 1002 * (or reset options register, as it's called for the first generation 1003 * 3c90x adapters) to return an incorrect result. I have encountered 1004 * one Dell Latitude laptop docking station with an integrated 3c905-TX 1005 * which doesn't have any of the 'mediaopt' bits set. This screws up 1006 * the attach routine pretty badly because it doesn't know what media 1007 * to look for. If we find ourselves in this predicament, this routine 1008 * will try to guess the media options values and warn the user of a 1009 * possible manufacturing defect with his adapter/system/whatever. 1010 */ 1011 static void 1012 xl_mediacheck(struct xl_softc *sc) 1013 { 1014 1015 /* 1016 * If some of the media options bits are set, assume they are 1017 * correct. If not, try to figure it out down below. 1018 * XXX I should check for 10baseFL, but I don't have an adapter 1019 * to test with. 1020 */ 1021 if (sc->xl_media & (XL_MEDIAOPT_MASK & ~XL_MEDIAOPT_VCO)) { 1022 /* 1023 * Check the XCVR value. If it's not in the normal range 1024 * of values, we need to fake it up here. 1025 */ 1026 if (sc->xl_xcvr <= XL_XCVR_AUTO) 1027 return; 1028 else { 1029 device_printf(sc->xl_dev, 1030 "bogus xcvr value in EEPROM (%x)\n", sc->xl_xcvr); 1031 device_printf(sc->xl_dev, 1032 "choosing new default based on card type\n"); 1033 } 1034 } else { 1035 if (sc->xl_type == XL_TYPE_905B && 1036 sc->xl_media & XL_MEDIAOPT_10FL) 1037 return; 1038 device_printf(sc->xl_dev, 1039 "WARNING: no media options bits set in the media options register!!\n"); 1040 device_printf(sc->xl_dev, 1041 "this could be a manufacturing defect in your adapter or system\n"); 1042 device_printf(sc->xl_dev, 1043 "attempting to guess media type; you should probably consult your vendor\n"); 1044 } 1045 1046 xl_choose_xcvr(sc, 1); 1047 } 1048 1049 static void 1050 xl_choose_xcvr(struct xl_softc *sc, int verbose) 1051 { 1052 u_int16_t devid; 1053 1054 /* 1055 * Read the device ID from the EEPROM. 1056 * This is what's loaded into the PCI device ID register, so it has 1057 * to be correct otherwise we wouldn't have gotten this far. 1058 */ 1059 xl_read_eeprom(sc, (caddr_t)&devid, XL_EE_PRODID, 1, 0); 1060 1061 switch (devid) { 1062 case TC_DEVICEID_BOOMERANG_10BT: /* 3c900-TPO */ 1063 case TC_DEVICEID_KRAKATOA_10BT: /* 3c900B-TPO */ 1064 sc->xl_media = XL_MEDIAOPT_BT; 1065 sc->xl_xcvr = XL_XCVR_10BT; 1066 if (verbose) 1067 device_printf(sc->xl_dev, 1068 "guessing 10BaseT transceiver\n"); 1069 break; 1070 case TC_DEVICEID_BOOMERANG_10BT_COMBO: /* 3c900-COMBO */ 1071 case TC_DEVICEID_KRAKATOA_10BT_COMBO: /* 3c900B-COMBO */ 1072 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI; 1073 sc->xl_xcvr = XL_XCVR_10BT; 1074 if (verbose) 1075 device_printf(sc->xl_dev, 1076 "guessing COMBO (AUI/BNC/TP)\n"); 1077 break; 1078 case TC_DEVICEID_KRAKATOA_10BT_TPC: /* 3c900B-TPC */ 1079 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC; 1080 sc->xl_xcvr = XL_XCVR_10BT; 1081 if (verbose) 1082 device_printf(sc->xl_dev, "guessing TPC (BNC/TP)\n"); 1083 break; 1084 case TC_DEVICEID_CYCLONE_10FL: /* 3c900B-FL */ 1085 sc->xl_media = XL_MEDIAOPT_10FL; 1086 sc->xl_xcvr = XL_XCVR_AUI; 1087 if (verbose) 1088 device_printf(sc->xl_dev, "guessing 10baseFL\n"); 1089 break; 1090 case TC_DEVICEID_BOOMERANG_10_100BT: /* 3c905-TX */ 1091 case TC_DEVICEID_HURRICANE_555: /* 3c555 */ 1092 case TC_DEVICEID_HURRICANE_556: /* 3c556 */ 1093 case TC_DEVICEID_HURRICANE_556B: /* 3c556B */ 1094 case TC_DEVICEID_HURRICANE_575A: /* 3c575TX */ 1095 case TC_DEVICEID_HURRICANE_575B: /* 3c575B */ 1096 case TC_DEVICEID_HURRICANE_575C: /* 3c575C */ 1097 case TC_DEVICEID_HURRICANE_656: /* 3c656 */ 1098 case TC_DEVICEID_HURRICANE_656B: /* 3c656B */ 1099 case TC_DEVICEID_TORNADO_656C: /* 3c656C */ 1100 case TC_DEVICEID_TORNADO_10_100BT_920B: /* 3c920B-EMB */ 1101 case TC_DEVICEID_TORNADO_10_100BT_920B_WNM: /* 3c920B-EMB-WNM */ 1102 sc->xl_media = XL_MEDIAOPT_MII; 1103 sc->xl_xcvr = XL_XCVR_MII; 1104 if (verbose) 1105 device_printf(sc->xl_dev, "guessing MII\n"); 1106 break; 1107 case TC_DEVICEID_BOOMERANG_100BT4: /* 3c905-T4 */ 1108 case TC_DEVICEID_CYCLONE_10_100BT4: /* 3c905B-T4 */ 1109 sc->xl_media = XL_MEDIAOPT_BT4; 1110 sc->xl_xcvr = XL_XCVR_MII; 1111 if (verbose) 1112 device_printf(sc->xl_dev, "guessing 100baseT4/MII\n"); 1113 break; 1114 case TC_DEVICEID_HURRICANE_10_100BT: /* 3c905B-TX */ 1115 case TC_DEVICEID_HURRICANE_10_100BT_SERV:/*3c980-TX */ 1116 case TC_DEVICEID_TORNADO_10_100BT_SERV: /* 3c980C-TX */ 1117 case TC_DEVICEID_HURRICANE_SOHO100TX: /* 3cSOHO100-TX */ 1118 case TC_DEVICEID_TORNADO_10_100BT: /* 3c905C-TX */ 1119 case TC_DEVICEID_TORNADO_HOMECONNECT: /* 3c450-TX */ 1120 sc->xl_media = XL_MEDIAOPT_BTX; 1121 sc->xl_xcvr = XL_XCVR_AUTO; 1122 if (verbose) 1123 device_printf(sc->xl_dev, "guessing 10/100 internal\n"); 1124 break; 1125 case TC_DEVICEID_CYCLONE_10_100_COMBO: /* 3c905B-COMBO */ 1126 sc->xl_media = XL_MEDIAOPT_BTX|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI; 1127 sc->xl_xcvr = XL_XCVR_AUTO; 1128 if (verbose) 1129 device_printf(sc->xl_dev, 1130 "guessing 10/100 plus BNC/AUI\n"); 1131 break; 1132 default: 1133 device_printf(sc->xl_dev, 1134 "unknown device ID: %x -- defaulting to 10baseT\n", devid); 1135 sc->xl_media = XL_MEDIAOPT_BT; 1136 break; 1137 } 1138 } 1139 1140 /* 1141 * Attach the interface. Allocate softc structures, do ifmedia 1142 * setup and ethernet/BPF attach. 1143 */ 1144 static int 1145 xl_attach(device_t dev) 1146 { 1147 u_char eaddr[ETHER_ADDR_LEN]; 1148 u_int16_t xcvr[2]; 1149 struct xl_softc *sc; 1150 struct ifnet *ifp; 1151 int media; 1152 int unit, error = 0, rid, res; 1153 uint16_t did; 1154 1155 sc = device_get_softc(dev); 1156 sc->xl_dev = dev; 1157 1158 unit = device_get_unit(dev); 1159 1160 mtx_init(&sc->xl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1161 MTX_DEF); 1162 ifmedia_init(&sc->ifmedia, 0, xl_ifmedia_upd, xl_ifmedia_sts); 1163 1164 did = pci_get_device(dev); 1165 1166 sc->xl_flags = 0; 1167 if (did == TC_DEVICEID_HURRICANE_555) 1168 sc->xl_flags |= XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_PHYOK; 1169 if (did == TC_DEVICEID_HURRICANE_556 || 1170 did == TC_DEVICEID_HURRICANE_556B) 1171 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK | 1172 XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_WEIRDRESET | 1173 XL_FLAG_INVERT_LED_PWR | XL_FLAG_INVERT_MII_PWR; 1174 if (did == TC_DEVICEID_HURRICANE_555 || 1175 did == TC_DEVICEID_HURRICANE_556) 1176 sc->xl_flags |= XL_FLAG_8BITROM; 1177 if (did == TC_DEVICEID_HURRICANE_556B) 1178 sc->xl_flags |= XL_FLAG_NO_XCVR_PWR; 1179 1180 if (did == TC_DEVICEID_HURRICANE_575B || 1181 did == TC_DEVICEID_HURRICANE_575C || 1182 did == TC_DEVICEID_HURRICANE_656B || 1183 did == TC_DEVICEID_TORNADO_656C) 1184 sc->xl_flags |= XL_FLAG_FUNCREG; 1185 if (did == TC_DEVICEID_HURRICANE_575A || 1186 did == TC_DEVICEID_HURRICANE_575B || 1187 did == TC_DEVICEID_HURRICANE_575C || 1188 did == TC_DEVICEID_HURRICANE_656B || 1189 did == TC_DEVICEID_TORNADO_656C) 1190 sc->xl_flags |= XL_FLAG_PHYOK | XL_FLAG_EEPROM_OFFSET_30 | 1191 XL_FLAG_8BITROM; 1192 if (did == TC_DEVICEID_HURRICANE_656) 1193 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK; 1194 if (did == TC_DEVICEID_HURRICANE_575B) 1195 sc->xl_flags |= XL_FLAG_INVERT_LED_PWR; 1196 if (did == TC_DEVICEID_HURRICANE_575C) 1197 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR; 1198 if (did == TC_DEVICEID_TORNADO_656C) 1199 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR; 1200 if (did == TC_DEVICEID_HURRICANE_656 || 1201 did == TC_DEVICEID_HURRICANE_656B) 1202 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR | 1203 XL_FLAG_INVERT_LED_PWR; 1204 if (did == TC_DEVICEID_TORNADO_10_100BT_920B || 1205 did == TC_DEVICEID_TORNADO_10_100BT_920B_WNM) 1206 sc->xl_flags |= XL_FLAG_PHYOK; 1207 1208 switch (did) { 1209 case TC_DEVICEID_BOOMERANG_10_100BT: /* 3c905-TX */ 1210 case TC_DEVICEID_HURRICANE_575A: 1211 case TC_DEVICEID_HURRICANE_575B: 1212 case TC_DEVICEID_HURRICANE_575C: 1213 sc->xl_flags |= XL_FLAG_NO_MMIO; 1214 break; 1215 default: 1216 break; 1217 } 1218 1219 /* 1220 * Map control/status registers. 1221 */ 1222 pci_enable_busmaster(dev); 1223 1224 if ((sc->xl_flags & XL_FLAG_NO_MMIO) == 0) { 1225 rid = XL_PCI_LOMEM; 1226 res = SYS_RES_MEMORY; 1227 1228 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE); 1229 } 1230 1231 if (sc->xl_res != NULL) { 1232 sc->xl_flags |= XL_FLAG_USE_MMIO; 1233 if (bootverbose) 1234 device_printf(dev, "using memory mapped I/O\n"); 1235 } else { 1236 rid = XL_PCI_LOIO; 1237 res = SYS_RES_IOPORT; 1238 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE); 1239 if (sc->xl_res == NULL) { 1240 device_printf(dev, "couldn't map ports/memory\n"); 1241 error = ENXIO; 1242 goto fail; 1243 } 1244 if (bootverbose) 1245 device_printf(dev, "using port I/O\n"); 1246 } 1247 1248 sc->xl_btag = rman_get_bustag(sc->xl_res); 1249 sc->xl_bhandle = rman_get_bushandle(sc->xl_res); 1250 1251 if (sc->xl_flags & XL_FLAG_FUNCREG) { 1252 rid = XL_PCI_FUNCMEM; 1253 sc->xl_fres = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1254 RF_ACTIVE); 1255 1256 if (sc->xl_fres == NULL) { 1257 device_printf(dev, "couldn't map funcreg memory\n"); 1258 error = ENXIO; 1259 goto fail; 1260 } 1261 1262 sc->xl_ftag = rman_get_bustag(sc->xl_fres); 1263 sc->xl_fhandle = rman_get_bushandle(sc->xl_fres); 1264 } 1265 1266 /* Allocate interrupt */ 1267 rid = 0; 1268 sc->xl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1269 RF_SHAREABLE | RF_ACTIVE); 1270 if (sc->xl_irq == NULL) { 1271 device_printf(dev, "couldn't map interrupt\n"); 1272 error = ENXIO; 1273 goto fail; 1274 } 1275 1276 /* Initialize interface name. */ 1277 ifp = sc->xl_ifp = if_alloc(IFT_ETHER); 1278 if (ifp == NULL) { 1279 device_printf(dev, "can not if_alloc()\n"); 1280 error = ENOSPC; 1281 goto fail; 1282 } 1283 ifp->if_softc = sc; 1284 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1285 1286 /* Reset the adapter. */ 1287 XL_LOCK(sc); 1288 xl_reset(sc); 1289 XL_UNLOCK(sc); 1290 1291 /* 1292 * Get station address from the EEPROM. 1293 */ 1294 if (xl_read_eeprom(sc, (caddr_t)&eaddr, XL_EE_OEM_ADR0, 3, 1)) { 1295 device_printf(dev, "failed to read station address\n"); 1296 error = ENXIO; 1297 goto fail; 1298 } 1299 1300 callout_init_mtx(&sc->xl_stat_callout, &sc->xl_mtx, 0); 1301 TASK_INIT(&sc->xl_task, 0, xl_rxeof_task, sc); 1302 1303 /* 1304 * Now allocate a tag for the DMA descriptor lists and a chunk 1305 * of DMA-able memory based on the tag. Also obtain the DMA 1306 * addresses of the RX and TX ring, which we'll need later. 1307 * All of our lists are allocated as a contiguous block 1308 * of memory. 1309 */ 1310 error = bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0, 1311 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1312 XL_RX_LIST_SZ, 1, XL_RX_LIST_SZ, 0, NULL, NULL, 1313 &sc->xl_ldata.xl_rx_tag); 1314 if (error) { 1315 device_printf(dev, "failed to allocate rx dma tag\n"); 1316 goto fail; 1317 } 1318 1319 error = bus_dmamem_alloc(sc->xl_ldata.xl_rx_tag, 1320 (void **)&sc->xl_ldata.xl_rx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1321 &sc->xl_ldata.xl_rx_dmamap); 1322 if (error) { 1323 device_printf(dev, "no memory for rx list buffers!\n"); 1324 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag); 1325 sc->xl_ldata.xl_rx_tag = NULL; 1326 goto fail; 1327 } 1328 1329 error = bus_dmamap_load(sc->xl_ldata.xl_rx_tag, 1330 sc->xl_ldata.xl_rx_dmamap, sc->xl_ldata.xl_rx_list, 1331 XL_RX_LIST_SZ, xl_dma_map_addr, 1332 &sc->xl_ldata.xl_rx_dmaaddr, BUS_DMA_NOWAIT); 1333 if (error) { 1334 device_printf(dev, "cannot get dma address of the rx ring!\n"); 1335 bus_dmamem_free(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_list, 1336 sc->xl_ldata.xl_rx_dmamap); 1337 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag); 1338 sc->xl_ldata.xl_rx_tag = NULL; 1339 goto fail; 1340 } 1341 1342 error = bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0, 1343 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1344 XL_TX_LIST_SZ, 1, XL_TX_LIST_SZ, 0, NULL, NULL, 1345 &sc->xl_ldata.xl_tx_tag); 1346 if (error) { 1347 device_printf(dev, "failed to allocate tx dma tag\n"); 1348 goto fail; 1349 } 1350 1351 error = bus_dmamem_alloc(sc->xl_ldata.xl_tx_tag, 1352 (void **)&sc->xl_ldata.xl_tx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1353 &sc->xl_ldata.xl_tx_dmamap); 1354 if (error) { 1355 device_printf(dev, "no memory for list buffers!\n"); 1356 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag); 1357 sc->xl_ldata.xl_tx_tag = NULL; 1358 goto fail; 1359 } 1360 1361 error = bus_dmamap_load(sc->xl_ldata.xl_tx_tag, 1362 sc->xl_ldata.xl_tx_dmamap, sc->xl_ldata.xl_tx_list, 1363 XL_TX_LIST_SZ, xl_dma_map_addr, 1364 &sc->xl_ldata.xl_tx_dmaaddr, BUS_DMA_NOWAIT); 1365 if (error) { 1366 device_printf(dev, "cannot get dma address of the tx ring!\n"); 1367 bus_dmamem_free(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_list, 1368 sc->xl_ldata.xl_tx_dmamap); 1369 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag); 1370 sc->xl_ldata.xl_tx_tag = NULL; 1371 goto fail; 1372 } 1373 1374 /* 1375 * Allocate a DMA tag for the mapping of mbufs. 1376 */ 1377 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 1378 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1379 MCLBYTES * XL_MAXFRAGS, XL_MAXFRAGS, MCLBYTES, 0, NULL, 1380 NULL, &sc->xl_mtag); 1381 if (error) { 1382 device_printf(dev, "failed to allocate mbuf dma tag\n"); 1383 goto fail; 1384 } 1385 1386 /* We need a spare DMA map for the RX ring. */ 1387 error = bus_dmamap_create(sc->xl_mtag, 0, &sc->xl_tmpmap); 1388 if (error) 1389 goto fail; 1390 1391 /* 1392 * Figure out the card type. 3c905B adapters have the 1393 * 'supportsNoTxLength' bit set in the capabilities 1394 * word in the EEPROM. 1395 * Note: my 3c575C CardBus card lies. It returns a value 1396 * of 0x1578 for its capabilities word, which is somewhat 1397 * nonsensical. Another way to distinguish a 3c90x chip 1398 * from a 3c90xB/C chip is to check for the 'supportsLargePackets' 1399 * bit. This will only be set for 3c90x boomerage chips. 1400 */ 1401 xl_read_eeprom(sc, (caddr_t)&sc->xl_caps, XL_EE_CAPS, 1, 0); 1402 if (sc->xl_caps & XL_CAPS_NO_TXLENGTH || 1403 !(sc->xl_caps & XL_CAPS_LARGE_PKTS)) 1404 sc->xl_type = XL_TYPE_905B; 1405 else 1406 sc->xl_type = XL_TYPE_90X; 1407 1408 /* Set the TX start threshold for best performance. */ 1409 sc->xl_tx_thresh = XL_MIN_FRAMELEN; 1410 1411 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1412 ifp->if_ioctl = xl_ioctl; 1413 ifp->if_capabilities = IFCAP_VLAN_MTU; 1414 if (sc->xl_type == XL_TYPE_905B) { 1415 ifp->if_hwassist = XL905B_CSUM_FEATURES; 1416 #ifdef XL905B_TXCSUM_BROKEN 1417 ifp->if_capabilities |= IFCAP_RXCSUM; 1418 #else 1419 ifp->if_capabilities |= IFCAP_HWCSUM; 1420 #endif 1421 } 1422 ifp->if_capenable = ifp->if_capabilities; 1423 #ifdef DEVICE_POLLING 1424 ifp->if_capabilities |= IFCAP_POLLING; 1425 #endif 1426 ifp->if_start = xl_start; 1427 ifp->if_init = xl_init; 1428 IFQ_SET_MAXLEN(&ifp->if_snd, XL_TX_LIST_CNT - 1); 1429 ifp->if_snd.ifq_drv_maxlen = XL_TX_LIST_CNT - 1; 1430 IFQ_SET_READY(&ifp->if_snd); 1431 1432 /* 1433 * Now we have to see what sort of media we have. 1434 * This includes probing for an MII interace and a 1435 * possible PHY. 1436 */ 1437 XL_SEL_WIN(3); 1438 sc->xl_media = CSR_READ_2(sc, XL_W3_MEDIA_OPT); 1439 if (bootverbose) 1440 device_printf(dev, "media options word: %x\n", sc->xl_media); 1441 1442 xl_read_eeprom(sc, (char *)&xcvr, XL_EE_ICFG_0, 2, 0); 1443 sc->xl_xcvr = xcvr[0] | xcvr[1] << 16; 1444 sc->xl_xcvr &= XL_ICFG_CONNECTOR_MASK; 1445 sc->xl_xcvr >>= XL_ICFG_CONNECTOR_BITS; 1446 1447 xl_mediacheck(sc); 1448 1449 if (sc->xl_media & XL_MEDIAOPT_MII || 1450 sc->xl_media & XL_MEDIAOPT_BTX || 1451 sc->xl_media & XL_MEDIAOPT_BT4) { 1452 if (bootverbose) 1453 device_printf(dev, "found MII/AUTO\n"); 1454 xl_setcfg(sc); 1455 if (mii_phy_probe(dev, &sc->xl_miibus, 1456 xl_ifmedia_upd, xl_ifmedia_sts)) { 1457 device_printf(dev, "no PHY found!\n"); 1458 error = ENXIO; 1459 goto fail; 1460 } 1461 goto done; 1462 } 1463 1464 /* 1465 * Sanity check. If the user has selected "auto" and this isn't 1466 * a 10/100 card of some kind, we need to force the transceiver 1467 * type to something sane. 1468 */ 1469 if (sc->xl_xcvr == XL_XCVR_AUTO) 1470 xl_choose_xcvr(sc, bootverbose); 1471 1472 /* 1473 * Do ifmedia setup. 1474 */ 1475 if (sc->xl_media & XL_MEDIAOPT_BT) { 1476 if (bootverbose) 1477 device_printf(dev, "found 10baseT\n"); 1478 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 1479 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL); 1480 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 1481 ifmedia_add(&sc->ifmedia, 1482 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 1483 } 1484 1485 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) { 1486 /* 1487 * Check for a 10baseFL board in disguise. 1488 */ 1489 if (sc->xl_type == XL_TYPE_905B && 1490 sc->xl_media == XL_MEDIAOPT_10FL) { 1491 if (bootverbose) 1492 device_printf(dev, "found 10baseFL\n"); 1493 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL, 0, NULL); 1494 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL|IFM_HDX, 1495 0, NULL); 1496 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 1497 ifmedia_add(&sc->ifmedia, 1498 IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL); 1499 } else { 1500 if (bootverbose) 1501 device_printf(dev, "found AUI\n"); 1502 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL); 1503 } 1504 } 1505 1506 if (sc->xl_media & XL_MEDIAOPT_BNC) { 1507 if (bootverbose) 1508 device_printf(dev, "found BNC\n"); 1509 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_2, 0, NULL); 1510 } 1511 1512 if (sc->xl_media & XL_MEDIAOPT_BFX) { 1513 if (bootverbose) 1514 device_printf(dev, "found 100baseFX\n"); 1515 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX, 0, NULL); 1516 } 1517 1518 media = IFM_ETHER|IFM_100_TX|IFM_FDX; 1519 xl_choose_media(sc, &media); 1520 1521 if (sc->xl_miibus == NULL) 1522 ifmedia_set(&sc->ifmedia, media); 1523 1524 done: 1525 if (sc->xl_flags & XL_FLAG_NO_XCVR_PWR) { 1526 XL_SEL_WIN(0); 1527 CSR_WRITE_2(sc, XL_W0_MFG_ID, XL_NO_XCVR_PWR_MAGICBITS); 1528 } 1529 1530 /* 1531 * Call MI attach routine. 1532 */ 1533 ether_ifattach(ifp, eaddr); 1534 1535 error = bus_setup_intr(dev, sc->xl_irq, INTR_TYPE_NET | INTR_MPSAFE, 1536 NULL, xl_intr, sc, &sc->xl_intrhand); 1537 if (error) { 1538 device_printf(dev, "couldn't set up irq\n"); 1539 ether_ifdetach(ifp); 1540 goto fail; 1541 } 1542 1543 fail: 1544 if (error) 1545 xl_detach(dev); 1546 1547 return (error); 1548 } 1549 1550 /* 1551 * Choose a default media. 1552 * XXX This is a leaf function only called by xl_attach() and 1553 * acquires/releases the non-recursible driver mutex to 1554 * satisfy lock assertions. 1555 */ 1556 static void 1557 xl_choose_media(struct xl_softc *sc, int *media) 1558 { 1559 1560 XL_LOCK(sc); 1561 1562 switch (sc->xl_xcvr) { 1563 case XL_XCVR_10BT: 1564 *media = IFM_ETHER|IFM_10_T; 1565 xl_setmode(sc, *media); 1566 break; 1567 case XL_XCVR_AUI: 1568 if (sc->xl_type == XL_TYPE_905B && 1569 sc->xl_media == XL_MEDIAOPT_10FL) { 1570 *media = IFM_ETHER|IFM_10_FL; 1571 xl_setmode(sc, *media); 1572 } else { 1573 *media = IFM_ETHER|IFM_10_5; 1574 xl_setmode(sc, *media); 1575 } 1576 break; 1577 case XL_XCVR_COAX: 1578 *media = IFM_ETHER|IFM_10_2; 1579 xl_setmode(sc, *media); 1580 break; 1581 case XL_XCVR_AUTO: 1582 case XL_XCVR_100BTX: 1583 case XL_XCVR_MII: 1584 /* Chosen by miibus */ 1585 break; 1586 case XL_XCVR_100BFX: 1587 *media = IFM_ETHER|IFM_100_FX; 1588 break; 1589 default: 1590 device_printf(sc->xl_dev, "unknown XCVR type: %d\n", 1591 sc->xl_xcvr); 1592 /* 1593 * This will probably be wrong, but it prevents 1594 * the ifmedia code from panicking. 1595 */ 1596 *media = IFM_ETHER|IFM_10_T; 1597 break; 1598 } 1599 1600 XL_UNLOCK(sc); 1601 } 1602 1603 /* 1604 * Shutdown hardware and free up resources. This can be called any 1605 * time after the mutex has been initialized. It is called in both 1606 * the error case in attach and the normal detach case so it needs 1607 * to be careful about only freeing resources that have actually been 1608 * allocated. 1609 */ 1610 static int 1611 xl_detach(device_t dev) 1612 { 1613 struct xl_softc *sc; 1614 struct ifnet *ifp; 1615 int rid, res; 1616 1617 sc = device_get_softc(dev); 1618 ifp = sc->xl_ifp; 1619 1620 KASSERT(mtx_initialized(&sc->xl_mtx), ("xl mutex not initialized")); 1621 1622 #ifdef DEVICE_POLLING 1623 if (ifp && ifp->if_capenable & IFCAP_POLLING) 1624 ether_poll_deregister(ifp); 1625 #endif 1626 1627 if (sc->xl_flags & XL_FLAG_USE_MMIO) { 1628 rid = XL_PCI_LOMEM; 1629 res = SYS_RES_MEMORY; 1630 } else { 1631 rid = XL_PCI_LOIO; 1632 res = SYS_RES_IOPORT; 1633 } 1634 1635 /* These should only be active if attach succeeded */ 1636 if (device_is_attached(dev)) { 1637 XL_LOCK(sc); 1638 xl_reset(sc); 1639 xl_stop(sc); 1640 XL_UNLOCK(sc); 1641 taskqueue_drain(taskqueue_swi, &sc->xl_task); 1642 callout_drain(&sc->xl_stat_callout); 1643 ether_ifdetach(ifp); 1644 } 1645 if (sc->xl_miibus) 1646 device_delete_child(dev, sc->xl_miibus); 1647 bus_generic_detach(dev); 1648 ifmedia_removeall(&sc->ifmedia); 1649 1650 if (sc->xl_intrhand) 1651 bus_teardown_intr(dev, sc->xl_irq, sc->xl_intrhand); 1652 if (sc->xl_irq) 1653 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq); 1654 if (sc->xl_fres != NULL) 1655 bus_release_resource(dev, SYS_RES_MEMORY, 1656 XL_PCI_FUNCMEM, sc->xl_fres); 1657 if (sc->xl_res) 1658 bus_release_resource(dev, res, rid, sc->xl_res); 1659 1660 if (ifp) 1661 if_free(ifp); 1662 1663 if (sc->xl_mtag) { 1664 bus_dmamap_destroy(sc->xl_mtag, sc->xl_tmpmap); 1665 bus_dma_tag_destroy(sc->xl_mtag); 1666 } 1667 if (sc->xl_ldata.xl_rx_tag) { 1668 bus_dmamap_unload(sc->xl_ldata.xl_rx_tag, 1669 sc->xl_ldata.xl_rx_dmamap); 1670 bus_dmamem_free(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_list, 1671 sc->xl_ldata.xl_rx_dmamap); 1672 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag); 1673 } 1674 if (sc->xl_ldata.xl_tx_tag) { 1675 bus_dmamap_unload(sc->xl_ldata.xl_tx_tag, 1676 sc->xl_ldata.xl_tx_dmamap); 1677 bus_dmamem_free(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_list, 1678 sc->xl_ldata.xl_tx_dmamap); 1679 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag); 1680 } 1681 1682 mtx_destroy(&sc->xl_mtx); 1683 1684 return (0); 1685 } 1686 1687 /* 1688 * Initialize the transmit descriptors. 1689 */ 1690 static int 1691 xl_list_tx_init(struct xl_softc *sc) 1692 { 1693 struct xl_chain_data *cd; 1694 struct xl_list_data *ld; 1695 int error, i; 1696 1697 XL_LOCK_ASSERT(sc); 1698 1699 cd = &sc->xl_cdata; 1700 ld = &sc->xl_ldata; 1701 for (i = 0; i < XL_TX_LIST_CNT; i++) { 1702 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i]; 1703 error = bus_dmamap_create(sc->xl_mtag, 0, 1704 &cd->xl_tx_chain[i].xl_map); 1705 if (error) 1706 return (error); 1707 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr + 1708 i * sizeof(struct xl_list); 1709 if (i == (XL_TX_LIST_CNT - 1)) 1710 cd->xl_tx_chain[i].xl_next = NULL; 1711 else 1712 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1]; 1713 } 1714 1715 cd->xl_tx_free = &cd->xl_tx_chain[0]; 1716 cd->xl_tx_tail = cd->xl_tx_head = NULL; 1717 1718 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE); 1719 return (0); 1720 } 1721 1722 /* 1723 * Initialize the transmit descriptors. 1724 */ 1725 static int 1726 xl_list_tx_init_90xB(struct xl_softc *sc) 1727 { 1728 struct xl_chain_data *cd; 1729 struct xl_list_data *ld; 1730 int error, i; 1731 1732 XL_LOCK_ASSERT(sc); 1733 1734 cd = &sc->xl_cdata; 1735 ld = &sc->xl_ldata; 1736 for (i = 0; i < XL_TX_LIST_CNT; i++) { 1737 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i]; 1738 error = bus_dmamap_create(sc->xl_mtag, 0, 1739 &cd->xl_tx_chain[i].xl_map); 1740 if (error) 1741 return (error); 1742 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr + 1743 i * sizeof(struct xl_list); 1744 if (i == (XL_TX_LIST_CNT - 1)) 1745 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[0]; 1746 else 1747 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1]; 1748 if (i == 0) 1749 cd->xl_tx_chain[i].xl_prev = 1750 &cd->xl_tx_chain[XL_TX_LIST_CNT - 1]; 1751 else 1752 cd->xl_tx_chain[i].xl_prev = 1753 &cd->xl_tx_chain[i - 1]; 1754 } 1755 1756 bzero(ld->xl_tx_list, XL_TX_LIST_SZ); 1757 ld->xl_tx_list[0].xl_status = htole32(XL_TXSTAT_EMPTY); 1758 1759 cd->xl_tx_prod = 1; 1760 cd->xl_tx_cons = 1; 1761 cd->xl_tx_cnt = 0; 1762 1763 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE); 1764 return (0); 1765 } 1766 1767 /* 1768 * Initialize the RX descriptors and allocate mbufs for them. Note that 1769 * we arrange the descriptors in a closed ring, so that the last descriptor 1770 * points back to the first. 1771 */ 1772 static int 1773 xl_list_rx_init(struct xl_softc *sc) 1774 { 1775 struct xl_chain_data *cd; 1776 struct xl_list_data *ld; 1777 int error, i, next; 1778 u_int32_t nextptr; 1779 1780 XL_LOCK_ASSERT(sc); 1781 1782 cd = &sc->xl_cdata; 1783 ld = &sc->xl_ldata; 1784 1785 for (i = 0; i < XL_RX_LIST_CNT; i++) { 1786 cd->xl_rx_chain[i].xl_ptr = &ld->xl_rx_list[i]; 1787 error = bus_dmamap_create(sc->xl_mtag, 0, 1788 &cd->xl_rx_chain[i].xl_map); 1789 if (error) 1790 return (error); 1791 error = xl_newbuf(sc, &cd->xl_rx_chain[i]); 1792 if (error) 1793 return (error); 1794 if (i == (XL_RX_LIST_CNT - 1)) 1795 next = 0; 1796 else 1797 next = i + 1; 1798 nextptr = ld->xl_rx_dmaaddr + 1799 next * sizeof(struct xl_list_onefrag); 1800 cd->xl_rx_chain[i].xl_next = &cd->xl_rx_chain[next]; 1801 ld->xl_rx_list[i].xl_next = htole32(nextptr); 1802 } 1803 1804 bus_dmamap_sync(ld->xl_rx_tag, ld->xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 1805 cd->xl_rx_head = &cd->xl_rx_chain[0]; 1806 1807 return (0); 1808 } 1809 1810 /* 1811 * Initialize an RX descriptor and attach an MBUF cluster. 1812 * If we fail to do so, we need to leave the old mbuf and 1813 * the old DMA map untouched so that it can be reused. 1814 */ 1815 static int 1816 xl_newbuf(struct xl_softc *sc, struct xl_chain_onefrag *c) 1817 { 1818 struct mbuf *m_new = NULL; 1819 bus_dmamap_t map; 1820 bus_dma_segment_t segs[1]; 1821 int error, nseg; 1822 1823 XL_LOCK_ASSERT(sc); 1824 1825 m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1826 if (m_new == NULL) 1827 return (ENOBUFS); 1828 1829 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1830 1831 /* Force longword alignment for packet payload. */ 1832 m_adj(m_new, ETHER_ALIGN); 1833 1834 error = bus_dmamap_load_mbuf_sg(sc->xl_mtag, sc->xl_tmpmap, m_new, 1835 segs, &nseg, BUS_DMA_NOWAIT); 1836 if (error) { 1837 m_freem(m_new); 1838 device_printf(sc->xl_dev, "can't map mbuf (error %d)\n", 1839 error); 1840 return (error); 1841 } 1842 KASSERT(nseg == 1, 1843 ("%s: too many DMA segments (%d)", __func__, nseg)); 1844 1845 bus_dmamap_unload(sc->xl_mtag, c->xl_map); 1846 map = c->xl_map; 1847 c->xl_map = sc->xl_tmpmap; 1848 sc->xl_tmpmap = map; 1849 c->xl_mbuf = m_new; 1850 c->xl_ptr->xl_frag.xl_len = htole32(m_new->m_len | XL_LAST_FRAG); 1851 c->xl_ptr->xl_status = 0; 1852 c->xl_ptr->xl_frag.xl_addr = htole32(segs->ds_addr); 1853 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREREAD); 1854 return (0); 1855 } 1856 1857 static int 1858 xl_rx_resync(struct xl_softc *sc) 1859 { 1860 struct xl_chain_onefrag *pos; 1861 int i; 1862 1863 XL_LOCK_ASSERT(sc); 1864 1865 pos = sc->xl_cdata.xl_rx_head; 1866 1867 for (i = 0; i < XL_RX_LIST_CNT; i++) { 1868 if (pos->xl_ptr->xl_status) 1869 break; 1870 pos = pos->xl_next; 1871 } 1872 1873 if (i == XL_RX_LIST_CNT) 1874 return (0); 1875 1876 sc->xl_cdata.xl_rx_head = pos; 1877 1878 return (EAGAIN); 1879 } 1880 1881 /* 1882 * A frame has been uploaded: pass the resulting mbuf chain up to 1883 * the higher level protocols. 1884 */ 1885 static int 1886 xl_rxeof(struct xl_softc *sc) 1887 { 1888 struct mbuf *m; 1889 struct ifnet *ifp = sc->xl_ifp; 1890 struct xl_chain_onefrag *cur_rx; 1891 int total_len = 0; 1892 int rx_npkts = 0; 1893 u_int32_t rxstat; 1894 1895 XL_LOCK_ASSERT(sc); 1896 again: 1897 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_dmamap, 1898 BUS_DMASYNC_POSTREAD); 1899 while ((rxstat = le32toh(sc->xl_cdata.xl_rx_head->xl_ptr->xl_status))) { 1900 #ifdef DEVICE_POLLING 1901 if (ifp->if_capenable & IFCAP_POLLING) { 1902 if (sc->rxcycles <= 0) 1903 break; 1904 sc->rxcycles--; 1905 } 1906 #endif 1907 cur_rx = sc->xl_cdata.xl_rx_head; 1908 sc->xl_cdata.xl_rx_head = cur_rx->xl_next; 1909 total_len = rxstat & XL_RXSTAT_LENMASK; 1910 1911 /* 1912 * Since we have told the chip to allow large frames, 1913 * we need to trap giant frame errors in software. We allow 1914 * a little more than the normal frame size to account for 1915 * frames with VLAN tags. 1916 */ 1917 if (total_len > XL_MAX_FRAMELEN) 1918 rxstat |= (XL_RXSTAT_UP_ERROR|XL_RXSTAT_OVERSIZE); 1919 1920 /* 1921 * If an error occurs, update stats, clear the 1922 * status word and leave the mbuf cluster in place: 1923 * it should simply get re-used next time this descriptor 1924 * comes up in the ring. 1925 */ 1926 if (rxstat & XL_RXSTAT_UP_ERROR) { 1927 ifp->if_ierrors++; 1928 cur_rx->xl_ptr->xl_status = 0; 1929 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 1930 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 1931 continue; 1932 } 1933 1934 /* 1935 * If the error bit was not set, the upload complete 1936 * bit should be set which means we have a valid packet. 1937 * If not, something truly strange has happened. 1938 */ 1939 if (!(rxstat & XL_RXSTAT_UP_CMPLT)) { 1940 device_printf(sc->xl_dev, 1941 "bad receive status -- packet dropped\n"); 1942 ifp->if_ierrors++; 1943 cur_rx->xl_ptr->xl_status = 0; 1944 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 1945 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 1946 continue; 1947 } 1948 1949 /* No errors; receive the packet. */ 1950 bus_dmamap_sync(sc->xl_mtag, cur_rx->xl_map, 1951 BUS_DMASYNC_POSTREAD); 1952 m = cur_rx->xl_mbuf; 1953 1954 /* 1955 * Try to conjure up a new mbuf cluster. If that 1956 * fails, it means we have an out of memory condition and 1957 * should leave the buffer in place and continue. This will 1958 * result in a lost packet, but there's little else we 1959 * can do in this situation. 1960 */ 1961 if (xl_newbuf(sc, cur_rx)) { 1962 ifp->if_ierrors++; 1963 cur_rx->xl_ptr->xl_status = 0; 1964 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 1965 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 1966 continue; 1967 } 1968 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 1969 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 1970 1971 ifp->if_ipackets++; 1972 m->m_pkthdr.rcvif = ifp; 1973 m->m_pkthdr.len = m->m_len = total_len; 1974 1975 if (ifp->if_capenable & IFCAP_RXCSUM) { 1976 /* Do IP checksum checking. */ 1977 if (rxstat & XL_RXSTAT_IPCKOK) 1978 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1979 if (!(rxstat & XL_RXSTAT_IPCKERR)) 1980 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1981 if ((rxstat & XL_RXSTAT_TCPCOK && 1982 !(rxstat & XL_RXSTAT_TCPCKERR)) || 1983 (rxstat & XL_RXSTAT_UDPCKOK && 1984 !(rxstat & XL_RXSTAT_UDPCKERR))) { 1985 m->m_pkthdr.csum_flags |= 1986 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1987 m->m_pkthdr.csum_data = 0xffff; 1988 } 1989 } 1990 1991 XL_UNLOCK(sc); 1992 (*ifp->if_input)(ifp, m); 1993 XL_LOCK(sc); 1994 rx_npkts++; 1995 1996 /* 1997 * If we are running from the taskqueue, the interface 1998 * might have been stopped while we were passing the last 1999 * packet up the network stack. 2000 */ 2001 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 2002 return (rx_npkts); 2003 } 2004 2005 /* 2006 * Handle the 'end of channel' condition. When the upload 2007 * engine hits the end of the RX ring, it will stall. This 2008 * is our cue to flush the RX ring, reload the uplist pointer 2009 * register and unstall the engine. 2010 * XXX This is actually a little goofy. With the ThunderLAN 2011 * chip, you get an interrupt when the receiver hits the end 2012 * of the receive ring, which tells you exactly when you 2013 * you need to reload the ring pointer. Here we have to 2014 * fake it. I'm mad at myself for not being clever enough 2015 * to avoid the use of a goto here. 2016 */ 2017 if (CSR_READ_4(sc, XL_UPLIST_PTR) == 0 || 2018 CSR_READ_4(sc, XL_UPLIST_STATUS) & XL_PKTSTAT_UP_STALLED) { 2019 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL); 2020 xl_wait(sc); 2021 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr); 2022 sc->xl_cdata.xl_rx_head = &sc->xl_cdata.xl_rx_chain[0]; 2023 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL); 2024 goto again; 2025 } 2026 return (rx_npkts); 2027 } 2028 2029 /* 2030 * Taskqueue wrapper for xl_rxeof(). 2031 */ 2032 static void 2033 xl_rxeof_task(void *arg, int pending) 2034 { 2035 struct xl_softc *sc = (struct xl_softc *)arg; 2036 2037 XL_LOCK(sc); 2038 if (sc->xl_ifp->if_drv_flags & IFF_DRV_RUNNING) 2039 xl_rxeof(sc); 2040 XL_UNLOCK(sc); 2041 } 2042 2043 /* 2044 * A frame was downloaded to the chip. It's safe for us to clean up 2045 * the list buffers. 2046 */ 2047 static void 2048 xl_txeof(struct xl_softc *sc) 2049 { 2050 struct xl_chain *cur_tx; 2051 struct ifnet *ifp = sc->xl_ifp; 2052 2053 XL_LOCK_ASSERT(sc); 2054 2055 /* 2056 * Go through our tx list and free mbufs for those 2057 * frames that have been uploaded. Note: the 3c905B 2058 * sets a special bit in the status word to let us 2059 * know that a frame has been downloaded, but the 2060 * original 3c900/3c905 adapters don't do that. 2061 * Consequently, we have to use a different test if 2062 * xl_type != XL_TYPE_905B. 2063 */ 2064 while (sc->xl_cdata.xl_tx_head != NULL) { 2065 cur_tx = sc->xl_cdata.xl_tx_head; 2066 2067 if (CSR_READ_4(sc, XL_DOWNLIST_PTR)) 2068 break; 2069 2070 sc->xl_cdata.xl_tx_head = cur_tx->xl_next; 2071 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map, 2072 BUS_DMASYNC_POSTWRITE); 2073 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map); 2074 m_freem(cur_tx->xl_mbuf); 2075 cur_tx->xl_mbuf = NULL; 2076 ifp->if_opackets++; 2077 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2078 2079 cur_tx->xl_next = sc->xl_cdata.xl_tx_free; 2080 sc->xl_cdata.xl_tx_free = cur_tx; 2081 } 2082 2083 if (sc->xl_cdata.xl_tx_head == NULL) { 2084 sc->xl_wdog_timer = 0; 2085 sc->xl_cdata.xl_tx_tail = NULL; 2086 } else { 2087 if (CSR_READ_4(sc, XL_DMACTL) & XL_DMACTL_DOWN_STALLED || 2088 !CSR_READ_4(sc, XL_DOWNLIST_PTR)) { 2089 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2090 sc->xl_cdata.xl_tx_head->xl_phys); 2091 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2092 } 2093 } 2094 } 2095 2096 static void 2097 xl_txeof_90xB(struct xl_softc *sc) 2098 { 2099 struct xl_chain *cur_tx = NULL; 2100 struct ifnet *ifp = sc->xl_ifp; 2101 int idx; 2102 2103 XL_LOCK_ASSERT(sc); 2104 2105 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap, 2106 BUS_DMASYNC_POSTREAD); 2107 idx = sc->xl_cdata.xl_tx_cons; 2108 while (idx != sc->xl_cdata.xl_tx_prod) { 2109 cur_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2110 2111 if (!(le32toh(cur_tx->xl_ptr->xl_status) & 2112 XL_TXSTAT_DL_COMPLETE)) 2113 break; 2114 2115 if (cur_tx->xl_mbuf != NULL) { 2116 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map, 2117 BUS_DMASYNC_POSTWRITE); 2118 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map); 2119 m_freem(cur_tx->xl_mbuf); 2120 cur_tx->xl_mbuf = NULL; 2121 } 2122 2123 ifp->if_opackets++; 2124 2125 sc->xl_cdata.xl_tx_cnt--; 2126 XL_INC(idx, XL_TX_LIST_CNT); 2127 } 2128 2129 if (sc->xl_cdata.xl_tx_cnt == 0) 2130 sc->xl_wdog_timer = 0; 2131 sc->xl_cdata.xl_tx_cons = idx; 2132 2133 if (cur_tx != NULL) 2134 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2135 } 2136 2137 /* 2138 * TX 'end of channel' interrupt handler. Actually, we should 2139 * only get a 'TX complete' interrupt if there's a transmit error, 2140 * so this is really TX error handler. 2141 */ 2142 static void 2143 xl_txeoc(struct xl_softc *sc) 2144 { 2145 u_int8_t txstat; 2146 2147 XL_LOCK_ASSERT(sc); 2148 2149 while ((txstat = CSR_READ_1(sc, XL_TX_STATUS))) { 2150 if (txstat & XL_TXSTATUS_UNDERRUN || 2151 txstat & XL_TXSTATUS_JABBER || 2152 txstat & XL_TXSTATUS_RECLAIM) { 2153 device_printf(sc->xl_dev, 2154 "transmission error: %x\n", txstat); 2155 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2156 xl_wait(sc); 2157 if (sc->xl_type == XL_TYPE_905B) { 2158 if (sc->xl_cdata.xl_tx_cnt) { 2159 int i; 2160 struct xl_chain *c; 2161 2162 i = sc->xl_cdata.xl_tx_cons; 2163 c = &sc->xl_cdata.xl_tx_chain[i]; 2164 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2165 c->xl_phys); 2166 CSR_WRITE_1(sc, XL_DOWN_POLL, 64); 2167 } 2168 } else { 2169 if (sc->xl_cdata.xl_tx_head != NULL) 2170 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2171 sc->xl_cdata.xl_tx_head->xl_phys); 2172 } 2173 /* 2174 * Remember to set this for the 2175 * first generation 3c90X chips. 2176 */ 2177 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8); 2178 if (txstat & XL_TXSTATUS_UNDERRUN && 2179 sc->xl_tx_thresh < XL_PACKET_SIZE) { 2180 sc->xl_tx_thresh += XL_MIN_FRAMELEN; 2181 device_printf(sc->xl_dev, 2182 "tx underrun, increasing tx start threshold to %d bytes\n", sc->xl_tx_thresh); 2183 } 2184 CSR_WRITE_2(sc, XL_COMMAND, 2185 XL_CMD_TX_SET_START|sc->xl_tx_thresh); 2186 if (sc->xl_type == XL_TYPE_905B) { 2187 CSR_WRITE_2(sc, XL_COMMAND, 2188 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4)); 2189 } 2190 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2191 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2192 } else { 2193 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2194 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2195 } 2196 /* 2197 * Write an arbitrary byte to the TX_STATUS register 2198 * to clear this interrupt/error and advance to the next. 2199 */ 2200 CSR_WRITE_1(sc, XL_TX_STATUS, 0x01); 2201 } 2202 } 2203 2204 static void 2205 xl_intr(void *arg) 2206 { 2207 struct xl_softc *sc = arg; 2208 struct ifnet *ifp = sc->xl_ifp; 2209 u_int16_t status; 2210 2211 XL_LOCK(sc); 2212 2213 #ifdef DEVICE_POLLING 2214 if (ifp->if_capenable & IFCAP_POLLING) { 2215 XL_UNLOCK(sc); 2216 return; 2217 } 2218 #endif 2219 2220 while ((status = CSR_READ_2(sc, XL_STATUS)) & XL_INTRS && 2221 status != 0xFFFF) { 2222 CSR_WRITE_2(sc, XL_COMMAND, 2223 XL_CMD_INTR_ACK|(status & XL_INTRS)); 2224 2225 if (status & XL_STAT_UP_COMPLETE) { 2226 int curpkts; 2227 2228 curpkts = ifp->if_ipackets; 2229 xl_rxeof(sc); 2230 if (curpkts == ifp->if_ipackets) { 2231 while (xl_rx_resync(sc)) 2232 xl_rxeof(sc); 2233 } 2234 } 2235 2236 if (status & XL_STAT_DOWN_COMPLETE) { 2237 if (sc->xl_type == XL_TYPE_905B) 2238 xl_txeof_90xB(sc); 2239 else 2240 xl_txeof(sc); 2241 } 2242 2243 if (status & XL_STAT_TX_COMPLETE) { 2244 ifp->if_oerrors++; 2245 xl_txeoc(sc); 2246 } 2247 2248 if (status & XL_STAT_ADFAIL) { 2249 xl_reset(sc); 2250 xl_init_locked(sc); 2251 } 2252 2253 if (status & XL_STAT_STATSOFLOW) { 2254 sc->xl_stats_no_timeout = 1; 2255 xl_stats_update_locked(sc); 2256 sc->xl_stats_no_timeout = 0; 2257 } 2258 } 2259 2260 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 2261 if (sc->xl_type == XL_TYPE_905B) 2262 xl_start_90xB_locked(ifp); 2263 else 2264 xl_start_locked(ifp); 2265 } 2266 2267 XL_UNLOCK(sc); 2268 } 2269 2270 #ifdef DEVICE_POLLING 2271 static int 2272 xl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 2273 { 2274 struct xl_softc *sc = ifp->if_softc; 2275 int rx_npkts = 0; 2276 2277 XL_LOCK(sc); 2278 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2279 rx_npkts = xl_poll_locked(ifp, cmd, count); 2280 XL_UNLOCK(sc); 2281 return (rx_npkts); 2282 } 2283 2284 static int 2285 xl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 2286 { 2287 struct xl_softc *sc = ifp->if_softc; 2288 int rx_npkts; 2289 2290 XL_LOCK_ASSERT(sc); 2291 2292 sc->rxcycles = count; 2293 rx_npkts = xl_rxeof(sc); 2294 if (sc->xl_type == XL_TYPE_905B) 2295 xl_txeof_90xB(sc); 2296 else 2297 xl_txeof(sc); 2298 2299 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 2300 if (sc->xl_type == XL_TYPE_905B) 2301 xl_start_90xB_locked(ifp); 2302 else 2303 xl_start_locked(ifp); 2304 } 2305 2306 if (cmd == POLL_AND_CHECK_STATUS) { 2307 u_int16_t status; 2308 2309 status = CSR_READ_2(sc, XL_STATUS); 2310 if (status & XL_INTRS && status != 0xFFFF) { 2311 CSR_WRITE_2(sc, XL_COMMAND, 2312 XL_CMD_INTR_ACK|(status & XL_INTRS)); 2313 2314 if (status & XL_STAT_TX_COMPLETE) { 2315 ifp->if_oerrors++; 2316 xl_txeoc(sc); 2317 } 2318 2319 if (status & XL_STAT_ADFAIL) { 2320 xl_reset(sc); 2321 xl_init_locked(sc); 2322 } 2323 2324 if (status & XL_STAT_STATSOFLOW) { 2325 sc->xl_stats_no_timeout = 1; 2326 xl_stats_update_locked(sc); 2327 sc->xl_stats_no_timeout = 0; 2328 } 2329 } 2330 } 2331 return (rx_npkts); 2332 } 2333 #endif /* DEVICE_POLLING */ 2334 2335 /* 2336 * XXX: This is an entry point for callout which needs to take the lock. 2337 */ 2338 static void 2339 xl_stats_update(void *xsc) 2340 { 2341 struct xl_softc *sc = xsc; 2342 2343 XL_LOCK_ASSERT(sc); 2344 2345 if (xl_watchdog(sc) == EJUSTRETURN) 2346 return; 2347 2348 xl_stats_update_locked(sc); 2349 } 2350 2351 static void 2352 xl_stats_update_locked(struct xl_softc *sc) 2353 { 2354 struct ifnet *ifp = sc->xl_ifp; 2355 struct xl_stats xl_stats; 2356 u_int8_t *p; 2357 int i; 2358 struct mii_data *mii = NULL; 2359 2360 XL_LOCK_ASSERT(sc); 2361 2362 bzero((char *)&xl_stats, sizeof(struct xl_stats)); 2363 2364 if (sc->xl_miibus != NULL) 2365 mii = device_get_softc(sc->xl_miibus); 2366 2367 p = (u_int8_t *)&xl_stats; 2368 2369 /* Read all the stats registers. */ 2370 XL_SEL_WIN(6); 2371 2372 for (i = 0; i < 16; i++) 2373 *p++ = CSR_READ_1(sc, XL_W6_CARRIER_LOST + i); 2374 2375 ifp->if_ierrors += xl_stats.xl_rx_overrun; 2376 2377 ifp->if_collisions += xl_stats.xl_tx_multi_collision + 2378 xl_stats.xl_tx_single_collision + xl_stats.xl_tx_late_collision; 2379 2380 /* 2381 * Boomerang and cyclone chips have an extra stats counter 2382 * in window 4 (BadSSD). We have to read this too in order 2383 * to clear out all the stats registers and avoid a statsoflow 2384 * interrupt. 2385 */ 2386 XL_SEL_WIN(4); 2387 CSR_READ_1(sc, XL_W4_BADSSD); 2388 2389 if ((mii != NULL) && (!sc->xl_stats_no_timeout)) 2390 mii_tick(mii); 2391 2392 XL_SEL_WIN(7); 2393 2394 if (!sc->xl_stats_no_timeout) 2395 callout_reset(&sc->xl_stat_callout, hz, xl_stats_update, sc); 2396 } 2397 2398 /* 2399 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 2400 * pointers to the fragment pointers. 2401 */ 2402 static int 2403 xl_encap(struct xl_softc *sc, struct xl_chain *c, struct mbuf **m_head) 2404 { 2405 struct mbuf *m_new; 2406 struct ifnet *ifp = sc->xl_ifp; 2407 int error, i, nseg, total_len; 2408 u_int32_t status; 2409 2410 XL_LOCK_ASSERT(sc); 2411 2412 error = bus_dmamap_load_mbuf_sg(sc->xl_mtag, c->xl_map, *m_head, 2413 sc->xl_cdata.xl_tx_segs, &nseg, BUS_DMA_NOWAIT); 2414 2415 if (error && error != EFBIG) { 2416 if_printf(ifp, "can't map mbuf (error %d)\n", error); 2417 return (error); 2418 } 2419 2420 /* 2421 * Handle special case: we used up all 63 fragments, 2422 * but we have more mbufs left in the chain. Copy the 2423 * data into an mbuf cluster. Note that we don't 2424 * bother clearing the values in the other fragment 2425 * pointers/counters; it wouldn't gain us anything, 2426 * and would waste cycles. 2427 */ 2428 if (error) { 2429 m_new = m_collapse(*m_head, M_DONTWAIT, XL_MAXFRAGS); 2430 if (m_new == NULL) { 2431 m_freem(*m_head); 2432 *m_head = NULL; 2433 return (ENOBUFS); 2434 } 2435 *m_head = m_new; 2436 2437 error = bus_dmamap_load_mbuf_sg(sc->xl_mtag, c->xl_map, 2438 *m_head, sc->xl_cdata.xl_tx_segs, &nseg, BUS_DMA_NOWAIT); 2439 if (error) { 2440 m_freem(*m_head); 2441 *m_head = NULL; 2442 if_printf(ifp, "can't map mbuf (error %d)\n", error); 2443 return (error); 2444 } 2445 } 2446 2447 KASSERT(nseg <= XL_MAXFRAGS, 2448 ("%s: too many DMA segments (%d)", __func__, nseg)); 2449 if (nseg == 0) { 2450 m_freem(*m_head); 2451 *m_head = NULL; 2452 return (EIO); 2453 } 2454 2455 total_len = 0; 2456 for (i = 0; i < nseg; i++) { 2457 KASSERT(sc->xl_cdata.xl_tx_segs[i].ds_len <= MCLBYTES, 2458 ("segment size too large")); 2459 c->xl_ptr->xl_frag[i].xl_addr = 2460 htole32(sc->xl_cdata.xl_tx_segs[i].ds_addr); 2461 c->xl_ptr->xl_frag[i].xl_len = 2462 htole32(sc->xl_cdata.xl_tx_segs[i].ds_len); 2463 total_len += sc->xl_cdata.xl_tx_segs[i].ds_len; 2464 } 2465 c->xl_ptr->xl_frag[nseg - 1].xl_len = 2466 htole32(sc->xl_cdata.xl_tx_segs[nseg - 1].ds_len | XL_LAST_FRAG); 2467 c->xl_ptr->xl_status = htole32(total_len); 2468 c->xl_ptr->xl_next = 0; 2469 2470 if (sc->xl_type == XL_TYPE_905B) { 2471 status = XL_TXSTAT_RND_DEFEAT; 2472 2473 #ifndef XL905B_TXCSUM_BROKEN 2474 if ((*m_head)->m_pkthdr.csum_flags) { 2475 if ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) 2476 status |= XL_TXSTAT_IPCKSUM; 2477 if ((*m_head)->m_pkthdr.csum_flags & CSUM_TCP) 2478 status |= XL_TXSTAT_TCPCKSUM; 2479 if ((*m_head)->m_pkthdr.csum_flags & CSUM_UDP) 2480 status |= XL_TXSTAT_UDPCKSUM; 2481 } 2482 #endif 2483 c->xl_ptr->xl_status = htole32(status); 2484 } 2485 2486 c->xl_mbuf = *m_head; 2487 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREWRITE); 2488 return (0); 2489 } 2490 2491 /* 2492 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2493 * to the mbuf data regions directly in the transmit lists. We also save a 2494 * copy of the pointers since the transmit list fragment pointers are 2495 * physical addresses. 2496 */ 2497 2498 static void 2499 xl_start(struct ifnet *ifp) 2500 { 2501 struct xl_softc *sc = ifp->if_softc; 2502 2503 XL_LOCK(sc); 2504 2505 if (sc->xl_type == XL_TYPE_905B) 2506 xl_start_90xB_locked(ifp); 2507 else 2508 xl_start_locked(ifp); 2509 2510 XL_UNLOCK(sc); 2511 } 2512 2513 static void 2514 xl_start_locked(struct ifnet *ifp) 2515 { 2516 struct xl_softc *sc = ifp->if_softc; 2517 struct mbuf *m_head = NULL; 2518 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx; 2519 u_int32_t status; 2520 int error; 2521 2522 XL_LOCK_ASSERT(sc); 2523 2524 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2525 IFF_DRV_RUNNING) 2526 return; 2527 /* 2528 * Check for an available queue slot. If there are none, 2529 * punt. 2530 */ 2531 if (sc->xl_cdata.xl_tx_free == NULL) { 2532 xl_txeoc(sc); 2533 xl_txeof(sc); 2534 if (sc->xl_cdata.xl_tx_free == NULL) { 2535 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2536 return; 2537 } 2538 } 2539 2540 start_tx = sc->xl_cdata.xl_tx_free; 2541 2542 for (; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2543 sc->xl_cdata.xl_tx_free != NULL;) { 2544 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2545 if (m_head == NULL) 2546 break; 2547 2548 /* Pick a descriptor off the free list. */ 2549 cur_tx = sc->xl_cdata.xl_tx_free; 2550 2551 /* Pack the data into the descriptor. */ 2552 error = xl_encap(sc, cur_tx, &m_head); 2553 if (error) { 2554 if (m_head == NULL) 2555 break; 2556 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2557 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2558 break; 2559 } 2560 2561 sc->xl_cdata.xl_tx_free = cur_tx->xl_next; 2562 cur_tx->xl_next = NULL; 2563 2564 /* Chain it together. */ 2565 if (prev != NULL) { 2566 prev->xl_next = cur_tx; 2567 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys); 2568 } 2569 prev = cur_tx; 2570 2571 /* 2572 * If there's a BPF listener, bounce a copy of this frame 2573 * to him. 2574 */ 2575 BPF_MTAP(ifp, cur_tx->xl_mbuf); 2576 } 2577 2578 /* 2579 * If there are no packets queued, bail. 2580 */ 2581 if (cur_tx == NULL) 2582 return; 2583 2584 /* 2585 * Place the request for the upload interrupt 2586 * in the last descriptor in the chain. This way, if 2587 * we're chaining several packets at once, we'll only 2588 * get an interrupt once for the whole chain rather than 2589 * once for each packet. 2590 */ 2591 cur_tx->xl_ptr->xl_status = htole32(le32toh(cur_tx->xl_ptr->xl_status) | 2592 XL_TXSTAT_DL_INTR); 2593 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap, 2594 BUS_DMASYNC_PREWRITE); 2595 2596 /* 2597 * Queue the packets. If the TX channel is clear, update 2598 * the downlist pointer register. 2599 */ 2600 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL); 2601 xl_wait(sc); 2602 2603 if (sc->xl_cdata.xl_tx_head != NULL) { 2604 sc->xl_cdata.xl_tx_tail->xl_next = start_tx; 2605 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_next = 2606 htole32(start_tx->xl_phys); 2607 status = sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status; 2608 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status = 2609 htole32(le32toh(status) & ~XL_TXSTAT_DL_INTR); 2610 sc->xl_cdata.xl_tx_tail = cur_tx; 2611 } else { 2612 sc->xl_cdata.xl_tx_head = start_tx; 2613 sc->xl_cdata.xl_tx_tail = cur_tx; 2614 } 2615 if (!CSR_READ_4(sc, XL_DOWNLIST_PTR)) 2616 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, start_tx->xl_phys); 2617 2618 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2619 2620 XL_SEL_WIN(7); 2621 2622 /* 2623 * Set a timeout in case the chip goes out to lunch. 2624 */ 2625 sc->xl_wdog_timer = 5; 2626 2627 /* 2628 * XXX Under certain conditions, usually on slower machines 2629 * where interrupts may be dropped, it's possible for the 2630 * adapter to chew up all the buffers in the receive ring 2631 * and stall, without us being able to do anything about it. 2632 * To guard against this, we need to make a pass over the 2633 * RX queue to make sure there aren't any packets pending. 2634 * Doing it here means we can flush the receive ring at the 2635 * same time the chip is DMAing the transmit descriptors we 2636 * just gave it. 2637 * 2638 * 3Com goes to some lengths to emphasize the Parallel Tasking (tm) 2639 * nature of their chips in all their marketing literature; 2640 * we may as well take advantage of it. :) 2641 */ 2642 taskqueue_enqueue(taskqueue_swi, &sc->xl_task); 2643 } 2644 2645 static void 2646 xl_start_90xB_locked(struct ifnet *ifp) 2647 { 2648 struct xl_softc *sc = ifp->if_softc; 2649 struct mbuf *m_head = NULL; 2650 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx; 2651 int error, idx; 2652 2653 XL_LOCK_ASSERT(sc); 2654 2655 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2656 IFF_DRV_RUNNING) 2657 return; 2658 2659 idx = sc->xl_cdata.xl_tx_prod; 2660 start_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2661 2662 for (; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2663 sc->xl_cdata.xl_tx_chain[idx].xl_mbuf == NULL;) { 2664 if ((XL_TX_LIST_CNT - sc->xl_cdata.xl_tx_cnt) < 3) { 2665 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2666 break; 2667 } 2668 2669 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2670 if (m_head == NULL) 2671 break; 2672 2673 cur_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2674 2675 /* Pack the data into the descriptor. */ 2676 error = xl_encap(sc, cur_tx, &m_head); 2677 if (error) { 2678 if (m_head == NULL) 2679 break; 2680 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2681 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2682 break; 2683 } 2684 2685 /* Chain it together. */ 2686 if (prev != NULL) 2687 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys); 2688 prev = cur_tx; 2689 2690 /* 2691 * If there's a BPF listener, bounce a copy of this frame 2692 * to him. 2693 */ 2694 BPF_MTAP(ifp, cur_tx->xl_mbuf); 2695 2696 XL_INC(idx, XL_TX_LIST_CNT); 2697 sc->xl_cdata.xl_tx_cnt++; 2698 } 2699 2700 /* 2701 * If there are no packets queued, bail. 2702 */ 2703 if (cur_tx == NULL) 2704 return; 2705 2706 /* 2707 * Place the request for the upload interrupt 2708 * in the last descriptor in the chain. This way, if 2709 * we're chaining several packets at once, we'll only 2710 * get an interrupt once for the whole chain rather than 2711 * once for each packet. 2712 */ 2713 cur_tx->xl_ptr->xl_status = htole32(le32toh(cur_tx->xl_ptr->xl_status) | 2714 XL_TXSTAT_DL_INTR); 2715 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap, 2716 BUS_DMASYNC_PREWRITE); 2717 2718 /* Start transmission */ 2719 sc->xl_cdata.xl_tx_prod = idx; 2720 start_tx->xl_prev->xl_ptr->xl_next = htole32(start_tx->xl_phys); 2721 2722 /* 2723 * Set a timeout in case the chip goes out to lunch. 2724 */ 2725 sc->xl_wdog_timer = 5; 2726 } 2727 2728 static void 2729 xl_init(void *xsc) 2730 { 2731 struct xl_softc *sc = xsc; 2732 2733 XL_LOCK(sc); 2734 xl_init_locked(sc); 2735 XL_UNLOCK(sc); 2736 } 2737 2738 static void 2739 xl_init_locked(struct xl_softc *sc) 2740 { 2741 struct ifnet *ifp = sc->xl_ifp; 2742 int error, i; 2743 u_int16_t rxfilt = 0; 2744 struct mii_data *mii = NULL; 2745 2746 XL_LOCK_ASSERT(sc); 2747 2748 /* 2749 * Cancel pending I/O and free all RX/TX buffers. 2750 */ 2751 xl_stop(sc); 2752 2753 if (sc->xl_miibus == NULL) { 2754 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 2755 xl_wait(sc); 2756 } 2757 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2758 xl_wait(sc); 2759 DELAY(10000); 2760 2761 if (sc->xl_miibus != NULL) 2762 mii = device_get_softc(sc->xl_miibus); 2763 2764 /* Init our MAC address */ 2765 XL_SEL_WIN(2); 2766 for (i = 0; i < ETHER_ADDR_LEN; i++) { 2767 CSR_WRITE_1(sc, XL_W2_STATION_ADDR_LO + i, 2768 IF_LLADDR(sc->xl_ifp)[i]); 2769 } 2770 2771 /* Clear the station mask. */ 2772 for (i = 0; i < 3; i++) 2773 CSR_WRITE_2(sc, XL_W2_STATION_MASK_LO + (i * 2), 0); 2774 #ifdef notdef 2775 /* Reset TX and RX. */ 2776 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 2777 xl_wait(sc); 2778 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2779 xl_wait(sc); 2780 #endif 2781 /* Init circular RX list. */ 2782 error = xl_list_rx_init(sc); 2783 if (error) { 2784 device_printf(sc->xl_dev, "initialization of the rx ring failed (%d)\n", 2785 error); 2786 xl_stop(sc); 2787 return; 2788 } 2789 2790 /* Init TX descriptors. */ 2791 if (sc->xl_type == XL_TYPE_905B) 2792 error = xl_list_tx_init_90xB(sc); 2793 else 2794 error = xl_list_tx_init(sc); 2795 if (error) { 2796 device_printf(sc->xl_dev, "initialization of the tx ring failed (%d)\n", 2797 error); 2798 xl_stop(sc); 2799 return; 2800 } 2801 2802 /* 2803 * Set the TX freethresh value. 2804 * Note that this has no effect on 3c905B "cyclone" 2805 * cards but is required for 3c900/3c905 "boomerang" 2806 * cards in order to enable the download engine. 2807 */ 2808 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8); 2809 2810 /* Set the TX start threshold for best performance. */ 2811 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_SET_START|sc->xl_tx_thresh); 2812 2813 /* 2814 * If this is a 3c905B, also set the tx reclaim threshold. 2815 * This helps cut down on the number of tx reclaim errors 2816 * that could happen on a busy network. The chip multiplies 2817 * the register value by 16 to obtain the actual threshold 2818 * in bytes, so we divide by 16 when setting the value here. 2819 * The existing threshold value can be examined by reading 2820 * the register at offset 9 in window 5. 2821 */ 2822 if (sc->xl_type == XL_TYPE_905B) { 2823 CSR_WRITE_2(sc, XL_COMMAND, 2824 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4)); 2825 } 2826 2827 /* Set RX filter bits. */ 2828 XL_SEL_WIN(5); 2829 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 2830 2831 /* Set the individual bit to receive frames for this host only. */ 2832 rxfilt |= XL_RXFILTER_INDIVIDUAL; 2833 2834 /* If we want promiscuous mode, set the allframes bit. */ 2835 if (ifp->if_flags & IFF_PROMISC) { 2836 rxfilt |= XL_RXFILTER_ALLFRAMES; 2837 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2838 } else { 2839 rxfilt &= ~XL_RXFILTER_ALLFRAMES; 2840 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2841 } 2842 2843 /* 2844 * Set capture broadcast bit to capture broadcast frames. 2845 */ 2846 if (ifp->if_flags & IFF_BROADCAST) { 2847 rxfilt |= XL_RXFILTER_BROADCAST; 2848 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2849 } else { 2850 rxfilt &= ~XL_RXFILTER_BROADCAST; 2851 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2852 } 2853 2854 /* 2855 * Program the multicast filter, if necessary. 2856 */ 2857 if (sc->xl_type == XL_TYPE_905B) 2858 xl_setmulti_hash(sc); 2859 else 2860 xl_setmulti(sc); 2861 2862 /* 2863 * Load the address of the RX list. We have to 2864 * stall the upload engine before we can manipulate 2865 * the uplist pointer register, then unstall it when 2866 * we're finished. We also have to wait for the 2867 * stall command to complete before proceeding. 2868 * Note that we have to do this after any RX resets 2869 * have completed since the uplist register is cleared 2870 * by a reset. 2871 */ 2872 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL); 2873 xl_wait(sc); 2874 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr); 2875 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL); 2876 xl_wait(sc); 2877 2878 if (sc->xl_type == XL_TYPE_905B) { 2879 /* Set polling interval */ 2880 CSR_WRITE_1(sc, XL_DOWN_POLL, 64); 2881 /* Load the address of the TX list */ 2882 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL); 2883 xl_wait(sc); 2884 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2885 sc->xl_cdata.xl_tx_chain[0].xl_phys); 2886 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2887 xl_wait(sc); 2888 } 2889 2890 /* 2891 * If the coax transceiver is on, make sure to enable 2892 * the DC-DC converter. 2893 */ 2894 XL_SEL_WIN(3); 2895 if (sc->xl_xcvr == XL_XCVR_COAX) 2896 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START); 2897 else 2898 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 2899 2900 /* 2901 * increase packet size to allow reception of 802.1q or ISL packets. 2902 * For the 3c90x chip, set the 'allow large packets' bit in the MAC 2903 * control register. For 3c90xB/C chips, use the RX packet size 2904 * register. 2905 */ 2906 2907 if (sc->xl_type == XL_TYPE_905B) 2908 CSR_WRITE_2(sc, XL_W3_MAXPKTSIZE, XL_PACKET_SIZE); 2909 else { 2910 u_int8_t macctl; 2911 macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL); 2912 macctl |= XL_MACCTRL_ALLOW_LARGE_PACK; 2913 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, macctl); 2914 } 2915 2916 /* Clear out the stats counters. */ 2917 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE); 2918 sc->xl_stats_no_timeout = 1; 2919 xl_stats_update_locked(sc); 2920 sc->xl_stats_no_timeout = 0; 2921 XL_SEL_WIN(4); 2922 CSR_WRITE_2(sc, XL_W4_NET_DIAG, XL_NETDIAG_UPPER_BYTES_ENABLE); 2923 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_ENABLE); 2924 2925 /* 2926 * Enable interrupts. 2927 */ 2928 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|0xFF); 2929 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|XL_INTRS); 2930 #ifdef DEVICE_POLLING 2931 /* Disable interrupts if we are polling. */ 2932 if (ifp->if_capenable & IFCAP_POLLING) 2933 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0); 2934 else 2935 #endif 2936 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|XL_INTRS); 2937 if (sc->xl_flags & XL_FLAG_FUNCREG) 2938 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000); 2939 2940 /* Set the RX early threshold */ 2941 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_THRESH|(XL_PACKET_SIZE >>2)); 2942 CSR_WRITE_2(sc, XL_DMACTL, XL_DMACTL_UP_RX_EARLY); 2943 2944 /* Enable receiver and transmitter. */ 2945 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2946 xl_wait(sc); 2947 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE); 2948 xl_wait(sc); 2949 2950 /* XXX Downcall to miibus. */ 2951 if (mii != NULL) 2952 mii_mediachg(mii); 2953 2954 /* Select window 7 for normal operations. */ 2955 XL_SEL_WIN(7); 2956 2957 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2958 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2959 2960 sc->xl_wdog_timer = 0; 2961 callout_reset(&sc->xl_stat_callout, hz, xl_stats_update, sc); 2962 } 2963 2964 /* 2965 * Set media options. 2966 */ 2967 static int 2968 xl_ifmedia_upd(struct ifnet *ifp) 2969 { 2970 struct xl_softc *sc = ifp->if_softc; 2971 struct ifmedia *ifm = NULL; 2972 struct mii_data *mii = NULL; 2973 2974 XL_LOCK(sc); 2975 2976 if (sc->xl_miibus != NULL) 2977 mii = device_get_softc(sc->xl_miibus); 2978 if (mii == NULL) 2979 ifm = &sc->ifmedia; 2980 else 2981 ifm = &mii->mii_media; 2982 2983 switch (IFM_SUBTYPE(ifm->ifm_media)) { 2984 case IFM_100_FX: 2985 case IFM_10_FL: 2986 case IFM_10_2: 2987 case IFM_10_5: 2988 xl_setmode(sc, ifm->ifm_media); 2989 XL_UNLOCK(sc); 2990 return (0); 2991 } 2992 2993 if (sc->xl_media & XL_MEDIAOPT_MII || 2994 sc->xl_media & XL_MEDIAOPT_BTX || 2995 sc->xl_media & XL_MEDIAOPT_BT4) { 2996 xl_init_locked(sc); 2997 } else { 2998 xl_setmode(sc, ifm->ifm_media); 2999 } 3000 3001 XL_UNLOCK(sc); 3002 3003 return (0); 3004 } 3005 3006 /* 3007 * Report current media status. 3008 */ 3009 static void 3010 xl_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3011 { 3012 struct xl_softc *sc = ifp->if_softc; 3013 u_int32_t icfg; 3014 u_int16_t status = 0; 3015 struct mii_data *mii = NULL; 3016 3017 XL_LOCK(sc); 3018 3019 if (sc->xl_miibus != NULL) 3020 mii = device_get_softc(sc->xl_miibus); 3021 3022 XL_SEL_WIN(4); 3023 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS); 3024 3025 XL_SEL_WIN(3); 3026 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG) & XL_ICFG_CONNECTOR_MASK; 3027 icfg >>= XL_ICFG_CONNECTOR_BITS; 3028 3029 ifmr->ifm_active = IFM_ETHER; 3030 ifmr->ifm_status = IFM_AVALID; 3031 3032 if ((status & XL_MEDIASTAT_CARRIER) == 0) 3033 ifmr->ifm_status |= IFM_ACTIVE; 3034 3035 switch (icfg) { 3036 case XL_XCVR_10BT: 3037 ifmr->ifm_active = IFM_ETHER|IFM_10_T; 3038 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX) 3039 ifmr->ifm_active |= IFM_FDX; 3040 else 3041 ifmr->ifm_active |= IFM_HDX; 3042 break; 3043 case XL_XCVR_AUI: 3044 if (sc->xl_type == XL_TYPE_905B && 3045 sc->xl_media == XL_MEDIAOPT_10FL) { 3046 ifmr->ifm_active = IFM_ETHER|IFM_10_FL; 3047 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX) 3048 ifmr->ifm_active |= IFM_FDX; 3049 else 3050 ifmr->ifm_active |= IFM_HDX; 3051 } else 3052 ifmr->ifm_active = IFM_ETHER|IFM_10_5; 3053 break; 3054 case XL_XCVR_COAX: 3055 ifmr->ifm_active = IFM_ETHER|IFM_10_2; 3056 break; 3057 /* 3058 * XXX MII and BTX/AUTO should be separate cases. 3059 */ 3060 3061 case XL_XCVR_100BTX: 3062 case XL_XCVR_AUTO: 3063 case XL_XCVR_MII: 3064 if (mii != NULL) { 3065 mii_pollstat(mii); 3066 ifmr->ifm_active = mii->mii_media_active; 3067 ifmr->ifm_status = mii->mii_media_status; 3068 } 3069 break; 3070 case XL_XCVR_100BFX: 3071 ifmr->ifm_active = IFM_ETHER|IFM_100_FX; 3072 break; 3073 default: 3074 if_printf(ifp, "unknown XCVR type: %d\n", icfg); 3075 break; 3076 } 3077 3078 XL_UNLOCK(sc); 3079 } 3080 3081 static int 3082 xl_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 3083 { 3084 struct xl_softc *sc = ifp->if_softc; 3085 struct ifreq *ifr = (struct ifreq *) data; 3086 int error = 0; 3087 struct mii_data *mii = NULL; 3088 u_int8_t rxfilt; 3089 3090 switch (command) { 3091 case SIOCSIFFLAGS: 3092 XL_LOCK(sc); 3093 3094 XL_SEL_WIN(5); 3095 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 3096 if (ifp->if_flags & IFF_UP) { 3097 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 3098 ifp->if_flags & IFF_PROMISC && 3099 !(sc->xl_if_flags & IFF_PROMISC)) { 3100 rxfilt |= XL_RXFILTER_ALLFRAMES; 3101 CSR_WRITE_2(sc, XL_COMMAND, 3102 XL_CMD_RX_SET_FILT|rxfilt); 3103 XL_SEL_WIN(7); 3104 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING && 3105 !(ifp->if_flags & IFF_PROMISC) && 3106 sc->xl_if_flags & IFF_PROMISC) { 3107 rxfilt &= ~XL_RXFILTER_ALLFRAMES; 3108 CSR_WRITE_2(sc, XL_COMMAND, 3109 XL_CMD_RX_SET_FILT|rxfilt); 3110 XL_SEL_WIN(7); 3111 } else { 3112 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 3113 xl_init_locked(sc); 3114 } 3115 } else { 3116 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3117 xl_stop(sc); 3118 } 3119 sc->xl_if_flags = ifp->if_flags; 3120 XL_UNLOCK(sc); 3121 error = 0; 3122 break; 3123 case SIOCADDMULTI: 3124 case SIOCDELMULTI: 3125 /* XXX Downcall from if_addmulti() possibly with locks held. */ 3126 XL_LOCK(sc); 3127 if (sc->xl_type == XL_TYPE_905B) 3128 xl_setmulti_hash(sc); 3129 else 3130 xl_setmulti(sc); 3131 XL_UNLOCK(sc); 3132 error = 0; 3133 break; 3134 case SIOCGIFMEDIA: 3135 case SIOCSIFMEDIA: 3136 if (sc->xl_miibus != NULL) 3137 mii = device_get_softc(sc->xl_miibus); 3138 if (mii == NULL) 3139 error = ifmedia_ioctl(ifp, ifr, 3140 &sc->ifmedia, command); 3141 else 3142 error = ifmedia_ioctl(ifp, ifr, 3143 &mii->mii_media, command); 3144 break; 3145 case SIOCSIFCAP: 3146 #ifdef DEVICE_POLLING 3147 if (ifr->ifr_reqcap & IFCAP_POLLING && 3148 !(ifp->if_capenable & IFCAP_POLLING)) { 3149 error = ether_poll_register(xl_poll, ifp); 3150 if (error) 3151 return(error); 3152 XL_LOCK(sc); 3153 /* Disable interrupts */ 3154 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0); 3155 ifp->if_capenable |= IFCAP_POLLING; 3156 XL_UNLOCK(sc); 3157 return (error); 3158 } 3159 if (!(ifr->ifr_reqcap & IFCAP_POLLING) && 3160 ifp->if_capenable & IFCAP_POLLING) { 3161 error = ether_poll_deregister(ifp); 3162 /* Enable interrupts. */ 3163 XL_LOCK(sc); 3164 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|0xFF); 3165 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|XL_INTRS); 3166 if (sc->xl_flags & XL_FLAG_FUNCREG) 3167 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 3168 4, 0x8000); 3169 ifp->if_capenable &= ~IFCAP_POLLING; 3170 XL_UNLOCK(sc); 3171 return (error); 3172 } 3173 #endif /* DEVICE_POLLING */ 3174 XL_LOCK(sc); 3175 ifp->if_capenable = ifr->ifr_reqcap; 3176 if (ifp->if_capenable & IFCAP_TXCSUM) 3177 ifp->if_hwassist = XL905B_CSUM_FEATURES; 3178 else 3179 ifp->if_hwassist = 0; 3180 XL_UNLOCK(sc); 3181 break; 3182 default: 3183 error = ether_ioctl(ifp, command, data); 3184 break; 3185 } 3186 3187 return (error); 3188 } 3189 3190 static int 3191 xl_watchdog(struct xl_softc *sc) 3192 { 3193 struct ifnet *ifp = sc->xl_ifp; 3194 u_int16_t status = 0; 3195 int misintr; 3196 3197 XL_LOCK_ASSERT(sc); 3198 3199 if (sc->xl_wdog_timer == 0 || --sc->xl_wdog_timer != 0) 3200 return (0); 3201 3202 xl_rxeof(sc); 3203 xl_txeoc(sc); 3204 misintr = 0; 3205 if (sc->xl_type == XL_TYPE_905B) { 3206 xl_txeof_90xB(sc); 3207 if (sc->xl_cdata.xl_tx_cnt == 0) 3208 misintr++; 3209 } else { 3210 xl_txeof(sc); 3211 if (sc->xl_cdata.xl_tx_head == NULL) 3212 misintr++; 3213 } 3214 if (misintr != 0) { 3215 device_printf(sc->xl_dev, 3216 "watchdog timeout (missed Tx interrupts) -- recovering\n"); 3217 return (0); 3218 } 3219 3220 ifp->if_oerrors++; 3221 XL_SEL_WIN(4); 3222 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS); 3223 device_printf(sc->xl_dev, "watchdog timeout\n"); 3224 3225 if (status & XL_MEDIASTAT_CARRIER) 3226 device_printf(sc->xl_dev, 3227 "no carrier - transceiver cable problem?\n"); 3228 3229 xl_reset(sc); 3230 xl_init_locked(sc); 3231 3232 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 3233 if (sc->xl_type == XL_TYPE_905B) 3234 xl_start_90xB_locked(ifp); 3235 else 3236 xl_start_locked(ifp); 3237 } 3238 3239 return (EJUSTRETURN); 3240 } 3241 3242 /* 3243 * Stop the adapter and free any mbufs allocated to the 3244 * RX and TX lists. 3245 */ 3246 static void 3247 xl_stop(struct xl_softc *sc) 3248 { 3249 register int i; 3250 struct ifnet *ifp = sc->xl_ifp; 3251 3252 XL_LOCK_ASSERT(sc); 3253 3254 sc->xl_wdog_timer = 0; 3255 3256 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISABLE); 3257 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE); 3258 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB); 3259 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISCARD); 3260 xl_wait(sc); 3261 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_DISABLE); 3262 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 3263 DELAY(800); 3264 3265 #ifdef foo 3266 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 3267 xl_wait(sc); 3268 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 3269 xl_wait(sc); 3270 #endif 3271 3272 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|XL_STAT_INTLATCH); 3273 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|0); 3274 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0); 3275 if (sc->xl_flags & XL_FLAG_FUNCREG) 3276 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000); 3277 3278 /* Stop the stats updater. */ 3279 callout_stop(&sc->xl_stat_callout); 3280 3281 /* 3282 * Free data in the RX lists. 3283 */ 3284 for (i = 0; i < XL_RX_LIST_CNT; i++) { 3285 if (sc->xl_cdata.xl_rx_chain[i].xl_mbuf != NULL) { 3286 bus_dmamap_unload(sc->xl_mtag, 3287 sc->xl_cdata.xl_rx_chain[i].xl_map); 3288 bus_dmamap_destroy(sc->xl_mtag, 3289 sc->xl_cdata.xl_rx_chain[i].xl_map); 3290 m_freem(sc->xl_cdata.xl_rx_chain[i].xl_mbuf); 3291 sc->xl_cdata.xl_rx_chain[i].xl_mbuf = NULL; 3292 } 3293 } 3294 if (sc->xl_ldata.xl_rx_list != NULL) 3295 bzero(sc->xl_ldata.xl_rx_list, XL_RX_LIST_SZ); 3296 /* 3297 * Free the TX list buffers. 3298 */ 3299 for (i = 0; i < XL_TX_LIST_CNT; i++) { 3300 if (sc->xl_cdata.xl_tx_chain[i].xl_mbuf != NULL) { 3301 bus_dmamap_unload(sc->xl_mtag, 3302 sc->xl_cdata.xl_tx_chain[i].xl_map); 3303 bus_dmamap_destroy(sc->xl_mtag, 3304 sc->xl_cdata.xl_tx_chain[i].xl_map); 3305 m_freem(sc->xl_cdata.xl_tx_chain[i].xl_mbuf); 3306 sc->xl_cdata.xl_tx_chain[i].xl_mbuf = NULL; 3307 } 3308 } 3309 if (sc->xl_ldata.xl_tx_list != NULL) 3310 bzero(sc->xl_ldata.xl_tx_list, XL_TX_LIST_SZ); 3311 3312 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 3313 } 3314 3315 /* 3316 * Stop all chip I/O so that the kernel's probe routines don't 3317 * get confused by errant DMAs when rebooting. 3318 */ 3319 static int 3320 xl_shutdown(device_t dev) 3321 { 3322 struct xl_softc *sc; 3323 3324 sc = device_get_softc(dev); 3325 3326 XL_LOCK(sc); 3327 xl_reset(sc); 3328 xl_stop(sc); 3329 XL_UNLOCK(sc); 3330 3331 return (0); 3332 } 3333 3334 static int 3335 xl_suspend(device_t dev) 3336 { 3337 struct xl_softc *sc; 3338 3339 sc = device_get_softc(dev); 3340 3341 XL_LOCK(sc); 3342 xl_stop(sc); 3343 XL_UNLOCK(sc); 3344 3345 return (0); 3346 } 3347 3348 static int 3349 xl_resume(device_t dev) 3350 { 3351 struct xl_softc *sc; 3352 struct ifnet *ifp; 3353 3354 sc = device_get_softc(dev); 3355 ifp = sc->xl_ifp; 3356 3357 XL_LOCK(sc); 3358 3359 xl_reset(sc); 3360 if (ifp->if_flags & IFF_UP) 3361 xl_init_locked(sc); 3362 3363 XL_UNLOCK(sc); 3364 3365 return (0); 3366 } 3367