1/*-
2 * Copyright (c) 2017 Ruslan Bukin <br@bsdpad.com>
3 * All rights reserved.
4 *
5 * This software was developed by SRI International and the University of
6 * Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237
7 * ("CTSRD"), as part of the DARPA CRASH research programme.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 *    notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 *    notice, this list of conditions and the following disclaimer in the
16 *    documentation and/or other materials provided with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 */
30
31/* /dts-v1/; */
32#include "socfpga_cyclone5_sockit.dts"
33
34/ {
35	model = "Terasic SoCkit";
36	compatible = "altr,socfpga-cyclone5", "altr,socfpga";
37
38	memreserve = < 0x00000000 0x1000 >, /* SMP trampoline */
39		     < 0x00001000 0x1000 >, /* virtio block */
40		     < 0x00002000 0x1000 >; /* virtio net */
41
42	soc {
43		/* Local timer */
44		timer@fffec600 {
45			clock-frequency = <200000000>;
46		};
47
48		/* Global timer */
49		global_timer: timer@fffec200 {
50			compatible = "arm,cortex-a9-global-timer";
51			reg = <0xfffec200 0x20>;
52			interrupts = <1 11 0xf04>;
53			clock-frequency = <200000000>;
54		};
55
56		beri_mem0: mem@d0000000 {
57			compatible = "sri-cambridge,beri-mem";
58			reg = <0xd0000000 0x10000000>; /* 256mb */
59			status = "okay";
60		};
61
62		pio0: pio@c0020000 {
63			compatible = "altr,pio";
64			reg = <0xc0020000 0x1000>; /* recv */
65			interrupts = < 76 >;
66			status = "okay";
67		};
68
69		pio1: pio@c0021000 {
70			compatible = "altr,pio";
71			reg = <0xc0021000 0x1000>; /* send */
72			interrupts = < 82 >; /* not in use on arm side */
73			status = "okay";
74		};
75
76		pio2: pio@c0022000 {
77			compatible = "altr,pio";
78			reg = <0xc0022000 0x1000>; /* recv */
79			interrupts = < 77 >;
80			status = "okay";
81		};
82
83		pio3: pio@c0023000 {
84			compatible = "altr,pio";
85			reg = <0xc0023000 0x1000>; /* send */
86			interrupts = < 83 >; /* not in use on arm side */
87			status = "okay";
88		};
89
90		beri_vtblk: vtblk@00001000 {
91			compatible = "sri-cambridge,beri-vtblk";
92			reg = <0x00001000 0x1000>;
93			pio-recv = <&pio0>;
94			pio-send = <&pio1>;
95			beri-mem = <&beri_mem0>;
96			status = "okay";
97		};
98
99		beri_vtnet: vtnet@00002000 {
100			compatible = "sri-cambridge,beri-vtnet";
101			reg = <0x00002000 0x1000>;
102			pio-recv = <&pio2>;
103			pio-send = <&pio3>;
104			beri-mem = <&beri_mem0>;
105			status = "okay";
106		};
107
108		beri_debug: ring@c0000000 {
109			compatible = "sri-cambridge,beri-ring";
110			reg = <0xc0000000 0x3000>;
111			interrupts = < 72 73 >;
112			device_name = "beri_debug";
113			data_size = <0x1000>;
114			data_read = <0x0>;
115			data_write = <0x1000>;
116			control_read = <0x2000>;
117			control_write = <0x2010>;
118			status = "okay";
119		};
120
121		beri_console: ring@c0004000 {
122			compatible = "sri-cambridge,beri-ring";
123			reg = <0xc0004000 0x3000>;
124			interrupts = < 74 75 >;
125			device_name = "beri_console";
126			data_size = <0x1000>;
127			data_read = <0x0>;
128			data_write = <0x1000>;
129			control_read = <0x2000>;
130			control_write = <0x2010>;
131			status = "okay";
132		};
133	};
134
135	chosen {
136		stdin = "serial0";
137		stdout = "serial0";
138	};
139};
140
141&mmc0 {
142	bus-frequency = <25000000>;
143};
144
145&uart0 {
146	clock-frequency = <100000000>;
147};
148
149&uart1 {
150	status = "disabled";
151};
152