1/*-
2 * Copyright (c) 2017 Ruslan Bukin <br@bsdpad.com>
3 * All rights reserved.
4 *
5 * This software was developed by SRI International and the University of
6 * Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237
7 * ("CTSRD"), as part of the DARPA CRASH research programme.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 *    notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 *    notice, this list of conditions and the following disclaimer in the
16 *    documentation and/or other materials provided with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 *
30 * $FreeBSD$
31 */
32
33/* /dts-v1/; */
34#include "socfpga_cyclone5_sockit.dts"
35
36/ {
37	model = "Terasic SoCkit";
38	compatible = "altr,socfpga-cyclone5", "altr,socfpga";
39
40	memreserve = < 0x00000000 0x1000 >, /* SMP trampoline */
41		     < 0x00001000 0x1000 >, /* virtio block */
42		     < 0x00002000 0x1000 >; /* virtio net */
43
44	soc {
45		/* Local timer */
46		timer@fffec600 {
47			clock-frequency = <200000000>;
48		};
49
50		/* Global timer */
51		global_timer: timer@fffec200 {
52			compatible = "arm,cortex-a9-global-timer";
53			reg = <0xfffec200 0x20>;
54			interrupts = <1 11 0xf04>;
55			clock-frequency = <200000000>;
56		};
57
58		beri_mem0: mem@d0000000 {
59			compatible = "sri-cambridge,beri-mem";
60			reg = <0xd0000000 0x10000000>; /* 256mb */
61			status = "okay";
62		};
63
64		pio0: pio@c0020000 {
65			compatible = "altr,pio";
66			reg = <0xc0020000 0x1000>; /* recv */
67			interrupts = < 76 >;
68			status = "okay";
69		};
70
71		pio1: pio@c0021000 {
72			compatible = "altr,pio";
73			reg = <0xc0021000 0x1000>; /* send */
74			interrupts = < 82 >; /* not in use on arm side */
75			status = "okay";
76		};
77
78		pio2: pio@c0022000 {
79			compatible = "altr,pio";
80			reg = <0xc0022000 0x1000>; /* recv */
81			interrupts = < 77 >;
82			status = "okay";
83		};
84
85		pio3: pio@c0023000 {
86			compatible = "altr,pio";
87			reg = <0xc0023000 0x1000>; /* send */
88			interrupts = < 83 >; /* not in use on arm side */
89			status = "okay";
90		};
91
92		beri_vtblk: vtblk@00001000 {
93			compatible = "sri-cambridge,beri-vtblk";
94			reg = <0x00001000 0x1000>;
95			pio-recv = <&pio0>;
96			pio-send = <&pio1>;
97			beri-mem = <&beri_mem0>;
98			status = "okay";
99		};
100
101		beri_vtnet: vtnet@00002000 {
102			compatible = "sri-cambridge,beri-vtnet";
103			reg = <0x00002000 0x1000>;
104			pio-recv = <&pio2>;
105			pio-send = <&pio3>;
106			beri-mem = <&beri_mem0>;
107			status = "okay";
108		};
109
110		beri_debug: ring@c0000000 {
111			compatible = "sri-cambridge,beri-ring";
112			reg = <0xc0000000 0x3000>;
113			interrupts = < 72 73 >;
114			device_name = "beri_debug";
115			data_size = <0x1000>;
116			data_read = <0x0>;
117			data_write = <0x1000>;
118			control_read = <0x2000>;
119			control_write = <0x2010>;
120			status = "okay";
121		};
122
123		beri_console: ring@c0004000 {
124			compatible = "sri-cambridge,beri-ring";
125			reg = <0xc0004000 0x3000>;
126			interrupts = < 74 75 >;
127			device_name = "beri_console";
128			data_size = <0x1000>;
129			data_read = <0x0>;
130			data_write = <0x1000>;
131			control_read = <0x2000>;
132			control_write = <0x2010>;
133			status = "okay";
134		};
135	};
136
137	chosen {
138		stdin = "serial0";
139		stdout = "serial0";
140	};
141};
142
143&mmc0 {
144	bus-frequency = <25000000>;
145};
146
147&uart0 {
148	clock-frequency = <100000000>;
149};
150
151&uart1 {
152	status = "disabled";
153};
154