xref: /freebsd/sys/dts/arm/vybrid.dtsi (revision 1d386b48)
1/*-
2 * Copyright (c) 2013-2014 Ruslan Bukin <br@bsdpad.com>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27/ {
28	model = "Freescale Vybrid Family";
29	compatible = "freescale,vybrid", "fsl,mvf";
30	#address-cells = <1>;
31	#size-cells = <1>;
32
33	interrupt-parent = <&GIC>;
34
35	aliases {
36		soc = &SOC;
37		serial0 = &serial0;
38		serial1 = &serial1;
39		sai0 = &sai0;
40		sai1 = &sai1;
41		sai2 = &sai2;
42		sai3 = &sai3;
43		esai = &esai;
44		adc0 = &adc0;
45		adc1 = &adc1;
46		edma0 = &edma0;
47		edma1 = &edma1;
48		src = &SRC;
49	};
50
51	SOC: vybrid {
52		#address-cells = <1>;
53		#size-cells = <1>;
54		compatible = "simple-bus";
55		ranges;
56		bus-frequency = <0>;
57
58		SRC: src@4006E000 {
59			compatible = "fsl,mvf600-src";
60			reg = <0x4006E000 0x100>;
61		};
62
63		mscm@40001000 {
64			compatible = "fsl,mvf600-mscm";
65			reg = <0x40001000 0x1000>;
66		};
67
68		GIC: interrupt-controller@01c81000 {
69			compatible = "arm,gic";
70			reg = 	<0x40003000 0x1000>,	/* Distributor Registers */
71				<0x40002100 0x100>;	/* CPU Interface Registers */
72			interrupt-controller;
73			#interrupt-cells = <1>;
74		};
75
76		anadig@40050000 {
77			compatible = "fsl,mvf600-anadig";
78			reg = <0x40050000 0x300>;
79		};
80
81		ccm@4006b000 {
82			compatible = "fsl,mvf600-ccm";
83			reg = <0x4006b000 0x1000>;
84			clock_names = "pll4";
85		};
86
87		mp_tmr@40002100 {
88			compatible = "arm,mpcore-timers";
89			clock-frequency = <133000000>;
90			#address-cells = <1>;
91			#size-cells = <0>;
92			reg = < 0x40002200 0x100 >, /* Global Timer Registers */
93			      < 0x40002600 0x100 >; /* Private Timer Registers */
94			interrupts = < 27 29 >;
95			interrupt-parent = < &GIC >;
96		};
97
98		dmamux@40024000 {
99			compatible = "fsl,mvf600-dmamux";
100			reg = <0x40024000 0x100>,
101			      <0x40025000 0x100>,
102			      <0x400A1000 0x100>,
103			      <0x400A2000 0x100>;
104		};
105
106		edma0: edma@40018000 {
107			compatible = "fsl,mvf600-edma";
108			reg = <0x40018000 0x1000>,
109			      <0x40019000 0x1000>; /* TCD */
110			interrupts = < 40 41 >;
111			interrupt-parent = <&GIC>;
112			device-id = < 0 >;
113			status = "disabled";
114		};
115
116		edma1: edma@40098000 {
117			compatible = "fsl,mvf600-edma";
118			reg = <0x40098000 0x1000>,
119			      <0x40099000 0x1000>; /* TCD */
120			interrupts = < 42 43 >;
121			interrupt-parent = <&GIC>;
122			device-id = < 1 >;
123			status = "disabled";
124		};
125
126		pit@40037000 {
127			compatible = "fsl,mvf600-pit";
128			reg = <0x40037000 0x1000>;
129			interrupts = < 71 >;
130			interrupt-parent = <&GIC>;
131			clock-frequency = < 24000000 >;
132		};
133
134		lptmr@40040000 {
135			compatible = "fsl,mvf600-lptmr";
136			reg = <0x40040000 0x1000>;
137			interrupts = < 72 >;
138			interrupt-parent = <&GIC>;
139			clock-frequency = < 24000000 >;
140		};
141
142		iomuxc@40048000 {
143			compatible = "fsl,mvf600-iomuxc";
144			reg = <0x40048000 0x1000>;
145		};
146
147		port@40049000 {
148			compatible = "fsl,mvf600-port";
149			reg = <0x40049000 0x5000>;
150			interrupts = < 139 140 141 142 143 >;
151			interrupt-parent = <&GIC>;
152		};
153
154		gpio@400FF000 {
155			compatible = "fsl,mvf600-gpio";
156			reg = <0x400FF000 0x200>;
157			#gpio-cells = <3>;
158			gpio-controller;
159		};
160
161		nand@400E0000 {
162			#address-cells = <1>;
163			#size-cells = <1>;
164			compatible = "fsl,mvf600-nand";
165			reg = <0x400E0000 0x10000>;
166			interrupts = < 115 >;
167			interrupt-parent = <&GIC>;
168			clock_names = "nand";
169			status = "disabled";
170
171			partition@40000 {
172				reg = <0x40000 0x200000>; /* 2MB */
173				label =	"u-boot";
174				read-only;
175			};
176
177			partition@240000 {
178				reg = <0x240000 0x200000>; /* 2MB */
179				label =	"test";
180			};
181
182			partition@440000 {
183				reg = <0x440000 0xa00000>; /* 10MB */
184				label =	"kernel";
185			};
186
187			partition@e40000 {
188				reg = <0xe40000 0x1e000000>; /* 480MB */
189				label =	"root";
190			};
191		};
192
193		sdhci0: sdhci@400B1000 {
194			compatible = "fsl,mvf600-sdhci";
195			reg = <0x400B1000 0x1000>;
196			interrupts = < 59 >;
197			interrupt-parent = <&GIC>;
198			clock-frequency = <50000000>;
199			status = "disabled";
200			clock_names = "esdhc0";
201		};
202
203		sdhci1: sdhci@400B2000 {
204			compatible = "fsl,mvf600-sdhci";
205			reg = <0x400B2000 0x1000>;
206			interrupts = < 60 >;
207			interrupt-parent = <&GIC>;
208			clock-frequency = <50000000>;
209			status = "disabled";
210			clock_names = "esdhc1";
211			iomux_config = < 14 0x500060
212					 15 0x500060
213					 16 0x500060
214					 17 0x500060
215					 18 0x500060
216					 19 0x500060 >;
217		};
218
219		serial0: serial@40027000 {
220			compatible = "fsl,mvf600-uart";
221			reg = <0x40027000 0x1000>;
222			interrupts = <93>;
223			interrupt-parent = <&GIC>;
224			current-speed = <115200>;
225			clock-frequency = < 24000000 >;
226			status = "disabled";
227		};
228
229		serial1: serial@40028000 {
230			compatible = "fsl,mvf600-uart";
231			reg = <0x40028000 0x1000>;
232			interrupts = <94>;
233			interrupt-parent = <&GIC>;
234			current-speed = <115200>;
235			clock-frequency = < 24000000 >;
236			status = "disabled";
237		};
238
239		usb@40034000 {
240			compatible = "fsl,mvf600-usb-ehci", "usb-ehci";
241			reg = < 0x40034000 0x1000 >, /* ehci */
242			      < 0x40035000 0x1000 >, /* usbc */
243			      < 0x40050800 0x100 >; /* phy */
244			interrupts = < 107 >;
245			interrupt-parent = <&GIC>;
246			iomux_config = < 134 0x0001be
247					   7 0x200060 >;
248		};
249
250		usb@400b4000 {
251			compatible = "fsl,mvf600-usb-ehci", "usb-ehci";
252			reg = < 0x400b4000 0x1000 >, /* ehci */
253			      < 0x400b5000 0x1000 >, /* usbc */
254			      < 0x40050C00 0x100 >; /* phy */
255			interrupts = < 108 >;
256			interrupt-parent = <&GIC>;
257			iomux_config = < 134 0x0001be
258					   7 0x200060 >;
259		};
260
261		fec0: ethernet@400D0000 {
262			compatible = "fsl,mvf600-fec";
263			reg = <0x400D0000 0x1000>;
264			interrupts = < 110 >;
265			interrupt-parent = <&GIC>;
266			phy-mode = "rmii";
267			phy-disable-preamble;
268			status = "disabled";
269			clock_names = "enet";
270			iomux_config = < 45 0x100061
271					 46 0x100061
272					 47 0x100061
273					 48 0x100060
274					 49 0x100060
275					 50 0x100060
276					 51 0x100060
277					 52 0x100060
278					 53 0x100060 >;
279		};
280
281		fec1: ethernet@400D1000 {
282			compatible = "fsl,mvf600-fec";
283			reg = <0x400D1000 0x1000>;
284			interrupts = < 111 >;
285			interrupt-parent = <&GIC>;
286			phy-mode = "rmii";
287			phy-disable-preamble;
288			status = "disabled";
289			clock_names = "enet";
290			iomux_config = < 54 0x103192
291					 55 0x103193
292					 56 0x103191
293					 57 0x103191
294					 58 0x103191
295					 59 0x103191
296					 60 0x103192
297					 61 0x103192
298					 62 0x103192 >;
299		};
300
301		sai0: sai@4002F000 {
302			compatible = "fsl,mvf600-sai";
303			reg = <0x4002F000 0x1000>;
304			interrupts = < 116 >;
305			interrupt-parent = <&GIC>;
306			status = "disabled";
307		};
308
309		sai1: sai@40030000 {
310			compatible = "fsl,mvf600-sai";
311			reg = <0x40030000 0x1000>;
312			interrupts = < 117 >;
313			interrupt-parent = <&GIC>;
314			status = "disabled";
315		};
316
317		sai2: sai@40031000 {
318			compatible = "fsl,mvf600-sai";
319			reg = <0x40031000 0x1000>;
320			interrupts = < 118 >;
321			interrupt-parent = <&GIC>;
322			status = "disabled";
323		};
324
325		sai3: sai@40032000 {
326			compatible = "fsl,mvf600-sai";
327			reg = <0x40032000 0x1000>;
328			interrupts = < 119 >;
329			interrupt-parent = <&GIC>;
330			status = "disabled";
331			edma-controller = <&edma1>;
332			edma-src-receive = < 8 >;
333			edma-src-transmit = < 9 >;
334			edma-mux-group = < 1 >;
335			clock_names = "sai3", "cko1";
336			iomux_config = < 16 0x200060
337					 19 0x200060
338					 21 0x200060
339					 40 0x400061 >; /* CKO1 */
340		};
341
342		esai: esai@40062000 {
343			compatible = "fsl,mvf600-esai";
344			reg = <0x40062000 0x1000>;
345			interrupts = < 120 >;
346			interrupt-parent = <&GIC>;
347			status = "disabled";
348			clock_names = "esai";
349			iomux_config = < 45 0x400061
350					 46 0x400061
351					 47 0x400061
352					 48 0x400060
353					 49 0x400060
354					 50 0x400060
355					 51 0x400060
356					 52 0x400060
357					 78 0x3038df
358					 40 0x400061 >;
359		};
360
361		spi0: spi@4002C000 {
362			compatible = "fsl,mvf600-spi";
363			reg = <0x4002C000 0x1000>;
364			interrupts = < 99 >;
365			interrupt-parent = <&GIC>;
366			status = "disabled";
367			iomux_config = < 40 0x100061
368					 41 0x100061
369					 42 0x100060
370					 43 0x100060
371					 44 0x100061 >;
372		};
373
374		spi1: spi@4002D000 {
375			compatible = "fsl,mvf600-spi";
376			reg = <0x4002D000 0x1000>;
377			interrupts = < 100 >;
378			interrupt-parent = <&GIC>;
379			status = "disabled";
380		};
381
382		spi2: spi@400AC000 {
383			compatible = "fsl,mvf600-spi";
384			reg = <0x400AC000 0x1000>;
385			interrupts = < 101 >;
386			interrupt-parent = <&GIC>;
387			status = "disabled";
388		};
389
390		spi3: spi@400AD000 {
391			compatible = "fsl,mvf600-spi";
392			reg = <0x400AD000 0x1000>;
393			interrupts = < 102 >;
394			interrupt-parent = <&GIC>;
395			status = "disabled";
396		};
397
398		i2c0: i2c@40066000 {
399			compatible = "fsl,mvf600-i2c";
400			reg = <0x40066000 0x1000>;
401			interrupts = < 103 >;
402			interrupt-parent = <&GIC>;
403			status = "disabled";
404			clock_names = "ipg";
405			iomux_config = <  36 0x2034d3
406					  37 0x2034d3
407					 207 0x1
408					 208 0x1 >;
409		};
410
411		i2c1: i2c@40067000 {
412			compatible = "fsl,mvf600-i2c";
413			reg = <0x40067000 0x1000>;
414			interrupts = < 104 >;
415			interrupt-parent = <&GIC>;
416			status = "disabled";
417		};
418
419		i2c2: i2c@400E6000 {
420			compatible = "fsl,mvf600-i2c";
421			reg = <0x400E6000 0x1000>;
422			interrupts = < 105 >;
423			interrupt-parent = <&GIC>;
424			status = "disabled";
425		};
426
427		i2c3: i2c@400E7000 {
428			compatible = "fsl,mvf600-i2c";
429			reg = <0x400E7000 0x1000>;
430			interrupts = < 106 >;
431			interrupt-parent = <&GIC>;
432			status = "disabled";
433		};
434
435		adc0: adc@4003B000 {
436			compatible = "fsl,mvf600-adc";
437			reg = <0x4003B000 0x1000>;
438			interrupts = < 85 >;
439			interrupt-parent = <&GIC>;
440			status = "disabled";
441		};
442
443		adc1: adc@400BB000 {
444			compatible = "fsl,mvf600-adc";
445			reg = <0x400BB000 0x1000>;
446			interrupts = < 86 >;
447			interrupt-parent = <&GIC>;
448			status = "disabled";
449		};
450
451		tcon0: tcon@4003D000 {
452			compatible = "fsl,mvf600-tcon";
453			reg = <0x4003D000 0x1000>;
454			status = "disabled";
455		};
456
457		dcu0: dcu4@40058000 {
458			compatible = "fsl,mvf600-dcu4";
459			reg = <0x40058000 0x7000>;
460			interrupts = < 62 >;
461			interrupt-parent = <&GIC>;
462			status = "disabled";
463			clock_names = "dcu0";
464			iomux_config = < 105 0x100044
465					 106 0x100044
466					 107 0x100060
467					 108 0x100060
468					 109 0x100060
469					 110 0x100060
470					 111 0x100060
471					 112 0x100060
472					 113 0x100060
473					 114 0x100060
474					 115 0x100060
475					 116 0x100060
476					 117 0x100060
477					 118 0x100060
478					 119 0x100060
479					 120 0x100060
480					 121 0x100060
481					 122 0x100060
482					 123 0x100060
483					 124 0x100060
484					 125 0x100060
485					 126 0x100060
486					 127 0x100060
487					 128 0x100060
488					 129 0x100060
489					 130 0x100060
490					 131 0x100060
491					 132 0x100060
492					 133 0x100060 >;
493		};
494	};
495};
496