1/* 2 * MPC8555 CDS Device Tree Source 3 * 4 * Copyright 2006, 2008 Freescale Semiconductor Inc. All rights reserved 5 * 6 * Neither the name of Freescale Semiconductor, Inc nor the names of 7 * its contributors may be used to endorse or promote products derived 8 * from this software without specific prior written permission. 9 * 10 * Freescale hereby publishes it under the following licenses: 11 * 12 * BSD License 13 * 14 * Redistribution and use in source and binary forms, with or 15 * without modification, are permitted provided that the following 16 * conditions are met: 17 * 18 * Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 21 * Redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in 23 * the documentation and/or other materials provided with the 24 * distribution. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND 27 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, 28 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 29 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 30 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 32 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 33 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 34 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 35 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 36 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGE. 39 * 40 * GNU General Public License, version 2 41 * 42 * This program is free software; you can redistribute it and/or 43 * modify it under the terms of the GNU General Public License 44 * as published by the Free Software Foundation; either version 2 45 * of the License, or (at your option) any later version. 46 * 47 * This program is distributed in the hope that it will be useful, 48 * but WITHOUT ANY WARRANTY; without even the implied warranty of 49 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 50 * GNU General Public License for more details. 51 * 52 * You should have received a copy of the GNU General Public License 53 * along with this program; if not, write to the Free Software 54 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, 55 * MA 02110-1301, USA. 56 * 57 * You may select the license of your choice. 58 *------------------------------------------------------------------ 59 */ 60 61/dts-v1/; 62 63/ { 64 model = "MPC8555CDS"; 65 compatible = "MPC8555CDS", "MPC85xxCDS"; 66 #address-cells = <1>; 67 #size-cells = <1>; 68 69 aliases { 70 ethernet0 = &enet0; 71 ethernet1 = &enet1; 72 serial0 = &serial0; 73 serial1 = &serial1; 74 pci0 = &pci0; 75 pci1 = &pci1; 76 }; 77 78 cpus { 79 #address-cells = <1>; 80 #size-cells = <0>; 81 82 PowerPC,8555@0 { 83 device_type = "cpu"; 84 reg = <0x0>; 85 d-cache-line-size = <32>; // 32 bytes 86 i-cache-line-size = <32>; // 32 bytes 87 d-cache-size = <0x8000>; // L1, 32K 88 i-cache-size = <0x8000>; // L1, 32K 89 timebase-frequency = <0>; // 33 MHz, from uboot 90 bus-frequency = <0>; // 166 MHz 91 clock-frequency = <0>; // 825 MHz, from uboot 92 next-level-cache = <&L2>; 93 }; 94 }; 95 96 memory { 97 device_type = "memory"; 98 reg = <0x0 0x10000000>; // 256M at 0x0 99 }; 100 101 localbus@e0005000 { 102 #address-cells = <2>; 103 #size-cells = <1>; 104 compatible = "fsl,lbc", "fsl,elbc"; 105 reg = <0xe0005000 0x1000>; 106 interrupts = <19 2>; 107 interrupt-parent = <&mpic>; 108 109 ranges = <0x0 0x0 0xff800000 0x00800000 110 0x1 0x0 0xff000000 0x00800000 111 0x2 0x0 0xf8000000 0x00008000>; 112 113 nor@0,0 { 114 #address-cells = <1>; 115 #size-cells = <1>; 116 compatible = "cfi-flash"; 117 reg = <0x0 0x0 0x00800000>; 118 bank-width = <2>; 119 device-width = <1>; 120 }; 121 122 nor@1,0 { 123 #address-cells = <1>; 124 #size-cells = <1>; 125 compatible = "cfi-flash"; 126 reg = <0x1 0x0 0x00800000>; 127 bank-width = <2>; 128 device-width = <1>; 129 }; 130 131 rtc@2,0 { 132 #address-cells = <1>; 133 #size-cells = <1>; 134 compatible = "dallas,ds1553"; 135 reg = <0x2 0x0 0x00008000>; 136 bank-width = <1>; 137 device-width = <1>; 138 }; 139 }; 140 141 soc8555@e0000000 { 142 #address-cells = <1>; 143 #size-cells = <1>; 144 device_type = "soc"; 145 compatible = "simple-bus"; 146 ranges = <0x0 0xe0000000 0x100000>; 147 bus-frequency = <0>; 148 149 ecm-law@0 { 150 compatible = "fsl,ecm-law"; 151 reg = <0x0 0x1000>; 152 fsl,num-laws = <8>; 153 }; 154 155 ecm@1000 { 156 compatible = "fsl,mpc8555-ecm", "fsl,ecm"; 157 reg = <0x1000 0x1000>; 158 interrupts = <17 2>; 159 interrupt-parent = <&mpic>; 160 }; 161 162 memory-controller@2000 { 163 compatible = "fsl,8555-memory-controller"; 164 reg = <0x2000 0x1000>; 165 interrupt-parent = <&mpic>; 166 interrupts = <18 2>; 167 }; 168 169 L2: l2-cache-controller@20000 { 170 compatible = "fsl,8555-l2-cache-controller"; 171 reg = <0x20000 0x1000>; 172 cache-line-size = <32>; // 32 bytes 173 cache-size = <0x40000>; // L2, 256K 174 interrupt-parent = <&mpic>; 175 interrupts = <16 2>; 176 }; 177 178 i2c@3000 { 179 #address-cells = <1>; 180 #size-cells = <0>; 181 cell-index = <0>; 182 compatible = "fsl-i2c"; 183 reg = <0x3000 0x100>; 184 interrupts = <43 2>; 185 interrupt-parent = <&mpic>; 186 dfsrr; 187 }; 188 189 dma@21300 { 190 #address-cells = <1>; 191 #size-cells = <1>; 192 compatible = "fsl,mpc8555-dma", "fsl,eloplus-dma"; 193 reg = <0x21300 0x4>; 194 ranges = <0x0 0x21100 0x200>; 195 cell-index = <0>; 196 dma-channel@0 { 197 compatible = "fsl,mpc8555-dma-channel", 198 "fsl,eloplus-dma-channel"; 199 reg = <0x0 0x80>; 200 cell-index = <0>; 201 interrupt-parent = <&mpic>; 202 interrupts = <20 2>; 203 }; 204 dma-channel@80 { 205 compatible = "fsl,mpc8555-dma-channel", 206 "fsl,eloplus-dma-channel"; 207 reg = <0x80 0x80>; 208 cell-index = <1>; 209 interrupt-parent = <&mpic>; 210 interrupts = <21 2>; 211 }; 212 dma-channel@100 { 213 compatible = "fsl,mpc8555-dma-channel", 214 "fsl,eloplus-dma-channel"; 215 reg = <0x100 0x80>; 216 cell-index = <2>; 217 interrupt-parent = <&mpic>; 218 interrupts = <22 2>; 219 }; 220 dma-channel@180 { 221 compatible = "fsl,mpc8555-dma-channel", 222 "fsl,eloplus-dma-channel"; 223 reg = <0x180 0x80>; 224 cell-index = <3>; 225 interrupt-parent = <&mpic>; 226 interrupts = <23 2>; 227 }; 228 }; 229 230 enet0: ethernet@24000 { 231 #address-cells = <1>; 232 #size-cells = <1>; 233 cell-index = <0>; 234 device_type = "network"; 235 model = "TSEC"; 236 compatible = "gianfar"; 237 reg = <0x24000 0x1000>; 238 ranges = <0x0 0x24000 0x1000>; 239 local-mac-address = [ 00 00 00 00 00 00 ]; 240 interrupts = <29 2 30 2 34 2>; 241 interrupt-parent = <&mpic>; 242 tbi-handle = <&tbi0>; 243 phy-handle = <&phy0>; 244 245 mdio@520 { 246 #address-cells = <1>; 247 #size-cells = <0>; 248 compatible = "fsl,gianfar-mdio"; 249 reg = <0x520 0x20>; 250 251 phy0: ethernet-phy@0 { 252 interrupt-parent = <&mpic>; 253 interrupts = <5 1>; 254 reg = <0x0>; 255 device_type = "ethernet-phy"; 256 }; 257 phy1: ethernet-phy@1 { 258 interrupt-parent = <&mpic>; 259 interrupts = <5 1>; 260 reg = <0x1>; 261 device_type = "ethernet-phy"; 262 }; 263 tbi0: tbi-phy@11 { 264 reg = <0x11>; 265 device_type = "tbi-phy"; 266 }; 267 }; 268 }; 269 270 enet1: ethernet@25000 { 271 #address-cells = <1>; 272 #size-cells = <1>; 273 cell-index = <1>; 274 device_type = "network"; 275 model = "TSEC"; 276 compatible = "gianfar"; 277 reg = <0x25000 0x1000>; 278 ranges = <0x0 0x25000 0x1000>; 279 local-mac-address = [ 00 00 00 00 00 00 ]; 280 interrupts = <35 2 36 2 40 2>; 281 interrupt-parent = <&mpic>; 282 tbi-handle = <&tbi1>; 283 phy-handle = <&phy1>; 284 285 mdio@520 { 286 #address-cells = <1>; 287 #size-cells = <0>; 288 compatible = "fsl,gianfar-tbi"; 289 reg = <0x520 0x20>; 290 291 tbi1: tbi-phy@11 { 292 reg = <0x11>; 293 device_type = "tbi-phy"; 294 }; 295 }; 296 }; 297 298 serial0: serial@4500 { 299 cell-index = <0>; 300 device_type = "serial"; 301 compatible = "ns16550"; 302 reg = <0x4500 0x100>; // reg base, size 303 clock-frequency = <0>; // should we fill in in uboot? 304 interrupts = <42 2>; 305 interrupt-parent = <&mpic>; 306 }; 307 308 serial1: serial@4600 { 309 cell-index = <1>; 310 device_type = "serial"; 311 compatible = "ns16550"; 312 reg = <0x4600 0x100>; // reg base, size 313 clock-frequency = <0>; // should we fill in in uboot? 314 interrupts = <42 2>; 315 interrupt-parent = <&mpic>; 316 }; 317 318 crypto@30000 { 319 compatible = "fsl,sec2.0"; 320 reg = <0x30000 0x10000>; 321 interrupts = <45 2>; 322 interrupt-parent = <&mpic>; 323 fsl,num-channels = <4>; 324 fsl,channel-fifo-len = <24>; 325 fsl,exec-units-mask = <0x7e>; 326 fsl,descriptor-types-mask = <0x01010ebf>; 327 }; 328 329 mpic: pic@40000 { 330 interrupt-controller; 331 #address-cells = <0>; 332 #interrupt-cells = <2>; 333 reg = <0x40000 0x40000>; 334 compatible = "chrp,open-pic"; 335 device_type = "open-pic"; 336 }; 337 338 cpm@80000 { 339 #address-cells = <1>; 340 #size-cells = <1>; 341 compatible = "fsl,mpc8555-cpm", "fsl,cpm2"; 342 reg = <0x80000 0x20000>; 343 interrupts = <46 2>; 344 interrupt-parent = <&mpic>; 345 }; 346 }; 347 348 pci0: pci@e0008000 { 349 interrupt-map-mask = <0x1f800 0x0 0x0 0x7>; 350 interrupt-map = < 351 352 /* IDSEL 0x10 */ 353 0x8000 0x0 0x0 0x1 &mpic 0x0 0x1 354 0x8000 0x0 0x0 0x2 &mpic 0x1 0x1 355 0x8000 0x0 0x0 0x3 &mpic 0x2 0x1 356 0x8000 0x0 0x0 0x4 &mpic 0x3 0x1 357 358 /* IDSEL 0x11 */ 359 0x8800 0x0 0x0 0x1 &mpic 0x0 0x1 360 0x8800 0x0 0x0 0x2 &mpic 0x1 0x1 361 0x8800 0x0 0x0 0x3 &mpic 0x2 0x1 362 0x8800 0x0 0x0 0x4 &mpic 0x3 0x1 363 364 /* IDSEL 0x12 (Slot 1) */ 365 0x9000 0x0 0x0 0x1 &mpic 0x0 0x1 366 0x9000 0x0 0x0 0x2 &mpic 0x1 0x1 367 0x9000 0x0 0x0 0x3 &mpic 0x2 0x1 368 0x9000 0x0 0x0 0x4 &mpic 0x3 0x1 369 370 /* IDSEL 0x13 (Slot 2) */ 371 0x9800 0x0 0x0 0x1 &mpic 0x1 0x1 372 0x9800 0x0 0x0 0x2 &mpic 0x2 0x1 373 0x9800 0x0 0x0 0x3 &mpic 0x3 0x1 374 0x9800 0x0 0x0 0x4 &mpic 0x0 0x1 375 376 /* IDSEL 0x14 (Slot 3) */ 377 0xa000 0x0 0x0 0x1 &mpic 0x2 0x1 378 0xa000 0x0 0x0 0x2 &mpic 0x3 0x1 379 0xa000 0x0 0x0 0x3 &mpic 0x0 0x1 380 0xa000 0x0 0x0 0x4 &mpic 0x1 0x1 381 382 /* IDSEL 0x15 (Slot 4) */ 383 0xa800 0x0 0x0 0x1 &mpic 0x3 0x1 384 0xa800 0x0 0x0 0x2 &mpic 0x0 0x1 385 0xa800 0x0 0x0 0x3 &mpic 0x1 0x1 386 0xa800 0x0 0x0 0x4 &mpic 0x2 0x1 387 388 /* Bus 1 (Tundra Bridge) */ 389 /* IDSEL 0x12 (ISA bridge) */ 390 0x19000 0x0 0x0 0x1 &mpic 0x0 0x1 391 0x19000 0x0 0x0 0x2 &mpic 0x1 0x1 392 0x19000 0x0 0x0 0x3 &mpic 0x2 0x1 393 0x19000 0x0 0x0 0x4 &mpic 0x3 0x1>; 394 interrupt-parent = <&mpic>; 395 interrupts = <24 2>; 396 bus-range = <0 0>; 397 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x10000000 398 0x1000000 0x0 0x0 0xfee00000 0x0 0x00010000>; 399 clock-frequency = <66666666>; 400 #interrupt-cells = <1>; 401 #size-cells = <2>; 402 #address-cells = <3>; 403 reg = <0xe0008000 0x1000>; 404 compatible = "fsl,mpc8540-pci"; 405 device_type = "pci"; 406 407 i8259@19000 { 408 interrupt-controller; 409 device_type = "interrupt-controller"; 410 reg = <0x19000 0x0 0x0 0x0 0x1>; 411 #address-cells = <0>; 412 #interrupt-cells = <2>; 413 compatible = "chrp,iic"; 414 interrupts = <1>; 415 interrupt-parent = <&pci0>; 416 }; 417 }; 418 419 pci1: pci@e0009000 { 420 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 421 interrupt-map = < 422 423 /* IDSEL 0x15 */ 424 0xa800 0x0 0x0 0x1 &mpic 0xb 0x1 425 0xa800 0x0 0x0 0x2 &mpic 0xb 0x1 426 0xa800 0x0 0x0 0x3 &mpic 0xb 0x1 427 0xa800 0x0 0x0 0x4 &mpic 0xb 0x1>; 428 interrupt-parent = <&mpic>; 429 interrupts = <25 2>; 430 bus-range = <0 0>; 431 ranges = <0x2000000 0x0 0x90000000 0x90000000 0x0 0x10000000 432 0x1000000 0x0 0x0 0xfee10000 0x0 0x00010000>; 433 clock-frequency = <66666666>; 434 #interrupt-cells = <1>; 435 #size-cells = <2>; 436 #address-cells = <3>; 437 reg = <0xe0009000 0x1000>; 438 compatible = "fsl,mpc8540-pci"; 439 device_type = "pci"; 440 }; 441}; 442