1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) KATO Takenori, 1997, 1998. 5 * 6 * All rights reserved. Unpublished rights reserved under the copyright 7 * laws of Japan. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer as 15 * the first lines of this file unmodified. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 #include "opt_cpu.h" 34 35 #include <sys/param.h> 36 #include <sys/kernel.h> 37 #include <sys/systm.h> 38 #include <sys/sysctl.h> 39 40 #include <machine/cputypes.h> 41 #include <machine/md_var.h> 42 #include <machine/psl.h> 43 #include <machine/specialreg.h> 44 45 #include <vm/vm.h> 46 #include <vm/pmap.h> 47 48 #ifdef I486_CPU 49 static void init_5x86(void); 50 static void init_bluelightning(void); 51 static void init_486dlc(void); 52 static void init_cy486dx(void); 53 #ifdef CPU_I486_ON_386 54 static void init_i486_on_386(void); 55 #endif 56 static void init_6x86(void); 57 #endif /* I486_CPU */ 58 59 #if defined(I586_CPU) && defined(CPU_WT_ALLOC) 60 static void enable_K5_wt_alloc(void); 61 static void enable_K6_wt_alloc(void); 62 static void enable_K6_2_wt_alloc(void); 63 #endif 64 65 #ifdef I686_CPU 66 static void init_6x86MX(void); 67 static void init_ppro(void); 68 static void init_mendocino(void); 69 #endif 70 71 static int hw_instruction_sse; 72 SYSCTL_INT(_hw, OID_AUTO, instruction_sse, CTLFLAG_RD, 73 &hw_instruction_sse, 0, "SIMD/MMX2 instructions available in CPU"); 74 /* 75 * -1: automatic (default) 76 * 0: keep enable CLFLUSH 77 * 1: force disable CLFLUSH 78 */ 79 static int hw_clflush_disable = -1; 80 81 u_int cyrix_did; /* Device ID of Cyrix CPU */ 82 83 #ifdef I486_CPU 84 /* 85 * IBM Blue Lightning 86 */ 87 static void 88 init_bluelightning(void) 89 { 90 register_t saveintr; 91 92 saveintr = intr_disable(); 93 94 load_cr0(rcr0() | CR0_CD | CR0_NW); 95 invd(); 96 97 #ifdef CPU_BLUELIGHTNING_FPU_OP_CACHE 98 wrmsr(0x1000, 0x9c92LL); /* FP operand can be cacheable on Cyrix FPU */ 99 #else 100 wrmsr(0x1000, 0x1c92LL); /* Intel FPU */ 101 #endif 102 /* Enables 13MB and 0-640KB cache. */ 103 wrmsr(0x1001, (0xd0LL << 32) | 0x3ff); 104 #ifdef CPU_BLUELIGHTNING_3X 105 wrmsr(0x1002, 0x04000000LL); /* Enables triple-clock mode. */ 106 #else 107 wrmsr(0x1002, 0x03000000LL); /* Enables double-clock mode. */ 108 #endif 109 110 /* Enable caching in CR0. */ 111 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */ 112 invd(); 113 intr_restore(saveintr); 114 } 115 116 /* 117 * Cyrix 486SLC/DLC/SR/DR series 118 */ 119 static void 120 init_486dlc(void) 121 { 122 register_t saveintr; 123 u_char ccr0; 124 125 saveintr = intr_disable(); 126 invd(); 127 128 ccr0 = read_cyrix_reg(CCR0); 129 #ifndef CYRIX_CACHE_WORKS 130 ccr0 |= CCR0_NC1 | CCR0_BARB; 131 write_cyrix_reg(CCR0, ccr0); 132 invd(); 133 #else 134 ccr0 &= ~CCR0_NC0; 135 #ifndef CYRIX_CACHE_REALLY_WORKS 136 ccr0 |= CCR0_NC1 | CCR0_BARB; 137 #else 138 ccr0 |= CCR0_NC1; 139 #endif 140 #ifdef CPU_DIRECT_MAPPED_CACHE 141 ccr0 |= CCR0_CO; /* Direct mapped mode. */ 142 #endif 143 write_cyrix_reg(CCR0, ccr0); 144 145 /* Clear non-cacheable region. */ 146 write_cyrix_reg(NCR1+2, NCR_SIZE_0K); 147 write_cyrix_reg(NCR2+2, NCR_SIZE_0K); 148 write_cyrix_reg(NCR3+2, NCR_SIZE_0K); 149 write_cyrix_reg(NCR4+2, NCR_SIZE_0K); 150 151 write_cyrix_reg(0, 0); /* dummy write */ 152 153 /* Enable caching in CR0. */ 154 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */ 155 invd(); 156 #endif /* !CYRIX_CACHE_WORKS */ 157 intr_restore(saveintr); 158 } 159 160 /* 161 * Cyrix 486S/DX series 162 */ 163 static void 164 init_cy486dx(void) 165 { 166 register_t saveintr; 167 u_char ccr2; 168 169 saveintr = intr_disable(); 170 invd(); 171 172 ccr2 = read_cyrix_reg(CCR2); 173 #ifdef CPU_SUSP_HLT 174 ccr2 |= CCR2_SUSP_HLT; 175 #endif 176 177 write_cyrix_reg(CCR2, ccr2); 178 intr_restore(saveintr); 179 } 180 181 /* 182 * Cyrix 5x86 183 */ 184 static void 185 init_5x86(void) 186 { 187 register_t saveintr; 188 u_char ccr2, ccr3, ccr4, pcr0; 189 190 saveintr = intr_disable(); 191 192 load_cr0(rcr0() | CR0_CD | CR0_NW); 193 wbinvd(); 194 195 (void)read_cyrix_reg(CCR3); /* dummy */ 196 197 /* Initialize CCR2. */ 198 ccr2 = read_cyrix_reg(CCR2); 199 ccr2 |= CCR2_WB; 200 #ifdef CPU_SUSP_HLT 201 ccr2 |= CCR2_SUSP_HLT; 202 #else 203 ccr2 &= ~CCR2_SUSP_HLT; 204 #endif 205 ccr2 |= CCR2_WT1; 206 write_cyrix_reg(CCR2, ccr2); 207 208 /* Initialize CCR4. */ 209 ccr3 = read_cyrix_reg(CCR3); 210 write_cyrix_reg(CCR3, CCR3_MAPEN0); 211 212 ccr4 = read_cyrix_reg(CCR4); 213 ccr4 |= CCR4_DTE; 214 ccr4 |= CCR4_MEM; 215 #ifdef CPU_FASTER_5X86_FPU 216 ccr4 |= CCR4_FASTFPE; 217 #else 218 ccr4 &= ~CCR4_FASTFPE; 219 #endif 220 ccr4 &= ~CCR4_IOMASK; 221 /******************************************************************** 222 * WARNING: The "BIOS Writers Guide" mentions that I/O recovery time 223 * should be 0 for errata fix. 224 ********************************************************************/ 225 #ifdef CPU_IORT 226 ccr4 |= CPU_IORT & CCR4_IOMASK; 227 #endif 228 write_cyrix_reg(CCR4, ccr4); 229 230 /* Initialize PCR0. */ 231 /**************************************************************** 232 * WARNING: RSTK_EN and LOOP_EN could make your system unstable. 233 * BTB_EN might make your system unstable. 234 ****************************************************************/ 235 pcr0 = read_cyrix_reg(PCR0); 236 #ifdef CPU_RSTK_EN 237 pcr0 |= PCR0_RSTK; 238 #else 239 pcr0 &= ~PCR0_RSTK; 240 #endif 241 #ifdef CPU_BTB_EN 242 pcr0 |= PCR0_BTB; 243 #else 244 pcr0 &= ~PCR0_BTB; 245 #endif 246 #ifdef CPU_LOOP_EN 247 pcr0 |= PCR0_LOOP; 248 #else 249 pcr0 &= ~PCR0_LOOP; 250 #endif 251 252 /**************************************************************** 253 * WARNING: if you use a memory mapped I/O device, don't use 254 * DISABLE_5X86_LSSER option, which may reorder memory mapped 255 * I/O access. 256 * IF YOUR MOTHERBOARD HAS PCI BUS, DON'T DISABLE LSSER. 257 ****************************************************************/ 258 #ifdef CPU_DISABLE_5X86_LSSER 259 pcr0 &= ~PCR0_LSSER; 260 #else 261 pcr0 |= PCR0_LSSER; 262 #endif 263 write_cyrix_reg(PCR0, pcr0); 264 265 /* Restore CCR3. */ 266 write_cyrix_reg(CCR3, ccr3); 267 268 (void)read_cyrix_reg(0x80); /* dummy */ 269 270 /* Unlock NW bit in CR0. */ 271 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW); 272 load_cr0((rcr0() & ~CR0_CD) | CR0_NW); /* CD = 0, NW = 1 */ 273 /* Lock NW bit in CR0. */ 274 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW); 275 276 intr_restore(saveintr); 277 } 278 279 #ifdef CPU_I486_ON_386 280 /* 281 * There are i486 based upgrade products for i386 machines. 282 * In this case, BIOS doesn't enable CPU cache. 283 */ 284 static void 285 init_i486_on_386(void) 286 { 287 register_t saveintr; 288 289 saveintr = intr_disable(); 290 291 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0, NW = 0 */ 292 293 intr_restore(saveintr); 294 } 295 #endif 296 297 /* 298 * Cyrix 6x86 299 * 300 * XXX - What should I do here? Please let me know. 301 */ 302 static void 303 init_6x86(void) 304 { 305 register_t saveintr; 306 u_char ccr3, ccr4; 307 308 saveintr = intr_disable(); 309 310 load_cr0(rcr0() | CR0_CD | CR0_NW); 311 wbinvd(); 312 313 /* Initialize CCR0. */ 314 write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) | CCR0_NC1); 315 316 /* Initialize CCR1. */ 317 #ifdef CPU_CYRIX_NO_LOCK 318 write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) | CCR1_NO_LOCK); 319 #else 320 write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) & ~CCR1_NO_LOCK); 321 #endif 322 323 /* Initialize CCR2. */ 324 #ifdef CPU_SUSP_HLT 325 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_SUSP_HLT); 326 #else 327 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_SUSP_HLT); 328 #endif 329 330 ccr3 = read_cyrix_reg(CCR3); 331 write_cyrix_reg(CCR3, CCR3_MAPEN0); 332 333 /* Initialize CCR4. */ 334 ccr4 = read_cyrix_reg(CCR4); 335 ccr4 |= CCR4_DTE; 336 ccr4 &= ~CCR4_IOMASK; 337 #ifdef CPU_IORT 338 write_cyrix_reg(CCR4, ccr4 | (CPU_IORT & CCR4_IOMASK)); 339 #else 340 write_cyrix_reg(CCR4, ccr4 | 7); 341 #endif 342 343 /* Initialize CCR5. */ 344 #ifdef CPU_WT_ALLOC 345 write_cyrix_reg(CCR5, read_cyrix_reg(CCR5) | CCR5_WT_ALLOC); 346 #endif 347 348 /* Restore CCR3. */ 349 write_cyrix_reg(CCR3, ccr3); 350 351 /* Unlock NW bit in CR0. */ 352 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW); 353 354 /* 355 * Earlier revision of the 6x86 CPU could crash the system if 356 * L1 cache is in write-back mode. 357 */ 358 if ((cyrix_did & 0xff00) > 0x1600) 359 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */ 360 else { 361 /* Revision 2.6 and lower. */ 362 #ifdef CYRIX_CACHE_REALLY_WORKS 363 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */ 364 #else 365 load_cr0((rcr0() & ~CR0_CD) | CR0_NW); /* CD = 0 and NW = 1 */ 366 #endif 367 } 368 369 /* Lock NW bit in CR0. */ 370 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW); 371 372 intr_restore(saveintr); 373 } 374 #endif /* I486_CPU */ 375 376 #ifdef I586_CPU 377 /* 378 * Rise mP6 379 */ 380 static void 381 init_rise(void) 382 { 383 384 /* 385 * The CMPXCHG8B instruction is always available but hidden. 386 */ 387 cpu_feature |= CPUID_CX8; 388 } 389 390 /* 391 * IDT WinChip C6/2/2A/2B/3 392 * 393 * http://www.centtech.com/winchip_bios_writers_guide_v4_0.pdf 394 */ 395 static void 396 init_winchip(void) 397 { 398 u_int regs[4]; 399 uint64_t fcr; 400 401 fcr = rdmsr(0x0107); 402 403 /* 404 * Set ECX8, DSMC, DTLOCK/EDCTLB, EMMX, and ERETSTK and clear DPDC. 405 */ 406 fcr |= (1 << 1) | (1 << 7) | (1 << 8) | (1 << 9) | (1 << 16); 407 fcr &= ~(1ULL << 11); 408 409 /* 410 * Additionally, set EBRPRED, E2MMX and EAMD3D for WinChip 2 and 3. 411 */ 412 if (CPUID_TO_MODEL(cpu_id) >= 8) 413 fcr |= (1 << 12) | (1 << 19) | (1 << 20); 414 415 wrmsr(0x0107, fcr); 416 do_cpuid(1, regs); 417 cpu_feature = regs[3]; 418 } 419 #endif 420 421 #ifdef I686_CPU 422 /* 423 * Cyrix 6x86MX (code-named M2) 424 * 425 * XXX - What should I do here? Please let me know. 426 */ 427 static void 428 init_6x86MX(void) 429 { 430 register_t saveintr; 431 u_char ccr3, ccr4; 432 433 saveintr = intr_disable(); 434 435 load_cr0(rcr0() | CR0_CD | CR0_NW); 436 wbinvd(); 437 438 /* Initialize CCR0. */ 439 write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) | CCR0_NC1); 440 441 /* Initialize CCR1. */ 442 #ifdef CPU_CYRIX_NO_LOCK 443 write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) | CCR1_NO_LOCK); 444 #else 445 write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) & ~CCR1_NO_LOCK); 446 #endif 447 448 /* Initialize CCR2. */ 449 #ifdef CPU_SUSP_HLT 450 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_SUSP_HLT); 451 #else 452 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_SUSP_HLT); 453 #endif 454 455 ccr3 = read_cyrix_reg(CCR3); 456 write_cyrix_reg(CCR3, CCR3_MAPEN0); 457 458 /* Initialize CCR4. */ 459 ccr4 = read_cyrix_reg(CCR4); 460 ccr4 &= ~CCR4_IOMASK; 461 #ifdef CPU_IORT 462 write_cyrix_reg(CCR4, ccr4 | (CPU_IORT & CCR4_IOMASK)); 463 #else 464 write_cyrix_reg(CCR4, ccr4 | 7); 465 #endif 466 467 /* Initialize CCR5. */ 468 #ifdef CPU_WT_ALLOC 469 write_cyrix_reg(CCR5, read_cyrix_reg(CCR5) | CCR5_WT_ALLOC); 470 #endif 471 472 /* Restore CCR3. */ 473 write_cyrix_reg(CCR3, ccr3); 474 475 /* Unlock NW bit in CR0. */ 476 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW); 477 478 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */ 479 480 /* Lock NW bit in CR0. */ 481 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW); 482 483 intr_restore(saveintr); 484 } 485 486 static int ppro_apic_used = -1; 487 488 static void 489 init_ppro(void) 490 { 491 u_int64_t apicbase; 492 493 /* 494 * Local APIC should be disabled if it is not going to be used. 495 */ 496 if (ppro_apic_used != 1) { 497 apicbase = rdmsr(MSR_APICBASE); 498 apicbase &= ~APICBASE_ENABLED; 499 wrmsr(MSR_APICBASE, apicbase); 500 ppro_apic_used = 0; 501 } 502 } 503 504 /* 505 * If the local APIC is going to be used after being disabled above, 506 * re-enable it and don't disable it in the future. 507 */ 508 void 509 ppro_reenable_apic(void) 510 { 511 u_int64_t apicbase; 512 513 if (ppro_apic_used == 0) { 514 apicbase = rdmsr(MSR_APICBASE); 515 apicbase |= APICBASE_ENABLED; 516 wrmsr(MSR_APICBASE, apicbase); 517 ppro_apic_used = 1; 518 } 519 } 520 521 /* 522 * Initialize BBL_CR_CTL3 (Control register 3: used to configure the 523 * L2 cache). 524 */ 525 static void 526 init_mendocino(void) 527 { 528 #ifdef CPU_PPRO2CELERON 529 register_t saveintr; 530 u_int64_t bbl_cr_ctl3; 531 532 saveintr = intr_disable(); 533 534 load_cr0(rcr0() | CR0_CD | CR0_NW); 535 wbinvd(); 536 537 bbl_cr_ctl3 = rdmsr(MSR_BBL_CR_CTL3); 538 539 /* If the L2 cache is configured, do nothing. */ 540 if (!(bbl_cr_ctl3 & 1)) { 541 bbl_cr_ctl3 = 0x134052bLL; 542 543 /* Set L2 Cache Latency (Default: 5). */ 544 #ifdef CPU_CELERON_L2_LATENCY 545 #if CPU_L2_LATENCY > 15 546 #error invalid CPU_L2_LATENCY. 547 #endif 548 bbl_cr_ctl3 |= CPU_L2_LATENCY << 1; 549 #else 550 bbl_cr_ctl3 |= 5 << 1; 551 #endif 552 wrmsr(MSR_BBL_CR_CTL3, bbl_cr_ctl3); 553 } 554 555 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); 556 intr_restore(saveintr); 557 #endif /* CPU_PPRO2CELERON */ 558 } 559 560 /* 561 * Initialize special VIA features 562 */ 563 static void 564 init_via(void) 565 { 566 u_int regs[4], val; 567 uint64_t fcr; 568 569 /* 570 * Explicitly enable CX8 and PGE on C3. 571 * 572 * http://www.via.com.tw/download/mainboards/6/13/VIA_C3_EBGA%20datasheet110.pdf 573 */ 574 if (CPUID_TO_MODEL(cpu_id) <= 9) 575 fcr = (1 << 1) | (1 << 7); 576 else 577 fcr = 0; 578 579 /* 580 * Check extended CPUID for PadLock features. 581 * 582 * http://www.via.com.tw/en/downloads/whitepapers/initiatives/padlock/programming_guide.pdf 583 */ 584 do_cpuid(0xc0000000, regs); 585 if (regs[0] >= 0xc0000001) { 586 do_cpuid(0xc0000001, regs); 587 val = regs[3]; 588 } else 589 val = 0; 590 591 /* Enable RNG if present. */ 592 if ((val & VIA_CPUID_HAS_RNG) != 0) { 593 via_feature_rng = VIA_HAS_RNG; 594 wrmsr(0x110B, rdmsr(0x110B) | VIA_CPUID_DO_RNG); 595 } 596 597 /* Enable PadLock if present. */ 598 if ((val & VIA_CPUID_HAS_ACE) != 0) 599 via_feature_xcrypt |= VIA_HAS_AES; 600 if ((val & VIA_CPUID_HAS_ACE2) != 0) 601 via_feature_xcrypt |= VIA_HAS_AESCTR; 602 if ((val & VIA_CPUID_HAS_PHE) != 0) 603 via_feature_xcrypt |= VIA_HAS_SHA; 604 if ((val & VIA_CPUID_HAS_PMM) != 0) 605 via_feature_xcrypt |= VIA_HAS_MM; 606 if (via_feature_xcrypt != 0) 607 fcr |= 1 << 28; 608 609 wrmsr(0x1107, rdmsr(0x1107) | fcr); 610 } 611 612 #endif /* I686_CPU */ 613 614 #if defined(I586_CPU) || defined(I686_CPU) 615 static void 616 init_transmeta(void) 617 { 618 u_int regs[0]; 619 620 /* Expose all hidden features. */ 621 wrmsr(0x80860004, rdmsr(0x80860004) | ~0UL); 622 do_cpuid(1, regs); 623 cpu_feature = regs[3]; 624 } 625 #endif 626 627 /* 628 * The value for the TSC_AUX MSR and rdtscp/rdpid on the invoking CPU. 629 * 630 * Caller should prevent CPU migration. 631 */ 632 u_int 633 cpu_auxmsr(void) 634 { 635 KASSERT((read_eflags() & PSL_I) == 0, ("context switch possible")); 636 return (PCPU_GET(cpuid)); 637 } 638 639 extern int elf32_nxstack; 640 641 void 642 initializecpu(void) 643 { 644 uint64_t msr; 645 646 switch (cpu) { 647 #ifdef I486_CPU 648 case CPU_BLUE: 649 init_bluelightning(); 650 break; 651 case CPU_486DLC: 652 init_486dlc(); 653 break; 654 case CPU_CY486DX: 655 init_cy486dx(); 656 break; 657 case CPU_M1SC: 658 init_5x86(); 659 break; 660 #ifdef CPU_I486_ON_386 661 case CPU_486: 662 init_i486_on_386(); 663 break; 664 #endif 665 case CPU_M1: 666 init_6x86(); 667 break; 668 #endif /* I486_CPU */ 669 #ifdef I586_CPU 670 case CPU_586: 671 switch (cpu_vendor_id) { 672 case CPU_VENDOR_AMD: 673 #ifdef CPU_WT_ALLOC 674 if (((cpu_id & 0x0f0) > 0) && 675 ((cpu_id & 0x0f0) < 0x60) && 676 ((cpu_id & 0x00f) > 3)) 677 enable_K5_wt_alloc(); 678 else if (((cpu_id & 0x0f0) > 0x80) || 679 (((cpu_id & 0x0f0) == 0x80) && 680 (cpu_id & 0x00f) > 0x07)) 681 enable_K6_2_wt_alloc(); 682 else if ((cpu_id & 0x0f0) > 0x50) 683 enable_K6_wt_alloc(); 684 #endif 685 if ((cpu_id & 0xf0) == 0xa0) 686 /* 687 * Make sure the TSC runs through 688 * suspension, otherwise we can't use 689 * it as timecounter 690 */ 691 wrmsr(0x1900, rdmsr(0x1900) | 0x20ULL); 692 break; 693 case CPU_VENDOR_CENTAUR: 694 init_winchip(); 695 break; 696 case CPU_VENDOR_TRANSMETA: 697 init_transmeta(); 698 break; 699 case CPU_VENDOR_RISE: 700 init_rise(); 701 break; 702 } 703 break; 704 #endif 705 #ifdef I686_CPU 706 case CPU_M2: 707 init_6x86MX(); 708 break; 709 case CPU_686: 710 switch (cpu_vendor_id) { 711 case CPU_VENDOR_INTEL: 712 switch (cpu_id & 0xff0) { 713 case 0x610: 714 init_ppro(); 715 break; 716 case 0x660: 717 init_mendocino(); 718 break; 719 } 720 break; 721 case CPU_VENDOR_AMD: 722 #ifdef CPU_ATHLON_SSE_HACK 723 /* 724 * Sometimes the BIOS doesn't enable SSE instructions. 725 * According to AMD document 20734, the mobile 726 * Duron, the (mobile) Athlon 4 and the Athlon MP 727 * support SSE. These correspond to cpu_id 0x66X 728 * or 0x67X. 729 */ 730 if ((cpu_feature & CPUID_XMM) == 0 && 731 ((cpu_id & ~0xf) == 0x660 || 732 (cpu_id & ~0xf) == 0x670 || 733 (cpu_id & ~0xf) == 0x680)) { 734 u_int regs[4]; 735 wrmsr(MSR_HWCR, rdmsr(MSR_HWCR) & ~0x08000); 736 do_cpuid(1, regs); 737 cpu_feature = regs[3]; 738 } 739 #endif 740 /* 741 * Detect C1E that breaks APIC. See comment in 742 * amd64/initcpu.c. 743 */ 744 if ((CPUID_TO_FAMILY(cpu_id) == 0xf || 745 CPUID_TO_FAMILY(cpu_id) == 0x10) && 746 (cpu_feature2 & CPUID2_HV) == 0) 747 cpu_amdc1e_bug = 1; 748 break; 749 case CPU_VENDOR_CENTAUR: 750 init_via(); 751 break; 752 case CPU_VENDOR_TRANSMETA: 753 init_transmeta(); 754 break; 755 } 756 break; 757 #endif 758 default: 759 break; 760 } 761 if ((cpu_feature & CPUID_XMM) && (cpu_feature & CPUID_FXSR)) { 762 load_cr4(rcr4() | CR4_FXSR | CR4_XMM); 763 cpu_fxsr = hw_instruction_sse = 1; 764 } 765 if (elf32_nxstack) { 766 msr = rdmsr(MSR_EFER) | EFER_NXE; 767 wrmsr(MSR_EFER, msr); 768 } 769 if ((amd_feature & AMDID_RDTSCP) != 0 || 770 (cpu_stdext_feature2 & CPUID_STDEXT2_RDPID) != 0) 771 wrmsr(MSR_TSC_AUX, cpu_auxmsr()); 772 } 773 774 void 775 initializecpucache(void) 776 { 777 778 /* 779 * CPUID with %eax = 1, %ebx returns 780 * Bits 15-8: CLFLUSH line size 781 * (Value * 8 = cache line size in bytes) 782 */ 783 if ((cpu_feature & CPUID_CLFSH) != 0) 784 cpu_clflush_line_size = ((cpu_procinfo >> 8) & 0xff) * 8; 785 /* 786 * XXXKIB: (temporary) hack to work around traps generated 787 * when CLFLUSHing APIC register window under virtualization 788 * environments. These environments tend to disable the 789 * CPUID_SS feature even though the native CPU supports it. 790 */ 791 TUNABLE_INT_FETCH("hw.clflush_disable", &hw_clflush_disable); 792 if (vm_guest != VM_GUEST_NO && hw_clflush_disable == -1) { 793 cpu_feature &= ~CPUID_CLFSH; 794 cpu_stdext_feature &= ~CPUID_STDEXT_CLFLUSHOPT; 795 } 796 /* 797 * The kernel's use of CLFLUSH{,OPT} can be disabled manually 798 * by setting the hw.clflush_disable tunable. 799 */ 800 if (hw_clflush_disable == 1) { 801 cpu_feature &= ~CPUID_CLFSH; 802 cpu_stdext_feature &= ~CPUID_STDEXT_CLFLUSHOPT; 803 } 804 } 805 806 #if defined(I586_CPU) && defined(CPU_WT_ALLOC) 807 /* 808 * Enable write allocate feature of AMD processors. 809 * Following two functions require the Maxmem variable being set. 810 */ 811 static void 812 enable_K5_wt_alloc(void) 813 { 814 u_int64_t msr; 815 register_t saveintr; 816 817 /* 818 * Write allocate is supported only on models 1, 2, and 3, with 819 * a stepping of 4 or greater. 820 */ 821 if (((cpu_id & 0xf0) > 0) && ((cpu_id & 0x0f) > 3)) { 822 saveintr = intr_disable(); 823 msr = rdmsr(0x83); /* HWCR */ 824 wrmsr(0x83, msr & !(0x10)); 825 826 /* 827 * We have to tell the chip where the top of memory is, 828 * since video cards could have frame bufferes there, 829 * memory-mapped I/O could be there, etc. 830 */ 831 if(Maxmem > 0) 832 msr = Maxmem / 16; 833 else 834 msr = 0; 835 msr |= AMD_WT_ALLOC_TME | AMD_WT_ALLOC_FRE; 836 837 /* 838 * There is no way to know whether 15-16M hole exists or not. 839 * Therefore, we disable write allocate for this range. 840 */ 841 wrmsr(0x86, 0x0ff00f0); 842 msr |= AMD_WT_ALLOC_PRE; 843 wrmsr(0x85, msr); 844 845 msr=rdmsr(0x83); 846 wrmsr(0x83, msr|0x10); /* enable write allocate */ 847 intr_restore(saveintr); 848 } 849 } 850 851 static void 852 enable_K6_wt_alloc(void) 853 { 854 quad_t size; 855 u_int64_t whcr; 856 register_t saveintr; 857 858 saveintr = intr_disable(); 859 wbinvd(); 860 861 #ifdef CPU_DISABLE_CACHE 862 /* 863 * Certain K6-2 box becomes unstable when write allocation is 864 * enabled. 865 */ 866 /* 867 * The AMD-K6 processer provides the 64-bit Test Register 12(TR12), 868 * but only the Cache Inhibit(CI) (bit 3 of TR12) is supported. 869 * All other bits in TR12 have no effect on the processer's operation. 870 * The I/O Trap Restart function (bit 9 of TR12) is always enabled 871 * on the AMD-K6. 872 */ 873 wrmsr(0x0000000e, (u_int64_t)0x0008); 874 #endif 875 /* Don't assume that memory size is aligned with 4M. */ 876 if (Maxmem > 0) 877 size = ((Maxmem >> 8) + 3) >> 2; 878 else 879 size = 0; 880 881 /* Limit is 508M bytes. */ 882 if (size > 0x7f) 883 size = 0x7f; 884 whcr = (rdmsr(0xc0000082) & ~(0x7fLL << 1)) | (size << 1); 885 886 #if defined(NO_MEMORY_HOLE) 887 if (whcr & (0x7fLL << 1)) 888 whcr |= 0x0001LL; 889 #else 890 /* 891 * There is no way to know whether 15-16M hole exists or not. 892 * Therefore, we disable write allocate for this range. 893 */ 894 whcr &= ~0x0001LL; 895 #endif 896 wrmsr(0x0c0000082, whcr); 897 898 intr_restore(saveintr); 899 } 900 901 static void 902 enable_K6_2_wt_alloc(void) 903 { 904 quad_t size; 905 u_int64_t whcr; 906 register_t saveintr; 907 908 saveintr = intr_disable(); 909 wbinvd(); 910 911 #ifdef CPU_DISABLE_CACHE 912 /* 913 * Certain K6-2 box becomes unstable when write allocation is 914 * enabled. 915 */ 916 /* 917 * The AMD-K6 processer provides the 64-bit Test Register 12(TR12), 918 * but only the Cache Inhibit(CI) (bit 3 of TR12) is supported. 919 * All other bits in TR12 have no effect on the processer's operation. 920 * The I/O Trap Restart function (bit 9 of TR12) is always enabled 921 * on the AMD-K6. 922 */ 923 wrmsr(0x0000000e, (u_int64_t)0x0008); 924 #endif 925 /* Don't assume that memory size is aligned with 4M. */ 926 if (Maxmem > 0) 927 size = ((Maxmem >> 8) + 3) >> 2; 928 else 929 size = 0; 930 931 /* Limit is 4092M bytes. */ 932 if (size > 0x3fff) 933 size = 0x3ff; 934 whcr = (rdmsr(0xc0000082) & ~(0x3ffLL << 22)) | (size << 22); 935 936 #if defined(NO_MEMORY_HOLE) 937 if (whcr & (0x3ffLL << 22)) 938 whcr |= 1LL << 16; 939 #else 940 /* 941 * There is no way to know whether 15-16M hole exists or not. 942 * Therefore, we disable write allocate for this range. 943 */ 944 whcr &= ~(1LL << 16); 945 #endif 946 wrmsr(0x0c0000082, whcr); 947 948 intr_restore(saveintr); 949 } 950 #endif /* I585_CPU && CPU_WT_ALLOC */ 951 952 #include "opt_ddb.h" 953 #ifdef DDB 954 #include <ddb/ddb.h> 955 956 DB_SHOW_COMMAND(cyrixreg, cyrixreg) 957 { 958 register_t saveintr; 959 u_int cr0; 960 u_char ccr1, ccr2, ccr3; 961 u_char ccr0 = 0, ccr4 = 0, ccr5 = 0, pcr0 = 0; 962 963 cr0 = rcr0(); 964 if (cpu_vendor_id == CPU_VENDOR_CYRIX) { 965 saveintr = intr_disable(); 966 967 if ((cpu != CPU_M1SC) && (cpu != CPU_CY486DX)) { 968 ccr0 = read_cyrix_reg(CCR0); 969 } 970 ccr1 = read_cyrix_reg(CCR1); 971 ccr2 = read_cyrix_reg(CCR2); 972 ccr3 = read_cyrix_reg(CCR3); 973 if ((cpu == CPU_M1SC) || (cpu == CPU_M1) || (cpu == CPU_M2)) { 974 write_cyrix_reg(CCR3, CCR3_MAPEN0); 975 ccr4 = read_cyrix_reg(CCR4); 976 if ((cpu == CPU_M1) || (cpu == CPU_M2)) 977 ccr5 = read_cyrix_reg(CCR5); 978 else 979 pcr0 = read_cyrix_reg(PCR0); 980 write_cyrix_reg(CCR3, ccr3); /* Restore CCR3. */ 981 } 982 intr_restore(saveintr); 983 984 if ((cpu != CPU_M1SC) && (cpu != CPU_CY486DX)) 985 printf("CCR0=%x, ", (u_int)ccr0); 986 987 printf("CCR1=%x, CCR2=%x, CCR3=%x", 988 (u_int)ccr1, (u_int)ccr2, (u_int)ccr3); 989 if ((cpu == CPU_M1SC) || (cpu == CPU_M1) || (cpu == CPU_M2)) { 990 printf(", CCR4=%x, ", (u_int)ccr4); 991 if (cpu == CPU_M1SC) 992 printf("PCR0=%x\n", pcr0); 993 else 994 printf("CCR5=%x\n", ccr5); 995 } 996 } 997 printf("CR0=%x\n", cr0); 998 } 999 #endif /* DDB */ 1000