1 /*- 2 * Copyright (c) 1990 William Jolitz. 3 * Copyright (c) 1991 The Regents of the University of California. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. Neither the name of the University nor the names of its contributors 15 * may be used to endorse or promote products derived from this software 16 * without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * from: @(#)npx.c 7.2 (Berkeley) 5/12/91 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 #include "opt_cpu.h" 37 #include "opt_isa.h" 38 #include "opt_npx.h" 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/bus.h> 43 #include <sys/kernel.h> 44 #include <sys/lock.h> 45 #include <sys/malloc.h> 46 #include <sys/module.h> 47 #include <sys/mutex.h> 48 #include <sys/mutex.h> 49 #include <sys/proc.h> 50 #include <sys/smp.h> 51 #include <sys/sysctl.h> 52 #include <machine/bus.h> 53 #include <sys/rman.h> 54 #ifdef NPX_DEBUG 55 #include <sys/syslog.h> 56 #endif 57 #include <sys/signalvar.h> 58 #include <vm/uma.h> 59 60 #include <machine/asmacros.h> 61 #include <machine/cputypes.h> 62 #include <machine/frame.h> 63 #include <machine/md_var.h> 64 #include <machine/pcb.h> 65 #include <machine/psl.h> 66 #include <machine/resource.h> 67 #include <machine/specialreg.h> 68 #include <machine/segments.h> 69 #include <machine/ucontext.h> 70 #include <x86/ifunc.h> 71 72 #include <machine/intr_machdep.h> 73 74 #ifdef DEV_ISA 75 #include <isa/isavar.h> 76 #endif 77 78 /* 79 * 387 and 287 Numeric Coprocessor Extension (NPX) Driver. 80 */ 81 82 #define fldcw(cw) __asm __volatile("fldcw %0" : : "m" (cw)) 83 #define fnclex() __asm __volatile("fnclex") 84 #define fninit() __asm __volatile("fninit") 85 #define fnsave(addr) __asm __volatile("fnsave %0" : "=m" (*(addr))) 86 #define fnstcw(addr) __asm __volatile("fnstcw %0" : "=m" (*(addr))) 87 #define fnstsw(addr) __asm __volatile("fnstsw %0" : "=am" (*(addr))) 88 #define fp_divide_by_0() __asm __volatile( \ 89 "fldz; fld1; fdiv %st,%st(1); fnop") 90 #define frstor(addr) __asm __volatile("frstor %0" : : "m" (*(addr))) 91 #define fxrstor(addr) __asm __volatile("fxrstor %0" : : "m" (*(addr))) 92 #define fxsave(addr) __asm __volatile("fxsave %0" : "=m" (*(addr))) 93 #define ldmxcsr(csr) __asm __volatile("ldmxcsr %0" : : "m" (csr)) 94 #define stmxcsr(addr) __asm __volatile("stmxcsr %0" : : "m" (*(addr))) 95 96 static __inline void 97 xrstor(char *addr, uint64_t mask) 98 { 99 uint32_t low, hi; 100 101 low = mask; 102 hi = mask >> 32; 103 __asm __volatile("xrstor %0" : : "m" (*addr), "a" (low), "d" (hi)); 104 } 105 106 static __inline void 107 xsave(char *addr, uint64_t mask) 108 { 109 uint32_t low, hi; 110 111 low = mask; 112 hi = mask >> 32; 113 __asm __volatile("xsave %0" : "=m" (*addr) : "a" (low), "d" (hi) : 114 "memory"); 115 } 116 117 static __inline void 118 xsaveopt(char *addr, uint64_t mask) 119 { 120 uint32_t low, hi; 121 122 low = mask; 123 hi = mask >> 32; 124 __asm __volatile("xsaveopt %0" : "=m" (*addr) : "a" (low), "d" (hi) : 125 "memory"); 126 } 127 128 #define start_emulating() load_cr0(rcr0() | CR0_TS) 129 #define stop_emulating() clts() 130 131 #define GET_FPU_CW(thread) \ 132 (cpu_fxsr ? \ 133 (thread)->td_pcb->pcb_save->sv_xmm.sv_env.en_cw : \ 134 (thread)->td_pcb->pcb_save->sv_87.sv_env.en_cw) 135 #define GET_FPU_SW(thread) \ 136 (cpu_fxsr ? \ 137 (thread)->td_pcb->pcb_save->sv_xmm.sv_env.en_sw : \ 138 (thread)->td_pcb->pcb_save->sv_87.sv_env.en_sw) 139 #define SET_FPU_CW(savefpu, value) do { \ 140 if (cpu_fxsr) \ 141 (savefpu)->sv_xmm.sv_env.en_cw = (value); \ 142 else \ 143 (savefpu)->sv_87.sv_env.en_cw = (value); \ 144 } while (0) 145 146 CTASSERT(sizeof(union savefpu) == 512); 147 CTASSERT(sizeof(struct xstate_hdr) == 64); 148 CTASSERT(sizeof(struct savefpu_ymm) == 832); 149 150 /* 151 * This requirement is to make it easier for asm code to calculate 152 * offset of the fpu save area from the pcb address. FPU save area 153 * must be 64-byte aligned. 154 */ 155 CTASSERT(sizeof(struct pcb) % XSAVE_AREA_ALIGN == 0); 156 157 /* 158 * Ensure the copy of XCR0 saved in a core is contained in the padding 159 * area. 160 */ 161 CTASSERT(X86_XSTATE_XCR0_OFFSET >= offsetof(struct savexmm, sv_pad) && 162 X86_XSTATE_XCR0_OFFSET + sizeof(uint64_t) <= sizeof(struct savexmm)); 163 164 static void fpu_clean_state(void); 165 166 static void fpurstor(union savefpu *); 167 168 int hw_float; 169 170 SYSCTL_INT(_hw, HW_FLOATINGPT, floatingpoint, CTLFLAG_RD, 171 &hw_float, 0, "Floating point instructions executed in hardware"); 172 173 int lazy_fpu_switch = 0; 174 SYSCTL_INT(_hw, OID_AUTO, lazy_fpu_switch, CTLFLAG_RWTUN | CTLFLAG_NOFETCH, 175 &lazy_fpu_switch, 0, 176 "Lazily load FPU context after context switch"); 177 178 u_int cpu_fxsr; /* SSE enabled */ 179 int use_xsave; 180 uint64_t xsave_mask; 181 static uma_zone_t fpu_save_area_zone; 182 static union savefpu *npx_initialstate; 183 184 static struct xsave_area_elm_descr { 185 u_int offset; 186 u_int size; 187 } *xsave_area_desc; 188 189 static volatile u_int npx_traps_while_probing; 190 191 alias_for_inthand_t probetrap; 192 __asm(" \n\ 193 .text \n\ 194 .p2align 2,0x90 \n\ 195 .type " __XSTRING(CNAME(probetrap)) ",@function \n\ 196 " __XSTRING(CNAME(probetrap)) ": \n\ 197 ss \n\ 198 incl " __XSTRING(CNAME(npx_traps_while_probing)) " \n\ 199 fnclex \n\ 200 iret \n\ 201 "); 202 203 /* 204 * Determine if an FPU is present and how to use it. 205 */ 206 static int 207 npx_probe(void) 208 { 209 struct gate_descriptor save_idt_npxtrap; 210 u_short control, status; 211 212 /* 213 * Modern CPUs all have an FPU that uses the INT16 interface 214 * and provide a simple way to verify that, so handle the 215 * common case right away. 216 */ 217 if (cpu_feature & CPUID_FPU) { 218 hw_float = 1; 219 return (1); 220 } 221 222 save_idt_npxtrap = idt[IDT_MF]; 223 setidt(IDT_MF, probetrap, SDT_SYS386TGT, SEL_KPL, 224 GSEL(GCODE_SEL, SEL_KPL)); 225 226 /* 227 * Don't trap while we're probing. 228 */ 229 stop_emulating(); 230 231 /* 232 * Finish resetting the coprocessor, if any. If there is an error 233 * pending, then we may get a bogus IRQ13, but npx_intr() will handle 234 * it OK. Bogus halts have never been observed, but we enabled 235 * IRQ13 and cleared the BUSY# latch early to handle them anyway. 236 */ 237 fninit(); 238 239 /* 240 * Don't use fwait here because it might hang. 241 * Don't use fnop here because it usually hangs if there is no FPU. 242 */ 243 DELAY(1000); /* wait for any IRQ13 */ 244 #ifdef DIAGNOSTIC 245 if (npx_traps_while_probing != 0) 246 printf("fninit caused %u bogus npx trap(s)\n", 247 npx_traps_while_probing); 248 #endif 249 /* 250 * Check for a status of mostly zero. 251 */ 252 status = 0x5a5a; 253 fnstsw(&status); 254 if ((status & 0xb8ff) == 0) { 255 /* 256 * Good, now check for a proper control word. 257 */ 258 control = 0x5a5a; 259 fnstcw(&control); 260 if ((control & 0x1f3f) == 0x033f) { 261 /* 262 * We have an npx, now divide by 0 to see if exception 263 * 16 works. 264 */ 265 control &= ~(1 << 2); /* enable divide by 0 trap */ 266 fldcw(control); 267 npx_traps_while_probing = 0; 268 fp_divide_by_0(); 269 if (npx_traps_while_probing != 0) { 270 /* 271 * Good, exception 16 works. 272 */ 273 hw_float = 1; 274 goto cleanup; 275 } 276 printf( 277 "FPU does not use exception 16 for error reporting\n"); 278 goto cleanup; 279 } 280 } 281 282 /* 283 * Probe failed. Floating point simply won't work. 284 * Notify user and disable FPU/MMX/SSE instruction execution. 285 */ 286 printf("WARNING: no FPU!\n"); 287 __asm __volatile("smsw %%ax; orb %0,%%al; lmsw %%ax" : : 288 "n" (CR0_EM | CR0_MP) : "ax"); 289 290 cleanup: 291 idt[IDT_MF] = save_idt_npxtrap; 292 return (hw_float); 293 } 294 295 static void 296 fpusave_xsaveopt(union savefpu *addr) 297 { 298 299 xsaveopt((char *)addr, xsave_mask); 300 } 301 302 static void 303 fpusave_xsave(union savefpu *addr) 304 { 305 306 xsave((char *)addr, xsave_mask); 307 } 308 309 static void 310 fpusave_fxsave(union savefpu *addr) 311 { 312 313 fxsave((char *)addr); 314 } 315 316 static void 317 fpusave_fnsave(union savefpu *addr) 318 { 319 320 fnsave((char *)addr); 321 } 322 323 DEFINE_IFUNC(, void, fpusave, (union savefpu *)) 324 { 325 if (use_xsave) 326 return ((cpu_stdext_feature & CPUID_EXTSTATE_XSAVEOPT) != 0 ? 327 fpusave_xsaveopt : fpusave_xsave); 328 if (cpu_fxsr) 329 return (fpusave_fxsave); 330 return (fpusave_fnsave); 331 } 332 333 /* 334 * Enable XSAVE if supported and allowed by user. 335 * Calculate the xsave_mask. 336 */ 337 static void 338 npxinit_bsp1(void) 339 { 340 u_int cp[4]; 341 uint64_t xsave_mask_user; 342 343 TUNABLE_INT_FETCH("hw.lazy_fpu_switch", &lazy_fpu_switch); 344 if (!use_xsave) 345 return; 346 cpuid_count(0xd, 0x0, cp); 347 xsave_mask = XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE; 348 if ((cp[0] & xsave_mask) != xsave_mask) 349 panic("CPU0 does not support X87 or SSE: %x", cp[0]); 350 xsave_mask = ((uint64_t)cp[3] << 32) | cp[0]; 351 xsave_mask_user = xsave_mask; 352 TUNABLE_QUAD_FETCH("hw.xsave_mask", &xsave_mask_user); 353 xsave_mask_user |= XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE; 354 xsave_mask &= xsave_mask_user; 355 if ((xsave_mask & XFEATURE_AVX512) != XFEATURE_AVX512) 356 xsave_mask &= ~XFEATURE_AVX512; 357 if ((xsave_mask & XFEATURE_MPX) != XFEATURE_MPX) 358 xsave_mask &= ~XFEATURE_MPX; 359 } 360 361 /* 362 * Calculate the fpu save area size. 363 */ 364 static void 365 npxinit_bsp2(void) 366 { 367 u_int cp[4]; 368 369 if (use_xsave) { 370 cpuid_count(0xd, 0x0, cp); 371 cpu_max_ext_state_size = cp[1]; 372 373 /* 374 * Reload the cpu_feature2, since we enabled OSXSAVE. 375 */ 376 do_cpuid(1, cp); 377 cpu_feature2 = cp[2]; 378 } else 379 cpu_max_ext_state_size = sizeof(union savefpu); 380 } 381 382 /* 383 * Initialize floating point unit. 384 */ 385 void 386 npxinit(bool bsp) 387 { 388 static union savefpu dummy; 389 register_t saveintr; 390 u_int mxcsr; 391 u_short control; 392 393 if (bsp) { 394 if (!npx_probe()) 395 return; 396 npxinit_bsp1(); 397 } 398 399 if (use_xsave) { 400 load_cr4(rcr4() | CR4_XSAVE); 401 load_xcr(XCR0, xsave_mask); 402 } 403 404 /* 405 * XCR0 shall be set up before CPU can report the save area size. 406 */ 407 if (bsp) 408 npxinit_bsp2(); 409 410 /* 411 * fninit has the same h/w bugs as fnsave. Use the detoxified 412 * fnsave to throw away any junk in the fpu. fpusave() initializes 413 * the fpu. 414 * 415 * It is too early for critical_enter() to work on AP. 416 */ 417 saveintr = intr_disable(); 418 stop_emulating(); 419 if (cpu_fxsr) 420 fninit(); 421 else 422 fnsave(&dummy); 423 control = __INITIAL_NPXCW__; 424 fldcw(control); 425 if (cpu_fxsr) { 426 mxcsr = __INITIAL_MXCSR__; 427 ldmxcsr(mxcsr); 428 } 429 start_emulating(); 430 intr_restore(saveintr); 431 } 432 433 /* 434 * On the boot CPU we generate a clean state that is used to 435 * initialize the floating point unit when it is first used by a 436 * process. 437 */ 438 static void 439 npxinitstate(void *arg __unused) 440 { 441 uint64_t *xstate_bv; 442 register_t saveintr; 443 int cp[4], i, max_ext_n; 444 445 if (!hw_float) 446 return; 447 448 /* Do potentially blocking operations before disabling interrupts. */ 449 fpu_save_area_zone = uma_zcreate("FPU_save_area", 450 cpu_max_ext_state_size, NULL, NULL, NULL, NULL, 451 XSAVE_AREA_ALIGN - 1, 0); 452 npx_initialstate = uma_zalloc(fpu_save_area_zone, M_WAITOK | M_ZERO); 453 if (use_xsave) { 454 if (xsave_mask >> 32 != 0) 455 max_ext_n = fls(xsave_mask >> 32) + 32; 456 else 457 max_ext_n = fls(xsave_mask); 458 xsave_area_desc = malloc(max_ext_n * sizeof(struct 459 xsave_area_elm_descr), M_DEVBUF, M_WAITOK | M_ZERO); 460 } 461 462 saveintr = intr_disable(); 463 stop_emulating(); 464 465 if (cpu_fxsr) 466 fpusave_fxsave(npx_initialstate); 467 else 468 fpusave_fnsave(npx_initialstate); 469 if (cpu_fxsr) { 470 if (npx_initialstate->sv_xmm.sv_env.en_mxcsr_mask) 471 cpu_mxcsr_mask = 472 npx_initialstate->sv_xmm.sv_env.en_mxcsr_mask; 473 else 474 cpu_mxcsr_mask = 0xFFBF; 475 476 /* 477 * The fninit instruction does not modify XMM 478 * registers or x87 registers (MM/ST). The fpusave 479 * call dumped the garbage contained in the registers 480 * after reset to the initial state saved. Clear XMM 481 * and x87 registers file image to make the startup 482 * program state and signal handler XMM/x87 register 483 * content predictable. 484 */ 485 bzero(npx_initialstate->sv_xmm.sv_fp, 486 sizeof(npx_initialstate->sv_xmm.sv_fp)); 487 bzero(npx_initialstate->sv_xmm.sv_xmm, 488 sizeof(npx_initialstate->sv_xmm.sv_xmm)); 489 490 } else 491 bzero(npx_initialstate->sv_87.sv_ac, 492 sizeof(npx_initialstate->sv_87.sv_ac)); 493 494 /* 495 * Create a table describing the layout of the CPU Extended 496 * Save Area. See Intel SDM rev. 075 Vol. 1 13.4.1 "Legacy 497 * Region of an XSAVE Area" for the source of offsets/sizes. 498 * Note that 32bit XSAVE does not use %xmm8-%xmm15, see 499 * 10.5.1.2 and 13.5.2 "SSE State". 500 */ 501 if (use_xsave) { 502 xstate_bv = (uint64_t *)((char *)(npx_initialstate + 1) + 503 offsetof(struct xstate_hdr, xstate_bv)); 504 *xstate_bv = XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE; 505 506 /* x87 state */ 507 xsave_area_desc[0].offset = 0; 508 xsave_area_desc[0].size = 160; 509 /* XMM */ 510 xsave_area_desc[1].offset = 160; 511 xsave_area_desc[1].size = 288 - 160; 512 513 for (i = 2; i < max_ext_n; i++) { 514 cpuid_count(0xd, i, cp); 515 xsave_area_desc[i].offset = cp[1]; 516 xsave_area_desc[i].size = cp[0]; 517 } 518 } 519 520 start_emulating(); 521 intr_restore(saveintr); 522 } 523 SYSINIT(npxinitstate, SI_SUB_CPU, SI_ORDER_ANY, npxinitstate, NULL); 524 525 /* 526 * Free coprocessor (if we have it). 527 */ 528 void 529 npxexit(struct thread *td) 530 { 531 532 critical_enter(); 533 if (curthread == PCPU_GET(fpcurthread)) { 534 stop_emulating(); 535 fpusave(curpcb->pcb_save); 536 start_emulating(); 537 PCPU_SET(fpcurthread, NULL); 538 } 539 critical_exit(); 540 #ifdef NPX_DEBUG 541 if (hw_float) { 542 u_int masked_exceptions; 543 544 masked_exceptions = GET_FPU_CW(td) & GET_FPU_SW(td) & 0x7f; 545 /* 546 * Log exceptions that would have trapped with the old 547 * control word (overflow, divide by 0, and invalid operand). 548 */ 549 if (masked_exceptions & 0x0d) 550 log(LOG_ERR, 551 "pid %d (%s) exited with masked floating point exceptions 0x%02x\n", 552 td->td_proc->p_pid, td->td_proc->p_comm, 553 masked_exceptions); 554 } 555 #endif 556 } 557 558 int 559 npxformat(void) 560 { 561 562 if (!hw_float) 563 return (_MC_FPFMT_NODEV); 564 if (cpu_fxsr) 565 return (_MC_FPFMT_XMM); 566 return (_MC_FPFMT_387); 567 } 568 569 /* 570 * The following mechanism is used to ensure that the FPE_... value 571 * that is passed as a trapcode to the signal handler of the user 572 * process does not have more than one bit set. 573 * 574 * Multiple bits may be set if the user process modifies the control 575 * word while a status word bit is already set. While this is a sign 576 * of bad coding, we have no choice than to narrow them down to one 577 * bit, since we must not send a trapcode that is not exactly one of 578 * the FPE_ macros. 579 * 580 * The mechanism has a static table with 127 entries. Each combination 581 * of the 7 FPU status word exception bits directly translates to a 582 * position in this table, where a single FPE_... value is stored. 583 * This FPE_... value stored there is considered the "most important" 584 * of the exception bits and will be sent as the signal code. The 585 * precedence of the bits is based upon Intel Document "Numerical 586 * Applications", Chapter "Special Computational Situations". 587 * 588 * The macro to choose one of these values does these steps: 1) Throw 589 * away status word bits that cannot be masked. 2) Throw away the bits 590 * currently masked in the control word, assuming the user isn't 591 * interested in them anymore. 3) Reinsert status word bit 7 (stack 592 * fault) if it is set, which cannot be masked but must be presered. 593 * 4) Use the remaining bits to point into the trapcode table. 594 * 595 * The 6 maskable bits in order of their preference, as stated in the 596 * above referenced Intel manual: 597 * 1 Invalid operation (FP_X_INV) 598 * 1a Stack underflow 599 * 1b Stack overflow 600 * 1c Operand of unsupported format 601 * 1d SNaN operand. 602 * 2 QNaN operand (not an exception, irrelavant here) 603 * 3 Any other invalid-operation not mentioned above or zero divide 604 * (FP_X_INV, FP_X_DZ) 605 * 4 Denormal operand (FP_X_DNML) 606 * 5 Numeric over/underflow (FP_X_OFL, FP_X_UFL) 607 * 6 Inexact result (FP_X_IMP) 608 */ 609 static char fpetable[128] = { 610 0, 611 FPE_FLTINV, /* 1 - INV */ 612 FPE_FLTUND, /* 2 - DNML */ 613 FPE_FLTINV, /* 3 - INV | DNML */ 614 FPE_FLTDIV, /* 4 - DZ */ 615 FPE_FLTINV, /* 5 - INV | DZ */ 616 FPE_FLTDIV, /* 6 - DNML | DZ */ 617 FPE_FLTINV, /* 7 - INV | DNML | DZ */ 618 FPE_FLTOVF, /* 8 - OFL */ 619 FPE_FLTINV, /* 9 - INV | OFL */ 620 FPE_FLTUND, /* A - DNML | OFL */ 621 FPE_FLTINV, /* B - INV | DNML | OFL */ 622 FPE_FLTDIV, /* C - DZ | OFL */ 623 FPE_FLTINV, /* D - INV | DZ | OFL */ 624 FPE_FLTDIV, /* E - DNML | DZ | OFL */ 625 FPE_FLTINV, /* F - INV | DNML | DZ | OFL */ 626 FPE_FLTUND, /* 10 - UFL */ 627 FPE_FLTINV, /* 11 - INV | UFL */ 628 FPE_FLTUND, /* 12 - DNML | UFL */ 629 FPE_FLTINV, /* 13 - INV | DNML | UFL */ 630 FPE_FLTDIV, /* 14 - DZ | UFL */ 631 FPE_FLTINV, /* 15 - INV | DZ | UFL */ 632 FPE_FLTDIV, /* 16 - DNML | DZ | UFL */ 633 FPE_FLTINV, /* 17 - INV | DNML | DZ | UFL */ 634 FPE_FLTOVF, /* 18 - OFL | UFL */ 635 FPE_FLTINV, /* 19 - INV | OFL | UFL */ 636 FPE_FLTUND, /* 1A - DNML | OFL | UFL */ 637 FPE_FLTINV, /* 1B - INV | DNML | OFL | UFL */ 638 FPE_FLTDIV, /* 1C - DZ | OFL | UFL */ 639 FPE_FLTINV, /* 1D - INV | DZ | OFL | UFL */ 640 FPE_FLTDIV, /* 1E - DNML | DZ | OFL | UFL */ 641 FPE_FLTINV, /* 1F - INV | DNML | DZ | OFL | UFL */ 642 FPE_FLTRES, /* 20 - IMP */ 643 FPE_FLTINV, /* 21 - INV | IMP */ 644 FPE_FLTUND, /* 22 - DNML | IMP */ 645 FPE_FLTINV, /* 23 - INV | DNML | IMP */ 646 FPE_FLTDIV, /* 24 - DZ | IMP */ 647 FPE_FLTINV, /* 25 - INV | DZ | IMP */ 648 FPE_FLTDIV, /* 26 - DNML | DZ | IMP */ 649 FPE_FLTINV, /* 27 - INV | DNML | DZ | IMP */ 650 FPE_FLTOVF, /* 28 - OFL | IMP */ 651 FPE_FLTINV, /* 29 - INV | OFL | IMP */ 652 FPE_FLTUND, /* 2A - DNML | OFL | IMP */ 653 FPE_FLTINV, /* 2B - INV | DNML | OFL | IMP */ 654 FPE_FLTDIV, /* 2C - DZ | OFL | IMP */ 655 FPE_FLTINV, /* 2D - INV | DZ | OFL | IMP */ 656 FPE_FLTDIV, /* 2E - DNML | DZ | OFL | IMP */ 657 FPE_FLTINV, /* 2F - INV | DNML | DZ | OFL | IMP */ 658 FPE_FLTUND, /* 30 - UFL | IMP */ 659 FPE_FLTINV, /* 31 - INV | UFL | IMP */ 660 FPE_FLTUND, /* 32 - DNML | UFL | IMP */ 661 FPE_FLTINV, /* 33 - INV | DNML | UFL | IMP */ 662 FPE_FLTDIV, /* 34 - DZ | UFL | IMP */ 663 FPE_FLTINV, /* 35 - INV | DZ | UFL | IMP */ 664 FPE_FLTDIV, /* 36 - DNML | DZ | UFL | IMP */ 665 FPE_FLTINV, /* 37 - INV | DNML | DZ | UFL | IMP */ 666 FPE_FLTOVF, /* 38 - OFL | UFL | IMP */ 667 FPE_FLTINV, /* 39 - INV | OFL | UFL | IMP */ 668 FPE_FLTUND, /* 3A - DNML | OFL | UFL | IMP */ 669 FPE_FLTINV, /* 3B - INV | DNML | OFL | UFL | IMP */ 670 FPE_FLTDIV, /* 3C - DZ | OFL | UFL | IMP */ 671 FPE_FLTINV, /* 3D - INV | DZ | OFL | UFL | IMP */ 672 FPE_FLTDIV, /* 3E - DNML | DZ | OFL | UFL | IMP */ 673 FPE_FLTINV, /* 3F - INV | DNML | DZ | OFL | UFL | IMP */ 674 FPE_FLTSUB, /* 40 - STK */ 675 FPE_FLTSUB, /* 41 - INV | STK */ 676 FPE_FLTUND, /* 42 - DNML | STK */ 677 FPE_FLTSUB, /* 43 - INV | DNML | STK */ 678 FPE_FLTDIV, /* 44 - DZ | STK */ 679 FPE_FLTSUB, /* 45 - INV | DZ | STK */ 680 FPE_FLTDIV, /* 46 - DNML | DZ | STK */ 681 FPE_FLTSUB, /* 47 - INV | DNML | DZ | STK */ 682 FPE_FLTOVF, /* 48 - OFL | STK */ 683 FPE_FLTSUB, /* 49 - INV | OFL | STK */ 684 FPE_FLTUND, /* 4A - DNML | OFL | STK */ 685 FPE_FLTSUB, /* 4B - INV | DNML | OFL | STK */ 686 FPE_FLTDIV, /* 4C - DZ | OFL | STK */ 687 FPE_FLTSUB, /* 4D - INV | DZ | OFL | STK */ 688 FPE_FLTDIV, /* 4E - DNML | DZ | OFL | STK */ 689 FPE_FLTSUB, /* 4F - INV | DNML | DZ | OFL | STK */ 690 FPE_FLTUND, /* 50 - UFL | STK */ 691 FPE_FLTSUB, /* 51 - INV | UFL | STK */ 692 FPE_FLTUND, /* 52 - DNML | UFL | STK */ 693 FPE_FLTSUB, /* 53 - INV | DNML | UFL | STK */ 694 FPE_FLTDIV, /* 54 - DZ | UFL | STK */ 695 FPE_FLTSUB, /* 55 - INV | DZ | UFL | STK */ 696 FPE_FLTDIV, /* 56 - DNML | DZ | UFL | STK */ 697 FPE_FLTSUB, /* 57 - INV | DNML | DZ | UFL | STK */ 698 FPE_FLTOVF, /* 58 - OFL | UFL | STK */ 699 FPE_FLTSUB, /* 59 - INV | OFL | UFL | STK */ 700 FPE_FLTUND, /* 5A - DNML | OFL | UFL | STK */ 701 FPE_FLTSUB, /* 5B - INV | DNML | OFL | UFL | STK */ 702 FPE_FLTDIV, /* 5C - DZ | OFL | UFL | STK */ 703 FPE_FLTSUB, /* 5D - INV | DZ | OFL | UFL | STK */ 704 FPE_FLTDIV, /* 5E - DNML | DZ | OFL | UFL | STK */ 705 FPE_FLTSUB, /* 5F - INV | DNML | DZ | OFL | UFL | STK */ 706 FPE_FLTRES, /* 60 - IMP | STK */ 707 FPE_FLTSUB, /* 61 - INV | IMP | STK */ 708 FPE_FLTUND, /* 62 - DNML | IMP | STK */ 709 FPE_FLTSUB, /* 63 - INV | DNML | IMP | STK */ 710 FPE_FLTDIV, /* 64 - DZ | IMP | STK */ 711 FPE_FLTSUB, /* 65 - INV | DZ | IMP | STK */ 712 FPE_FLTDIV, /* 66 - DNML | DZ | IMP | STK */ 713 FPE_FLTSUB, /* 67 - INV | DNML | DZ | IMP | STK */ 714 FPE_FLTOVF, /* 68 - OFL | IMP | STK */ 715 FPE_FLTSUB, /* 69 - INV | OFL | IMP | STK */ 716 FPE_FLTUND, /* 6A - DNML | OFL | IMP | STK */ 717 FPE_FLTSUB, /* 6B - INV | DNML | OFL | IMP | STK */ 718 FPE_FLTDIV, /* 6C - DZ | OFL | IMP | STK */ 719 FPE_FLTSUB, /* 6D - INV | DZ | OFL | IMP | STK */ 720 FPE_FLTDIV, /* 6E - DNML | DZ | OFL | IMP | STK */ 721 FPE_FLTSUB, /* 6F - INV | DNML | DZ | OFL | IMP | STK */ 722 FPE_FLTUND, /* 70 - UFL | IMP | STK */ 723 FPE_FLTSUB, /* 71 - INV | UFL | IMP | STK */ 724 FPE_FLTUND, /* 72 - DNML | UFL | IMP | STK */ 725 FPE_FLTSUB, /* 73 - INV | DNML | UFL | IMP | STK */ 726 FPE_FLTDIV, /* 74 - DZ | UFL | IMP | STK */ 727 FPE_FLTSUB, /* 75 - INV | DZ | UFL | IMP | STK */ 728 FPE_FLTDIV, /* 76 - DNML | DZ | UFL | IMP | STK */ 729 FPE_FLTSUB, /* 77 - INV | DNML | DZ | UFL | IMP | STK */ 730 FPE_FLTOVF, /* 78 - OFL | UFL | IMP | STK */ 731 FPE_FLTSUB, /* 79 - INV | OFL | UFL | IMP | STK */ 732 FPE_FLTUND, /* 7A - DNML | OFL | UFL | IMP | STK */ 733 FPE_FLTSUB, /* 7B - INV | DNML | OFL | UFL | IMP | STK */ 734 FPE_FLTDIV, /* 7C - DZ | OFL | UFL | IMP | STK */ 735 FPE_FLTSUB, /* 7D - INV | DZ | OFL | UFL | IMP | STK */ 736 FPE_FLTDIV, /* 7E - DNML | DZ | OFL | UFL | IMP | STK */ 737 FPE_FLTSUB, /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */ 738 }; 739 740 /* 741 * Read the FP status and control words, then generate si_code value 742 * for SIGFPE. The error code chosen will be one of the 743 * FPE_... macros. It will be sent as the second argument to old 744 * BSD-style signal handlers and as "siginfo_t->si_code" (second 745 * argument) to SA_SIGINFO signal handlers. 746 * 747 * Some time ago, we cleared the x87 exceptions with FNCLEX there. 748 * Clearing exceptions was necessary mainly to avoid IRQ13 bugs. The 749 * usermode code which understands the FPU hardware enough to enable 750 * the exceptions, can also handle clearing the exception state in the 751 * handler. The only consequence of not clearing the exception is the 752 * rethrow of the SIGFPE on return from the signal handler and 753 * reexecution of the corresponding instruction. 754 * 755 * For XMM traps, the exceptions were never cleared. 756 */ 757 int 758 npxtrap_x87(void) 759 { 760 u_short control, status; 761 762 if (!hw_float) { 763 printf( 764 "npxtrap_x87: fpcurthread = %p, curthread = %p, hw_float = %d\n", 765 PCPU_GET(fpcurthread), curthread, hw_float); 766 panic("npxtrap from nowhere"); 767 } 768 critical_enter(); 769 770 /* 771 * Interrupt handling (for another interrupt) may have pushed the 772 * state to memory. Fetch the relevant parts of the state from 773 * wherever they are. 774 */ 775 if (PCPU_GET(fpcurthread) != curthread) { 776 control = GET_FPU_CW(curthread); 777 status = GET_FPU_SW(curthread); 778 } else { 779 fnstcw(&control); 780 fnstsw(&status); 781 } 782 critical_exit(); 783 return (fpetable[status & ((~control & 0x3f) | 0x40)]); 784 } 785 786 int 787 npxtrap_sse(void) 788 { 789 u_int mxcsr; 790 791 if (!hw_float) { 792 printf( 793 "npxtrap_sse: fpcurthread = %p, curthread = %p, hw_float = %d\n", 794 PCPU_GET(fpcurthread), curthread, hw_float); 795 panic("npxtrap from nowhere"); 796 } 797 critical_enter(); 798 if (PCPU_GET(fpcurthread) != curthread) 799 mxcsr = curthread->td_pcb->pcb_save->sv_xmm.sv_env.en_mxcsr; 800 else 801 stmxcsr(&mxcsr); 802 critical_exit(); 803 return (fpetable[(mxcsr & (~mxcsr >> 7)) & 0x3f]); 804 } 805 806 static void 807 restore_npx_curthread(struct thread *td, struct pcb *pcb) 808 { 809 810 /* 811 * Record new context early in case frstor causes a trap. 812 */ 813 PCPU_SET(fpcurthread, td); 814 815 stop_emulating(); 816 if (cpu_fxsr) 817 fpu_clean_state(); 818 819 if ((pcb->pcb_flags & PCB_NPXINITDONE) == 0) { 820 /* 821 * This is the first time this thread has used the FPU or 822 * the PCB doesn't contain a clean FPU state. Explicitly 823 * load an initial state. 824 * 825 * We prefer to restore the state from the actual save 826 * area in PCB instead of directly loading from 827 * npx_initialstate, to ignite the XSAVEOPT 828 * tracking engine. 829 */ 830 bcopy(npx_initialstate, pcb->pcb_save, cpu_max_ext_state_size); 831 fpurstor(pcb->pcb_save); 832 if (pcb->pcb_initial_npxcw != __INITIAL_NPXCW__) 833 fldcw(pcb->pcb_initial_npxcw); 834 pcb->pcb_flags |= PCB_NPXINITDONE; 835 if (PCB_USER_FPU(pcb)) 836 pcb->pcb_flags |= PCB_NPXUSERINITDONE; 837 } else { 838 fpurstor(pcb->pcb_save); 839 } 840 } 841 842 /* 843 * Implement device not available (DNA) exception 844 * 845 * It would be better to switch FP context here (if curthread != fpcurthread) 846 * and not necessarily for every context switch, but it is too hard to 847 * access foreign pcb's. 848 */ 849 int 850 npxdna(void) 851 { 852 struct thread *td; 853 854 if (!hw_float) 855 return (0); 856 td = curthread; 857 critical_enter(); 858 859 KASSERT((curpcb->pcb_flags & PCB_NPXNOSAVE) == 0, 860 ("npxdna while in fpu_kern_enter(FPU_KERN_NOCTX)")); 861 if (__predict_false(PCPU_GET(fpcurthread) == td)) { 862 /* 863 * Some virtual machines seems to set %cr0.TS at 864 * arbitrary moments. Silently clear the TS bit 865 * regardless of the eager/lazy FPU context switch 866 * mode. 867 */ 868 stop_emulating(); 869 } else { 870 if (__predict_false(PCPU_GET(fpcurthread) != NULL)) { 871 printf( 872 "npxdna: fpcurthread = %p (%d), curthread = %p (%d)\n", 873 PCPU_GET(fpcurthread), 874 PCPU_GET(fpcurthread)->td_proc->p_pid, 875 td, td->td_proc->p_pid); 876 panic("npxdna"); 877 } 878 restore_npx_curthread(td, td->td_pcb); 879 } 880 critical_exit(); 881 return (1); 882 } 883 884 /* 885 * Wrapper for fpusave() called from context switch routines. 886 * 887 * npxsave() must be called with interrupts disabled, so that it clears 888 * fpcurthread atomically with saving the state. We require callers to do the 889 * disabling, since most callers need to disable interrupts anyway to call 890 * npxsave() atomically with checking fpcurthread. 891 */ 892 void 893 npxsave(union savefpu *addr) 894 { 895 896 stop_emulating(); 897 fpusave(addr); 898 } 899 900 void npxswitch(struct thread *td, struct pcb *pcb); 901 void 902 npxswitch(struct thread *td, struct pcb *pcb) 903 { 904 905 if (lazy_fpu_switch || (td->td_pflags & TDP_KTHREAD) != 0 || 906 !PCB_USER_FPU(pcb)) { 907 start_emulating(); 908 PCPU_SET(fpcurthread, NULL); 909 } else if (PCPU_GET(fpcurthread) != td) { 910 restore_npx_curthread(td, pcb); 911 } 912 } 913 914 /* 915 * Unconditionally save the current co-processor state across suspend and 916 * resume. 917 */ 918 void 919 npxsuspend(union savefpu *addr) 920 { 921 register_t cr0; 922 923 if (!hw_float) 924 return; 925 if (PCPU_GET(fpcurthread) == NULL) { 926 bcopy(npx_initialstate, addr, cpu_max_ext_state_size); 927 return; 928 } 929 cr0 = rcr0(); 930 stop_emulating(); 931 fpusave(addr); 932 load_cr0(cr0); 933 } 934 935 void 936 npxresume(union savefpu *addr) 937 { 938 register_t cr0; 939 940 if (!hw_float) 941 return; 942 943 cr0 = rcr0(); 944 npxinit(false); 945 stop_emulating(); 946 fpurstor(addr); 947 load_cr0(cr0); 948 } 949 950 void 951 npxdrop(void) 952 { 953 struct thread *td; 954 955 /* 956 * Discard pending exceptions in the !cpu_fxsr case so that unmasked 957 * ones don't cause a panic on the next frstor. 958 */ 959 if (!cpu_fxsr) 960 fnclex(); 961 962 td = PCPU_GET(fpcurthread); 963 KASSERT(td == curthread, ("fpudrop: fpcurthread != curthread")); 964 CRITICAL_ASSERT(td); 965 PCPU_SET(fpcurthread, NULL); 966 td->td_pcb->pcb_flags &= ~PCB_NPXINITDONE; 967 start_emulating(); 968 } 969 970 /* 971 * Get the user state of the FPU into pcb->pcb_user_save without 972 * dropping ownership (if possible). It returns the FPU ownership 973 * status. 974 */ 975 int 976 npxgetregs(struct thread *td) 977 { 978 struct pcb *pcb; 979 uint64_t *xstate_bv, bit; 980 char *sa; 981 int max_ext_n, i; 982 int owned; 983 984 if (!hw_float) 985 return (_MC_FPOWNED_NONE); 986 987 pcb = td->td_pcb; 988 critical_enter(); 989 if ((pcb->pcb_flags & PCB_NPXINITDONE) == 0) { 990 bcopy(npx_initialstate, get_pcb_user_save_pcb(pcb), 991 cpu_max_ext_state_size); 992 SET_FPU_CW(get_pcb_user_save_pcb(pcb), pcb->pcb_initial_npxcw); 993 npxuserinited(td); 994 critical_exit(); 995 return (_MC_FPOWNED_PCB); 996 } 997 if (td == PCPU_GET(fpcurthread)) { 998 fpusave(get_pcb_user_save_pcb(pcb)); 999 if (!cpu_fxsr) 1000 /* 1001 * fnsave initializes the FPU and destroys whatever 1002 * context it contains. Make sure the FPU owner 1003 * starts with a clean state next time. 1004 */ 1005 npxdrop(); 1006 owned = _MC_FPOWNED_FPU; 1007 } else { 1008 owned = _MC_FPOWNED_PCB; 1009 } 1010 if (use_xsave) { 1011 /* 1012 * Handle partially saved state. 1013 */ 1014 sa = (char *)get_pcb_user_save_pcb(pcb); 1015 xstate_bv = (uint64_t *)(sa + sizeof(union savefpu) + 1016 offsetof(struct xstate_hdr, xstate_bv)); 1017 if (xsave_mask >> 32 != 0) 1018 max_ext_n = fls(xsave_mask >> 32) + 32; 1019 else 1020 max_ext_n = fls(xsave_mask); 1021 for (i = 0; i < max_ext_n; i++) { 1022 bit = 1ULL << i; 1023 if ((xsave_mask & bit) == 0 || (*xstate_bv & bit) != 0) 1024 continue; 1025 bcopy((char *)npx_initialstate + 1026 xsave_area_desc[i].offset, 1027 sa + xsave_area_desc[i].offset, 1028 xsave_area_desc[i].size); 1029 *xstate_bv |= bit; 1030 } 1031 } 1032 critical_exit(); 1033 return (owned); 1034 } 1035 1036 void 1037 npxuserinited(struct thread *td) 1038 { 1039 struct pcb *pcb; 1040 1041 CRITICAL_ASSERT(td); 1042 pcb = td->td_pcb; 1043 if (PCB_USER_FPU(pcb)) 1044 pcb->pcb_flags |= PCB_NPXINITDONE; 1045 pcb->pcb_flags |= PCB_NPXUSERINITDONE; 1046 } 1047 1048 int 1049 npxsetxstate(struct thread *td, char *xfpustate, size_t xfpustate_size) 1050 { 1051 struct xstate_hdr *hdr, *ehdr; 1052 size_t len, max_len; 1053 uint64_t bv; 1054 1055 /* XXXKIB should we clear all extended state in xstate_bv instead ? */ 1056 if (xfpustate == NULL) 1057 return (0); 1058 if (!use_xsave) 1059 return (EOPNOTSUPP); 1060 1061 len = xfpustate_size; 1062 if (len < sizeof(struct xstate_hdr)) 1063 return (EINVAL); 1064 max_len = cpu_max_ext_state_size - sizeof(union savefpu); 1065 if (len > max_len) 1066 return (EINVAL); 1067 1068 ehdr = (struct xstate_hdr *)xfpustate; 1069 bv = ehdr->xstate_bv; 1070 1071 /* 1072 * Avoid #gp. 1073 */ 1074 if (bv & ~xsave_mask) 1075 return (EINVAL); 1076 1077 hdr = (struct xstate_hdr *)(get_pcb_user_save_td(td) + 1); 1078 1079 hdr->xstate_bv = bv; 1080 bcopy(xfpustate + sizeof(struct xstate_hdr), 1081 (char *)(hdr + 1), len - sizeof(struct xstate_hdr)); 1082 1083 return (0); 1084 } 1085 1086 int 1087 npxsetregs(struct thread *td, union savefpu *addr, char *xfpustate, 1088 size_t xfpustate_size) 1089 { 1090 struct pcb *pcb; 1091 int error; 1092 1093 if (!hw_float) 1094 return (ENXIO); 1095 1096 if (cpu_fxsr) 1097 addr->sv_xmm.sv_env.en_mxcsr &= cpu_mxcsr_mask; 1098 pcb = td->td_pcb; 1099 error = 0; 1100 critical_enter(); 1101 if (td == PCPU_GET(fpcurthread) && PCB_USER_FPU(pcb)) { 1102 error = npxsetxstate(td, xfpustate, xfpustate_size); 1103 if (error == 0) { 1104 if (!cpu_fxsr) 1105 fnclex(); /* As in npxdrop(). */ 1106 bcopy(addr, get_pcb_user_save_td(td), sizeof(*addr)); 1107 fpurstor(get_pcb_user_save_td(td)); 1108 pcb->pcb_flags |= PCB_NPXUSERINITDONE | PCB_NPXINITDONE; 1109 } 1110 } else { 1111 error = npxsetxstate(td, xfpustate, xfpustate_size); 1112 if (error == 0) { 1113 bcopy(addr, get_pcb_user_save_td(td), sizeof(*addr)); 1114 npxuserinited(td); 1115 } 1116 } 1117 critical_exit(); 1118 return (error); 1119 } 1120 1121 static void 1122 npx_fill_fpregs_xmm1(struct savexmm *sv_xmm, struct save87 *sv_87) 1123 { 1124 struct env87 *penv_87; 1125 struct envxmm *penv_xmm; 1126 struct fpacc87 *fx_reg; 1127 int i, st; 1128 uint64_t mantissa; 1129 uint16_t tw, exp; 1130 uint8_t ab_tw; 1131 1132 penv_87 = &sv_87->sv_env; 1133 penv_xmm = &sv_xmm->sv_env; 1134 1135 /* FPU control/status */ 1136 penv_87->en_cw = penv_xmm->en_cw; 1137 penv_87->en_sw = penv_xmm->en_sw; 1138 penv_87->en_fip = penv_xmm->en_fip; 1139 penv_87->en_fcs = penv_xmm->en_fcs; 1140 penv_87->en_opcode = penv_xmm->en_opcode; 1141 penv_87->en_foo = penv_xmm->en_foo; 1142 penv_87->en_fos = penv_xmm->en_fos; 1143 1144 /* 1145 * FPU registers and tags. 1146 * For ST(i), i = fpu_reg - top; we start with fpu_reg=7. 1147 */ 1148 st = 7 - ((penv_xmm->en_sw >> 11) & 7); 1149 ab_tw = penv_xmm->en_tw; 1150 tw = 0; 1151 for (i = 0x80; i != 0; i >>= 1) { 1152 sv_87->sv_ac[st] = sv_xmm->sv_fp[st].fp_acc; 1153 tw <<= 2; 1154 if (ab_tw & i) { 1155 /* Non-empty - we need to check ST(i) */ 1156 fx_reg = &sv_xmm->sv_fp[st].fp_acc; 1157 /* The first 64 bits contain the mantissa. */ 1158 mantissa = *((uint64_t *)fx_reg->fp_bytes); 1159 /* 1160 * The final 16 bits contain the sign bit and the exponent. 1161 * Mask the sign bit since it is of no consequence to these 1162 * tests. 1163 */ 1164 exp = *((uint16_t *)&fx_reg->fp_bytes[8]) & 0x7fff; 1165 if (exp == 0) { 1166 if (mantissa == 0) 1167 tw |= 1; /* Zero */ 1168 else 1169 tw |= 2; /* Denormal */ 1170 } else if (exp == 0x7fff) 1171 tw |= 2; /* Infinity or NaN */ 1172 } else 1173 tw |= 3; /* Empty */ 1174 st = (st - 1) & 7; 1175 } 1176 penv_87->en_tw = tw; 1177 } 1178 1179 void 1180 npx_fill_fpregs_xmm(struct savexmm *sv_xmm, struct save87 *sv_87) 1181 { 1182 1183 bzero(sv_87, sizeof(*sv_87)); 1184 npx_fill_fpregs_xmm1(sv_xmm, sv_87); 1185 } 1186 1187 void 1188 npx_set_fpregs_xmm(struct save87 *sv_87, struct savexmm *sv_xmm) 1189 { 1190 struct env87 *penv_87; 1191 struct envxmm *penv_xmm; 1192 int i; 1193 1194 penv_87 = &sv_87->sv_env; 1195 penv_xmm = &sv_xmm->sv_env; 1196 1197 /* FPU control/status */ 1198 penv_xmm->en_cw = penv_87->en_cw; 1199 penv_xmm->en_sw = penv_87->en_sw; 1200 penv_xmm->en_fip = penv_87->en_fip; 1201 penv_xmm->en_fcs = penv_87->en_fcs; 1202 penv_xmm->en_opcode = penv_87->en_opcode; 1203 penv_xmm->en_foo = penv_87->en_foo; 1204 penv_xmm->en_fos = penv_87->en_fos; 1205 1206 /* 1207 * FPU registers and tags. 1208 * Abridged / Full translation (values in binary), see FXSAVE spec. 1209 * 0 11 1210 * 1 00, 01, 10 1211 */ 1212 penv_xmm->en_tw = 0; 1213 for (i = 0; i < 8; ++i) { 1214 sv_xmm->sv_fp[i].fp_acc = sv_87->sv_ac[i]; 1215 if ((penv_87->en_tw & (3 << i * 2)) != (3 << i * 2)) 1216 penv_xmm->en_tw |= 1 << i; 1217 } 1218 } 1219 1220 void 1221 npx_get_fsave(void *addr) 1222 { 1223 struct thread *td; 1224 union savefpu *sv; 1225 1226 td = curthread; 1227 npxgetregs(td); 1228 sv = get_pcb_user_save_td(td); 1229 if (cpu_fxsr) 1230 npx_fill_fpregs_xmm1(&sv->sv_xmm, addr); 1231 else 1232 bcopy(sv, addr, sizeof(struct env87) + 1233 sizeof(struct fpacc87[8])); 1234 } 1235 1236 int 1237 npx_set_fsave(void *addr) 1238 { 1239 union savefpu sv; 1240 int error; 1241 1242 bzero(&sv, sizeof(sv)); 1243 if (cpu_fxsr) 1244 npx_set_fpregs_xmm(addr, &sv.sv_xmm); 1245 else 1246 bcopy(addr, &sv, sizeof(struct env87) + 1247 sizeof(struct fpacc87[8])); 1248 error = npxsetregs(curthread, &sv, NULL, 0); 1249 return (error); 1250 } 1251 1252 /* 1253 * On AuthenticAMD processors, the fxrstor instruction does not restore 1254 * the x87's stored last instruction pointer, last data pointer, and last 1255 * opcode values, except in the rare case in which the exception summary 1256 * (ES) bit in the x87 status word is set to 1. 1257 * 1258 * In order to avoid leaking this information across processes, we clean 1259 * these values by performing a dummy load before executing fxrstor(). 1260 */ 1261 static void 1262 fpu_clean_state(void) 1263 { 1264 static float dummy_variable = 0.0; 1265 u_short status; 1266 1267 /* 1268 * Clear the ES bit in the x87 status word if it is currently 1269 * set, in order to avoid causing a fault in the upcoming load. 1270 */ 1271 fnstsw(&status); 1272 if (status & 0x80) 1273 fnclex(); 1274 1275 /* 1276 * Load the dummy variable into the x87 stack. This mangles 1277 * the x87 stack, but we don't care since we're about to call 1278 * fxrstor() anyway. 1279 */ 1280 __asm __volatile("ffree %%st(7); flds %0" : : "m" (dummy_variable)); 1281 } 1282 1283 static void 1284 fpurstor(union savefpu *addr) 1285 { 1286 1287 if (use_xsave) 1288 xrstor((char *)addr, xsave_mask); 1289 else if (cpu_fxsr) 1290 fxrstor(addr); 1291 else 1292 frstor(addr); 1293 } 1294 1295 #ifdef DEV_ISA 1296 /* 1297 * This sucks up the legacy ISA support assignments from PNPBIOS/ACPI. 1298 */ 1299 static struct isa_pnp_id npxisa_ids[] = { 1300 { 0x040cd041, "Legacy ISA coprocessor support" }, /* PNP0C04 */ 1301 { 0 } 1302 }; 1303 1304 static int 1305 npxisa_probe(device_t dev) 1306 { 1307 int result; 1308 if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, npxisa_ids)) <= 0) { 1309 device_quiet(dev); 1310 } 1311 return(result); 1312 } 1313 1314 static int 1315 npxisa_attach(device_t dev) 1316 { 1317 return (0); 1318 } 1319 1320 static device_method_t npxisa_methods[] = { 1321 /* Device interface */ 1322 DEVMETHOD(device_probe, npxisa_probe), 1323 DEVMETHOD(device_attach, npxisa_attach), 1324 DEVMETHOD(device_detach, bus_generic_detach), 1325 DEVMETHOD(device_shutdown, bus_generic_shutdown), 1326 DEVMETHOD(device_suspend, bus_generic_suspend), 1327 DEVMETHOD(device_resume, bus_generic_resume), 1328 { 0, 0 } 1329 }; 1330 1331 static driver_t npxisa_driver = { 1332 "npxisa", 1333 npxisa_methods, 1334 1, /* no softc */ 1335 }; 1336 1337 DRIVER_MODULE(npxisa, isa, npxisa_driver, 0, 0); 1338 DRIVER_MODULE(npxisa, acpi, npxisa_driver, 0, 0); 1339 ISA_PNP_INFO(npxisa_ids); 1340 #endif /* DEV_ISA */ 1341 1342 static MALLOC_DEFINE(M_FPUKERN_CTX, "fpukern_ctx", 1343 "Kernel contexts for FPU state"); 1344 1345 #define FPU_KERN_CTX_NPXINITDONE 0x01 1346 #define FPU_KERN_CTX_DUMMY 0x02 1347 #define FPU_KERN_CTX_INUSE 0x04 1348 1349 struct fpu_kern_ctx { 1350 union savefpu *prev; 1351 uint32_t flags; 1352 char hwstate1[]; 1353 }; 1354 1355 struct fpu_kern_ctx * 1356 fpu_kern_alloc_ctx(u_int flags) 1357 { 1358 struct fpu_kern_ctx *res; 1359 size_t sz; 1360 1361 sz = sizeof(struct fpu_kern_ctx) + XSAVE_AREA_ALIGN + 1362 cpu_max_ext_state_size; 1363 res = malloc(sz, M_FPUKERN_CTX, ((flags & FPU_KERN_NOWAIT) ? 1364 M_NOWAIT : M_WAITOK) | M_ZERO); 1365 return (res); 1366 } 1367 1368 void 1369 fpu_kern_free_ctx(struct fpu_kern_ctx *ctx) 1370 { 1371 1372 KASSERT((ctx->flags & FPU_KERN_CTX_INUSE) == 0, ("free'ing inuse ctx")); 1373 /* XXXKIB clear the memory ? */ 1374 free(ctx, M_FPUKERN_CTX); 1375 } 1376 1377 static union savefpu * 1378 fpu_kern_ctx_savefpu(struct fpu_kern_ctx *ctx) 1379 { 1380 vm_offset_t p; 1381 1382 p = (vm_offset_t)&ctx->hwstate1; 1383 p = roundup2(p, XSAVE_AREA_ALIGN); 1384 return ((union savefpu *)p); 1385 } 1386 1387 void 1388 fpu_kern_enter(struct thread *td, struct fpu_kern_ctx *ctx, u_int flags) 1389 { 1390 struct pcb *pcb; 1391 1392 pcb = td->td_pcb; 1393 KASSERT((flags & FPU_KERN_NOCTX) != 0 || ctx != NULL, 1394 ("ctx is required when !FPU_KERN_NOCTX")); 1395 KASSERT(ctx == NULL || (ctx->flags & FPU_KERN_CTX_INUSE) == 0, 1396 ("using inuse ctx")); 1397 KASSERT((pcb->pcb_flags & PCB_NPXNOSAVE) == 0, 1398 ("recursive fpu_kern_enter while in PCB_NPXNOSAVE state")); 1399 1400 if ((flags & FPU_KERN_NOCTX) != 0) { 1401 critical_enter(); 1402 stop_emulating(); 1403 if (curthread == PCPU_GET(fpcurthread)) { 1404 fpusave(curpcb->pcb_save); 1405 PCPU_SET(fpcurthread, NULL); 1406 } else { 1407 KASSERT(PCPU_GET(fpcurthread) == NULL, 1408 ("invalid fpcurthread")); 1409 } 1410 1411 /* 1412 * This breaks XSAVEOPT tracker, but 1413 * PCB_NPXNOSAVE state is supposed to never need to 1414 * save FPU context at all. 1415 */ 1416 fpurstor(npx_initialstate); 1417 pcb->pcb_flags |= PCB_KERNNPX | PCB_NPXNOSAVE | PCB_NPXINITDONE; 1418 return; 1419 } 1420 if ((flags & FPU_KERN_KTHR) != 0 && is_fpu_kern_thread(0)) { 1421 ctx->flags = FPU_KERN_CTX_DUMMY | FPU_KERN_CTX_INUSE; 1422 return; 1423 } 1424 pcb = td->td_pcb; 1425 critical_enter(); 1426 KASSERT(!PCB_USER_FPU(pcb) || pcb->pcb_save == 1427 get_pcb_user_save_pcb(pcb), ("mangled pcb_save")); 1428 ctx->flags = FPU_KERN_CTX_INUSE; 1429 if ((pcb->pcb_flags & PCB_NPXINITDONE) != 0) 1430 ctx->flags |= FPU_KERN_CTX_NPXINITDONE; 1431 npxexit(td); 1432 ctx->prev = pcb->pcb_save; 1433 pcb->pcb_save = fpu_kern_ctx_savefpu(ctx); 1434 pcb->pcb_flags |= PCB_KERNNPX; 1435 pcb->pcb_flags &= ~PCB_NPXINITDONE; 1436 critical_exit(); 1437 } 1438 1439 int 1440 fpu_kern_leave(struct thread *td, struct fpu_kern_ctx *ctx) 1441 { 1442 struct pcb *pcb; 1443 1444 pcb = td->td_pcb; 1445 1446 if ((pcb->pcb_flags & PCB_NPXNOSAVE) != 0) { 1447 KASSERT(ctx == NULL, ("non-null ctx after FPU_KERN_NOCTX")); 1448 KASSERT(PCPU_GET(fpcurthread) == NULL, 1449 ("non-NULL fpcurthread for PCB_NPXNOSAVE")); 1450 CRITICAL_ASSERT(td); 1451 1452 pcb->pcb_flags &= ~(PCB_NPXNOSAVE | PCB_NPXINITDONE); 1453 start_emulating(); 1454 } else { 1455 KASSERT((ctx->flags & FPU_KERN_CTX_INUSE) != 0, 1456 ("leaving not inuse ctx")); 1457 ctx->flags &= ~FPU_KERN_CTX_INUSE; 1458 1459 if (is_fpu_kern_thread(0) && 1460 (ctx->flags & FPU_KERN_CTX_DUMMY) != 0) 1461 return (0); 1462 KASSERT((ctx->flags & FPU_KERN_CTX_DUMMY) == 0, 1463 ("dummy ctx")); 1464 critical_enter(); 1465 if (curthread == PCPU_GET(fpcurthread)) 1466 npxdrop(); 1467 pcb->pcb_save = ctx->prev; 1468 } 1469 1470 if (pcb->pcb_save == get_pcb_user_save_pcb(pcb)) { 1471 if ((pcb->pcb_flags & PCB_NPXUSERINITDONE) != 0) { 1472 pcb->pcb_flags |= PCB_NPXINITDONE; 1473 if ((pcb->pcb_flags & PCB_KERNNPX_THR) == 0) 1474 pcb->pcb_flags &= ~PCB_KERNNPX; 1475 } else if ((pcb->pcb_flags & PCB_KERNNPX_THR) == 0) 1476 pcb->pcb_flags &= ~(PCB_NPXINITDONE | PCB_KERNNPX); 1477 } else { 1478 if ((ctx->flags & FPU_KERN_CTX_NPXINITDONE) != 0) 1479 pcb->pcb_flags |= PCB_NPXINITDONE; 1480 else 1481 pcb->pcb_flags &= ~PCB_NPXINITDONE; 1482 KASSERT(!PCB_USER_FPU(pcb), ("unpaired fpu_kern_leave")); 1483 } 1484 critical_exit(); 1485 return (0); 1486 } 1487 1488 int 1489 fpu_kern_thread(u_int flags) 1490 { 1491 1492 KASSERT((curthread->td_pflags & TDP_KTHREAD) != 0, 1493 ("Only kthread may use fpu_kern_thread")); 1494 KASSERT(curpcb->pcb_save == get_pcb_user_save_pcb(curpcb), 1495 ("mangled pcb_save")); 1496 KASSERT(PCB_USER_FPU(curpcb), ("recursive call")); 1497 1498 curpcb->pcb_flags |= PCB_KERNNPX | PCB_KERNNPX_THR; 1499 return (0); 1500 } 1501 1502 int 1503 is_fpu_kern_thread(u_int flags) 1504 { 1505 1506 if ((curthread->td_pflags & TDP_KTHREAD) == 0) 1507 return (0); 1508 return ((curpcb->pcb_flags & PCB_KERNNPX_THR) != 0); 1509 } 1510 1511 /* 1512 * FPU save area alloc/free/init utility routines 1513 */ 1514 union savefpu * 1515 fpu_save_area_alloc(void) 1516 { 1517 1518 return (uma_zalloc(fpu_save_area_zone, M_WAITOK)); 1519 } 1520 1521 void 1522 fpu_save_area_free(union savefpu *fsa) 1523 { 1524 1525 uma_zfree(fpu_save_area_zone, fsa); 1526 } 1527 1528 void 1529 fpu_save_area_reset(union savefpu *fsa) 1530 { 1531 1532 bcopy(npx_initialstate, fsa, cpu_max_ext_state_size); 1533 } 1534