1 /*- 2 * Copyright (c) 1990 William Jolitz. 3 * Copyright (c) 1991 The Regents of the University of California. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. Neither the name of the University nor the names of its contributors 15 * may be used to endorse or promote products derived from this software 16 * without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * from: @(#)npx.c 7.2 (Berkeley) 5/12/91 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 #include "opt_cpu.h" 37 #include "opt_isa.h" 38 #include "opt_npx.h" 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/bus.h> 43 #include <sys/kernel.h> 44 #include <sys/lock.h> 45 #include <sys/malloc.h> 46 #include <sys/module.h> 47 #include <sys/mutex.h> 48 #include <sys/mutex.h> 49 #include <sys/proc.h> 50 #include <sys/smp.h> 51 #include <sys/sysctl.h> 52 #include <machine/bus.h> 53 #include <sys/rman.h> 54 #ifdef NPX_DEBUG 55 #include <sys/syslog.h> 56 #endif 57 #include <sys/signalvar.h> 58 #include <vm/uma.h> 59 60 #include <machine/asmacros.h> 61 #include <machine/cputypes.h> 62 #include <machine/frame.h> 63 #include <machine/md_var.h> 64 #include <machine/pcb.h> 65 #include <machine/psl.h> 66 #include <machine/resource.h> 67 #include <machine/specialreg.h> 68 #include <machine/segments.h> 69 #include <machine/ucontext.h> 70 #include <x86/ifunc.h> 71 72 #include <machine/intr_machdep.h> 73 74 #ifdef DEV_ISA 75 #include <isa/isavar.h> 76 #endif 77 78 /* 79 * 387 and 287 Numeric Coprocessor Extension (NPX) Driver. 80 */ 81 82 #if defined(__GNUCLIKE_ASM) && !defined(lint) 83 84 #define fldcw(cw) __asm __volatile("fldcw %0" : : "m" (cw)) 85 #define fnclex() __asm __volatile("fnclex") 86 #define fninit() __asm __volatile("fninit") 87 #define fnsave(addr) __asm __volatile("fnsave %0" : "=m" (*(addr))) 88 #define fnstcw(addr) __asm __volatile("fnstcw %0" : "=m" (*(addr))) 89 #define fnstsw(addr) __asm __volatile("fnstsw %0" : "=am" (*(addr))) 90 #define fp_divide_by_0() __asm __volatile( \ 91 "fldz; fld1; fdiv %st,%st(1); fnop") 92 #define frstor(addr) __asm __volatile("frstor %0" : : "m" (*(addr))) 93 #define fxrstor(addr) __asm __volatile("fxrstor %0" : : "m" (*(addr))) 94 #define fxsave(addr) __asm __volatile("fxsave %0" : "=m" (*(addr))) 95 #define ldmxcsr(csr) __asm __volatile("ldmxcsr %0" : : "m" (csr)) 96 #define stmxcsr(addr) __asm __volatile("stmxcsr %0" : : "m" (*(addr))) 97 98 static __inline void 99 xrstor(char *addr, uint64_t mask) 100 { 101 uint32_t low, hi; 102 103 low = mask; 104 hi = mask >> 32; 105 __asm __volatile("xrstor %0" : : "m" (*addr), "a" (low), "d" (hi)); 106 } 107 108 static __inline void 109 xsave(char *addr, uint64_t mask) 110 { 111 uint32_t low, hi; 112 113 low = mask; 114 hi = mask >> 32; 115 __asm __volatile("xsave %0" : "=m" (*addr) : "a" (low), "d" (hi) : 116 "memory"); 117 } 118 119 static __inline void 120 xsaveopt(char *addr, uint64_t mask) 121 { 122 uint32_t low, hi; 123 124 low = mask; 125 hi = mask >> 32; 126 __asm __volatile("xsaveopt %0" : "=m" (*addr) : "a" (low), "d" (hi) : 127 "memory"); 128 } 129 #else /* !(__GNUCLIKE_ASM && !lint) */ 130 131 void fldcw(u_short cw); 132 void fnclex(void); 133 void fninit(void); 134 void fnsave(caddr_t addr); 135 void fnstcw(caddr_t addr); 136 void fnstsw(caddr_t addr); 137 void fp_divide_by_0(void); 138 void frstor(caddr_t addr); 139 void fxsave(caddr_t addr); 140 void fxrstor(caddr_t addr); 141 void ldmxcsr(u_int csr); 142 void stmxcsr(u_int *csr); 143 void xrstor(char *addr, uint64_t mask); 144 void xsave(char *addr, uint64_t mask); 145 void xsaveopt(char *addr, uint64_t mask); 146 147 #endif /* __GNUCLIKE_ASM && !lint */ 148 149 #define start_emulating() load_cr0(rcr0() | CR0_TS) 150 #define stop_emulating() clts() 151 152 #define GET_FPU_CW(thread) \ 153 (cpu_fxsr ? \ 154 (thread)->td_pcb->pcb_save->sv_xmm.sv_env.en_cw : \ 155 (thread)->td_pcb->pcb_save->sv_87.sv_env.en_cw) 156 #define GET_FPU_SW(thread) \ 157 (cpu_fxsr ? \ 158 (thread)->td_pcb->pcb_save->sv_xmm.sv_env.en_sw : \ 159 (thread)->td_pcb->pcb_save->sv_87.sv_env.en_sw) 160 #define SET_FPU_CW(savefpu, value) do { \ 161 if (cpu_fxsr) \ 162 (savefpu)->sv_xmm.sv_env.en_cw = (value); \ 163 else \ 164 (savefpu)->sv_87.sv_env.en_cw = (value); \ 165 } while (0) 166 167 CTASSERT(sizeof(union savefpu) == 512); 168 CTASSERT(sizeof(struct xstate_hdr) == 64); 169 CTASSERT(sizeof(struct savefpu_ymm) == 832); 170 171 /* 172 * This requirement is to make it easier for asm code to calculate 173 * offset of the fpu save area from the pcb address. FPU save area 174 * must be 64-byte aligned. 175 */ 176 CTASSERT(sizeof(struct pcb) % XSAVE_AREA_ALIGN == 0); 177 178 /* 179 * Ensure the copy of XCR0 saved in a core is contained in the padding 180 * area. 181 */ 182 CTASSERT(X86_XSTATE_XCR0_OFFSET >= offsetof(struct savexmm, sv_pad) && 183 X86_XSTATE_XCR0_OFFSET + sizeof(uint64_t) <= sizeof(struct savexmm)); 184 185 static void fpu_clean_state(void); 186 187 static void fpurstor(union savefpu *); 188 189 int hw_float; 190 191 SYSCTL_INT(_hw, HW_FLOATINGPT, floatingpoint, CTLFLAG_RD, 192 &hw_float, 0, "Floating point instructions executed in hardware"); 193 194 int lazy_fpu_switch = 0; 195 SYSCTL_INT(_hw, OID_AUTO, lazy_fpu_switch, CTLFLAG_RWTUN | CTLFLAG_NOFETCH, 196 &lazy_fpu_switch, 0, 197 "Lazily load FPU context after context switch"); 198 199 int use_xsave; 200 uint64_t xsave_mask; 201 static uma_zone_t fpu_save_area_zone; 202 static union savefpu *npx_initialstate; 203 204 struct xsave_area_elm_descr { 205 u_int offset; 206 u_int size; 207 } *xsave_area_desc; 208 209 static volatile u_int npx_traps_while_probing; 210 211 alias_for_inthand_t probetrap; 212 __asm(" \n\ 213 .text \n\ 214 .p2align 2,0x90 \n\ 215 .type " __XSTRING(CNAME(probetrap)) ",@function \n\ 216 " __XSTRING(CNAME(probetrap)) ": \n\ 217 ss \n\ 218 incl " __XSTRING(CNAME(npx_traps_while_probing)) " \n\ 219 fnclex \n\ 220 iret \n\ 221 "); 222 223 /* 224 * Determine if an FPU is present and how to use it. 225 */ 226 static int 227 npx_probe(void) 228 { 229 struct gate_descriptor save_idt_npxtrap; 230 u_short control, status; 231 232 /* 233 * Modern CPUs all have an FPU that uses the INT16 interface 234 * and provide a simple way to verify that, so handle the 235 * common case right away. 236 */ 237 if (cpu_feature & CPUID_FPU) { 238 hw_float = 1; 239 return (1); 240 } 241 242 save_idt_npxtrap = idt[IDT_MF]; 243 setidt(IDT_MF, probetrap, SDT_SYS386TGT, SEL_KPL, 244 GSEL(GCODE_SEL, SEL_KPL)); 245 246 /* 247 * Don't trap while we're probing. 248 */ 249 stop_emulating(); 250 251 /* 252 * Finish resetting the coprocessor, if any. If there is an error 253 * pending, then we may get a bogus IRQ13, but npx_intr() will handle 254 * it OK. Bogus halts have never been observed, but we enabled 255 * IRQ13 and cleared the BUSY# latch early to handle them anyway. 256 */ 257 fninit(); 258 259 /* 260 * Don't use fwait here because it might hang. 261 * Don't use fnop here because it usually hangs if there is no FPU. 262 */ 263 DELAY(1000); /* wait for any IRQ13 */ 264 #ifdef DIAGNOSTIC 265 if (npx_traps_while_probing != 0) 266 printf("fninit caused %u bogus npx trap(s)\n", 267 npx_traps_while_probing); 268 #endif 269 /* 270 * Check for a status of mostly zero. 271 */ 272 status = 0x5a5a; 273 fnstsw(&status); 274 if ((status & 0xb8ff) == 0) { 275 /* 276 * Good, now check for a proper control word. 277 */ 278 control = 0x5a5a; 279 fnstcw(&control); 280 if ((control & 0x1f3f) == 0x033f) { 281 /* 282 * We have an npx, now divide by 0 to see if exception 283 * 16 works. 284 */ 285 control &= ~(1 << 2); /* enable divide by 0 trap */ 286 fldcw(control); 287 npx_traps_while_probing = 0; 288 fp_divide_by_0(); 289 if (npx_traps_while_probing != 0) { 290 /* 291 * Good, exception 16 works. 292 */ 293 hw_float = 1; 294 goto cleanup; 295 } 296 printf( 297 "FPU does not use exception 16 for error reporting\n"); 298 goto cleanup; 299 } 300 } 301 302 /* 303 * Probe failed. Floating point simply won't work. 304 * Notify user and disable FPU/MMX/SSE instruction execution. 305 */ 306 printf("WARNING: no FPU!\n"); 307 __asm __volatile("smsw %%ax; orb %0,%%al; lmsw %%ax" : : 308 "n" (CR0_EM | CR0_MP) : "ax"); 309 310 cleanup: 311 idt[IDT_MF] = save_idt_npxtrap; 312 return (hw_float); 313 } 314 315 static void 316 fpusave_xsaveopt(union savefpu *addr) 317 { 318 319 xsaveopt((char *)addr, xsave_mask); 320 } 321 322 static void 323 fpusave_xsave(union savefpu *addr) 324 { 325 326 xsave((char *)addr, xsave_mask); 327 } 328 329 static void 330 fpusave_fxsave(union savefpu *addr) 331 { 332 333 fxsave((char *)addr); 334 } 335 336 static void 337 fpusave_fnsave(union savefpu *addr) 338 { 339 340 fnsave((char *)addr); 341 } 342 343 static void 344 init_xsave(void) 345 { 346 347 if (use_xsave) 348 return; 349 if (!cpu_fxsr || (cpu_feature2 & CPUID2_XSAVE) == 0) 350 return; 351 use_xsave = 1; 352 TUNABLE_INT_FETCH("hw.use_xsave", &use_xsave); 353 } 354 355 DEFINE_IFUNC(, void, fpusave, (union savefpu *)) 356 { 357 358 init_xsave(); 359 if (use_xsave) 360 return ((cpu_stdext_feature & CPUID_EXTSTATE_XSAVEOPT) != 0 ? 361 fpusave_xsaveopt : fpusave_xsave); 362 if (cpu_fxsr) 363 return (fpusave_fxsave); 364 return (fpusave_fnsave); 365 } 366 367 /* 368 * Enable XSAVE if supported and allowed by user. 369 * Calculate the xsave_mask. 370 */ 371 static void 372 npxinit_bsp1(void) 373 { 374 u_int cp[4]; 375 uint64_t xsave_mask_user; 376 377 TUNABLE_INT_FETCH("hw.lazy_fpu_switch", &lazy_fpu_switch); 378 if (!use_xsave) 379 return; 380 cpuid_count(0xd, 0x0, cp); 381 xsave_mask = XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE; 382 if ((cp[0] & xsave_mask) != xsave_mask) 383 panic("CPU0 does not support X87 or SSE: %x", cp[0]); 384 xsave_mask = ((uint64_t)cp[3] << 32) | cp[0]; 385 xsave_mask_user = xsave_mask; 386 TUNABLE_QUAD_FETCH("hw.xsave_mask", &xsave_mask_user); 387 xsave_mask_user |= XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE; 388 xsave_mask &= xsave_mask_user; 389 if ((xsave_mask & XFEATURE_AVX512) != XFEATURE_AVX512) 390 xsave_mask &= ~XFEATURE_AVX512; 391 if ((xsave_mask & XFEATURE_MPX) != XFEATURE_MPX) 392 xsave_mask &= ~XFEATURE_MPX; 393 } 394 395 /* 396 * Calculate the fpu save area size. 397 */ 398 static void 399 npxinit_bsp2(void) 400 { 401 u_int cp[4]; 402 403 if (use_xsave) { 404 cpuid_count(0xd, 0x0, cp); 405 cpu_max_ext_state_size = cp[1]; 406 407 /* 408 * Reload the cpu_feature2, since we enabled OSXSAVE. 409 */ 410 do_cpuid(1, cp); 411 cpu_feature2 = cp[2]; 412 } else 413 cpu_max_ext_state_size = sizeof(union savefpu); 414 } 415 416 /* 417 * Initialize floating point unit. 418 */ 419 void 420 npxinit(bool bsp) 421 { 422 static union savefpu dummy; 423 register_t saveintr; 424 u_int mxcsr; 425 u_short control; 426 427 if (bsp) { 428 if (!npx_probe()) 429 return; 430 npxinit_bsp1(); 431 } 432 433 if (use_xsave) { 434 load_cr4(rcr4() | CR4_XSAVE); 435 load_xcr(XCR0, xsave_mask); 436 } 437 438 /* 439 * XCR0 shall be set up before CPU can report the save area size. 440 */ 441 if (bsp) 442 npxinit_bsp2(); 443 444 /* 445 * fninit has the same h/w bugs as fnsave. Use the detoxified 446 * fnsave to throw away any junk in the fpu. fpusave() initializes 447 * the fpu. 448 * 449 * It is too early for critical_enter() to work on AP. 450 */ 451 saveintr = intr_disable(); 452 stop_emulating(); 453 if (cpu_fxsr) 454 fninit(); 455 else 456 fnsave(&dummy); 457 control = __INITIAL_NPXCW__; 458 fldcw(control); 459 if (cpu_fxsr) { 460 mxcsr = __INITIAL_MXCSR__; 461 ldmxcsr(mxcsr); 462 } 463 start_emulating(); 464 intr_restore(saveintr); 465 } 466 467 /* 468 * On the boot CPU we generate a clean state that is used to 469 * initialize the floating point unit when it is first used by a 470 * process. 471 */ 472 static void 473 npxinitstate(void *arg __unused) 474 { 475 uint64_t *xstate_bv; 476 register_t saveintr; 477 int cp[4], i, max_ext_n; 478 479 if (!hw_float) 480 return; 481 482 npx_initialstate = malloc(cpu_max_ext_state_size, M_DEVBUF, 483 M_WAITOK | M_ZERO); 484 saveintr = intr_disable(); 485 stop_emulating(); 486 487 if (cpu_fxsr) 488 fpusave_fxsave(npx_initialstate); 489 else 490 fpusave_fnsave(npx_initialstate); 491 if (cpu_fxsr) { 492 if (npx_initialstate->sv_xmm.sv_env.en_mxcsr_mask) 493 cpu_mxcsr_mask = 494 npx_initialstate->sv_xmm.sv_env.en_mxcsr_mask; 495 else 496 cpu_mxcsr_mask = 0xFFBF; 497 498 /* 499 * The fninit instruction does not modify XMM 500 * registers or x87 registers (MM/ST). The fpusave 501 * call dumped the garbage contained in the registers 502 * after reset to the initial state saved. Clear XMM 503 * and x87 registers file image to make the startup 504 * program state and signal handler XMM/x87 register 505 * content predictable. 506 */ 507 bzero(npx_initialstate->sv_xmm.sv_fp, 508 sizeof(npx_initialstate->sv_xmm.sv_fp)); 509 bzero(npx_initialstate->sv_xmm.sv_xmm, 510 sizeof(npx_initialstate->sv_xmm.sv_xmm)); 511 512 } else 513 bzero(npx_initialstate->sv_87.sv_ac, 514 sizeof(npx_initialstate->sv_87.sv_ac)); 515 516 /* 517 * Create a table describing the layout of the CPU Extended 518 * Save Area. 519 */ 520 if (use_xsave) { 521 xstate_bv = (uint64_t *)((char *)(npx_initialstate + 1) + 522 offsetof(struct xstate_hdr, xstate_bv)); 523 *xstate_bv = XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE; 524 525 if (xsave_mask >> 32 != 0) 526 max_ext_n = fls(xsave_mask >> 32) + 32; 527 else 528 max_ext_n = fls(xsave_mask); 529 xsave_area_desc = malloc(max_ext_n * sizeof(struct 530 xsave_area_elm_descr), M_DEVBUF, M_WAITOK | M_ZERO); 531 /* x87 state */ 532 xsave_area_desc[0].offset = 0; 533 xsave_area_desc[0].size = 160; 534 /* XMM */ 535 xsave_area_desc[1].offset = 160; 536 xsave_area_desc[1].size = 288 - 160; 537 538 for (i = 2; i < max_ext_n; i++) { 539 cpuid_count(0xd, i, cp); 540 xsave_area_desc[i].offset = cp[1]; 541 xsave_area_desc[i].size = cp[0]; 542 } 543 } 544 545 fpu_save_area_zone = uma_zcreate("FPU_save_area", 546 cpu_max_ext_state_size, NULL, NULL, NULL, NULL, 547 XSAVE_AREA_ALIGN - 1, 0); 548 549 start_emulating(); 550 intr_restore(saveintr); 551 } 552 SYSINIT(npxinitstate, SI_SUB_DRIVERS, SI_ORDER_ANY, npxinitstate, NULL); 553 554 /* 555 * Free coprocessor (if we have it). 556 */ 557 void 558 npxexit(struct thread *td) 559 { 560 561 critical_enter(); 562 if (curthread == PCPU_GET(fpcurthread)) { 563 stop_emulating(); 564 fpusave(curpcb->pcb_save); 565 start_emulating(); 566 PCPU_SET(fpcurthread, NULL); 567 } 568 critical_exit(); 569 #ifdef NPX_DEBUG 570 if (hw_float) { 571 u_int masked_exceptions; 572 573 masked_exceptions = GET_FPU_CW(td) & GET_FPU_SW(td) & 0x7f; 574 /* 575 * Log exceptions that would have trapped with the old 576 * control word (overflow, divide by 0, and invalid operand). 577 */ 578 if (masked_exceptions & 0x0d) 579 log(LOG_ERR, 580 "pid %d (%s) exited with masked floating point exceptions 0x%02x\n", 581 td->td_proc->p_pid, td->td_proc->p_comm, 582 masked_exceptions); 583 } 584 #endif 585 } 586 587 int 588 npxformat(void) 589 { 590 591 if (!hw_float) 592 return (_MC_FPFMT_NODEV); 593 if (cpu_fxsr) 594 return (_MC_FPFMT_XMM); 595 return (_MC_FPFMT_387); 596 } 597 598 /* 599 * The following mechanism is used to ensure that the FPE_... value 600 * that is passed as a trapcode to the signal handler of the user 601 * process does not have more than one bit set. 602 * 603 * Multiple bits may be set if the user process modifies the control 604 * word while a status word bit is already set. While this is a sign 605 * of bad coding, we have no choise than to narrow them down to one 606 * bit, since we must not send a trapcode that is not exactly one of 607 * the FPE_ macros. 608 * 609 * The mechanism has a static table with 127 entries. Each combination 610 * of the 7 FPU status word exception bits directly translates to a 611 * position in this table, where a single FPE_... value is stored. 612 * This FPE_... value stored there is considered the "most important" 613 * of the exception bits and will be sent as the signal code. The 614 * precedence of the bits is based upon Intel Document "Numerical 615 * Applications", Chapter "Special Computational Situations". 616 * 617 * The macro to choose one of these values does these steps: 1) Throw 618 * away status word bits that cannot be masked. 2) Throw away the bits 619 * currently masked in the control word, assuming the user isn't 620 * interested in them anymore. 3) Reinsert status word bit 7 (stack 621 * fault) if it is set, which cannot be masked but must be presered. 622 * 4) Use the remaining bits to point into the trapcode table. 623 * 624 * The 6 maskable bits in order of their preference, as stated in the 625 * above referenced Intel manual: 626 * 1 Invalid operation (FP_X_INV) 627 * 1a Stack underflow 628 * 1b Stack overflow 629 * 1c Operand of unsupported format 630 * 1d SNaN operand. 631 * 2 QNaN operand (not an exception, irrelavant here) 632 * 3 Any other invalid-operation not mentioned above or zero divide 633 * (FP_X_INV, FP_X_DZ) 634 * 4 Denormal operand (FP_X_DNML) 635 * 5 Numeric over/underflow (FP_X_OFL, FP_X_UFL) 636 * 6 Inexact result (FP_X_IMP) 637 */ 638 static char fpetable[128] = { 639 0, 640 FPE_FLTINV, /* 1 - INV */ 641 FPE_FLTUND, /* 2 - DNML */ 642 FPE_FLTINV, /* 3 - INV | DNML */ 643 FPE_FLTDIV, /* 4 - DZ */ 644 FPE_FLTINV, /* 5 - INV | DZ */ 645 FPE_FLTDIV, /* 6 - DNML | DZ */ 646 FPE_FLTINV, /* 7 - INV | DNML | DZ */ 647 FPE_FLTOVF, /* 8 - OFL */ 648 FPE_FLTINV, /* 9 - INV | OFL */ 649 FPE_FLTUND, /* A - DNML | OFL */ 650 FPE_FLTINV, /* B - INV | DNML | OFL */ 651 FPE_FLTDIV, /* C - DZ | OFL */ 652 FPE_FLTINV, /* D - INV | DZ | OFL */ 653 FPE_FLTDIV, /* E - DNML | DZ | OFL */ 654 FPE_FLTINV, /* F - INV | DNML | DZ | OFL */ 655 FPE_FLTUND, /* 10 - UFL */ 656 FPE_FLTINV, /* 11 - INV | UFL */ 657 FPE_FLTUND, /* 12 - DNML | UFL */ 658 FPE_FLTINV, /* 13 - INV | DNML | UFL */ 659 FPE_FLTDIV, /* 14 - DZ | UFL */ 660 FPE_FLTINV, /* 15 - INV | DZ | UFL */ 661 FPE_FLTDIV, /* 16 - DNML | DZ | UFL */ 662 FPE_FLTINV, /* 17 - INV | DNML | DZ | UFL */ 663 FPE_FLTOVF, /* 18 - OFL | UFL */ 664 FPE_FLTINV, /* 19 - INV | OFL | UFL */ 665 FPE_FLTUND, /* 1A - DNML | OFL | UFL */ 666 FPE_FLTINV, /* 1B - INV | DNML | OFL | UFL */ 667 FPE_FLTDIV, /* 1C - DZ | OFL | UFL */ 668 FPE_FLTINV, /* 1D - INV | DZ | OFL | UFL */ 669 FPE_FLTDIV, /* 1E - DNML | DZ | OFL | UFL */ 670 FPE_FLTINV, /* 1F - INV | DNML | DZ | OFL | UFL */ 671 FPE_FLTRES, /* 20 - IMP */ 672 FPE_FLTINV, /* 21 - INV | IMP */ 673 FPE_FLTUND, /* 22 - DNML | IMP */ 674 FPE_FLTINV, /* 23 - INV | DNML | IMP */ 675 FPE_FLTDIV, /* 24 - DZ | IMP */ 676 FPE_FLTINV, /* 25 - INV | DZ | IMP */ 677 FPE_FLTDIV, /* 26 - DNML | DZ | IMP */ 678 FPE_FLTINV, /* 27 - INV | DNML | DZ | IMP */ 679 FPE_FLTOVF, /* 28 - OFL | IMP */ 680 FPE_FLTINV, /* 29 - INV | OFL | IMP */ 681 FPE_FLTUND, /* 2A - DNML | OFL | IMP */ 682 FPE_FLTINV, /* 2B - INV | DNML | OFL | IMP */ 683 FPE_FLTDIV, /* 2C - DZ | OFL | IMP */ 684 FPE_FLTINV, /* 2D - INV | DZ | OFL | IMP */ 685 FPE_FLTDIV, /* 2E - DNML | DZ | OFL | IMP */ 686 FPE_FLTINV, /* 2F - INV | DNML | DZ | OFL | IMP */ 687 FPE_FLTUND, /* 30 - UFL | IMP */ 688 FPE_FLTINV, /* 31 - INV | UFL | IMP */ 689 FPE_FLTUND, /* 32 - DNML | UFL | IMP */ 690 FPE_FLTINV, /* 33 - INV | DNML | UFL | IMP */ 691 FPE_FLTDIV, /* 34 - DZ | UFL | IMP */ 692 FPE_FLTINV, /* 35 - INV | DZ | UFL | IMP */ 693 FPE_FLTDIV, /* 36 - DNML | DZ | UFL | IMP */ 694 FPE_FLTINV, /* 37 - INV | DNML | DZ | UFL | IMP */ 695 FPE_FLTOVF, /* 38 - OFL | UFL | IMP */ 696 FPE_FLTINV, /* 39 - INV | OFL | UFL | IMP */ 697 FPE_FLTUND, /* 3A - DNML | OFL | UFL | IMP */ 698 FPE_FLTINV, /* 3B - INV | DNML | OFL | UFL | IMP */ 699 FPE_FLTDIV, /* 3C - DZ | OFL | UFL | IMP */ 700 FPE_FLTINV, /* 3D - INV | DZ | OFL | UFL | IMP */ 701 FPE_FLTDIV, /* 3E - DNML | DZ | OFL | UFL | IMP */ 702 FPE_FLTINV, /* 3F - INV | DNML | DZ | OFL | UFL | IMP */ 703 FPE_FLTSUB, /* 40 - STK */ 704 FPE_FLTSUB, /* 41 - INV | STK */ 705 FPE_FLTUND, /* 42 - DNML | STK */ 706 FPE_FLTSUB, /* 43 - INV | DNML | STK */ 707 FPE_FLTDIV, /* 44 - DZ | STK */ 708 FPE_FLTSUB, /* 45 - INV | DZ | STK */ 709 FPE_FLTDIV, /* 46 - DNML | DZ | STK */ 710 FPE_FLTSUB, /* 47 - INV | DNML | DZ | STK */ 711 FPE_FLTOVF, /* 48 - OFL | STK */ 712 FPE_FLTSUB, /* 49 - INV | OFL | STK */ 713 FPE_FLTUND, /* 4A - DNML | OFL | STK */ 714 FPE_FLTSUB, /* 4B - INV | DNML | OFL | STK */ 715 FPE_FLTDIV, /* 4C - DZ | OFL | STK */ 716 FPE_FLTSUB, /* 4D - INV | DZ | OFL | STK */ 717 FPE_FLTDIV, /* 4E - DNML | DZ | OFL | STK */ 718 FPE_FLTSUB, /* 4F - INV | DNML | DZ | OFL | STK */ 719 FPE_FLTUND, /* 50 - UFL | STK */ 720 FPE_FLTSUB, /* 51 - INV | UFL | STK */ 721 FPE_FLTUND, /* 52 - DNML | UFL | STK */ 722 FPE_FLTSUB, /* 53 - INV | DNML | UFL | STK */ 723 FPE_FLTDIV, /* 54 - DZ | UFL | STK */ 724 FPE_FLTSUB, /* 55 - INV | DZ | UFL | STK */ 725 FPE_FLTDIV, /* 56 - DNML | DZ | UFL | STK */ 726 FPE_FLTSUB, /* 57 - INV | DNML | DZ | UFL | STK */ 727 FPE_FLTOVF, /* 58 - OFL | UFL | STK */ 728 FPE_FLTSUB, /* 59 - INV | OFL | UFL | STK */ 729 FPE_FLTUND, /* 5A - DNML | OFL | UFL | STK */ 730 FPE_FLTSUB, /* 5B - INV | DNML | OFL | UFL | STK */ 731 FPE_FLTDIV, /* 5C - DZ | OFL | UFL | STK */ 732 FPE_FLTSUB, /* 5D - INV | DZ | OFL | UFL | STK */ 733 FPE_FLTDIV, /* 5E - DNML | DZ | OFL | UFL | STK */ 734 FPE_FLTSUB, /* 5F - INV | DNML | DZ | OFL | UFL | STK */ 735 FPE_FLTRES, /* 60 - IMP | STK */ 736 FPE_FLTSUB, /* 61 - INV | IMP | STK */ 737 FPE_FLTUND, /* 62 - DNML | IMP | STK */ 738 FPE_FLTSUB, /* 63 - INV | DNML | IMP | STK */ 739 FPE_FLTDIV, /* 64 - DZ | IMP | STK */ 740 FPE_FLTSUB, /* 65 - INV | DZ | IMP | STK */ 741 FPE_FLTDIV, /* 66 - DNML | DZ | IMP | STK */ 742 FPE_FLTSUB, /* 67 - INV | DNML | DZ | IMP | STK */ 743 FPE_FLTOVF, /* 68 - OFL | IMP | STK */ 744 FPE_FLTSUB, /* 69 - INV | OFL | IMP | STK */ 745 FPE_FLTUND, /* 6A - DNML | OFL | IMP | STK */ 746 FPE_FLTSUB, /* 6B - INV | DNML | OFL | IMP | STK */ 747 FPE_FLTDIV, /* 6C - DZ | OFL | IMP | STK */ 748 FPE_FLTSUB, /* 6D - INV | DZ | OFL | IMP | STK */ 749 FPE_FLTDIV, /* 6E - DNML | DZ | OFL | IMP | STK */ 750 FPE_FLTSUB, /* 6F - INV | DNML | DZ | OFL | IMP | STK */ 751 FPE_FLTUND, /* 70 - UFL | IMP | STK */ 752 FPE_FLTSUB, /* 71 - INV | UFL | IMP | STK */ 753 FPE_FLTUND, /* 72 - DNML | UFL | IMP | STK */ 754 FPE_FLTSUB, /* 73 - INV | DNML | UFL | IMP | STK */ 755 FPE_FLTDIV, /* 74 - DZ | UFL | IMP | STK */ 756 FPE_FLTSUB, /* 75 - INV | DZ | UFL | IMP | STK */ 757 FPE_FLTDIV, /* 76 - DNML | DZ | UFL | IMP | STK */ 758 FPE_FLTSUB, /* 77 - INV | DNML | DZ | UFL | IMP | STK */ 759 FPE_FLTOVF, /* 78 - OFL | UFL | IMP | STK */ 760 FPE_FLTSUB, /* 79 - INV | OFL | UFL | IMP | STK */ 761 FPE_FLTUND, /* 7A - DNML | OFL | UFL | IMP | STK */ 762 FPE_FLTSUB, /* 7B - INV | DNML | OFL | UFL | IMP | STK */ 763 FPE_FLTDIV, /* 7C - DZ | OFL | UFL | IMP | STK */ 764 FPE_FLTSUB, /* 7D - INV | DZ | OFL | UFL | IMP | STK */ 765 FPE_FLTDIV, /* 7E - DNML | DZ | OFL | UFL | IMP | STK */ 766 FPE_FLTSUB, /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */ 767 }; 768 769 /* 770 * Read the FP status and control words, then generate si_code value 771 * for SIGFPE. The error code chosen will be one of the 772 * FPE_... macros. It will be sent as the second argument to old 773 * BSD-style signal handlers and as "siginfo_t->si_code" (second 774 * argument) to SA_SIGINFO signal handlers. 775 * 776 * Some time ago, we cleared the x87 exceptions with FNCLEX there. 777 * Clearing exceptions was necessary mainly to avoid IRQ13 bugs. The 778 * usermode code which understands the FPU hardware enough to enable 779 * the exceptions, can also handle clearing the exception state in the 780 * handler. The only consequence of not clearing the exception is the 781 * rethrow of the SIGFPE on return from the signal handler and 782 * reexecution of the corresponding instruction. 783 * 784 * For XMM traps, the exceptions were never cleared. 785 */ 786 int 787 npxtrap_x87(void) 788 { 789 u_short control, status; 790 791 if (!hw_float) { 792 printf( 793 "npxtrap_x87: fpcurthread = %p, curthread = %p, hw_float = %d\n", 794 PCPU_GET(fpcurthread), curthread, hw_float); 795 panic("npxtrap from nowhere"); 796 } 797 critical_enter(); 798 799 /* 800 * Interrupt handling (for another interrupt) may have pushed the 801 * state to memory. Fetch the relevant parts of the state from 802 * wherever they are. 803 */ 804 if (PCPU_GET(fpcurthread) != curthread) { 805 control = GET_FPU_CW(curthread); 806 status = GET_FPU_SW(curthread); 807 } else { 808 fnstcw(&control); 809 fnstsw(&status); 810 } 811 critical_exit(); 812 return (fpetable[status & ((~control & 0x3f) | 0x40)]); 813 } 814 815 int 816 npxtrap_sse(void) 817 { 818 u_int mxcsr; 819 820 if (!hw_float) { 821 printf( 822 "npxtrap_sse: fpcurthread = %p, curthread = %p, hw_float = %d\n", 823 PCPU_GET(fpcurthread), curthread, hw_float); 824 panic("npxtrap from nowhere"); 825 } 826 critical_enter(); 827 if (PCPU_GET(fpcurthread) != curthread) 828 mxcsr = curthread->td_pcb->pcb_save->sv_xmm.sv_env.en_mxcsr; 829 else 830 stmxcsr(&mxcsr); 831 critical_exit(); 832 return (fpetable[(mxcsr & (~mxcsr >> 7)) & 0x3f]); 833 } 834 835 static void 836 restore_npx_curthread(struct thread *td, struct pcb *pcb) 837 { 838 839 /* 840 * Record new context early in case frstor causes a trap. 841 */ 842 PCPU_SET(fpcurthread, td); 843 844 stop_emulating(); 845 if (cpu_fxsr) 846 fpu_clean_state(); 847 848 if ((pcb->pcb_flags & PCB_NPXINITDONE) == 0) { 849 /* 850 * This is the first time this thread has used the FPU or 851 * the PCB doesn't contain a clean FPU state. Explicitly 852 * load an initial state. 853 * 854 * We prefer to restore the state from the actual save 855 * area in PCB instead of directly loading from 856 * npx_initialstate, to ignite the XSAVEOPT 857 * tracking engine. 858 */ 859 bcopy(npx_initialstate, pcb->pcb_save, cpu_max_ext_state_size); 860 fpurstor(pcb->pcb_save); 861 if (pcb->pcb_initial_npxcw != __INITIAL_NPXCW__) 862 fldcw(pcb->pcb_initial_npxcw); 863 pcb->pcb_flags |= PCB_NPXINITDONE; 864 if (PCB_USER_FPU(pcb)) 865 pcb->pcb_flags |= PCB_NPXUSERINITDONE; 866 } else { 867 fpurstor(pcb->pcb_save); 868 } 869 } 870 871 /* 872 * Implement device not available (DNA) exception 873 * 874 * It would be better to switch FP context here (if curthread != fpcurthread) 875 * and not necessarily for every context switch, but it is too hard to 876 * access foreign pcb's. 877 */ 878 int 879 npxdna(void) 880 { 881 struct thread *td; 882 883 if (!hw_float) 884 return (0); 885 td = curthread; 886 critical_enter(); 887 if (__predict_false(PCPU_GET(fpcurthread) == td)) { 888 /* 889 * Some virtual machines seems to set %cr0.TS at 890 * arbitrary moments. Silently clear the TS bit 891 * regardless of the eager/lazy FPU context switch 892 * mode. 893 */ 894 stop_emulating(); 895 } else { 896 if (__predict_false(PCPU_GET(fpcurthread) != NULL)) { 897 printf( 898 "npxdna: fpcurthread = %p (%d), curthread = %p (%d)\n", 899 PCPU_GET(fpcurthread), 900 PCPU_GET(fpcurthread)->td_proc->p_pid, 901 td, td->td_proc->p_pid); 902 panic("npxdna"); 903 } 904 restore_npx_curthread(td, td->td_pcb); 905 } 906 critical_exit(); 907 return (1); 908 } 909 910 /* 911 * Wrapper for fpusave() called from context switch routines. 912 * 913 * npxsave() must be called with interrupts disabled, so that it clears 914 * fpcurthread atomically with saving the state. We require callers to do the 915 * disabling, since most callers need to disable interrupts anyway to call 916 * npxsave() atomically with checking fpcurthread. 917 */ 918 void 919 npxsave(union savefpu *addr) 920 { 921 922 stop_emulating(); 923 fpusave(addr); 924 } 925 926 void npxswitch(struct thread *td, struct pcb *pcb); 927 void 928 npxswitch(struct thread *td, struct pcb *pcb) 929 { 930 931 if (lazy_fpu_switch || (td->td_pflags & TDP_KTHREAD) != 0 || 932 !PCB_USER_FPU(pcb)) { 933 start_emulating(); 934 PCPU_SET(fpcurthread, NULL); 935 } else if (PCPU_GET(fpcurthread) != td) { 936 restore_npx_curthread(td, pcb); 937 } 938 } 939 940 /* 941 * Unconditionally save the current co-processor state across suspend and 942 * resume. 943 */ 944 void 945 npxsuspend(union savefpu *addr) 946 { 947 register_t cr0; 948 949 if (!hw_float) 950 return; 951 if (PCPU_GET(fpcurthread) == NULL) { 952 bcopy(npx_initialstate, addr, cpu_max_ext_state_size); 953 return; 954 } 955 cr0 = rcr0(); 956 stop_emulating(); 957 fpusave(addr); 958 load_cr0(cr0); 959 } 960 961 void 962 npxresume(union savefpu *addr) 963 { 964 register_t cr0; 965 966 if (!hw_float) 967 return; 968 969 cr0 = rcr0(); 970 npxinit(false); 971 stop_emulating(); 972 fpurstor(addr); 973 load_cr0(cr0); 974 } 975 976 void 977 npxdrop(void) 978 { 979 struct thread *td; 980 981 /* 982 * Discard pending exceptions in the !cpu_fxsr case so that unmasked 983 * ones don't cause a panic on the next frstor. 984 */ 985 if (!cpu_fxsr) 986 fnclex(); 987 988 td = PCPU_GET(fpcurthread); 989 KASSERT(td == curthread, ("fpudrop: fpcurthread != curthread")); 990 CRITICAL_ASSERT(td); 991 PCPU_SET(fpcurthread, NULL); 992 td->td_pcb->pcb_flags &= ~PCB_NPXINITDONE; 993 start_emulating(); 994 } 995 996 /* 997 * Get the user state of the FPU into pcb->pcb_user_save without 998 * dropping ownership (if possible). It returns the FPU ownership 999 * status. 1000 */ 1001 int 1002 npxgetregs(struct thread *td) 1003 { 1004 struct pcb *pcb; 1005 uint64_t *xstate_bv, bit; 1006 char *sa; 1007 int max_ext_n, i; 1008 int owned; 1009 1010 if (!hw_float) 1011 return (_MC_FPOWNED_NONE); 1012 1013 pcb = td->td_pcb; 1014 critical_enter(); 1015 if ((pcb->pcb_flags & PCB_NPXINITDONE) == 0) { 1016 bcopy(npx_initialstate, get_pcb_user_save_pcb(pcb), 1017 cpu_max_ext_state_size); 1018 SET_FPU_CW(get_pcb_user_save_pcb(pcb), pcb->pcb_initial_npxcw); 1019 npxuserinited(td); 1020 critical_exit(); 1021 return (_MC_FPOWNED_PCB); 1022 } 1023 if (td == PCPU_GET(fpcurthread)) { 1024 fpusave(get_pcb_user_save_pcb(pcb)); 1025 if (!cpu_fxsr) 1026 /* 1027 * fnsave initializes the FPU and destroys whatever 1028 * context it contains. Make sure the FPU owner 1029 * starts with a clean state next time. 1030 */ 1031 npxdrop(); 1032 owned = _MC_FPOWNED_FPU; 1033 } else { 1034 owned = _MC_FPOWNED_PCB; 1035 } 1036 if (use_xsave) { 1037 /* 1038 * Handle partially saved state. 1039 */ 1040 sa = (char *)get_pcb_user_save_pcb(pcb); 1041 xstate_bv = (uint64_t *)(sa + sizeof(union savefpu) + 1042 offsetof(struct xstate_hdr, xstate_bv)); 1043 if (xsave_mask >> 32 != 0) 1044 max_ext_n = fls(xsave_mask >> 32) + 32; 1045 else 1046 max_ext_n = fls(xsave_mask); 1047 for (i = 0; i < max_ext_n; i++) { 1048 bit = 1ULL << i; 1049 if ((xsave_mask & bit) == 0 || (*xstate_bv & bit) != 0) 1050 continue; 1051 bcopy((char *)npx_initialstate + 1052 xsave_area_desc[i].offset, 1053 sa + xsave_area_desc[i].offset, 1054 xsave_area_desc[i].size); 1055 *xstate_bv |= bit; 1056 } 1057 } 1058 critical_exit(); 1059 return (owned); 1060 } 1061 1062 void 1063 npxuserinited(struct thread *td) 1064 { 1065 struct pcb *pcb; 1066 1067 CRITICAL_ASSERT(td); 1068 pcb = td->td_pcb; 1069 if (PCB_USER_FPU(pcb)) 1070 pcb->pcb_flags |= PCB_NPXINITDONE; 1071 pcb->pcb_flags |= PCB_NPXUSERINITDONE; 1072 } 1073 1074 int 1075 npxsetxstate(struct thread *td, char *xfpustate, size_t xfpustate_size) 1076 { 1077 struct xstate_hdr *hdr, *ehdr; 1078 size_t len, max_len; 1079 uint64_t bv; 1080 1081 /* XXXKIB should we clear all extended state in xstate_bv instead ? */ 1082 if (xfpustate == NULL) 1083 return (0); 1084 if (!use_xsave) 1085 return (EOPNOTSUPP); 1086 1087 len = xfpustate_size; 1088 if (len < sizeof(struct xstate_hdr)) 1089 return (EINVAL); 1090 max_len = cpu_max_ext_state_size - sizeof(union savefpu); 1091 if (len > max_len) 1092 return (EINVAL); 1093 1094 ehdr = (struct xstate_hdr *)xfpustate; 1095 bv = ehdr->xstate_bv; 1096 1097 /* 1098 * Avoid #gp. 1099 */ 1100 if (bv & ~xsave_mask) 1101 return (EINVAL); 1102 1103 hdr = (struct xstate_hdr *)(get_pcb_user_save_td(td) + 1); 1104 1105 hdr->xstate_bv = bv; 1106 bcopy(xfpustate + sizeof(struct xstate_hdr), 1107 (char *)(hdr + 1), len - sizeof(struct xstate_hdr)); 1108 1109 return (0); 1110 } 1111 1112 int 1113 npxsetregs(struct thread *td, union savefpu *addr, char *xfpustate, 1114 size_t xfpustate_size) 1115 { 1116 struct pcb *pcb; 1117 int error; 1118 1119 if (!hw_float) 1120 return (ENXIO); 1121 1122 if (cpu_fxsr) 1123 addr->sv_xmm.sv_env.en_mxcsr &= cpu_mxcsr_mask; 1124 pcb = td->td_pcb; 1125 error = 0; 1126 critical_enter(); 1127 if (td == PCPU_GET(fpcurthread) && PCB_USER_FPU(pcb)) { 1128 error = npxsetxstate(td, xfpustate, xfpustate_size); 1129 if (error == 0) { 1130 if (!cpu_fxsr) 1131 fnclex(); /* As in npxdrop(). */ 1132 bcopy(addr, get_pcb_user_save_td(td), sizeof(*addr)); 1133 fpurstor(get_pcb_user_save_td(td)); 1134 pcb->pcb_flags |= PCB_NPXUSERINITDONE | PCB_NPXINITDONE; 1135 } 1136 } else { 1137 error = npxsetxstate(td, xfpustate, xfpustate_size); 1138 if (error == 0) { 1139 bcopy(addr, get_pcb_user_save_td(td), sizeof(*addr)); 1140 npxuserinited(td); 1141 } 1142 } 1143 critical_exit(); 1144 return (error); 1145 } 1146 1147 static void 1148 npx_fill_fpregs_xmm1(struct savexmm *sv_xmm, struct save87 *sv_87) 1149 { 1150 struct env87 *penv_87; 1151 struct envxmm *penv_xmm; 1152 int i; 1153 1154 penv_87 = &sv_87->sv_env; 1155 penv_xmm = &sv_xmm->sv_env; 1156 1157 /* FPU control/status */ 1158 penv_87->en_cw = penv_xmm->en_cw; 1159 penv_87->en_sw = penv_xmm->en_sw; 1160 penv_87->en_fip = penv_xmm->en_fip; 1161 penv_87->en_fcs = penv_xmm->en_fcs; 1162 penv_87->en_opcode = penv_xmm->en_opcode; 1163 penv_87->en_foo = penv_xmm->en_foo; 1164 penv_87->en_fos = penv_xmm->en_fos; 1165 1166 /* FPU registers and tags */ 1167 penv_87->en_tw = 0xffff; 1168 for (i = 0; i < 8; ++i) { 1169 sv_87->sv_ac[i] = sv_xmm->sv_fp[i].fp_acc; 1170 if ((penv_xmm->en_tw & (1 << i)) != 0) 1171 /* zero and special are set as valid */ 1172 penv_87->en_tw &= ~(3 << i * 2); 1173 } 1174 } 1175 1176 void 1177 npx_fill_fpregs_xmm(struct savexmm *sv_xmm, struct save87 *sv_87) 1178 { 1179 1180 bzero(sv_87, sizeof(*sv_87)); 1181 npx_fill_fpregs_xmm1(sv_xmm, sv_87); 1182 } 1183 1184 void 1185 npx_set_fpregs_xmm(struct save87 *sv_87, struct savexmm *sv_xmm) 1186 { 1187 struct env87 *penv_87; 1188 struct envxmm *penv_xmm; 1189 int i; 1190 1191 penv_87 = &sv_87->sv_env; 1192 penv_xmm = &sv_xmm->sv_env; 1193 1194 /* FPU control/status */ 1195 penv_xmm->en_cw = penv_87->en_cw; 1196 penv_xmm->en_sw = penv_87->en_sw; 1197 penv_xmm->en_fip = penv_87->en_fip; 1198 penv_xmm->en_fcs = penv_87->en_fcs; 1199 penv_xmm->en_opcode = penv_87->en_opcode; 1200 penv_xmm->en_foo = penv_87->en_foo; 1201 penv_xmm->en_fos = penv_87->en_fos; 1202 1203 /* 1204 * FPU registers and tags. 1205 * Abridged / Full translation (values in binary), see FXSAVE spec. 1206 * 0 11 1207 * 1 00, 01, 10 1208 */ 1209 penv_xmm->en_tw = 0; 1210 for (i = 0; i < 8; ++i) { 1211 sv_xmm->sv_fp[i].fp_acc = sv_87->sv_ac[i]; 1212 if ((penv_87->en_tw & (3 << i * 2)) != (3 << i * 2)) 1213 penv_xmm->en_tw |= 1 << i; 1214 } 1215 } 1216 1217 void 1218 npx_get_fsave(void *addr) 1219 { 1220 struct thread *td; 1221 union savefpu *sv; 1222 1223 td = curthread; 1224 npxgetregs(td); 1225 sv = get_pcb_user_save_td(td); 1226 if (cpu_fxsr) 1227 npx_fill_fpregs_xmm1(&sv->sv_xmm, addr); 1228 else 1229 bcopy(sv, addr, sizeof(struct env87) + 1230 sizeof(struct fpacc87[8])); 1231 } 1232 1233 int 1234 npx_set_fsave(void *addr) 1235 { 1236 union savefpu sv; 1237 int error; 1238 1239 bzero(&sv, sizeof(sv)); 1240 if (cpu_fxsr) 1241 npx_set_fpregs_xmm(addr, &sv.sv_xmm); 1242 else 1243 bcopy(addr, &sv, sizeof(struct env87) + 1244 sizeof(struct fpacc87[8])); 1245 error = npxsetregs(curthread, &sv, NULL, 0); 1246 return (error); 1247 } 1248 1249 /* 1250 * On AuthenticAMD processors, the fxrstor instruction does not restore 1251 * the x87's stored last instruction pointer, last data pointer, and last 1252 * opcode values, except in the rare case in which the exception summary 1253 * (ES) bit in the x87 status word is set to 1. 1254 * 1255 * In order to avoid leaking this information across processes, we clean 1256 * these values by performing a dummy load before executing fxrstor(). 1257 */ 1258 static void 1259 fpu_clean_state(void) 1260 { 1261 static float dummy_variable = 0.0; 1262 u_short status; 1263 1264 /* 1265 * Clear the ES bit in the x87 status word if it is currently 1266 * set, in order to avoid causing a fault in the upcoming load. 1267 */ 1268 fnstsw(&status); 1269 if (status & 0x80) 1270 fnclex(); 1271 1272 /* 1273 * Load the dummy variable into the x87 stack. This mangles 1274 * the x87 stack, but we don't care since we're about to call 1275 * fxrstor() anyway. 1276 */ 1277 __asm __volatile("ffree %%st(7); flds %0" : : "m" (dummy_variable)); 1278 } 1279 1280 static void 1281 fpurstor(union savefpu *addr) 1282 { 1283 1284 if (use_xsave) 1285 xrstor((char *)addr, xsave_mask); 1286 else if (cpu_fxsr) 1287 fxrstor(addr); 1288 else 1289 frstor(addr); 1290 } 1291 1292 #ifdef DEV_ISA 1293 /* 1294 * This sucks up the legacy ISA support assignments from PNPBIOS/ACPI. 1295 */ 1296 static struct isa_pnp_id npxisa_ids[] = { 1297 { 0x040cd041, "Legacy ISA coprocessor support" }, /* PNP0C04 */ 1298 { 0 } 1299 }; 1300 1301 static int 1302 npxisa_probe(device_t dev) 1303 { 1304 int result; 1305 if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, npxisa_ids)) <= 0) { 1306 device_quiet(dev); 1307 } 1308 return(result); 1309 } 1310 1311 static int 1312 npxisa_attach(device_t dev) 1313 { 1314 return (0); 1315 } 1316 1317 static device_method_t npxisa_methods[] = { 1318 /* Device interface */ 1319 DEVMETHOD(device_probe, npxisa_probe), 1320 DEVMETHOD(device_attach, npxisa_attach), 1321 DEVMETHOD(device_detach, bus_generic_detach), 1322 DEVMETHOD(device_shutdown, bus_generic_shutdown), 1323 DEVMETHOD(device_suspend, bus_generic_suspend), 1324 DEVMETHOD(device_resume, bus_generic_resume), 1325 1326 { 0, 0 } 1327 }; 1328 1329 static driver_t npxisa_driver = { 1330 "npxisa", 1331 npxisa_methods, 1332 1, /* no softc */ 1333 }; 1334 1335 static devclass_t npxisa_devclass; 1336 1337 DRIVER_MODULE(npxisa, isa, npxisa_driver, npxisa_devclass, 0, 0); 1338 DRIVER_MODULE(npxisa, acpi, npxisa_driver, npxisa_devclass, 0, 0); 1339 ISA_PNP_INFO(npxisa_ids); 1340 #endif /* DEV_ISA */ 1341 1342 static MALLOC_DEFINE(M_FPUKERN_CTX, "fpukern_ctx", 1343 "Kernel contexts for FPU state"); 1344 1345 #define FPU_KERN_CTX_NPXINITDONE 0x01 1346 #define FPU_KERN_CTX_DUMMY 0x02 1347 #define FPU_KERN_CTX_INUSE 0x04 1348 1349 struct fpu_kern_ctx { 1350 union savefpu *prev; 1351 uint32_t flags; 1352 char hwstate1[]; 1353 }; 1354 1355 struct fpu_kern_ctx * 1356 fpu_kern_alloc_ctx(u_int flags) 1357 { 1358 struct fpu_kern_ctx *res; 1359 size_t sz; 1360 1361 sz = sizeof(struct fpu_kern_ctx) + XSAVE_AREA_ALIGN + 1362 cpu_max_ext_state_size; 1363 res = malloc(sz, M_FPUKERN_CTX, ((flags & FPU_KERN_NOWAIT) ? 1364 M_NOWAIT : M_WAITOK) | M_ZERO); 1365 return (res); 1366 } 1367 1368 void 1369 fpu_kern_free_ctx(struct fpu_kern_ctx *ctx) 1370 { 1371 1372 KASSERT((ctx->flags & FPU_KERN_CTX_INUSE) == 0, ("free'ing inuse ctx")); 1373 /* XXXKIB clear the memory ? */ 1374 free(ctx, M_FPUKERN_CTX); 1375 } 1376 1377 static union savefpu * 1378 fpu_kern_ctx_savefpu(struct fpu_kern_ctx *ctx) 1379 { 1380 vm_offset_t p; 1381 1382 p = (vm_offset_t)&ctx->hwstate1; 1383 p = roundup2(p, XSAVE_AREA_ALIGN); 1384 return ((union savefpu *)p); 1385 } 1386 1387 void 1388 fpu_kern_enter(struct thread *td, struct fpu_kern_ctx *ctx, u_int flags) 1389 { 1390 struct pcb *pcb; 1391 1392 KASSERT((ctx->flags & FPU_KERN_CTX_INUSE) == 0, ("using inuse ctx")); 1393 1394 if ((flags & FPU_KERN_KTHR) != 0 && is_fpu_kern_thread(0)) { 1395 ctx->flags = FPU_KERN_CTX_DUMMY | FPU_KERN_CTX_INUSE; 1396 return; 1397 } 1398 pcb = td->td_pcb; 1399 critical_enter(); 1400 KASSERT(!PCB_USER_FPU(pcb) || pcb->pcb_save == 1401 get_pcb_user_save_pcb(pcb), ("mangled pcb_save")); 1402 ctx->flags = FPU_KERN_CTX_INUSE; 1403 if ((pcb->pcb_flags & PCB_NPXINITDONE) != 0) 1404 ctx->flags |= FPU_KERN_CTX_NPXINITDONE; 1405 npxexit(td); 1406 ctx->prev = pcb->pcb_save; 1407 pcb->pcb_save = fpu_kern_ctx_savefpu(ctx); 1408 pcb->pcb_flags |= PCB_KERNNPX; 1409 pcb->pcb_flags &= ~PCB_NPXINITDONE; 1410 critical_exit(); 1411 } 1412 1413 int 1414 fpu_kern_leave(struct thread *td, struct fpu_kern_ctx *ctx) 1415 { 1416 struct pcb *pcb; 1417 1418 KASSERT((ctx->flags & FPU_KERN_CTX_INUSE) != 0, 1419 ("leaving not inuse ctx")); 1420 ctx->flags &= ~FPU_KERN_CTX_INUSE; 1421 1422 if (is_fpu_kern_thread(0) && (ctx->flags & FPU_KERN_CTX_DUMMY) != 0) 1423 return (0); 1424 pcb = td->td_pcb; 1425 critical_enter(); 1426 if (curthread == PCPU_GET(fpcurthread)) 1427 npxdrop(); 1428 pcb->pcb_save = ctx->prev; 1429 if (pcb->pcb_save == get_pcb_user_save_pcb(pcb)) { 1430 if ((pcb->pcb_flags & PCB_NPXUSERINITDONE) != 0) 1431 pcb->pcb_flags |= PCB_NPXINITDONE; 1432 else 1433 pcb->pcb_flags &= ~PCB_NPXINITDONE; 1434 pcb->pcb_flags &= ~PCB_KERNNPX; 1435 } else { 1436 if ((ctx->flags & FPU_KERN_CTX_NPXINITDONE) != 0) 1437 pcb->pcb_flags |= PCB_NPXINITDONE; 1438 else 1439 pcb->pcb_flags &= ~PCB_NPXINITDONE; 1440 KASSERT(!PCB_USER_FPU(pcb), ("unpaired fpu_kern_leave")); 1441 } 1442 critical_exit(); 1443 return (0); 1444 } 1445 1446 int 1447 fpu_kern_thread(u_int flags) 1448 { 1449 1450 KASSERT((curthread->td_pflags & TDP_KTHREAD) != 0, 1451 ("Only kthread may use fpu_kern_thread")); 1452 KASSERT(curpcb->pcb_save == get_pcb_user_save_pcb(curpcb), 1453 ("mangled pcb_save")); 1454 KASSERT(PCB_USER_FPU(curpcb), ("recursive call")); 1455 1456 curpcb->pcb_flags |= PCB_KERNNPX; 1457 return (0); 1458 } 1459 1460 int 1461 is_fpu_kern_thread(u_int flags) 1462 { 1463 1464 if ((curthread->td_pflags & TDP_KTHREAD) == 0) 1465 return (0); 1466 return ((curpcb->pcb_flags & PCB_KERNNPX) != 0); 1467 } 1468 1469 /* 1470 * FPU save area alloc/free/init utility routines 1471 */ 1472 union savefpu * 1473 fpu_save_area_alloc(void) 1474 { 1475 1476 return (uma_zalloc(fpu_save_area_zone, M_WAITOK)); 1477 } 1478 1479 void 1480 fpu_save_area_free(union savefpu *fsa) 1481 { 1482 1483 uma_zfree(fpu_save_area_zone, fsa); 1484 } 1485 1486 void 1487 fpu_save_area_reset(union savefpu *fsa) 1488 { 1489 1490 bcopy(npx_initialstate, fsa, cpu_max_ext_state_size); 1491 } 1492