1 /*- 2 * SPDX-License-Identifier: BSD-4-Clause 3 * 4 * Copyright (c) 1991 Regents of the University of California. 5 * All rights reserved. 6 * Copyright (c) 1994 John S. Dyson 7 * All rights reserved. 8 * Copyright (c) 1994 David Greenman 9 * All rights reserved. 10 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu> 11 * All rights reserved. 12 * 13 * This code is derived from software contributed to Berkeley by 14 * the Systems Programming Group of the University of Utah Computer 15 * Science Department and William Jolitz of UUNET Technologies Inc. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions 19 * are met: 20 * 1. Redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer. 22 * 2. Redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution. 25 * 3. All advertising materials mentioning features or use of this software 26 * must display the following acknowledgement: 27 * This product includes software developed by the University of 28 * California, Berkeley and its contributors. 29 * 4. Neither the name of the University nor the names of its contributors 30 * may be used to endorse or promote products derived from this software 31 * without specific prior written permission. 32 * 33 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 34 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 35 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 36 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 37 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 38 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 39 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 41 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 42 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 43 * SUCH DAMAGE. 44 * 45 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91 46 */ 47 /*- 48 * Copyright (c) 2003 Networks Associates Technology, Inc. 49 * All rights reserved. 50 * Copyright (c) 2018 The FreeBSD Foundation 51 * All rights reserved. 52 * 53 * This software was developed for the FreeBSD Project by Jake Burkholder, 54 * Safeport Network Services, and Network Associates Laboratories, the 55 * Security Research Division of Network Associates, Inc. under 56 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA 57 * CHATS research program. 58 * 59 * Portions of this software were developed by 60 * Konstantin Belousov <kib@FreeBSD.org> under sponsorship from 61 * the FreeBSD Foundation. 62 * 63 * Redistribution and use in source and binary forms, with or without 64 * modification, are permitted provided that the following conditions 65 * are met: 66 * 1. Redistributions of source code must retain the above copyright 67 * notice, this list of conditions and the following disclaimer. 68 * 2. Redistributions in binary form must reproduce the above copyright 69 * notice, this list of conditions and the following disclaimer in the 70 * documentation and/or other materials provided with the distribution. 71 * 72 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 73 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 74 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 75 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 76 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 77 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 78 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 79 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 80 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 81 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 82 * SUCH DAMAGE. 83 */ 84 85 #include <sys/cdefs.h> 86 __FBSDID("$FreeBSD$"); 87 88 /* 89 * Manages physical address maps. 90 * 91 * Since the information managed by this module is 92 * also stored by the logical address mapping module, 93 * this module may throw away valid virtual-to-physical 94 * mappings at almost any time. However, invalidations 95 * of virtual-to-physical mappings must be done as 96 * requested. 97 * 98 * In order to cope with hardware architectures which 99 * make virtual-to-physical map invalidates expensive, 100 * this module may delay invalidate or reduced protection 101 * operations until such time as they are actually 102 * necessary. This module is given full information as 103 * to which processors are currently using which maps, 104 * and to when physical maps must be made correct. 105 */ 106 107 #include "opt_apic.h" 108 #include "opt_cpu.h" 109 #include "opt_pmap.h" 110 #include "opt_smp.h" 111 #include "opt_vm.h" 112 113 #include <sys/param.h> 114 #include <sys/systm.h> 115 #include <sys/kernel.h> 116 #include <sys/ktr.h> 117 #include <sys/lock.h> 118 #include <sys/malloc.h> 119 #include <sys/mman.h> 120 #include <sys/msgbuf.h> 121 #include <sys/mutex.h> 122 #include <sys/proc.h> 123 #include <sys/rwlock.h> 124 #include <sys/sf_buf.h> 125 #include <sys/sx.h> 126 #include <sys/vmmeter.h> 127 #include <sys/sched.h> 128 #include <sys/sysctl.h> 129 #include <sys/smp.h> 130 #include <sys/vmem.h> 131 132 #include <vm/vm.h> 133 #include <vm/vm_param.h> 134 #include <vm/vm_kern.h> 135 #include <vm/vm_page.h> 136 #include <vm/vm_map.h> 137 #include <vm/vm_object.h> 138 #include <vm/vm_extern.h> 139 #include <vm/vm_pageout.h> 140 #include <vm/vm_pager.h> 141 #include <vm/vm_phys.h> 142 #include <vm/vm_radix.h> 143 #include <vm/vm_reserv.h> 144 #include <vm/uma.h> 145 146 #ifdef DEV_APIC 147 #include <sys/bus.h> 148 #include <machine/intr_machdep.h> 149 #include <x86/apicvar.h> 150 #endif 151 #include <x86/ifunc.h> 152 #include <machine/bootinfo.h> 153 #include <machine/cpu.h> 154 #include <machine/cputypes.h> 155 #include <machine/md_var.h> 156 #include <machine/pcb.h> 157 #include <machine/specialreg.h> 158 #ifdef SMP 159 #include <machine/smp.h> 160 #endif 161 #include <machine/pmap_base.h> 162 163 #if !defined(DIAGNOSTIC) 164 #ifdef __GNUC_GNU_INLINE__ 165 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline 166 #else 167 #define PMAP_INLINE extern inline 168 #endif 169 #else 170 #define PMAP_INLINE 171 #endif 172 173 #ifdef PV_STATS 174 #define PV_STAT(x) do { x ; } while (0) 175 #else 176 #define PV_STAT(x) do { } while (0) 177 #endif 178 179 #define pa_index(pa) ((pa) >> PDRSHIFT) 180 #define pa_to_pvh(pa) (&pv_table[pa_index(pa)]) 181 182 /* 183 * PTmap is recursive pagemap at top of virtual address space. 184 * Within PTmap, the page directory can be found (third indirection). 185 */ 186 #define PTmap ((pt_entry_t *)(PTDPTDI << PDRSHIFT)) 187 #define PTD ((pd_entry_t *)((PTDPTDI << PDRSHIFT) + (PTDPTDI * PAGE_SIZE))) 188 #define PTDpde ((pd_entry_t *)((PTDPTDI << PDRSHIFT) + (PTDPTDI * PAGE_SIZE) + \ 189 (PTDPTDI * PDESIZE))) 190 191 /* 192 * Translate a virtual address to the kernel virtual address of its page table 193 * entry (PTE). This can be used recursively. If the address of a PTE as 194 * previously returned by this macro is itself given as the argument, then the 195 * address of the page directory entry (PDE) that maps the PTE will be 196 * returned. 197 * 198 * This macro may be used before pmap_bootstrap() is called. 199 */ 200 #define vtopte(va) (PTmap + i386_btop(va)) 201 202 /* 203 * Get PDEs and PTEs for user/kernel address space 204 */ 205 #define pmap_pde(m, v) (&((m)->pm_pdir[(vm_offset_t)(v) >> PDRSHIFT])) 206 #define pdir_pde(m, v) (m[(vm_offset_t)(v) >> PDRSHIFT]) 207 208 #define pmap_pde_v(pte) ((*(int *)pte & PG_V) != 0) 209 #define pmap_pte_w(pte) ((*(int *)pte & PG_W) != 0) 210 #define pmap_pte_m(pte) ((*(int *)pte & PG_M) != 0) 211 #define pmap_pte_u(pte) ((*(int *)pte & PG_A) != 0) 212 #define pmap_pte_v(pte) ((*(int *)pte & PG_V) != 0) 213 214 #define pmap_pte_set_w(pte, v) ((v) ? atomic_set_int((u_int *)(pte), PG_W) : \ 215 atomic_clear_int((u_int *)(pte), PG_W)) 216 #define pmap_pte_set_prot(pte, v) ((*(int *)pte &= ~PG_PROT), (*(int *)pte |= (v))) 217 218 _Static_assert(sizeof(struct pmap) <= sizeof(struct pmap_KBI), 219 "pmap_KBI"); 220 221 static int pgeflag = 0; /* PG_G or-in */ 222 static int pseflag = 0; /* PG_PS or-in */ 223 224 static int nkpt = NKPT; 225 226 #ifdef PMAP_PAE_COMP 227 pt_entry_t pg_nx; 228 static uma_zone_t pdptzone; 229 #endif 230 231 _Static_assert(VM_MAXUSER_ADDRESS == VADDR(TRPTDI, 0), "VM_MAXUSER_ADDRESS"); 232 _Static_assert(VM_MAX_KERNEL_ADDRESS <= VADDR(PTDPTDI, 0), 233 "VM_MAX_KERNEL_ADDRESS"); 234 _Static_assert(PMAP_MAP_LOW == VADDR(LOWPTDI, 0), "PMAP_MAP_LOW"); 235 _Static_assert(KERNLOAD == (KERNPTDI << PDRSHIFT), "KERNLOAD"); 236 237 extern int pat_works; 238 extern int pg_ps_enabled; 239 240 extern int elf32_nxstack; 241 242 #define PAT_INDEX_SIZE 8 243 static int pat_index[PAT_INDEX_SIZE]; /* cache mode to PAT index conversion */ 244 245 /* 246 * pmap_mapdev support pre initialization (i.e. console) 247 */ 248 #define PMAP_PREINIT_MAPPING_COUNT 8 249 static struct pmap_preinit_mapping { 250 vm_paddr_t pa; 251 vm_offset_t va; 252 vm_size_t sz; 253 int mode; 254 } pmap_preinit_mapping[PMAP_PREINIT_MAPPING_COUNT]; 255 static int pmap_initialized; 256 257 static struct rwlock_padalign pvh_global_lock; 258 259 /* 260 * Data for the pv entry allocation mechanism 261 */ 262 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks); 263 extern int pv_entry_max, pv_entry_count; 264 static int pv_entry_high_water = 0; 265 static struct md_page *pv_table; 266 extern int shpgperproc; 267 268 static struct pv_chunk *pv_chunkbase; /* KVA block for pv_chunks */ 269 static int pv_maxchunks; /* How many chunks we have KVA for */ 270 static vm_offset_t pv_vafree; /* freelist stored in the PTE */ 271 272 /* 273 * All those kernel PT submaps that BSD is so fond of 274 */ 275 static pt_entry_t *CMAP3; 276 static pd_entry_t *KPTD; 277 static caddr_t CADDR3; 278 279 /* 280 * Crashdump maps. 281 */ 282 static caddr_t crashdumpmap; 283 284 static pt_entry_t *PMAP1 = NULL, *PMAP2, *PMAP3; 285 static pt_entry_t *PADDR1 = NULL, *PADDR2, *PADDR3; 286 #ifdef SMP 287 static int PMAP1cpu, PMAP3cpu; 288 extern int PMAP1changedcpu; 289 #endif 290 extern int PMAP1changed; 291 extern int PMAP1unchanged; 292 static struct mtx PMAP2mutex; 293 294 /* 295 * Internal flags for pmap_enter()'s helper functions. 296 */ 297 #define PMAP_ENTER_NORECLAIM 0x1000000 /* Don't reclaim PV entries. */ 298 #define PMAP_ENTER_NOREPLACE 0x2000000 /* Don't replace mappings. */ 299 300 static void free_pv_chunk(struct pv_chunk *pc); 301 static void free_pv_entry(pmap_t pmap, pv_entry_t pv); 302 static pv_entry_t get_pv_entry(pmap_t pmap, boolean_t try); 303 static void pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa); 304 static bool pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, pd_entry_t pde, 305 u_int flags); 306 #if VM_NRESERVLEVEL > 0 307 static void pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa); 308 #endif 309 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va); 310 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, 311 vm_offset_t va); 312 static int pmap_pvh_wired_mappings(struct md_page *pvh, int count); 313 314 static boolean_t pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va); 315 static bool pmap_enter_4mpage(pmap_t pmap, vm_offset_t va, vm_page_t m, 316 vm_prot_t prot); 317 static int pmap_enter_pde(pmap_t pmap, vm_offset_t va, pd_entry_t newpde, 318 u_int flags, vm_page_t m); 319 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, 320 vm_page_t m, vm_prot_t prot, vm_page_t mpte); 321 static int pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte); 322 static void pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va, 323 pd_entry_t pde); 324 static void pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte); 325 static boolean_t pmap_is_modified_pvh(struct md_page *pvh); 326 static boolean_t pmap_is_referenced_pvh(struct md_page *pvh); 327 static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode); 328 static void pmap_kenter_pde(vm_offset_t va, pd_entry_t newpde); 329 static void pmap_pde_attr(pd_entry_t *pde, int cache_bits); 330 #if VM_NRESERVLEVEL > 0 331 static void pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va); 332 #endif 333 static boolean_t pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, 334 vm_prot_t prot); 335 static void pmap_pte_attr(pt_entry_t *pte, int cache_bits); 336 static void pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva, 337 struct spglist *free); 338 static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva, 339 struct spglist *free); 340 static vm_page_t pmap_remove_pt_page(pmap_t pmap, vm_offset_t va); 341 static void pmap_remove_page(struct pmap *pmap, vm_offset_t va, 342 struct spglist *free); 343 static bool pmap_remove_ptes(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, 344 struct spglist *free); 345 static void pmap_remove_entry(struct pmap *pmap, vm_page_t m, 346 vm_offset_t va); 347 static void pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m); 348 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, 349 vm_page_t m); 350 static void pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, 351 pd_entry_t newpde); 352 static void pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde); 353 354 static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va, u_int flags); 355 356 static vm_page_t _pmap_allocpte(pmap_t pmap, u_int ptepindex, u_int flags); 357 static void _pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free); 358 static pt_entry_t *pmap_pte_quick(pmap_t pmap, vm_offset_t va); 359 static void pmap_pte_release(pt_entry_t *pte); 360 static int pmap_unuse_pt(pmap_t, vm_offset_t, struct spglist *); 361 #ifdef PMAP_PAE_COMP 362 static void *pmap_pdpt_allocf(uma_zone_t zone, vm_size_t bytes, int domain, 363 uint8_t *flags, int wait); 364 #endif 365 static void pmap_init_trm(void); 366 static void pmap_invalidate_all_int(pmap_t pmap); 367 368 static __inline void pagezero(void *page); 369 370 CTASSERT(1 << PDESHIFT == sizeof(pd_entry_t)); 371 CTASSERT(1 << PTESHIFT == sizeof(pt_entry_t)); 372 373 extern char _end[]; 374 extern u_long physfree; /* phys addr of next free page */ 375 extern u_long vm86phystk;/* PA of vm86/bios stack */ 376 extern u_long vm86paddr;/* address of vm86 region */ 377 extern int vm86pa; /* phys addr of vm86 region */ 378 extern u_long KERNend; /* phys addr end of kernel (just after bss) */ 379 #ifdef PMAP_PAE_COMP 380 pd_entry_t *IdlePTD_pae; /* phys addr of kernel PTD */ 381 pdpt_entry_t *IdlePDPT; /* phys addr of kernel PDPT */ 382 pt_entry_t *KPTmap_pae; /* address of kernel page tables */ 383 #define IdlePTD IdlePTD_pae 384 #define KPTmap KPTmap_pae 385 #else 386 pd_entry_t *IdlePTD_nopae; 387 pt_entry_t *KPTmap_nopae; 388 #define IdlePTD IdlePTD_nopae 389 #define KPTmap KPTmap_nopae 390 #endif 391 extern u_long KPTphys; /* phys addr of kernel page tables */ 392 extern u_long tramp_idleptd; 393 394 static u_long 395 allocpages(u_int cnt, u_long *physfree) 396 { 397 u_long res; 398 399 res = *physfree; 400 *physfree += PAGE_SIZE * cnt; 401 bzero((void *)res, PAGE_SIZE * cnt); 402 return (res); 403 } 404 405 static void 406 pmap_cold_map(u_long pa, u_long va, u_long cnt) 407 { 408 pt_entry_t *pt; 409 410 for (pt = (pt_entry_t *)KPTphys + atop(va); cnt > 0; 411 cnt--, pt++, va += PAGE_SIZE, pa += PAGE_SIZE) 412 *pt = pa | PG_V | PG_RW | PG_A | PG_M; 413 } 414 415 static void 416 pmap_cold_mapident(u_long pa, u_long cnt) 417 { 418 419 pmap_cold_map(pa, pa, cnt); 420 } 421 422 _Static_assert(LOWPTDI * 2 * NBPDR == KERNBASE, 423 "Broken double-map of zero PTD"); 424 425 static void 426 __CONCAT(PMTYPE, remap_lower)(bool enable) 427 { 428 int i; 429 430 for (i = 0; i < LOWPTDI; i++) 431 IdlePTD[i] = enable ? IdlePTD[LOWPTDI + i] : 0; 432 load_cr3(rcr3()); /* invalidate TLB */ 433 } 434 435 /* 436 * Called from locore.s before paging is enabled. Sets up the first 437 * kernel page table. Since kernel is mapped with PA == VA, this code 438 * does not require relocations. 439 */ 440 void 441 __CONCAT(PMTYPE, cold)(void) 442 { 443 pt_entry_t *pt; 444 u_long a; 445 u_int cr3, ncr4; 446 447 physfree = (u_long)&_end; 448 if (bootinfo.bi_esymtab != 0) 449 physfree = bootinfo.bi_esymtab; 450 if (bootinfo.bi_kernend != 0) 451 physfree = bootinfo.bi_kernend; 452 physfree = roundup2(physfree, NBPDR); 453 KERNend = physfree; 454 455 /* Allocate Kernel Page Tables */ 456 KPTphys = allocpages(NKPT, &physfree); 457 KPTmap = (pt_entry_t *)KPTphys; 458 459 /* Allocate Page Table Directory */ 460 #ifdef PMAP_PAE_COMP 461 /* XXX only need 32 bytes (easier for now) */ 462 IdlePDPT = (pdpt_entry_t *)allocpages(1, &physfree); 463 #endif 464 IdlePTD = (pd_entry_t *)allocpages(NPGPTD, &physfree); 465 466 /* 467 * Allocate KSTACK. Leave a guard page between IdlePTD and 468 * proc0kstack, to control stack overflow for thread0 and 469 * prevent corruption of the page table. We leak the guard 470 * physical memory due to 1:1 mappings. 471 */ 472 allocpages(1, &physfree); 473 proc0kstack = allocpages(TD0_KSTACK_PAGES, &physfree); 474 475 /* vm86/bios stack */ 476 vm86phystk = allocpages(1, &physfree); 477 478 /* pgtable + ext + IOPAGES */ 479 vm86paddr = vm86pa = allocpages(3, &physfree); 480 481 /* Install page tables into PTD. Page table page 1 is wasted. */ 482 for (a = 0; a < NKPT; a++) 483 IdlePTD[a] = (KPTphys + ptoa(a)) | PG_V | PG_RW | PG_A | PG_M; 484 485 #ifdef PMAP_PAE_COMP 486 /* PAE install PTD pointers into PDPT */ 487 for (a = 0; a < NPGPTD; a++) 488 IdlePDPT[a] = ((u_int)IdlePTD + ptoa(a)) | PG_V; 489 #endif 490 491 /* 492 * Install recursive mapping for kernel page tables into 493 * itself. 494 */ 495 for (a = 0; a < NPGPTD; a++) 496 IdlePTD[PTDPTDI + a] = ((u_int)IdlePTD + ptoa(a)) | PG_V | 497 PG_RW; 498 499 /* 500 * Initialize page table pages mapping physical address zero 501 * through the (physical) end of the kernel. Many of these 502 * pages must be reserved, and we reserve them all and map 503 * them linearly for convenience. We do this even if we've 504 * enabled PSE above; we'll just switch the corresponding 505 * kernel PDEs before we turn on paging. 506 * 507 * This and all other page table entries allow read and write 508 * access for various reasons. Kernel mappings never have any 509 * access restrictions. 510 */ 511 pmap_cold_mapident(0, atop(NBPDR) * LOWPTDI); 512 pmap_cold_map(0, NBPDR * LOWPTDI, atop(NBPDR) * LOWPTDI); 513 pmap_cold_mapident(KERNBASE, atop(KERNend - KERNBASE)); 514 515 /* Map page table directory */ 516 #ifdef PMAP_PAE_COMP 517 pmap_cold_mapident((u_long)IdlePDPT, 1); 518 #endif 519 pmap_cold_mapident((u_long)IdlePTD, NPGPTD); 520 521 /* Map early KPTmap. It is really pmap_cold_mapident. */ 522 pmap_cold_map(KPTphys, (u_long)KPTmap, NKPT); 523 524 /* Map proc0kstack */ 525 pmap_cold_mapident(proc0kstack, TD0_KSTACK_PAGES); 526 /* ISA hole already mapped */ 527 528 pmap_cold_mapident(vm86phystk, 1); 529 pmap_cold_mapident(vm86pa, 3); 530 531 /* Map page 0 into the vm86 page table */ 532 *(pt_entry_t *)vm86pa = 0 | PG_RW | PG_U | PG_A | PG_M | PG_V; 533 534 /* ...likewise for the ISA hole for vm86 */ 535 for (pt = (pt_entry_t *)vm86pa + atop(ISA_HOLE_START), a = 0; 536 a < atop(ISA_HOLE_LENGTH); a++, pt++) 537 *pt = (ISA_HOLE_START + ptoa(a)) | PG_RW | PG_U | PG_A | 538 PG_M | PG_V; 539 540 /* Enable PSE, PGE, VME, and PAE if configured. */ 541 ncr4 = 0; 542 if ((cpu_feature & CPUID_PSE) != 0) { 543 ncr4 |= CR4_PSE; 544 pseflag = PG_PS; 545 /* 546 * Superpage mapping of the kernel text. Existing 4k 547 * page table pages are wasted. 548 */ 549 for (a = KERNBASE; a < KERNend; a += NBPDR) 550 IdlePTD[a >> PDRSHIFT] = a | PG_PS | PG_A | PG_M | 551 PG_RW | PG_V; 552 } 553 if ((cpu_feature & CPUID_PGE) != 0) { 554 ncr4 |= CR4_PGE; 555 pgeflag = PG_G; 556 } 557 ncr4 |= (cpu_feature & CPUID_VME) != 0 ? CR4_VME : 0; 558 #ifdef PMAP_PAE_COMP 559 ncr4 |= CR4_PAE; 560 #endif 561 if (ncr4 != 0) 562 load_cr4(rcr4() | ncr4); 563 564 /* Now enable paging */ 565 #ifdef PMAP_PAE_COMP 566 cr3 = (u_int)IdlePDPT; 567 #else 568 cr3 = (u_int)IdlePTD; 569 #endif 570 tramp_idleptd = cr3; 571 load_cr3(cr3); 572 load_cr0(rcr0() | CR0_PG); 573 574 /* 575 * Now running relocated at KERNBASE where the system is 576 * linked to run. 577 */ 578 579 /* 580 * Remove the lowest part of the double mapping of low memory 581 * to get some null pointer checks. 582 */ 583 __CONCAT(PMTYPE, remap_lower)(false); 584 585 kernel_vm_end = /* 0 + */ NKPT * NBPDR; 586 #ifdef PMAP_PAE_COMP 587 i386_pmap_VM_NFREEORDER = VM_NFREEORDER_PAE; 588 i386_pmap_VM_LEVEL_0_ORDER = VM_LEVEL_0_ORDER_PAE; 589 i386_pmap_PDRSHIFT = PDRSHIFT_PAE; 590 #else 591 i386_pmap_VM_NFREEORDER = VM_NFREEORDER_NOPAE; 592 i386_pmap_VM_LEVEL_0_ORDER = VM_LEVEL_0_ORDER_NOPAE; 593 i386_pmap_PDRSHIFT = PDRSHIFT_NOPAE; 594 #endif 595 } 596 597 static void 598 __CONCAT(PMTYPE, set_nx)(void) 599 { 600 601 #ifdef PMAP_PAE_COMP 602 if ((amd_feature & AMDID_NX) == 0) 603 return; 604 pg_nx = PG_NX; 605 elf32_nxstack = 1; 606 /* EFER.EFER_NXE is set in initializecpu(). */ 607 #endif 608 } 609 610 /* 611 * Bootstrap the system enough to run with virtual memory. 612 * 613 * On the i386 this is called after pmap_cold() created initial 614 * kernel page table and enabled paging, and just syncs the pmap 615 * module with what has already been done. 616 */ 617 static void 618 __CONCAT(PMTYPE, bootstrap)(vm_paddr_t firstaddr) 619 { 620 vm_offset_t va; 621 pt_entry_t *pte, *unused; 622 struct pcpu *pc; 623 u_long res; 624 int i; 625 626 res = atop(firstaddr - (vm_paddr_t)KERNLOAD); 627 628 /* 629 * Add a physical memory segment (vm_phys_seg) corresponding to the 630 * preallocated kernel page table pages so that vm_page structures 631 * representing these pages will be created. The vm_page structures 632 * are required for promotion of the corresponding kernel virtual 633 * addresses to superpage mappings. 634 */ 635 vm_phys_add_seg(KPTphys, KPTphys + ptoa(nkpt)); 636 637 /* 638 * Initialize the first available kernel virtual address. 639 * However, using "firstaddr" may waste a few pages of the 640 * kernel virtual address space, because pmap_cold() may not 641 * have mapped every physical page that it allocated. 642 * Preferably, pmap_cold() would provide a first unused 643 * virtual address in addition to "firstaddr". 644 */ 645 virtual_avail = (vm_offset_t)firstaddr; 646 virtual_end = VM_MAX_KERNEL_ADDRESS; 647 648 /* 649 * Initialize the kernel pmap (which is statically allocated). 650 * Count bootstrap data as being resident in case any of this data is 651 * later unmapped (using pmap_remove()) and freed. 652 */ 653 PMAP_LOCK_INIT(kernel_pmap); 654 kernel_pmap->pm_pdir = IdlePTD; 655 #ifdef PMAP_PAE_COMP 656 kernel_pmap->pm_pdpt = IdlePDPT; 657 #endif 658 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */ 659 kernel_pmap->pm_stats.resident_count = res; 660 TAILQ_INIT(&kernel_pmap->pm_pvchunk); 661 662 /* 663 * Initialize the global pv list lock. 664 */ 665 rw_init(&pvh_global_lock, "pmap pv global"); 666 667 /* 668 * Reserve some special page table entries/VA space for temporary 669 * mapping of pages. 670 */ 671 #define SYSMAP(c, p, v, n) \ 672 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n); 673 674 va = virtual_avail; 675 pte = vtopte(va); 676 677 678 /* 679 * Initialize temporary map objects on the current CPU for use 680 * during early boot. 681 * CMAP1/CMAP2 are used for zeroing and copying pages. 682 * CMAP3 is used for the boot-time memory test. 683 */ 684 pc = get_pcpu(); 685 mtx_init(&pc->pc_cmap_lock, "SYSMAPS", NULL, MTX_DEF); 686 SYSMAP(caddr_t, pc->pc_cmap_pte1, pc->pc_cmap_addr1, 1) 687 SYSMAP(caddr_t, pc->pc_cmap_pte2, pc->pc_cmap_addr2, 1) 688 SYSMAP(vm_offset_t, pte, pc->pc_qmap_addr, 1) 689 690 SYSMAP(caddr_t, CMAP3, CADDR3, 1); 691 692 /* 693 * Crashdump maps. 694 */ 695 SYSMAP(caddr_t, unused, crashdumpmap, MAXDUMPPGS) 696 697 /* 698 * ptvmmap is used for reading arbitrary physical pages via /dev/mem. 699 */ 700 SYSMAP(caddr_t, unused, ptvmmap, 1) 701 702 /* 703 * msgbufp is used to map the system message buffer. 704 */ 705 SYSMAP(struct msgbuf *, unused, msgbufp, atop(round_page(msgbufsize))) 706 707 /* 708 * KPTmap is used by pmap_kextract(). 709 * 710 * KPTmap is first initialized by pmap_cold(). However, that initial 711 * KPTmap can only support NKPT page table pages. Here, a larger 712 * KPTmap is created that can support KVA_PAGES page table pages. 713 */ 714 SYSMAP(pt_entry_t *, KPTD, KPTmap, KVA_PAGES) 715 716 for (i = 0; i < NKPT; i++) 717 KPTD[i] = (KPTphys + ptoa(i)) | PG_RW | PG_V; 718 719 /* 720 * PADDR1 and PADDR2 are used by pmap_pte_quick() and pmap_pte(), 721 * respectively. 722 */ 723 SYSMAP(pt_entry_t *, PMAP1, PADDR1, 1) 724 SYSMAP(pt_entry_t *, PMAP2, PADDR2, 1) 725 SYSMAP(pt_entry_t *, PMAP3, PADDR3, 1) 726 727 mtx_init(&PMAP2mutex, "PMAP2", NULL, MTX_DEF); 728 729 virtual_avail = va; 730 731 /* 732 * Initialize the PAT MSR if present. 733 * pmap_init_pat() clears and sets CR4_PGE, which, as a 734 * side-effect, invalidates stale PG_G TLB entries that might 735 * have been created in our pre-boot environment. We assume 736 * that PAT support implies PGE and in reverse, PGE presence 737 * comes with PAT. Both features were added for Pentium Pro. 738 */ 739 pmap_init_pat(); 740 } 741 742 static void 743 pmap_init_reserved_pages(void) 744 { 745 struct pcpu *pc; 746 vm_offset_t pages; 747 int i; 748 749 #ifdef PMAP_PAE_COMP 750 if (!pae_mode) 751 return; 752 #else 753 if (pae_mode) 754 return; 755 #endif 756 CPU_FOREACH(i) { 757 pc = pcpu_find(i); 758 mtx_init(&pc->pc_copyout_mlock, "cpmlk", NULL, MTX_DEF | 759 MTX_NEW); 760 pc->pc_copyout_maddr = kva_alloc(ptoa(2)); 761 if (pc->pc_copyout_maddr == 0) 762 panic("unable to allocate non-sleepable copyout KVA"); 763 sx_init(&pc->pc_copyout_slock, "cpslk"); 764 pc->pc_copyout_saddr = kva_alloc(ptoa(2)); 765 if (pc->pc_copyout_saddr == 0) 766 panic("unable to allocate sleepable copyout KVA"); 767 pc->pc_pmap_eh_va = kva_alloc(ptoa(1)); 768 if (pc->pc_pmap_eh_va == 0) 769 panic("unable to allocate pmap_extract_and_hold KVA"); 770 pc->pc_pmap_eh_ptep = (char *)vtopte(pc->pc_pmap_eh_va); 771 772 /* 773 * Skip if the mappings have already been initialized, 774 * i.e. this is the BSP. 775 */ 776 if (pc->pc_cmap_addr1 != 0) 777 continue; 778 779 mtx_init(&pc->pc_cmap_lock, "SYSMAPS", NULL, MTX_DEF); 780 pages = kva_alloc(PAGE_SIZE * 3); 781 if (pages == 0) 782 panic("unable to allocate CMAP KVA"); 783 pc->pc_cmap_pte1 = vtopte(pages); 784 pc->pc_cmap_pte2 = vtopte(pages + PAGE_SIZE); 785 pc->pc_cmap_addr1 = (caddr_t)pages; 786 pc->pc_cmap_addr2 = (caddr_t)(pages + PAGE_SIZE); 787 pc->pc_qmap_addr = pages + ptoa(2); 788 } 789 } 790 791 SYSINIT(rpages_init, SI_SUB_CPU, SI_ORDER_ANY, pmap_init_reserved_pages, NULL); 792 793 /* 794 * Setup the PAT MSR. 795 */ 796 static void 797 __CONCAT(PMTYPE, init_pat)(void) 798 { 799 int pat_table[PAT_INDEX_SIZE]; 800 uint64_t pat_msr; 801 u_long cr0, cr4; 802 int i; 803 804 /* Set default PAT index table. */ 805 for (i = 0; i < PAT_INDEX_SIZE; i++) 806 pat_table[i] = -1; 807 pat_table[PAT_WRITE_BACK] = 0; 808 pat_table[PAT_WRITE_THROUGH] = 1; 809 pat_table[PAT_UNCACHEABLE] = 3; 810 pat_table[PAT_WRITE_COMBINING] = 3; 811 pat_table[PAT_WRITE_PROTECTED] = 3; 812 pat_table[PAT_UNCACHED] = 3; 813 814 /* 815 * Bail if this CPU doesn't implement PAT. 816 * We assume that PAT support implies PGE. 817 */ 818 if ((cpu_feature & CPUID_PAT) == 0) { 819 for (i = 0; i < PAT_INDEX_SIZE; i++) 820 pat_index[i] = pat_table[i]; 821 pat_works = 0; 822 return; 823 } 824 825 /* 826 * Due to some Intel errata, we can only safely use the lower 4 827 * PAT entries. 828 * 829 * Intel Pentium III Processor Specification Update 830 * Errata E.27 (Upper Four PAT Entries Not Usable With Mode B 831 * or Mode C Paging) 832 * 833 * Intel Pentium IV Processor Specification Update 834 * Errata N46 (PAT Index MSB May Be Calculated Incorrectly) 835 */ 836 if (cpu_vendor_id == CPU_VENDOR_INTEL && 837 !(CPUID_TO_FAMILY(cpu_id) == 6 && CPUID_TO_MODEL(cpu_id) >= 0xe)) 838 pat_works = 0; 839 840 /* Initialize default PAT entries. */ 841 pat_msr = PAT_VALUE(0, PAT_WRITE_BACK) | 842 PAT_VALUE(1, PAT_WRITE_THROUGH) | 843 PAT_VALUE(2, PAT_UNCACHED) | 844 PAT_VALUE(3, PAT_UNCACHEABLE) | 845 PAT_VALUE(4, PAT_WRITE_BACK) | 846 PAT_VALUE(5, PAT_WRITE_THROUGH) | 847 PAT_VALUE(6, PAT_UNCACHED) | 848 PAT_VALUE(7, PAT_UNCACHEABLE); 849 850 if (pat_works) { 851 /* 852 * Leave the indices 0-3 at the default of WB, WT, UC-, and UC. 853 * Program 5 and 6 as WP and WC. 854 * Leave 4 and 7 as WB and UC. 855 */ 856 pat_msr &= ~(PAT_MASK(5) | PAT_MASK(6)); 857 pat_msr |= PAT_VALUE(5, PAT_WRITE_PROTECTED) | 858 PAT_VALUE(6, PAT_WRITE_COMBINING); 859 pat_table[PAT_UNCACHED] = 2; 860 pat_table[PAT_WRITE_PROTECTED] = 5; 861 pat_table[PAT_WRITE_COMBINING] = 6; 862 } else { 863 /* 864 * Just replace PAT Index 2 with WC instead of UC-. 865 */ 866 pat_msr &= ~PAT_MASK(2); 867 pat_msr |= PAT_VALUE(2, PAT_WRITE_COMBINING); 868 pat_table[PAT_WRITE_COMBINING] = 2; 869 } 870 871 /* Disable PGE. */ 872 cr4 = rcr4(); 873 load_cr4(cr4 & ~CR4_PGE); 874 875 /* Disable caches (CD = 1, NW = 0). */ 876 cr0 = rcr0(); 877 load_cr0((cr0 & ~CR0_NW) | CR0_CD); 878 879 /* Flushes caches and TLBs. */ 880 wbinvd(); 881 invltlb(); 882 883 /* Update PAT and index table. */ 884 wrmsr(MSR_PAT, pat_msr); 885 for (i = 0; i < PAT_INDEX_SIZE; i++) 886 pat_index[i] = pat_table[i]; 887 888 /* Flush caches and TLBs again. */ 889 wbinvd(); 890 invltlb(); 891 892 /* Restore caches and PGE. */ 893 load_cr0(cr0); 894 load_cr4(cr4); 895 } 896 897 #ifdef PMAP_PAE_COMP 898 static void * 899 pmap_pdpt_allocf(uma_zone_t zone, vm_size_t bytes, int domain, uint8_t *flags, 900 int wait) 901 { 902 903 /* Inform UMA that this allocator uses kernel_map/object. */ 904 *flags = UMA_SLAB_KERNEL; 905 return ((void *)kmem_alloc_contig_domainset(DOMAINSET_FIXED(domain), 906 bytes, wait, 0x0ULL, 0xffffffffULL, 1, 0, VM_MEMATTR_DEFAULT)); 907 } 908 #endif 909 910 /* 911 * Abuse the pte nodes for unmapped kva to thread a kva freelist through. 912 * Requirements: 913 * - Must deal with pages in order to ensure that none of the PG_* bits 914 * are ever set, PG_V in particular. 915 * - Assumes we can write to ptes without pte_store() atomic ops, even 916 * on PAE systems. This should be ok. 917 * - Assumes nothing will ever test these addresses for 0 to indicate 918 * no mapping instead of correctly checking PG_V. 919 * - Assumes a vm_offset_t will fit in a pte (true for i386). 920 * Because PG_V is never set, there can be no mappings to invalidate. 921 */ 922 static vm_offset_t 923 pmap_ptelist_alloc(vm_offset_t *head) 924 { 925 pt_entry_t *pte; 926 vm_offset_t va; 927 928 va = *head; 929 if (va == 0) 930 panic("pmap_ptelist_alloc: exhausted ptelist KVA"); 931 pte = vtopte(va); 932 *head = *pte; 933 if (*head & PG_V) 934 panic("pmap_ptelist_alloc: va with PG_V set!"); 935 *pte = 0; 936 return (va); 937 } 938 939 static void 940 pmap_ptelist_free(vm_offset_t *head, vm_offset_t va) 941 { 942 pt_entry_t *pte; 943 944 if (va & PG_V) 945 panic("pmap_ptelist_free: freeing va with PG_V set!"); 946 pte = vtopte(va); 947 *pte = *head; /* virtual! PG_V is 0 though */ 948 *head = va; 949 } 950 951 static void 952 pmap_ptelist_init(vm_offset_t *head, void *base, int npages) 953 { 954 int i; 955 vm_offset_t va; 956 957 *head = 0; 958 for (i = npages - 1; i >= 0; i--) { 959 va = (vm_offset_t)base + i * PAGE_SIZE; 960 pmap_ptelist_free(head, va); 961 } 962 } 963 964 965 /* 966 * Initialize the pmap module. 967 * Called by vm_init, to initialize any structures that the pmap 968 * system needs to map virtual memory. 969 */ 970 static void 971 __CONCAT(PMTYPE, init)(void) 972 { 973 struct pmap_preinit_mapping *ppim; 974 vm_page_t mpte; 975 vm_size_t s; 976 int i, pv_npg; 977 978 /* 979 * Initialize the vm page array entries for the kernel pmap's 980 * page table pages. 981 */ 982 PMAP_LOCK(kernel_pmap); 983 for (i = 0; i < NKPT; i++) { 984 mpte = PHYS_TO_VM_PAGE(KPTphys + ptoa(i)); 985 KASSERT(mpte >= vm_page_array && 986 mpte < &vm_page_array[vm_page_array_size], 987 ("pmap_init: page table page is out of range")); 988 mpte->pindex = i + KPTDI; 989 mpte->phys_addr = KPTphys + ptoa(i); 990 mpte->wire_count = 1; 991 if (pseflag != 0 && 992 KERNBASE <= i << PDRSHIFT && i << PDRSHIFT < KERNend && 993 pmap_insert_pt_page(kernel_pmap, mpte)) 994 panic("pmap_init: pmap_insert_pt_page failed"); 995 } 996 PMAP_UNLOCK(kernel_pmap); 997 vm_wire_add(NKPT); 998 999 /* 1000 * Initialize the address space (zone) for the pv entries. Set a 1001 * high water mark so that the system can recover from excessive 1002 * numbers of pv entries. 1003 */ 1004 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc); 1005 pv_entry_max = shpgperproc * maxproc + vm_cnt.v_page_count; 1006 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max); 1007 pv_entry_max = roundup(pv_entry_max, _NPCPV); 1008 pv_entry_high_water = 9 * (pv_entry_max / 10); 1009 1010 /* 1011 * If the kernel is running on a virtual machine, then it must assume 1012 * that MCA is enabled by the hypervisor. Moreover, the kernel must 1013 * be prepared for the hypervisor changing the vendor and family that 1014 * are reported by CPUID. Consequently, the workaround for AMD Family 1015 * 10h Erratum 383 is enabled if the processor's feature set does not 1016 * include at least one feature that is only supported by older Intel 1017 * or newer AMD processors. 1018 */ 1019 if (vm_guest != VM_GUEST_NO && (cpu_feature & CPUID_SS) == 0 && 1020 (cpu_feature2 & (CPUID2_SSSE3 | CPUID2_SSE41 | CPUID2_AESNI | 1021 CPUID2_AVX | CPUID2_XSAVE)) == 0 && (amd_feature2 & (AMDID2_XOP | 1022 AMDID2_FMA4)) == 0) 1023 workaround_erratum383 = 1; 1024 1025 /* 1026 * Are large page mappings supported and enabled? 1027 */ 1028 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled); 1029 if (pseflag == 0) 1030 pg_ps_enabled = 0; 1031 else if (pg_ps_enabled) { 1032 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0, 1033 ("pmap_init: can't assign to pagesizes[1]")); 1034 pagesizes[1] = NBPDR; 1035 } 1036 1037 /* 1038 * Calculate the size of the pv head table for superpages. 1039 * Handle the possibility that "vm_phys_segs[...].end" is zero. 1040 */ 1041 pv_npg = trunc_4mpage(vm_phys_segs[vm_phys_nsegs - 1].end - 1042 PAGE_SIZE) / NBPDR + 1; 1043 1044 /* 1045 * Allocate memory for the pv head table for superpages. 1046 */ 1047 s = (vm_size_t)(pv_npg * sizeof(struct md_page)); 1048 s = round_page(s); 1049 pv_table = (struct md_page *)kmem_malloc(s, M_WAITOK | M_ZERO); 1050 for (i = 0; i < pv_npg; i++) 1051 TAILQ_INIT(&pv_table[i].pv_list); 1052 1053 pv_maxchunks = MAX(pv_entry_max / _NPCPV, maxproc); 1054 pv_chunkbase = (struct pv_chunk *)kva_alloc(PAGE_SIZE * pv_maxchunks); 1055 if (pv_chunkbase == NULL) 1056 panic("pmap_init: not enough kvm for pv chunks"); 1057 pmap_ptelist_init(&pv_vafree, pv_chunkbase, pv_maxchunks); 1058 #ifdef PMAP_PAE_COMP 1059 pdptzone = uma_zcreate("PDPT", NPGPTD * sizeof(pdpt_entry_t), NULL, 1060 NULL, NULL, NULL, (NPGPTD * sizeof(pdpt_entry_t)) - 1, 1061 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1062 uma_zone_set_allocf(pdptzone, pmap_pdpt_allocf); 1063 #endif 1064 1065 pmap_initialized = 1; 1066 pmap_init_trm(); 1067 1068 if (!bootverbose) 1069 return; 1070 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) { 1071 ppim = pmap_preinit_mapping + i; 1072 if (ppim->va == 0) 1073 continue; 1074 printf("PPIM %u: PA=%#jx, VA=%#x, size=%#x, mode=%#x\n", i, 1075 (uintmax_t)ppim->pa, ppim->va, ppim->sz, ppim->mode); 1076 } 1077 1078 } 1079 1080 extern u_long pmap_pde_demotions; 1081 extern u_long pmap_pde_mappings; 1082 extern u_long pmap_pde_p_failures; 1083 extern u_long pmap_pde_promotions; 1084 1085 /*************************************************** 1086 * Low level helper routines..... 1087 ***************************************************/ 1088 1089 static boolean_t 1090 __CONCAT(PMTYPE, is_valid_memattr)(pmap_t pmap __unused, vm_memattr_t mode) 1091 { 1092 1093 return (mode >= 0 && mode < PAT_INDEX_SIZE && 1094 pat_index[(int)mode] >= 0); 1095 } 1096 1097 /* 1098 * Determine the appropriate bits to set in a PTE or PDE for a specified 1099 * caching mode. 1100 */ 1101 static int 1102 __CONCAT(PMTYPE, cache_bits)(pmap_t pmap, int mode, boolean_t is_pde) 1103 { 1104 int cache_bits, pat_flag, pat_idx; 1105 1106 if (!pmap_is_valid_memattr(pmap, mode)) 1107 panic("Unknown caching mode %d\n", mode); 1108 1109 /* The PAT bit is different for PTE's and PDE's. */ 1110 pat_flag = is_pde ? PG_PDE_PAT : PG_PTE_PAT; 1111 1112 /* Map the caching mode to a PAT index. */ 1113 pat_idx = pat_index[mode]; 1114 1115 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */ 1116 cache_bits = 0; 1117 if (pat_idx & 0x4) 1118 cache_bits |= pat_flag; 1119 if (pat_idx & 0x2) 1120 cache_bits |= PG_NC_PCD; 1121 if (pat_idx & 0x1) 1122 cache_bits |= PG_NC_PWT; 1123 return (cache_bits); 1124 } 1125 1126 static bool 1127 __CONCAT(PMTYPE, ps_enabled)(pmap_t pmap __unused) 1128 { 1129 1130 return (pg_ps_enabled); 1131 } 1132 1133 /* 1134 * The caller is responsible for maintaining TLB consistency. 1135 */ 1136 static void 1137 pmap_kenter_pde(vm_offset_t va, pd_entry_t newpde) 1138 { 1139 pd_entry_t *pde; 1140 1141 pde = pmap_pde(kernel_pmap, va); 1142 pde_store(pde, newpde); 1143 } 1144 1145 /* 1146 * After changing the page size for the specified virtual address in the page 1147 * table, flush the corresponding entries from the processor's TLB. Only the 1148 * calling processor's TLB is affected. 1149 * 1150 * The calling thread must be pinned to a processor. 1151 */ 1152 static void 1153 pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde) 1154 { 1155 1156 if ((newpde & PG_PS) == 0) 1157 /* Demotion: flush a specific 2MB page mapping. */ 1158 invlpg(va); 1159 else /* if ((newpde & PG_G) == 0) */ 1160 /* 1161 * Promotion: flush every 4KB page mapping from the TLB 1162 * because there are too many to flush individually. 1163 */ 1164 invltlb(); 1165 } 1166 1167 #ifdef SMP 1168 /* 1169 * For SMP, these functions have to use the IPI mechanism for coherence. 1170 * 1171 * N.B.: Before calling any of the following TLB invalidation functions, 1172 * the calling processor must ensure that all stores updating a non- 1173 * kernel page table are globally performed. Otherwise, another 1174 * processor could cache an old, pre-update entry without being 1175 * invalidated. This can happen one of two ways: (1) The pmap becomes 1176 * active on another processor after its pm_active field is checked by 1177 * one of the following functions but before a store updating the page 1178 * table is globally performed. (2) The pmap becomes active on another 1179 * processor before its pm_active field is checked but due to 1180 * speculative loads one of the following functions stills reads the 1181 * pmap as inactive on the other processor. 1182 * 1183 * The kernel page table is exempt because its pm_active field is 1184 * immutable. The kernel page table is always active on every 1185 * processor. 1186 */ 1187 static void 1188 pmap_invalidate_page_int(pmap_t pmap, vm_offset_t va) 1189 { 1190 cpuset_t *mask, other_cpus; 1191 u_int cpuid; 1192 1193 sched_pin(); 1194 if (pmap == kernel_pmap) { 1195 invlpg(va); 1196 mask = &all_cpus; 1197 } else if (!CPU_CMP(&pmap->pm_active, &all_cpus)) { 1198 mask = &all_cpus; 1199 } else { 1200 cpuid = PCPU_GET(cpuid); 1201 other_cpus = all_cpus; 1202 CPU_CLR(cpuid, &other_cpus); 1203 CPU_AND(&other_cpus, &pmap->pm_active); 1204 mask = &other_cpus; 1205 } 1206 smp_masked_invlpg(*mask, va, pmap); 1207 sched_unpin(); 1208 } 1209 1210 /* 4k PTEs -- Chosen to exceed the total size of Broadwell L2 TLB */ 1211 #define PMAP_INVLPG_THRESHOLD (4 * 1024 * PAGE_SIZE) 1212 1213 static void 1214 pmap_invalidate_range_int(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 1215 { 1216 cpuset_t *mask, other_cpus; 1217 vm_offset_t addr; 1218 u_int cpuid; 1219 1220 if (eva - sva >= PMAP_INVLPG_THRESHOLD) { 1221 pmap_invalidate_all_int(pmap); 1222 return; 1223 } 1224 1225 sched_pin(); 1226 if (pmap == kernel_pmap) { 1227 for (addr = sva; addr < eva; addr += PAGE_SIZE) 1228 invlpg(addr); 1229 mask = &all_cpus; 1230 } else if (!CPU_CMP(&pmap->pm_active, &all_cpus)) { 1231 mask = &all_cpus; 1232 } else { 1233 cpuid = PCPU_GET(cpuid); 1234 other_cpus = all_cpus; 1235 CPU_CLR(cpuid, &other_cpus); 1236 CPU_AND(&other_cpus, &pmap->pm_active); 1237 mask = &other_cpus; 1238 } 1239 smp_masked_invlpg_range(*mask, sva, eva, pmap); 1240 sched_unpin(); 1241 } 1242 1243 static void 1244 pmap_invalidate_all_int(pmap_t pmap) 1245 { 1246 cpuset_t *mask, other_cpus; 1247 u_int cpuid; 1248 1249 sched_pin(); 1250 if (pmap == kernel_pmap) { 1251 invltlb(); 1252 mask = &all_cpus; 1253 } else if (!CPU_CMP(&pmap->pm_active, &all_cpus)) { 1254 mask = &all_cpus; 1255 } else { 1256 cpuid = PCPU_GET(cpuid); 1257 other_cpus = all_cpus; 1258 CPU_CLR(cpuid, &other_cpus); 1259 CPU_AND(&other_cpus, &pmap->pm_active); 1260 mask = &other_cpus; 1261 } 1262 smp_masked_invltlb(*mask, pmap); 1263 sched_unpin(); 1264 } 1265 1266 static void 1267 __CONCAT(PMTYPE, invalidate_cache)(void) 1268 { 1269 1270 sched_pin(); 1271 wbinvd(); 1272 smp_cache_flush(); 1273 sched_unpin(); 1274 } 1275 1276 struct pde_action { 1277 cpuset_t invalidate; /* processors that invalidate their TLB */ 1278 vm_offset_t va; 1279 pd_entry_t *pde; 1280 pd_entry_t newpde; 1281 u_int store; /* processor that updates the PDE */ 1282 }; 1283 1284 static void 1285 pmap_update_pde_kernel(void *arg) 1286 { 1287 struct pde_action *act = arg; 1288 pd_entry_t *pde; 1289 1290 if (act->store == PCPU_GET(cpuid)) { 1291 pde = pmap_pde(kernel_pmap, act->va); 1292 pde_store(pde, act->newpde); 1293 } 1294 } 1295 1296 static void 1297 pmap_update_pde_user(void *arg) 1298 { 1299 struct pde_action *act = arg; 1300 1301 if (act->store == PCPU_GET(cpuid)) 1302 pde_store(act->pde, act->newpde); 1303 } 1304 1305 static void 1306 pmap_update_pde_teardown(void *arg) 1307 { 1308 struct pde_action *act = arg; 1309 1310 if (CPU_ISSET(PCPU_GET(cpuid), &act->invalidate)) 1311 pmap_update_pde_invalidate(act->va, act->newpde); 1312 } 1313 1314 /* 1315 * Change the page size for the specified virtual address in a way that 1316 * prevents any possibility of the TLB ever having two entries that map the 1317 * same virtual address using different page sizes. This is the recommended 1318 * workaround for Erratum 383 on AMD Family 10h processors. It prevents a 1319 * machine check exception for a TLB state that is improperly diagnosed as a 1320 * hardware error. 1321 */ 1322 static void 1323 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde) 1324 { 1325 struct pde_action act; 1326 cpuset_t active, other_cpus; 1327 u_int cpuid; 1328 1329 sched_pin(); 1330 cpuid = PCPU_GET(cpuid); 1331 other_cpus = all_cpus; 1332 CPU_CLR(cpuid, &other_cpus); 1333 if (pmap == kernel_pmap) 1334 active = all_cpus; 1335 else 1336 active = pmap->pm_active; 1337 if (CPU_OVERLAP(&active, &other_cpus)) { 1338 act.store = cpuid; 1339 act.invalidate = active; 1340 act.va = va; 1341 act.pde = pde; 1342 act.newpde = newpde; 1343 CPU_SET(cpuid, &active); 1344 smp_rendezvous_cpus(active, 1345 smp_no_rendezvous_barrier, pmap == kernel_pmap ? 1346 pmap_update_pde_kernel : pmap_update_pde_user, 1347 pmap_update_pde_teardown, &act); 1348 } else { 1349 if (pmap == kernel_pmap) 1350 pmap_kenter_pde(va, newpde); 1351 else 1352 pde_store(pde, newpde); 1353 if (CPU_ISSET(cpuid, &active)) 1354 pmap_update_pde_invalidate(va, newpde); 1355 } 1356 sched_unpin(); 1357 } 1358 #else /* !SMP */ 1359 /* 1360 * Normal, non-SMP, 486+ invalidation functions. 1361 * We inline these within pmap.c for speed. 1362 */ 1363 static void 1364 pmap_invalidate_page_int(pmap_t pmap, vm_offset_t va) 1365 { 1366 1367 if (pmap == kernel_pmap) 1368 invlpg(va); 1369 } 1370 1371 static void 1372 pmap_invalidate_range_int(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 1373 { 1374 vm_offset_t addr; 1375 1376 if (pmap == kernel_pmap) 1377 for (addr = sva; addr < eva; addr += PAGE_SIZE) 1378 invlpg(addr); 1379 } 1380 1381 static void 1382 pmap_invalidate_all_int(pmap_t pmap) 1383 { 1384 1385 if (pmap == kernel_pmap) 1386 invltlb(); 1387 } 1388 1389 static void 1390 __CONCAT(PMTYPE, invalidate_cache)(void) 1391 { 1392 1393 wbinvd(); 1394 } 1395 1396 static void 1397 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde) 1398 { 1399 1400 if (pmap == kernel_pmap) 1401 pmap_kenter_pde(va, newpde); 1402 else 1403 pde_store(pde, newpde); 1404 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active)) 1405 pmap_update_pde_invalidate(va, newpde); 1406 } 1407 #endif /* !SMP */ 1408 1409 static void 1410 __CONCAT(PMTYPE, invalidate_page)(pmap_t pmap, vm_offset_t va) 1411 { 1412 1413 pmap_invalidate_page_int(pmap, va); 1414 } 1415 1416 static void 1417 __CONCAT(PMTYPE, invalidate_range)(pmap_t pmap, vm_offset_t sva, 1418 vm_offset_t eva) 1419 { 1420 1421 pmap_invalidate_range_int(pmap, sva, eva); 1422 } 1423 1424 static void 1425 __CONCAT(PMTYPE, invalidate_all)(pmap_t pmap) 1426 { 1427 1428 pmap_invalidate_all_int(pmap); 1429 } 1430 1431 static void 1432 pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va, pd_entry_t pde) 1433 { 1434 1435 /* 1436 * When the PDE has PG_PROMOTED set, the 2- or 4MB page mapping was 1437 * created by a promotion that did not invalidate the 512 or 1024 4KB 1438 * page mappings that might exist in the TLB. Consequently, at this 1439 * point, the TLB may hold both 4KB and 2- or 4MB page mappings for 1440 * the address range [va, va + NBPDR). Therefore, the entire range 1441 * must be invalidated here. In contrast, when PG_PROMOTED is clear, 1442 * the TLB will not hold any 4KB page mappings for the address range 1443 * [va, va + NBPDR), and so a single INVLPG suffices to invalidate the 1444 * 2- or 4MB page mapping from the TLB. 1445 */ 1446 if ((pde & PG_PROMOTED) != 0) 1447 pmap_invalidate_range_int(pmap, va, va + NBPDR - 1); 1448 else 1449 pmap_invalidate_page_int(pmap, va); 1450 } 1451 1452 /* 1453 * Are we current address space or kernel? 1454 */ 1455 static __inline int 1456 pmap_is_current(pmap_t pmap) 1457 { 1458 1459 return (pmap == kernel_pmap); 1460 } 1461 1462 /* 1463 * If the given pmap is not the current or kernel pmap, the returned pte must 1464 * be released by passing it to pmap_pte_release(). 1465 */ 1466 static pt_entry_t * 1467 __CONCAT(PMTYPE, pte)(pmap_t pmap, vm_offset_t va) 1468 { 1469 pd_entry_t newpf; 1470 pd_entry_t *pde; 1471 1472 pde = pmap_pde(pmap, va); 1473 if (*pde & PG_PS) 1474 return (pde); 1475 if (*pde != 0) { 1476 /* are we current address space or kernel? */ 1477 if (pmap_is_current(pmap)) 1478 return (vtopte(va)); 1479 mtx_lock(&PMAP2mutex); 1480 newpf = *pde & PG_FRAME; 1481 if ((*PMAP2 & PG_FRAME) != newpf) { 1482 *PMAP2 = newpf | PG_RW | PG_V | PG_A | PG_M; 1483 pmap_invalidate_page_int(kernel_pmap, 1484 (vm_offset_t)PADDR2); 1485 } 1486 return (PADDR2 + (i386_btop(va) & (NPTEPG - 1))); 1487 } 1488 return (NULL); 1489 } 1490 1491 /* 1492 * Releases a pte that was obtained from pmap_pte(). Be prepared for the pte 1493 * being NULL. 1494 */ 1495 static __inline void 1496 pmap_pte_release(pt_entry_t *pte) 1497 { 1498 1499 if ((pt_entry_t *)((vm_offset_t)pte & ~PAGE_MASK) == PADDR2) 1500 mtx_unlock(&PMAP2mutex); 1501 } 1502 1503 /* 1504 * NB: The sequence of updating a page table followed by accesses to the 1505 * corresponding pages is subject to the situation described in the "AMD64 1506 * Architecture Programmer's Manual Volume 2: System Programming" rev. 3.23, 1507 * "7.3.1 Special Coherency Considerations". Therefore, issuing the INVLPG 1508 * right after modifying the PTE bits is crucial. 1509 */ 1510 static __inline void 1511 invlcaddr(void *caddr) 1512 { 1513 1514 invlpg((u_int)caddr); 1515 } 1516 1517 /* 1518 * Super fast pmap_pte routine best used when scanning 1519 * the pv lists. This eliminates many coarse-grained 1520 * invltlb calls. Note that many of the pv list 1521 * scans are across different pmaps. It is very wasteful 1522 * to do an entire invltlb for checking a single mapping. 1523 * 1524 * If the given pmap is not the current pmap, pvh_global_lock 1525 * must be held and curthread pinned to a CPU. 1526 */ 1527 static pt_entry_t * 1528 pmap_pte_quick(pmap_t pmap, vm_offset_t va) 1529 { 1530 pd_entry_t newpf; 1531 pd_entry_t *pde; 1532 1533 pde = pmap_pde(pmap, va); 1534 if (*pde & PG_PS) 1535 return (pde); 1536 if (*pde != 0) { 1537 /* are we current address space or kernel? */ 1538 if (pmap_is_current(pmap)) 1539 return (vtopte(va)); 1540 rw_assert(&pvh_global_lock, RA_WLOCKED); 1541 KASSERT(curthread->td_pinned > 0, ("curthread not pinned")); 1542 newpf = *pde & PG_FRAME; 1543 if ((*PMAP1 & PG_FRAME) != newpf) { 1544 *PMAP1 = newpf | PG_RW | PG_V | PG_A | PG_M; 1545 #ifdef SMP 1546 PMAP1cpu = PCPU_GET(cpuid); 1547 #endif 1548 invlcaddr(PADDR1); 1549 PMAP1changed++; 1550 } else 1551 #ifdef SMP 1552 if (PMAP1cpu != PCPU_GET(cpuid)) { 1553 PMAP1cpu = PCPU_GET(cpuid); 1554 invlcaddr(PADDR1); 1555 PMAP1changedcpu++; 1556 } else 1557 #endif 1558 PMAP1unchanged++; 1559 return (PADDR1 + (i386_btop(va) & (NPTEPG - 1))); 1560 } 1561 return (0); 1562 } 1563 1564 static pt_entry_t * 1565 pmap_pte_quick3(pmap_t pmap, vm_offset_t va) 1566 { 1567 pd_entry_t newpf; 1568 pd_entry_t *pde; 1569 1570 pde = pmap_pde(pmap, va); 1571 if (*pde & PG_PS) 1572 return (pde); 1573 if (*pde != 0) { 1574 rw_assert(&pvh_global_lock, RA_WLOCKED); 1575 KASSERT(curthread->td_pinned > 0, ("curthread not pinned")); 1576 newpf = *pde & PG_FRAME; 1577 if ((*PMAP3 & PG_FRAME) != newpf) { 1578 *PMAP3 = newpf | PG_RW | PG_V | PG_A | PG_M; 1579 #ifdef SMP 1580 PMAP3cpu = PCPU_GET(cpuid); 1581 #endif 1582 invlcaddr(PADDR3); 1583 PMAP1changed++; 1584 } else 1585 #ifdef SMP 1586 if (PMAP3cpu != PCPU_GET(cpuid)) { 1587 PMAP3cpu = PCPU_GET(cpuid); 1588 invlcaddr(PADDR3); 1589 PMAP1changedcpu++; 1590 } else 1591 #endif 1592 PMAP1unchanged++; 1593 return (PADDR3 + (i386_btop(va) & (NPTEPG - 1))); 1594 } 1595 return (0); 1596 } 1597 1598 static pt_entry_t 1599 pmap_pte_ufast(pmap_t pmap, vm_offset_t va, pd_entry_t pde) 1600 { 1601 pt_entry_t *eh_ptep, pte, *ptep; 1602 1603 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1604 pde &= PG_FRAME; 1605 critical_enter(); 1606 eh_ptep = (pt_entry_t *)PCPU_GET(pmap_eh_ptep); 1607 if ((*eh_ptep & PG_FRAME) != pde) { 1608 *eh_ptep = pde | PG_RW | PG_V | PG_A | PG_M; 1609 invlcaddr((void *)PCPU_GET(pmap_eh_va)); 1610 } 1611 ptep = (pt_entry_t *)PCPU_GET(pmap_eh_va) + (i386_btop(va) & 1612 (NPTEPG - 1)); 1613 pte = *ptep; 1614 critical_exit(); 1615 return (pte); 1616 } 1617 1618 /* 1619 * Extract from the kernel page table the physical address that is mapped by 1620 * the given virtual address "va". 1621 * 1622 * This function may be used before pmap_bootstrap() is called. 1623 */ 1624 static vm_paddr_t 1625 __CONCAT(PMTYPE, kextract)(vm_offset_t va) 1626 { 1627 vm_paddr_t pa; 1628 1629 if ((pa = pte_load(&PTD[va >> PDRSHIFT])) & PG_PS) { 1630 pa = (pa & PG_PS_FRAME) | (va & PDRMASK); 1631 } else { 1632 /* 1633 * Beware of a concurrent promotion that changes the PDE at 1634 * this point! For example, vtopte() must not be used to 1635 * access the PTE because it would use the new PDE. It is, 1636 * however, safe to use the old PDE because the page table 1637 * page is preserved by the promotion. 1638 */ 1639 pa = KPTmap[i386_btop(va)]; 1640 pa = (pa & PG_FRAME) | (va & PAGE_MASK); 1641 } 1642 return (pa); 1643 } 1644 1645 /* 1646 * Routine: pmap_extract 1647 * Function: 1648 * Extract the physical page address associated 1649 * with the given map/virtual_address pair. 1650 */ 1651 static vm_paddr_t 1652 __CONCAT(PMTYPE, extract)(pmap_t pmap, vm_offset_t va) 1653 { 1654 vm_paddr_t rtval; 1655 pt_entry_t pte; 1656 pd_entry_t pde; 1657 1658 rtval = 0; 1659 PMAP_LOCK(pmap); 1660 pde = pmap->pm_pdir[va >> PDRSHIFT]; 1661 if (pde != 0) { 1662 if ((pde & PG_PS) != 0) 1663 rtval = (pde & PG_PS_FRAME) | (va & PDRMASK); 1664 else { 1665 pte = pmap_pte_ufast(pmap, va, pde); 1666 rtval = (pte & PG_FRAME) | (va & PAGE_MASK); 1667 } 1668 } 1669 PMAP_UNLOCK(pmap); 1670 return (rtval); 1671 } 1672 1673 /* 1674 * Routine: pmap_extract_and_hold 1675 * Function: 1676 * Atomically extract and hold the physical page 1677 * with the given pmap and virtual address pair 1678 * if that mapping permits the given protection. 1679 */ 1680 static vm_page_t 1681 __CONCAT(PMTYPE, extract_and_hold)(pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1682 { 1683 pd_entry_t pde; 1684 pt_entry_t pte; 1685 vm_page_t m; 1686 vm_paddr_t pa; 1687 1688 pa = 0; 1689 m = NULL; 1690 PMAP_LOCK(pmap); 1691 retry: 1692 pde = *pmap_pde(pmap, va); 1693 if (pde != 0) { 1694 if (pde & PG_PS) { 1695 if ((pde & PG_RW) || (prot & VM_PROT_WRITE) == 0) { 1696 if (vm_page_pa_tryrelock(pmap, (pde & 1697 PG_PS_FRAME) | (va & PDRMASK), &pa)) 1698 goto retry; 1699 m = PHYS_TO_VM_PAGE(pa); 1700 } 1701 } else { 1702 pte = pmap_pte_ufast(pmap, va, pde); 1703 if (pte != 0 && 1704 ((pte & PG_RW) || (prot & VM_PROT_WRITE) == 0)) { 1705 if (vm_page_pa_tryrelock(pmap, pte & PG_FRAME, 1706 &pa)) 1707 goto retry; 1708 m = PHYS_TO_VM_PAGE(pa); 1709 } 1710 } 1711 if (m != NULL) 1712 vm_page_hold(m); 1713 } 1714 PA_UNLOCK_COND(pa); 1715 PMAP_UNLOCK(pmap); 1716 return (m); 1717 } 1718 1719 /*************************************************** 1720 * Low level mapping routines..... 1721 ***************************************************/ 1722 1723 /* 1724 * Add a wired page to the kva. 1725 * Note: not SMP coherent. 1726 * 1727 * This function may be used before pmap_bootstrap() is called. 1728 */ 1729 static void 1730 __CONCAT(PMTYPE, kenter)(vm_offset_t va, vm_paddr_t pa) 1731 { 1732 pt_entry_t *pte; 1733 1734 pte = vtopte(va); 1735 pte_store(pte, pa | PG_RW | PG_V); 1736 } 1737 1738 static __inline void 1739 pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode) 1740 { 1741 pt_entry_t *pte; 1742 1743 pte = vtopte(va); 1744 pte_store(pte, pa | PG_RW | PG_V | pmap_cache_bits(kernel_pmap, 1745 mode, 0)); 1746 } 1747 1748 /* 1749 * Remove a page from the kernel pagetables. 1750 * Note: not SMP coherent. 1751 * 1752 * This function may be used before pmap_bootstrap() is called. 1753 */ 1754 static void 1755 __CONCAT(PMTYPE, kremove)(vm_offset_t va) 1756 { 1757 pt_entry_t *pte; 1758 1759 pte = vtopte(va); 1760 pte_clear(pte); 1761 } 1762 1763 /* 1764 * Used to map a range of physical addresses into kernel 1765 * virtual address space. 1766 * 1767 * The value passed in '*virt' is a suggested virtual address for 1768 * the mapping. Architectures which can support a direct-mapped 1769 * physical to virtual region can return the appropriate address 1770 * within that region, leaving '*virt' unchanged. Other 1771 * architectures should map the pages starting at '*virt' and 1772 * update '*virt' with the first usable address after the mapped 1773 * region. 1774 */ 1775 static vm_offset_t 1776 __CONCAT(PMTYPE, map)(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, 1777 int prot) 1778 { 1779 vm_offset_t va, sva; 1780 vm_paddr_t superpage_offset; 1781 pd_entry_t newpde; 1782 1783 va = *virt; 1784 /* 1785 * Does the physical address range's size and alignment permit at 1786 * least one superpage mapping to be created? 1787 */ 1788 superpage_offset = start & PDRMASK; 1789 if ((end - start) - ((NBPDR - superpage_offset) & PDRMASK) >= NBPDR) { 1790 /* 1791 * Increase the starting virtual address so that its alignment 1792 * does not preclude the use of superpage mappings. 1793 */ 1794 if ((va & PDRMASK) < superpage_offset) 1795 va = (va & ~PDRMASK) + superpage_offset; 1796 else if ((va & PDRMASK) > superpage_offset) 1797 va = ((va + PDRMASK) & ~PDRMASK) + superpage_offset; 1798 } 1799 sva = va; 1800 while (start < end) { 1801 if ((start & PDRMASK) == 0 && end - start >= NBPDR && 1802 pseflag != 0) { 1803 KASSERT((va & PDRMASK) == 0, 1804 ("pmap_map: misaligned va %#x", va)); 1805 newpde = start | PG_PS | PG_RW | PG_V; 1806 pmap_kenter_pde(va, newpde); 1807 va += NBPDR; 1808 start += NBPDR; 1809 } else { 1810 pmap_kenter(va, start); 1811 va += PAGE_SIZE; 1812 start += PAGE_SIZE; 1813 } 1814 } 1815 pmap_invalidate_range_int(kernel_pmap, sva, va); 1816 *virt = va; 1817 return (sva); 1818 } 1819 1820 1821 /* 1822 * Add a list of wired pages to the kva 1823 * this routine is only used for temporary 1824 * kernel mappings that do not need to have 1825 * page modification or references recorded. 1826 * Note that old mappings are simply written 1827 * over. The page *must* be wired. 1828 * Note: SMP coherent. Uses a ranged shootdown IPI. 1829 */ 1830 static void 1831 __CONCAT(PMTYPE, qenter)(vm_offset_t sva, vm_page_t *ma, int count) 1832 { 1833 pt_entry_t *endpte, oldpte, pa, *pte; 1834 vm_page_t m; 1835 1836 oldpte = 0; 1837 pte = vtopte(sva); 1838 endpte = pte + count; 1839 while (pte < endpte) { 1840 m = *ma++; 1841 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(kernel_pmap, 1842 m->md.pat_mode, 0); 1843 if ((*pte & (PG_FRAME | PG_PTE_CACHE)) != pa) { 1844 oldpte |= *pte; 1845 #ifdef PMAP_PAE_COMP 1846 pte_store(pte, pa | pg_nx | PG_RW | PG_V); 1847 #else 1848 pte_store(pte, pa | PG_RW | PG_V); 1849 #endif 1850 } 1851 pte++; 1852 } 1853 if (__predict_false((oldpte & PG_V) != 0)) 1854 pmap_invalidate_range_int(kernel_pmap, sva, sva + count * 1855 PAGE_SIZE); 1856 } 1857 1858 /* 1859 * This routine tears out page mappings from the 1860 * kernel -- it is meant only for temporary mappings. 1861 * Note: SMP coherent. Uses a ranged shootdown IPI. 1862 */ 1863 static void 1864 __CONCAT(PMTYPE, qremove)(vm_offset_t sva, int count) 1865 { 1866 vm_offset_t va; 1867 1868 va = sva; 1869 while (count-- > 0) { 1870 pmap_kremove(va); 1871 va += PAGE_SIZE; 1872 } 1873 pmap_invalidate_range_int(kernel_pmap, sva, va); 1874 } 1875 1876 /*************************************************** 1877 * Page table page management routines..... 1878 ***************************************************/ 1879 /* 1880 * Schedule the specified unused page table page to be freed. Specifically, 1881 * add the page to the specified list of pages that will be released to the 1882 * physical memory manager after the TLB has been updated. 1883 */ 1884 static __inline void 1885 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free, 1886 boolean_t set_PG_ZERO) 1887 { 1888 1889 if (set_PG_ZERO) 1890 m->flags |= PG_ZERO; 1891 else 1892 m->flags &= ~PG_ZERO; 1893 SLIST_INSERT_HEAD(free, m, plinks.s.ss); 1894 } 1895 1896 /* 1897 * Inserts the specified page table page into the specified pmap's collection 1898 * of idle page table pages. Each of a pmap's page table pages is responsible 1899 * for mapping a distinct range of virtual addresses. The pmap's collection is 1900 * ordered by this virtual address range. 1901 */ 1902 static __inline int 1903 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte) 1904 { 1905 1906 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1907 return (vm_radix_insert(&pmap->pm_root, mpte)); 1908 } 1909 1910 /* 1911 * Removes the page table page mapping the specified virtual address from the 1912 * specified pmap's collection of idle page table pages, and returns it. 1913 * Otherwise, returns NULL if there is no page table page corresponding to the 1914 * specified virtual address. 1915 */ 1916 static __inline vm_page_t 1917 pmap_remove_pt_page(pmap_t pmap, vm_offset_t va) 1918 { 1919 1920 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1921 return (vm_radix_remove(&pmap->pm_root, va >> PDRSHIFT)); 1922 } 1923 1924 /* 1925 * Decrements a page table page's wire count, which is used to record the 1926 * number of valid page table entries within the page. If the wire count 1927 * drops to zero, then the page table page is unmapped. Returns TRUE if the 1928 * page table page was unmapped and FALSE otherwise. 1929 */ 1930 static inline boolean_t 1931 pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free) 1932 { 1933 1934 --m->wire_count; 1935 if (m->wire_count == 0) { 1936 _pmap_unwire_ptp(pmap, m, free); 1937 return (TRUE); 1938 } else 1939 return (FALSE); 1940 } 1941 1942 static void 1943 _pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free) 1944 { 1945 1946 /* 1947 * unmap the page table page 1948 */ 1949 pmap->pm_pdir[m->pindex] = 0; 1950 --pmap->pm_stats.resident_count; 1951 1952 /* 1953 * There is not need to invalidate the recursive mapping since 1954 * we never instantiate such mapping for the usermode pmaps, 1955 * and never remove page table pages from the kernel pmap. 1956 * Put page on a list so that it is released since all TLB 1957 * shootdown is done. 1958 */ 1959 MPASS(pmap != kernel_pmap); 1960 pmap_add_delayed_free_list(m, free, TRUE); 1961 } 1962 1963 /* 1964 * After removing a page table entry, this routine is used to 1965 * conditionally free the page, and manage the hold/wire counts. 1966 */ 1967 static int 1968 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, struct spglist *free) 1969 { 1970 pd_entry_t ptepde; 1971 vm_page_t mpte; 1972 1973 if (pmap == kernel_pmap) 1974 return (0); 1975 ptepde = *pmap_pde(pmap, va); 1976 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME); 1977 return (pmap_unwire_ptp(pmap, mpte, free)); 1978 } 1979 1980 /* 1981 * Initialize the pmap for the swapper process. 1982 */ 1983 static void 1984 __CONCAT(PMTYPE, pinit0)(pmap_t pmap) 1985 { 1986 1987 PMAP_LOCK_INIT(pmap); 1988 pmap->pm_pdir = IdlePTD; 1989 #ifdef PMAP_PAE_COMP 1990 pmap->pm_pdpt = IdlePDPT; 1991 #endif 1992 pmap->pm_root.rt_root = 0; 1993 CPU_ZERO(&pmap->pm_active); 1994 TAILQ_INIT(&pmap->pm_pvchunk); 1995 bzero(&pmap->pm_stats, sizeof pmap->pm_stats); 1996 pmap_activate_boot(pmap); 1997 } 1998 1999 /* 2000 * Initialize a preallocated and zeroed pmap structure, 2001 * such as one in a vmspace structure. 2002 */ 2003 static int 2004 __CONCAT(PMTYPE, pinit)(pmap_t pmap) 2005 { 2006 vm_page_t m; 2007 int i; 2008 2009 /* 2010 * No need to allocate page table space yet but we do need a valid 2011 * page directory table. 2012 */ 2013 if (pmap->pm_pdir == NULL) { 2014 pmap->pm_pdir = (pd_entry_t *)kva_alloc(NBPTD); 2015 if (pmap->pm_pdir == NULL) 2016 return (0); 2017 #ifdef PMAP_PAE_COMP 2018 pmap->pm_pdpt = uma_zalloc(pdptzone, M_WAITOK | M_ZERO); 2019 KASSERT(((vm_offset_t)pmap->pm_pdpt & 2020 ((NPGPTD * sizeof(pdpt_entry_t)) - 1)) == 0, 2021 ("pmap_pinit: pdpt misaligned")); 2022 KASSERT(pmap_kextract((vm_offset_t)pmap->pm_pdpt) < (4ULL<<30), 2023 ("pmap_pinit: pdpt above 4g")); 2024 #endif 2025 pmap->pm_root.rt_root = 0; 2026 } 2027 KASSERT(vm_radix_is_empty(&pmap->pm_root), 2028 ("pmap_pinit: pmap has reserved page table page(s)")); 2029 2030 /* 2031 * allocate the page directory page(s) 2032 */ 2033 for (i = 0; i < NPGPTD; i++) { 2034 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ | 2035 VM_ALLOC_WIRED | VM_ALLOC_ZERO | VM_ALLOC_WAITOK); 2036 pmap->pm_ptdpg[i] = m; 2037 #ifdef PMAP_PAE_COMP 2038 pmap->pm_pdpt[i] = VM_PAGE_TO_PHYS(m) | PG_V; 2039 #endif 2040 } 2041 2042 pmap_qenter((vm_offset_t)pmap->pm_pdir, pmap->pm_ptdpg, NPGPTD); 2043 2044 for (i = 0; i < NPGPTD; i++) 2045 if ((pmap->pm_ptdpg[i]->flags & PG_ZERO) == 0) 2046 pagezero(pmap->pm_pdir + (i * NPDEPG)); 2047 2048 /* Install the trampoline mapping. */ 2049 pmap->pm_pdir[TRPTDI] = PTD[TRPTDI]; 2050 2051 CPU_ZERO(&pmap->pm_active); 2052 TAILQ_INIT(&pmap->pm_pvchunk); 2053 bzero(&pmap->pm_stats, sizeof pmap->pm_stats); 2054 2055 return (1); 2056 } 2057 2058 /* 2059 * this routine is called if the page table page is not 2060 * mapped correctly. 2061 */ 2062 static vm_page_t 2063 _pmap_allocpte(pmap_t pmap, u_int ptepindex, u_int flags) 2064 { 2065 vm_paddr_t ptepa; 2066 vm_page_t m; 2067 2068 /* 2069 * Allocate a page table page. 2070 */ 2071 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ | 2072 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) { 2073 if ((flags & PMAP_ENTER_NOSLEEP) == 0) { 2074 PMAP_UNLOCK(pmap); 2075 rw_wunlock(&pvh_global_lock); 2076 vm_wait(NULL); 2077 rw_wlock(&pvh_global_lock); 2078 PMAP_LOCK(pmap); 2079 } 2080 2081 /* 2082 * Indicate the need to retry. While waiting, the page table 2083 * page may have been allocated. 2084 */ 2085 return (NULL); 2086 } 2087 if ((m->flags & PG_ZERO) == 0) 2088 pmap_zero_page(m); 2089 2090 /* 2091 * Map the pagetable page into the process address space, if 2092 * it isn't already there. 2093 */ 2094 2095 pmap->pm_stats.resident_count++; 2096 2097 ptepa = VM_PAGE_TO_PHYS(m); 2098 pmap->pm_pdir[ptepindex] = 2099 (pd_entry_t) (ptepa | PG_U | PG_RW | PG_V | PG_A | PG_M); 2100 2101 return (m); 2102 } 2103 2104 static vm_page_t 2105 pmap_allocpte(pmap_t pmap, vm_offset_t va, u_int flags) 2106 { 2107 u_int ptepindex; 2108 pd_entry_t ptepa; 2109 vm_page_t m; 2110 2111 /* 2112 * Calculate pagetable page index 2113 */ 2114 ptepindex = va >> PDRSHIFT; 2115 retry: 2116 /* 2117 * Get the page directory entry 2118 */ 2119 ptepa = pmap->pm_pdir[ptepindex]; 2120 2121 /* 2122 * This supports switching from a 4MB page to a 2123 * normal 4K page. 2124 */ 2125 if (ptepa & PG_PS) { 2126 (void)pmap_demote_pde(pmap, &pmap->pm_pdir[ptepindex], va); 2127 ptepa = pmap->pm_pdir[ptepindex]; 2128 } 2129 2130 /* 2131 * If the page table page is mapped, we just increment the 2132 * hold count, and activate it. 2133 */ 2134 if (ptepa) { 2135 m = PHYS_TO_VM_PAGE(ptepa & PG_FRAME); 2136 m->wire_count++; 2137 } else { 2138 /* 2139 * Here if the pte page isn't mapped, or if it has 2140 * been deallocated. 2141 */ 2142 m = _pmap_allocpte(pmap, ptepindex, flags); 2143 if (m == NULL && (flags & PMAP_ENTER_NOSLEEP) == 0) 2144 goto retry; 2145 } 2146 return (m); 2147 } 2148 2149 2150 /*************************************************** 2151 * Pmap allocation/deallocation routines. 2152 ***************************************************/ 2153 2154 /* 2155 * Release any resources held by the given physical map. 2156 * Called when a pmap initialized by pmap_pinit is being released. 2157 * Should only be called if the map contains no valid mappings. 2158 */ 2159 static void 2160 __CONCAT(PMTYPE, release)(pmap_t pmap) 2161 { 2162 vm_page_t m; 2163 int i; 2164 2165 KASSERT(pmap->pm_stats.resident_count == 0, 2166 ("pmap_release: pmap resident count %ld != 0", 2167 pmap->pm_stats.resident_count)); 2168 KASSERT(vm_radix_is_empty(&pmap->pm_root), 2169 ("pmap_release: pmap has reserved page table page(s)")); 2170 KASSERT(CPU_EMPTY(&pmap->pm_active), 2171 ("releasing active pmap %p", pmap)); 2172 2173 pmap_qremove((vm_offset_t)pmap->pm_pdir, NPGPTD); 2174 2175 for (i = 0; i < NPGPTD; i++) { 2176 m = pmap->pm_ptdpg[i]; 2177 #ifdef PMAP_PAE_COMP 2178 KASSERT(VM_PAGE_TO_PHYS(m) == (pmap->pm_pdpt[i] & PG_FRAME), 2179 ("pmap_release: got wrong ptd page")); 2180 #endif 2181 vm_page_unwire_noq(m); 2182 vm_page_free(m); 2183 } 2184 } 2185 2186 /* 2187 * grow the number of kernel page table entries, if needed 2188 */ 2189 static void 2190 __CONCAT(PMTYPE, growkernel)(vm_offset_t addr) 2191 { 2192 vm_paddr_t ptppaddr; 2193 vm_page_t nkpg; 2194 pd_entry_t newpdir; 2195 2196 mtx_assert(&kernel_map->system_mtx, MA_OWNED); 2197 addr = roundup2(addr, NBPDR); 2198 if (addr - 1 >= vm_map_max(kernel_map)) 2199 addr = vm_map_max(kernel_map); 2200 while (kernel_vm_end < addr) { 2201 if (pdir_pde(PTD, kernel_vm_end)) { 2202 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK; 2203 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) { 2204 kernel_vm_end = vm_map_max(kernel_map); 2205 break; 2206 } 2207 continue; 2208 } 2209 2210 nkpg = vm_page_alloc(NULL, kernel_vm_end >> PDRSHIFT, 2211 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | 2212 VM_ALLOC_ZERO); 2213 if (nkpg == NULL) 2214 panic("pmap_growkernel: no memory to grow kernel"); 2215 2216 nkpt++; 2217 2218 if ((nkpg->flags & PG_ZERO) == 0) 2219 pmap_zero_page(nkpg); 2220 ptppaddr = VM_PAGE_TO_PHYS(nkpg); 2221 newpdir = (pd_entry_t) (ptppaddr | PG_V | PG_RW | PG_A | PG_M); 2222 pdir_pde(KPTD, kernel_vm_end) = newpdir; 2223 2224 pmap_kenter_pde(kernel_vm_end, newpdir); 2225 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK; 2226 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) { 2227 kernel_vm_end = vm_map_max(kernel_map); 2228 break; 2229 } 2230 } 2231 } 2232 2233 2234 /*************************************************** 2235 * page management routines. 2236 ***************************************************/ 2237 2238 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE); 2239 CTASSERT(_NPCM == 11); 2240 CTASSERT(_NPCPV == 336); 2241 2242 static __inline struct pv_chunk * 2243 pv_to_chunk(pv_entry_t pv) 2244 { 2245 2246 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK)); 2247 } 2248 2249 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap) 2250 2251 #define PC_FREE0_9 0xfffffffful /* Free values for index 0 through 9 */ 2252 #define PC_FREE10 0x0000fffful /* Free values for index 10 */ 2253 2254 static const uint32_t pc_freemask[_NPCM] = { 2255 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9, 2256 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9, 2257 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9, 2258 PC_FREE0_9, PC_FREE10 2259 }; 2260 2261 #ifdef PV_STATS 2262 extern int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail; 2263 extern long pv_entry_frees, pv_entry_allocs; 2264 extern int pv_entry_spare; 2265 #endif 2266 2267 /* 2268 * We are in a serious low memory condition. Resort to 2269 * drastic measures to free some pages so we can allocate 2270 * another pv entry chunk. 2271 */ 2272 static vm_page_t 2273 pmap_pv_reclaim(pmap_t locked_pmap) 2274 { 2275 struct pch newtail; 2276 struct pv_chunk *pc; 2277 struct md_page *pvh; 2278 pd_entry_t *pde; 2279 pmap_t pmap; 2280 pt_entry_t *pte, tpte; 2281 pv_entry_t pv; 2282 vm_offset_t va; 2283 vm_page_t m, m_pc; 2284 struct spglist free; 2285 uint32_t inuse; 2286 int bit, field, freed; 2287 2288 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED); 2289 pmap = NULL; 2290 m_pc = NULL; 2291 SLIST_INIT(&free); 2292 TAILQ_INIT(&newtail); 2293 while ((pc = TAILQ_FIRST(&pv_chunks)) != NULL && (pv_vafree == 0 || 2294 SLIST_EMPTY(&free))) { 2295 TAILQ_REMOVE(&pv_chunks, pc, pc_lru); 2296 if (pmap != pc->pc_pmap) { 2297 if (pmap != NULL) { 2298 pmap_invalidate_all_int(pmap); 2299 if (pmap != locked_pmap) 2300 PMAP_UNLOCK(pmap); 2301 } 2302 pmap = pc->pc_pmap; 2303 /* Avoid deadlock and lock recursion. */ 2304 if (pmap > locked_pmap) 2305 PMAP_LOCK(pmap); 2306 else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap)) { 2307 pmap = NULL; 2308 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru); 2309 continue; 2310 } 2311 } 2312 2313 /* 2314 * Destroy every non-wired, 4 KB page mapping in the chunk. 2315 */ 2316 freed = 0; 2317 for (field = 0; field < _NPCM; field++) { 2318 for (inuse = ~pc->pc_map[field] & pc_freemask[field]; 2319 inuse != 0; inuse &= ~(1UL << bit)) { 2320 bit = bsfl(inuse); 2321 pv = &pc->pc_pventry[field * 32 + bit]; 2322 va = pv->pv_va; 2323 pde = pmap_pde(pmap, va); 2324 if ((*pde & PG_PS) != 0) 2325 continue; 2326 pte = __CONCAT(PMTYPE, pte)(pmap, va); 2327 tpte = *pte; 2328 if ((tpte & PG_W) == 0) 2329 tpte = pte_load_clear(pte); 2330 pmap_pte_release(pte); 2331 if ((tpte & PG_W) != 0) 2332 continue; 2333 KASSERT(tpte != 0, 2334 ("pmap_pv_reclaim: pmap %p va %x zero pte", 2335 pmap, va)); 2336 if ((tpte & PG_G) != 0) 2337 pmap_invalidate_page_int(pmap, va); 2338 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME); 2339 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 2340 vm_page_dirty(m); 2341 if ((tpte & PG_A) != 0) 2342 vm_page_aflag_set(m, PGA_REFERENCED); 2343 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next); 2344 if (TAILQ_EMPTY(&m->md.pv_list) && 2345 (m->flags & PG_FICTITIOUS) == 0) { 2346 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 2347 if (TAILQ_EMPTY(&pvh->pv_list)) { 2348 vm_page_aflag_clear(m, 2349 PGA_WRITEABLE); 2350 } 2351 } 2352 pc->pc_map[field] |= 1UL << bit; 2353 pmap_unuse_pt(pmap, va, &free); 2354 freed++; 2355 } 2356 } 2357 if (freed == 0) { 2358 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru); 2359 continue; 2360 } 2361 /* Every freed mapping is for a 4 KB page. */ 2362 pmap->pm_stats.resident_count -= freed; 2363 PV_STAT(pv_entry_frees += freed); 2364 PV_STAT(pv_entry_spare += freed); 2365 pv_entry_count -= freed; 2366 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2367 for (field = 0; field < _NPCM; field++) 2368 if (pc->pc_map[field] != pc_freemask[field]) { 2369 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, 2370 pc_list); 2371 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru); 2372 2373 /* 2374 * One freed pv entry in locked_pmap is 2375 * sufficient. 2376 */ 2377 if (pmap == locked_pmap) 2378 goto out; 2379 break; 2380 } 2381 if (field == _NPCM) { 2382 PV_STAT(pv_entry_spare -= _NPCPV); 2383 PV_STAT(pc_chunk_count--); 2384 PV_STAT(pc_chunk_frees++); 2385 /* Entire chunk is free; return it. */ 2386 m_pc = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc)); 2387 pmap_qremove((vm_offset_t)pc, 1); 2388 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc); 2389 break; 2390 } 2391 } 2392 out: 2393 TAILQ_CONCAT(&pv_chunks, &newtail, pc_lru); 2394 if (pmap != NULL) { 2395 pmap_invalidate_all_int(pmap); 2396 if (pmap != locked_pmap) 2397 PMAP_UNLOCK(pmap); 2398 } 2399 if (m_pc == NULL && pv_vafree != 0 && SLIST_EMPTY(&free)) { 2400 m_pc = SLIST_FIRST(&free); 2401 SLIST_REMOVE_HEAD(&free, plinks.s.ss); 2402 /* Recycle a freed page table page. */ 2403 m_pc->wire_count = 1; 2404 } 2405 vm_page_free_pages_toq(&free, true); 2406 return (m_pc); 2407 } 2408 2409 /* 2410 * free the pv_entry back to the free list 2411 */ 2412 static void 2413 free_pv_entry(pmap_t pmap, pv_entry_t pv) 2414 { 2415 struct pv_chunk *pc; 2416 int idx, field, bit; 2417 2418 rw_assert(&pvh_global_lock, RA_WLOCKED); 2419 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2420 PV_STAT(pv_entry_frees++); 2421 PV_STAT(pv_entry_spare++); 2422 pv_entry_count--; 2423 pc = pv_to_chunk(pv); 2424 idx = pv - &pc->pc_pventry[0]; 2425 field = idx / 32; 2426 bit = idx % 32; 2427 pc->pc_map[field] |= 1ul << bit; 2428 for (idx = 0; idx < _NPCM; idx++) 2429 if (pc->pc_map[idx] != pc_freemask[idx]) { 2430 /* 2431 * 98% of the time, pc is already at the head of the 2432 * list. If it isn't already, move it to the head. 2433 */ 2434 if (__predict_false(TAILQ_FIRST(&pmap->pm_pvchunk) != 2435 pc)) { 2436 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2437 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, 2438 pc_list); 2439 } 2440 return; 2441 } 2442 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2443 free_pv_chunk(pc); 2444 } 2445 2446 static void 2447 free_pv_chunk(struct pv_chunk *pc) 2448 { 2449 vm_page_t m; 2450 2451 TAILQ_REMOVE(&pv_chunks, pc, pc_lru); 2452 PV_STAT(pv_entry_spare -= _NPCPV); 2453 PV_STAT(pc_chunk_count--); 2454 PV_STAT(pc_chunk_frees++); 2455 /* entire chunk is free, return it */ 2456 m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc)); 2457 pmap_qremove((vm_offset_t)pc, 1); 2458 vm_page_unwire(m, PQ_NONE); 2459 vm_page_free(m); 2460 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc); 2461 } 2462 2463 /* 2464 * get a new pv_entry, allocating a block from the system 2465 * when needed. 2466 */ 2467 static pv_entry_t 2468 get_pv_entry(pmap_t pmap, boolean_t try) 2469 { 2470 static const struct timeval printinterval = { 60, 0 }; 2471 static struct timeval lastprint; 2472 int bit, field; 2473 pv_entry_t pv; 2474 struct pv_chunk *pc; 2475 vm_page_t m; 2476 2477 rw_assert(&pvh_global_lock, RA_WLOCKED); 2478 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2479 PV_STAT(pv_entry_allocs++); 2480 pv_entry_count++; 2481 if (pv_entry_count > pv_entry_high_water) 2482 if (ratecheck(&lastprint, &printinterval)) 2483 printf("Approaching the limit on PV entries, consider " 2484 "increasing either the vm.pmap.shpgperproc or the " 2485 "vm.pmap.pv_entries tunable.\n"); 2486 retry: 2487 pc = TAILQ_FIRST(&pmap->pm_pvchunk); 2488 if (pc != NULL) { 2489 for (field = 0; field < _NPCM; field++) { 2490 if (pc->pc_map[field]) { 2491 bit = bsfl(pc->pc_map[field]); 2492 break; 2493 } 2494 } 2495 if (field < _NPCM) { 2496 pv = &pc->pc_pventry[field * 32 + bit]; 2497 pc->pc_map[field] &= ~(1ul << bit); 2498 /* If this was the last item, move it to tail */ 2499 for (field = 0; field < _NPCM; field++) 2500 if (pc->pc_map[field] != 0) { 2501 PV_STAT(pv_entry_spare--); 2502 return (pv); /* not full, return */ 2503 } 2504 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2505 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list); 2506 PV_STAT(pv_entry_spare--); 2507 return (pv); 2508 } 2509 } 2510 /* 2511 * Access to the ptelist "pv_vafree" is synchronized by the pvh 2512 * global lock. If "pv_vafree" is currently non-empty, it will 2513 * remain non-empty until pmap_ptelist_alloc() completes. 2514 */ 2515 if (pv_vafree == 0 || (m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | 2516 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) { 2517 if (try) { 2518 pv_entry_count--; 2519 PV_STAT(pc_chunk_tryfail++); 2520 return (NULL); 2521 } 2522 m = pmap_pv_reclaim(pmap); 2523 if (m == NULL) 2524 goto retry; 2525 } 2526 PV_STAT(pc_chunk_count++); 2527 PV_STAT(pc_chunk_allocs++); 2528 pc = (struct pv_chunk *)pmap_ptelist_alloc(&pv_vafree); 2529 pmap_qenter((vm_offset_t)pc, &m, 1); 2530 pc->pc_pmap = pmap; 2531 pc->pc_map[0] = pc_freemask[0] & ~1ul; /* preallocated bit 0 */ 2532 for (field = 1; field < _NPCM; field++) 2533 pc->pc_map[field] = pc_freemask[field]; 2534 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru); 2535 pv = &pc->pc_pventry[0]; 2536 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list); 2537 PV_STAT(pv_entry_spare += _NPCPV - 1); 2538 return (pv); 2539 } 2540 2541 static __inline pv_entry_t 2542 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va) 2543 { 2544 pv_entry_t pv; 2545 2546 rw_assert(&pvh_global_lock, RA_WLOCKED); 2547 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) { 2548 if (pmap == PV_PMAP(pv) && va == pv->pv_va) { 2549 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next); 2550 break; 2551 } 2552 } 2553 return (pv); 2554 } 2555 2556 static void 2557 pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa) 2558 { 2559 struct md_page *pvh; 2560 pv_entry_t pv; 2561 vm_offset_t va_last; 2562 vm_page_t m; 2563 2564 rw_assert(&pvh_global_lock, RA_WLOCKED); 2565 KASSERT((pa & PDRMASK) == 0, 2566 ("pmap_pv_demote_pde: pa is not 4mpage aligned")); 2567 2568 /* 2569 * Transfer the 4mpage's pv entry for this mapping to the first 2570 * page's pv list. 2571 */ 2572 pvh = pa_to_pvh(pa); 2573 va = trunc_4mpage(va); 2574 pv = pmap_pvh_remove(pvh, pmap, va); 2575 KASSERT(pv != NULL, ("pmap_pv_demote_pde: pv not found")); 2576 m = PHYS_TO_VM_PAGE(pa); 2577 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next); 2578 /* Instantiate the remaining NPTEPG - 1 pv entries. */ 2579 va_last = va + NBPDR - PAGE_SIZE; 2580 do { 2581 m++; 2582 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2583 ("pmap_pv_demote_pde: page %p is not managed", m)); 2584 va += PAGE_SIZE; 2585 pmap_insert_entry(pmap, va, m); 2586 } while (va < va_last); 2587 } 2588 2589 #if VM_NRESERVLEVEL > 0 2590 static void 2591 pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa) 2592 { 2593 struct md_page *pvh; 2594 pv_entry_t pv; 2595 vm_offset_t va_last; 2596 vm_page_t m; 2597 2598 rw_assert(&pvh_global_lock, RA_WLOCKED); 2599 KASSERT((pa & PDRMASK) == 0, 2600 ("pmap_pv_promote_pde: pa is not 4mpage aligned")); 2601 2602 /* 2603 * Transfer the first page's pv entry for this mapping to the 2604 * 4mpage's pv list. Aside from avoiding the cost of a call 2605 * to get_pv_entry(), a transfer avoids the possibility that 2606 * get_pv_entry() calls pmap_collect() and that pmap_collect() 2607 * removes one of the mappings that is being promoted. 2608 */ 2609 m = PHYS_TO_VM_PAGE(pa); 2610 va = trunc_4mpage(va); 2611 pv = pmap_pvh_remove(&m->md, pmap, va); 2612 KASSERT(pv != NULL, ("pmap_pv_promote_pde: pv not found")); 2613 pvh = pa_to_pvh(pa); 2614 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next); 2615 /* Free the remaining NPTEPG - 1 pv entries. */ 2616 va_last = va + NBPDR - PAGE_SIZE; 2617 do { 2618 m++; 2619 va += PAGE_SIZE; 2620 pmap_pvh_free(&m->md, pmap, va); 2621 } while (va < va_last); 2622 } 2623 #endif /* VM_NRESERVLEVEL > 0 */ 2624 2625 static void 2626 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va) 2627 { 2628 pv_entry_t pv; 2629 2630 pv = pmap_pvh_remove(pvh, pmap, va); 2631 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found")); 2632 free_pv_entry(pmap, pv); 2633 } 2634 2635 static void 2636 pmap_remove_entry(pmap_t pmap, vm_page_t m, vm_offset_t va) 2637 { 2638 struct md_page *pvh; 2639 2640 rw_assert(&pvh_global_lock, RA_WLOCKED); 2641 pmap_pvh_free(&m->md, pmap, va); 2642 if (TAILQ_EMPTY(&m->md.pv_list) && (m->flags & PG_FICTITIOUS) == 0) { 2643 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 2644 if (TAILQ_EMPTY(&pvh->pv_list)) 2645 vm_page_aflag_clear(m, PGA_WRITEABLE); 2646 } 2647 } 2648 2649 /* 2650 * Create a pv entry for page at pa for 2651 * (pmap, va). 2652 */ 2653 static void 2654 pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m) 2655 { 2656 pv_entry_t pv; 2657 2658 rw_assert(&pvh_global_lock, RA_WLOCKED); 2659 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2660 pv = get_pv_entry(pmap, FALSE); 2661 pv->pv_va = va; 2662 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next); 2663 } 2664 2665 /* 2666 * Conditionally create a pv entry. 2667 */ 2668 static boolean_t 2669 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m) 2670 { 2671 pv_entry_t pv; 2672 2673 rw_assert(&pvh_global_lock, RA_WLOCKED); 2674 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2675 if (pv_entry_count < pv_entry_high_water && 2676 (pv = get_pv_entry(pmap, TRUE)) != NULL) { 2677 pv->pv_va = va; 2678 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next); 2679 return (TRUE); 2680 } else 2681 return (FALSE); 2682 } 2683 2684 /* 2685 * Create the pv entries for each of the pages within a superpage. 2686 */ 2687 static bool 2688 pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, pd_entry_t pde, u_int flags) 2689 { 2690 struct md_page *pvh; 2691 pv_entry_t pv; 2692 bool noreclaim; 2693 2694 rw_assert(&pvh_global_lock, RA_WLOCKED); 2695 noreclaim = (flags & PMAP_ENTER_NORECLAIM) != 0; 2696 if ((noreclaim && pv_entry_count >= pv_entry_high_water) || 2697 (pv = get_pv_entry(pmap, noreclaim)) == NULL) 2698 return (false); 2699 pv->pv_va = va; 2700 pvh = pa_to_pvh(pde & PG_PS_FRAME); 2701 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next); 2702 return (true); 2703 } 2704 2705 /* 2706 * Fills a page table page with mappings to consecutive physical pages. 2707 */ 2708 static void 2709 pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte) 2710 { 2711 pt_entry_t *pte; 2712 2713 for (pte = firstpte; pte < firstpte + NPTEPG; pte++) { 2714 *pte = newpte; 2715 newpte += PAGE_SIZE; 2716 } 2717 } 2718 2719 /* 2720 * Tries to demote a 2- or 4MB page mapping. If demotion fails, the 2721 * 2- or 4MB page mapping is invalidated. 2722 */ 2723 static boolean_t 2724 pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va) 2725 { 2726 pd_entry_t newpde, oldpde; 2727 pt_entry_t *firstpte, newpte; 2728 vm_paddr_t mptepa; 2729 vm_page_t mpte; 2730 struct spglist free; 2731 vm_offset_t sva; 2732 2733 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2734 oldpde = *pde; 2735 KASSERT((oldpde & (PG_PS | PG_V)) == (PG_PS | PG_V), 2736 ("pmap_demote_pde: oldpde is missing PG_PS and/or PG_V")); 2737 if ((oldpde & PG_A) == 0 || (mpte = pmap_remove_pt_page(pmap, va)) == 2738 NULL) { 2739 KASSERT((oldpde & PG_W) == 0, 2740 ("pmap_demote_pde: page table page for a wired mapping" 2741 " is missing")); 2742 2743 /* 2744 * Invalidate the 2- or 4MB page mapping and return 2745 * "failure" if the mapping was never accessed or the 2746 * allocation of the new page table page fails. 2747 */ 2748 if ((oldpde & PG_A) == 0 || (mpte = vm_page_alloc(NULL, 2749 va >> PDRSHIFT, VM_ALLOC_NOOBJ | VM_ALLOC_NORMAL | 2750 VM_ALLOC_WIRED)) == NULL) { 2751 SLIST_INIT(&free); 2752 sva = trunc_4mpage(va); 2753 pmap_remove_pde(pmap, pde, sva, &free); 2754 if ((oldpde & PG_G) == 0) 2755 pmap_invalidate_pde_page(pmap, sva, oldpde); 2756 vm_page_free_pages_toq(&free, true); 2757 CTR2(KTR_PMAP, "pmap_demote_pde: failure for va %#x" 2758 " in pmap %p", va, pmap); 2759 return (FALSE); 2760 } 2761 if (pmap != kernel_pmap) 2762 pmap->pm_stats.resident_count++; 2763 } 2764 mptepa = VM_PAGE_TO_PHYS(mpte); 2765 2766 /* 2767 * If the page mapping is in the kernel's address space, then the 2768 * KPTmap can provide access to the page table page. Otherwise, 2769 * temporarily map the page table page (mpte) into the kernel's 2770 * address space at either PADDR1 or PADDR2. 2771 */ 2772 if (pmap == kernel_pmap) 2773 firstpte = &KPTmap[i386_btop(trunc_4mpage(va))]; 2774 else if (curthread->td_pinned > 0 && rw_wowned(&pvh_global_lock)) { 2775 if ((*PMAP1 & PG_FRAME) != mptepa) { 2776 *PMAP1 = mptepa | PG_RW | PG_V | PG_A | PG_M; 2777 #ifdef SMP 2778 PMAP1cpu = PCPU_GET(cpuid); 2779 #endif 2780 invlcaddr(PADDR1); 2781 PMAP1changed++; 2782 } else 2783 #ifdef SMP 2784 if (PMAP1cpu != PCPU_GET(cpuid)) { 2785 PMAP1cpu = PCPU_GET(cpuid); 2786 invlcaddr(PADDR1); 2787 PMAP1changedcpu++; 2788 } else 2789 #endif 2790 PMAP1unchanged++; 2791 firstpte = PADDR1; 2792 } else { 2793 mtx_lock(&PMAP2mutex); 2794 if ((*PMAP2 & PG_FRAME) != mptepa) { 2795 *PMAP2 = mptepa | PG_RW | PG_V | PG_A | PG_M; 2796 pmap_invalidate_page_int(kernel_pmap, 2797 (vm_offset_t)PADDR2); 2798 } 2799 firstpte = PADDR2; 2800 } 2801 newpde = mptepa | PG_M | PG_A | (oldpde & PG_U) | PG_RW | PG_V; 2802 KASSERT((oldpde & PG_A) != 0, 2803 ("pmap_demote_pde: oldpde is missing PG_A")); 2804 KASSERT((oldpde & (PG_M | PG_RW)) != PG_RW, 2805 ("pmap_demote_pde: oldpde is missing PG_M")); 2806 newpte = oldpde & ~PG_PS; 2807 if ((newpte & PG_PDE_PAT) != 0) 2808 newpte ^= PG_PDE_PAT | PG_PTE_PAT; 2809 2810 /* 2811 * If the page table page is new, initialize it. 2812 */ 2813 if (mpte->wire_count == 1) { 2814 mpte->wire_count = NPTEPG; 2815 pmap_fill_ptp(firstpte, newpte); 2816 } 2817 KASSERT((*firstpte & PG_FRAME) == (newpte & PG_FRAME), 2818 ("pmap_demote_pde: firstpte and newpte map different physical" 2819 " addresses")); 2820 2821 /* 2822 * If the mapping has changed attributes, update the page table 2823 * entries. 2824 */ 2825 if ((*firstpte & PG_PTE_PROMOTE) != (newpte & PG_PTE_PROMOTE)) 2826 pmap_fill_ptp(firstpte, newpte); 2827 2828 /* 2829 * Demote the mapping. This pmap is locked. The old PDE has 2830 * PG_A set. If the old PDE has PG_RW set, it also has PG_M 2831 * set. Thus, there is no danger of a race with another 2832 * processor changing the setting of PG_A and/or PG_M between 2833 * the read above and the store below. 2834 */ 2835 if (workaround_erratum383) 2836 pmap_update_pde(pmap, va, pde, newpde); 2837 else if (pmap == kernel_pmap) 2838 pmap_kenter_pde(va, newpde); 2839 else 2840 pde_store(pde, newpde); 2841 if (firstpte == PADDR2) 2842 mtx_unlock(&PMAP2mutex); 2843 2844 /* 2845 * Invalidate the recursive mapping of the page table page. 2846 */ 2847 pmap_invalidate_page_int(pmap, (vm_offset_t)vtopte(va)); 2848 2849 /* 2850 * Demote the pv entry. This depends on the earlier demotion 2851 * of the mapping. Specifically, the (re)creation of a per- 2852 * page pv entry might trigger the execution of pmap_collect(), 2853 * which might reclaim a newly (re)created per-page pv entry 2854 * and destroy the associated mapping. In order to destroy 2855 * the mapping, the PDE must have already changed from mapping 2856 * the 2mpage to referencing the page table page. 2857 */ 2858 if ((oldpde & PG_MANAGED) != 0) 2859 pmap_pv_demote_pde(pmap, va, oldpde & PG_PS_FRAME); 2860 2861 pmap_pde_demotions++; 2862 CTR2(KTR_PMAP, "pmap_demote_pde: success for va %#x" 2863 " in pmap %p", va, pmap); 2864 return (TRUE); 2865 } 2866 2867 /* 2868 * Removes a 2- or 4MB page mapping from the kernel pmap. 2869 */ 2870 static void 2871 pmap_remove_kernel_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va) 2872 { 2873 pd_entry_t newpde; 2874 vm_paddr_t mptepa; 2875 vm_page_t mpte; 2876 2877 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2878 mpte = pmap_remove_pt_page(pmap, va); 2879 if (mpte == NULL) 2880 panic("pmap_remove_kernel_pde: Missing pt page."); 2881 2882 mptepa = VM_PAGE_TO_PHYS(mpte); 2883 newpde = mptepa | PG_M | PG_A | PG_RW | PG_V; 2884 2885 /* 2886 * Initialize the page table page. 2887 */ 2888 pagezero((void *)&KPTmap[i386_btop(trunc_4mpage(va))]); 2889 2890 /* 2891 * Remove the mapping. 2892 */ 2893 if (workaround_erratum383) 2894 pmap_update_pde(pmap, va, pde, newpde); 2895 else 2896 pmap_kenter_pde(va, newpde); 2897 2898 /* 2899 * Invalidate the recursive mapping of the page table page. 2900 */ 2901 pmap_invalidate_page_int(pmap, (vm_offset_t)vtopte(va)); 2902 } 2903 2904 /* 2905 * pmap_remove_pde: do the things to unmap a superpage in a process 2906 */ 2907 static void 2908 pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva, 2909 struct spglist *free) 2910 { 2911 struct md_page *pvh; 2912 pd_entry_t oldpde; 2913 vm_offset_t eva, va; 2914 vm_page_t m, mpte; 2915 2916 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2917 KASSERT((sva & PDRMASK) == 0, 2918 ("pmap_remove_pde: sva is not 4mpage aligned")); 2919 oldpde = pte_load_clear(pdq); 2920 if (oldpde & PG_W) 2921 pmap->pm_stats.wired_count -= NBPDR / PAGE_SIZE; 2922 2923 /* 2924 * Machines that don't support invlpg, also don't support 2925 * PG_G. 2926 */ 2927 if ((oldpde & PG_G) != 0) 2928 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde); 2929 2930 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE; 2931 if (oldpde & PG_MANAGED) { 2932 pvh = pa_to_pvh(oldpde & PG_PS_FRAME); 2933 pmap_pvh_free(pvh, pmap, sva); 2934 eva = sva + NBPDR; 2935 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME); 2936 va < eva; va += PAGE_SIZE, m++) { 2937 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW)) 2938 vm_page_dirty(m); 2939 if (oldpde & PG_A) 2940 vm_page_aflag_set(m, PGA_REFERENCED); 2941 if (TAILQ_EMPTY(&m->md.pv_list) && 2942 TAILQ_EMPTY(&pvh->pv_list)) 2943 vm_page_aflag_clear(m, PGA_WRITEABLE); 2944 } 2945 } 2946 if (pmap == kernel_pmap) { 2947 pmap_remove_kernel_pde(pmap, pdq, sva); 2948 } else { 2949 mpte = pmap_remove_pt_page(pmap, sva); 2950 if (mpte != NULL) { 2951 pmap->pm_stats.resident_count--; 2952 KASSERT(mpte->wire_count == NPTEPG, 2953 ("pmap_remove_pde: pte page wire count error")); 2954 mpte->wire_count = 0; 2955 pmap_add_delayed_free_list(mpte, free, FALSE); 2956 } 2957 } 2958 } 2959 2960 /* 2961 * pmap_remove_pte: do the things to unmap a page in a process 2962 */ 2963 static int 2964 pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va, 2965 struct spglist *free) 2966 { 2967 pt_entry_t oldpte; 2968 vm_page_t m; 2969 2970 rw_assert(&pvh_global_lock, RA_WLOCKED); 2971 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2972 oldpte = pte_load_clear(ptq); 2973 KASSERT(oldpte != 0, 2974 ("pmap_remove_pte: pmap %p va %x zero pte", pmap, va)); 2975 if (oldpte & PG_W) 2976 pmap->pm_stats.wired_count -= 1; 2977 /* 2978 * Machines that don't support invlpg, also don't support 2979 * PG_G. 2980 */ 2981 if (oldpte & PG_G) 2982 pmap_invalidate_page_int(kernel_pmap, va); 2983 pmap->pm_stats.resident_count -= 1; 2984 if (oldpte & PG_MANAGED) { 2985 m = PHYS_TO_VM_PAGE(oldpte & PG_FRAME); 2986 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 2987 vm_page_dirty(m); 2988 if (oldpte & PG_A) 2989 vm_page_aflag_set(m, PGA_REFERENCED); 2990 pmap_remove_entry(pmap, m, va); 2991 } 2992 return (pmap_unuse_pt(pmap, va, free)); 2993 } 2994 2995 /* 2996 * Remove a single page from a process address space 2997 */ 2998 static void 2999 pmap_remove_page(pmap_t pmap, vm_offset_t va, struct spglist *free) 3000 { 3001 pt_entry_t *pte; 3002 3003 rw_assert(&pvh_global_lock, RA_WLOCKED); 3004 KASSERT(curthread->td_pinned > 0, ("curthread not pinned")); 3005 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 3006 if ((pte = pmap_pte_quick(pmap, va)) == NULL || *pte == 0) 3007 return; 3008 pmap_remove_pte(pmap, pte, va, free); 3009 pmap_invalidate_page_int(pmap, va); 3010 } 3011 3012 /* 3013 * Removes the specified range of addresses from the page table page. 3014 */ 3015 static bool 3016 pmap_remove_ptes(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, 3017 struct spglist *free) 3018 { 3019 pt_entry_t *pte; 3020 bool anyvalid; 3021 3022 rw_assert(&pvh_global_lock, RA_WLOCKED); 3023 KASSERT(curthread->td_pinned > 0, ("curthread not pinned")); 3024 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 3025 anyvalid = false; 3026 for (pte = pmap_pte_quick(pmap, sva); sva != eva; pte++, 3027 sva += PAGE_SIZE) { 3028 if (*pte == 0) 3029 continue; 3030 3031 /* 3032 * The TLB entry for a PG_G mapping is invalidated by 3033 * pmap_remove_pte(). 3034 */ 3035 if ((*pte & PG_G) == 0) 3036 anyvalid = true; 3037 3038 if (pmap_remove_pte(pmap, pte, sva, free)) 3039 break; 3040 } 3041 return (anyvalid); 3042 } 3043 3044 /* 3045 * Remove the given range of addresses from the specified map. 3046 * 3047 * It is assumed that the start and end are properly 3048 * rounded to the page size. 3049 */ 3050 static void 3051 __CONCAT(PMTYPE, remove)(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 3052 { 3053 vm_offset_t pdnxt; 3054 pd_entry_t ptpaddr; 3055 struct spglist free; 3056 int anyvalid; 3057 3058 /* 3059 * Perform an unsynchronized read. This is, however, safe. 3060 */ 3061 if (pmap->pm_stats.resident_count == 0) 3062 return; 3063 3064 anyvalid = 0; 3065 SLIST_INIT(&free); 3066 3067 rw_wlock(&pvh_global_lock); 3068 sched_pin(); 3069 PMAP_LOCK(pmap); 3070 3071 /* 3072 * special handling of removing one page. a very 3073 * common operation and easy to short circuit some 3074 * code. 3075 */ 3076 if ((sva + PAGE_SIZE == eva) && 3077 ((pmap->pm_pdir[(sva >> PDRSHIFT)] & PG_PS) == 0)) { 3078 pmap_remove_page(pmap, sva, &free); 3079 goto out; 3080 } 3081 3082 for (; sva < eva; sva = pdnxt) { 3083 u_int pdirindex; 3084 3085 /* 3086 * Calculate index for next page table. 3087 */ 3088 pdnxt = (sva + NBPDR) & ~PDRMASK; 3089 if (pdnxt < sva) 3090 pdnxt = eva; 3091 if (pmap->pm_stats.resident_count == 0) 3092 break; 3093 3094 pdirindex = sva >> PDRSHIFT; 3095 ptpaddr = pmap->pm_pdir[pdirindex]; 3096 3097 /* 3098 * Weed out invalid mappings. Note: we assume that the page 3099 * directory table is always allocated, and in kernel virtual. 3100 */ 3101 if (ptpaddr == 0) 3102 continue; 3103 3104 /* 3105 * Check for large page. 3106 */ 3107 if ((ptpaddr & PG_PS) != 0) { 3108 /* 3109 * Are we removing the entire large page? If not, 3110 * demote the mapping and fall through. 3111 */ 3112 if (sva + NBPDR == pdnxt && eva >= pdnxt) { 3113 /* 3114 * The TLB entry for a PG_G mapping is 3115 * invalidated by pmap_remove_pde(). 3116 */ 3117 if ((ptpaddr & PG_G) == 0) 3118 anyvalid = 1; 3119 pmap_remove_pde(pmap, 3120 &pmap->pm_pdir[pdirindex], sva, &free); 3121 continue; 3122 } else if (!pmap_demote_pde(pmap, 3123 &pmap->pm_pdir[pdirindex], sva)) { 3124 /* The large page mapping was destroyed. */ 3125 continue; 3126 } 3127 } 3128 3129 /* 3130 * Limit our scan to either the end of the va represented 3131 * by the current page table page, or to the end of the 3132 * range being removed. 3133 */ 3134 if (pdnxt > eva) 3135 pdnxt = eva; 3136 3137 if (pmap_remove_ptes(pmap, sva, pdnxt, &free)) 3138 anyvalid = 1; 3139 } 3140 out: 3141 sched_unpin(); 3142 if (anyvalid) 3143 pmap_invalidate_all_int(pmap); 3144 rw_wunlock(&pvh_global_lock); 3145 PMAP_UNLOCK(pmap); 3146 vm_page_free_pages_toq(&free, true); 3147 } 3148 3149 /* 3150 * Routine: pmap_remove_all 3151 * Function: 3152 * Removes this physical page from 3153 * all physical maps in which it resides. 3154 * Reflects back modify bits to the pager. 3155 * 3156 * Notes: 3157 * Original versions of this routine were very 3158 * inefficient because they iteratively called 3159 * pmap_remove (slow...) 3160 */ 3161 3162 static void 3163 __CONCAT(PMTYPE, remove_all)(vm_page_t m) 3164 { 3165 struct md_page *pvh; 3166 pv_entry_t pv; 3167 pmap_t pmap; 3168 pt_entry_t *pte, tpte; 3169 pd_entry_t *pde; 3170 vm_offset_t va; 3171 struct spglist free; 3172 3173 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 3174 ("pmap_remove_all: page %p is not managed", m)); 3175 SLIST_INIT(&free); 3176 rw_wlock(&pvh_global_lock); 3177 sched_pin(); 3178 if ((m->flags & PG_FICTITIOUS) != 0) 3179 goto small_mappings; 3180 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 3181 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) { 3182 va = pv->pv_va; 3183 pmap = PV_PMAP(pv); 3184 PMAP_LOCK(pmap); 3185 pde = pmap_pde(pmap, va); 3186 (void)pmap_demote_pde(pmap, pde, va); 3187 PMAP_UNLOCK(pmap); 3188 } 3189 small_mappings: 3190 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) { 3191 pmap = PV_PMAP(pv); 3192 PMAP_LOCK(pmap); 3193 pmap->pm_stats.resident_count--; 3194 pde = pmap_pde(pmap, pv->pv_va); 3195 KASSERT((*pde & PG_PS) == 0, ("pmap_remove_all: found" 3196 " a 4mpage in page %p's pv list", m)); 3197 pte = pmap_pte_quick(pmap, pv->pv_va); 3198 tpte = pte_load_clear(pte); 3199 KASSERT(tpte != 0, ("pmap_remove_all: pmap %p va %x zero pte", 3200 pmap, pv->pv_va)); 3201 if (tpte & PG_W) 3202 pmap->pm_stats.wired_count--; 3203 if (tpte & PG_A) 3204 vm_page_aflag_set(m, PGA_REFERENCED); 3205 3206 /* 3207 * Update the vm_page_t clean and reference bits. 3208 */ 3209 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 3210 vm_page_dirty(m); 3211 pmap_unuse_pt(pmap, pv->pv_va, &free); 3212 pmap_invalidate_page_int(pmap, pv->pv_va); 3213 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next); 3214 free_pv_entry(pmap, pv); 3215 PMAP_UNLOCK(pmap); 3216 } 3217 vm_page_aflag_clear(m, PGA_WRITEABLE); 3218 sched_unpin(); 3219 rw_wunlock(&pvh_global_lock); 3220 vm_page_free_pages_toq(&free, true); 3221 } 3222 3223 /* 3224 * pmap_protect_pde: do the things to protect a 4mpage in a process 3225 */ 3226 static boolean_t 3227 pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, vm_prot_t prot) 3228 { 3229 pd_entry_t newpde, oldpde; 3230 vm_offset_t eva, va; 3231 vm_page_t m; 3232 boolean_t anychanged; 3233 3234 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 3235 KASSERT((sva & PDRMASK) == 0, 3236 ("pmap_protect_pde: sva is not 4mpage aligned")); 3237 anychanged = FALSE; 3238 retry: 3239 oldpde = newpde = *pde; 3240 if ((oldpde & (PG_MANAGED | PG_M | PG_RW)) == 3241 (PG_MANAGED | PG_M | PG_RW)) { 3242 eva = sva + NBPDR; 3243 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME); 3244 va < eva; va += PAGE_SIZE, m++) 3245 vm_page_dirty(m); 3246 } 3247 if ((prot & VM_PROT_WRITE) == 0) 3248 newpde &= ~(PG_RW | PG_M); 3249 #ifdef PMAP_PAE_COMP 3250 if ((prot & VM_PROT_EXECUTE) == 0 && !i386_read_exec) 3251 newpde |= pg_nx; 3252 #endif 3253 if (newpde != oldpde) { 3254 /* 3255 * As an optimization to future operations on this PDE, clear 3256 * PG_PROMOTED. The impending invalidation will remove any 3257 * lingering 4KB page mappings from the TLB. 3258 */ 3259 if (!pde_cmpset(pde, oldpde, newpde & ~PG_PROMOTED)) 3260 goto retry; 3261 if ((oldpde & PG_G) != 0) 3262 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde); 3263 else 3264 anychanged = TRUE; 3265 } 3266 return (anychanged); 3267 } 3268 3269 /* 3270 * Set the physical protection on the 3271 * specified range of this map as requested. 3272 */ 3273 static void 3274 __CONCAT(PMTYPE, protect)(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, 3275 vm_prot_t prot) 3276 { 3277 vm_offset_t pdnxt; 3278 pd_entry_t ptpaddr; 3279 pt_entry_t *pte; 3280 boolean_t anychanged, pv_lists_locked; 3281 3282 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot)); 3283 if (prot == VM_PROT_NONE) { 3284 pmap_remove(pmap, sva, eva); 3285 return; 3286 } 3287 3288 #ifdef PMAP_PAE_COMP 3289 if ((prot & (VM_PROT_WRITE | VM_PROT_EXECUTE)) == 3290 (VM_PROT_WRITE | VM_PROT_EXECUTE)) 3291 return; 3292 #else 3293 if (prot & VM_PROT_WRITE) 3294 return; 3295 #endif 3296 3297 if (pmap_is_current(pmap)) 3298 pv_lists_locked = FALSE; 3299 else { 3300 pv_lists_locked = TRUE; 3301 resume: 3302 rw_wlock(&pvh_global_lock); 3303 sched_pin(); 3304 } 3305 anychanged = FALSE; 3306 3307 PMAP_LOCK(pmap); 3308 for (; sva < eva; sva = pdnxt) { 3309 pt_entry_t obits, pbits; 3310 u_int pdirindex; 3311 3312 pdnxt = (sva + NBPDR) & ~PDRMASK; 3313 if (pdnxt < sva) 3314 pdnxt = eva; 3315 3316 pdirindex = sva >> PDRSHIFT; 3317 ptpaddr = pmap->pm_pdir[pdirindex]; 3318 3319 /* 3320 * Weed out invalid mappings. Note: we assume that the page 3321 * directory table is always allocated, and in kernel virtual. 3322 */ 3323 if (ptpaddr == 0) 3324 continue; 3325 3326 /* 3327 * Check for large page. 3328 */ 3329 if ((ptpaddr & PG_PS) != 0) { 3330 /* 3331 * Are we protecting the entire large page? If not, 3332 * demote the mapping and fall through. 3333 */ 3334 if (sva + NBPDR == pdnxt && eva >= pdnxt) { 3335 /* 3336 * The TLB entry for a PG_G mapping is 3337 * invalidated by pmap_protect_pde(). 3338 */ 3339 if (pmap_protect_pde(pmap, 3340 &pmap->pm_pdir[pdirindex], sva, prot)) 3341 anychanged = TRUE; 3342 continue; 3343 } else { 3344 if (!pv_lists_locked) { 3345 pv_lists_locked = TRUE; 3346 if (!rw_try_wlock(&pvh_global_lock)) { 3347 if (anychanged) 3348 pmap_invalidate_all_int( 3349 pmap); 3350 PMAP_UNLOCK(pmap); 3351 goto resume; 3352 } 3353 sched_pin(); 3354 } 3355 if (!pmap_demote_pde(pmap, 3356 &pmap->pm_pdir[pdirindex], sva)) { 3357 /* 3358 * The large page mapping was 3359 * destroyed. 3360 */ 3361 continue; 3362 } 3363 } 3364 } 3365 3366 if (pdnxt > eva) 3367 pdnxt = eva; 3368 3369 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++, 3370 sva += PAGE_SIZE) { 3371 vm_page_t m; 3372 3373 retry: 3374 /* 3375 * Regardless of whether a pte is 32 or 64 bits in 3376 * size, PG_RW, PG_A, and PG_M are among the least 3377 * significant 32 bits. 3378 */ 3379 obits = pbits = *pte; 3380 if ((pbits & PG_V) == 0) 3381 continue; 3382 3383 if ((prot & VM_PROT_WRITE) == 0) { 3384 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) == 3385 (PG_MANAGED | PG_M | PG_RW)) { 3386 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME); 3387 vm_page_dirty(m); 3388 } 3389 pbits &= ~(PG_RW | PG_M); 3390 } 3391 #ifdef PMAP_PAE_COMP 3392 if ((prot & VM_PROT_EXECUTE) == 0 && !i386_read_exec) 3393 pbits |= pg_nx; 3394 #endif 3395 3396 if (pbits != obits) { 3397 #ifdef PMAP_PAE_COMP 3398 if (!atomic_cmpset_64(pte, obits, pbits)) 3399 goto retry; 3400 #else 3401 if (!atomic_cmpset_int((u_int *)pte, obits, 3402 pbits)) 3403 goto retry; 3404 #endif 3405 if (obits & PG_G) 3406 pmap_invalidate_page_int(pmap, sva); 3407 else 3408 anychanged = TRUE; 3409 } 3410 } 3411 } 3412 if (anychanged) 3413 pmap_invalidate_all_int(pmap); 3414 if (pv_lists_locked) { 3415 sched_unpin(); 3416 rw_wunlock(&pvh_global_lock); 3417 } 3418 PMAP_UNLOCK(pmap); 3419 } 3420 3421 #if VM_NRESERVLEVEL > 0 3422 /* 3423 * Tries to promote the 512 or 1024, contiguous 4KB page mappings that are 3424 * within a single page table page (PTP) to a single 2- or 4MB page mapping. 3425 * For promotion to occur, two conditions must be met: (1) the 4KB page 3426 * mappings must map aligned, contiguous physical memory and (2) the 4KB page 3427 * mappings must have identical characteristics. 3428 * 3429 * Managed (PG_MANAGED) mappings within the kernel address space are not 3430 * promoted. The reason is that kernel PDEs are replicated in each pmap but 3431 * pmap_clear_ptes() and pmap_ts_referenced() only read the PDE from the kernel 3432 * pmap. 3433 */ 3434 static void 3435 pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va) 3436 { 3437 pd_entry_t newpde; 3438 pt_entry_t *firstpte, oldpte, pa, *pte; 3439 vm_offset_t oldpteva; 3440 vm_page_t mpte; 3441 3442 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 3443 3444 /* 3445 * Examine the first PTE in the specified PTP. Abort if this PTE is 3446 * either invalid, unused, or does not map the first 4KB physical page 3447 * within a 2- or 4MB page. 3448 */ 3449 firstpte = pmap_pte_quick(pmap, trunc_4mpage(va)); 3450 setpde: 3451 newpde = *firstpte; 3452 if ((newpde & ((PG_FRAME & PDRMASK) | PG_A | PG_V)) != (PG_A | PG_V)) { 3453 pmap_pde_p_failures++; 3454 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x" 3455 " in pmap %p", va, pmap); 3456 return; 3457 } 3458 if ((*firstpte & PG_MANAGED) != 0 && pmap == kernel_pmap) { 3459 pmap_pde_p_failures++; 3460 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x" 3461 " in pmap %p", va, pmap); 3462 return; 3463 } 3464 if ((newpde & (PG_M | PG_RW)) == PG_RW) { 3465 /* 3466 * When PG_M is already clear, PG_RW can be cleared without 3467 * a TLB invalidation. 3468 */ 3469 if (!atomic_cmpset_int((u_int *)firstpte, newpde, newpde & 3470 ~PG_RW)) 3471 goto setpde; 3472 newpde &= ~PG_RW; 3473 } 3474 3475 /* 3476 * Examine each of the other PTEs in the specified PTP. Abort if this 3477 * PTE maps an unexpected 4KB physical page or does not have identical 3478 * characteristics to the first PTE. 3479 */ 3480 pa = (newpde & (PG_PS_FRAME | PG_A | PG_V)) + NBPDR - PAGE_SIZE; 3481 for (pte = firstpte + NPTEPG - 1; pte > firstpte; pte--) { 3482 setpte: 3483 oldpte = *pte; 3484 if ((oldpte & (PG_FRAME | PG_A | PG_V)) != pa) { 3485 pmap_pde_p_failures++; 3486 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x" 3487 " in pmap %p", va, pmap); 3488 return; 3489 } 3490 if ((oldpte & (PG_M | PG_RW)) == PG_RW) { 3491 /* 3492 * When PG_M is already clear, PG_RW can be cleared 3493 * without a TLB invalidation. 3494 */ 3495 if (!atomic_cmpset_int((u_int *)pte, oldpte, 3496 oldpte & ~PG_RW)) 3497 goto setpte; 3498 oldpte &= ~PG_RW; 3499 oldpteva = (oldpte & PG_FRAME & PDRMASK) | 3500 (va & ~PDRMASK); 3501 CTR2(KTR_PMAP, "pmap_promote_pde: protect for va %#x" 3502 " in pmap %p", oldpteva, pmap); 3503 } 3504 if ((oldpte & PG_PTE_PROMOTE) != (newpde & PG_PTE_PROMOTE)) { 3505 pmap_pde_p_failures++; 3506 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x" 3507 " in pmap %p", va, pmap); 3508 return; 3509 } 3510 pa -= PAGE_SIZE; 3511 } 3512 3513 /* 3514 * Save the page table page in its current state until the PDE 3515 * mapping the superpage is demoted by pmap_demote_pde() or 3516 * destroyed by pmap_remove_pde(). 3517 */ 3518 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME); 3519 KASSERT(mpte >= vm_page_array && 3520 mpte < &vm_page_array[vm_page_array_size], 3521 ("pmap_promote_pde: page table page is out of range")); 3522 KASSERT(mpte->pindex == va >> PDRSHIFT, 3523 ("pmap_promote_pde: page table page's pindex is wrong")); 3524 if (pmap_insert_pt_page(pmap, mpte)) { 3525 pmap_pde_p_failures++; 3526 CTR2(KTR_PMAP, 3527 "pmap_promote_pde: failure for va %#x in pmap %p", va, 3528 pmap); 3529 return; 3530 } 3531 3532 /* 3533 * Promote the pv entries. 3534 */ 3535 if ((newpde & PG_MANAGED) != 0) 3536 pmap_pv_promote_pde(pmap, va, newpde & PG_PS_FRAME); 3537 3538 /* 3539 * Propagate the PAT index to its proper position. 3540 */ 3541 if ((newpde & PG_PTE_PAT) != 0) 3542 newpde ^= PG_PDE_PAT | PG_PTE_PAT; 3543 3544 /* 3545 * Map the superpage. 3546 */ 3547 if (workaround_erratum383) 3548 pmap_update_pde(pmap, va, pde, PG_PS | newpde); 3549 else if (pmap == kernel_pmap) 3550 pmap_kenter_pde(va, PG_PROMOTED | PG_PS | newpde); 3551 else 3552 pde_store(pde, PG_PROMOTED | PG_PS | newpde); 3553 3554 pmap_pde_promotions++; 3555 CTR2(KTR_PMAP, "pmap_promote_pde: success for va %#x" 3556 " in pmap %p", va, pmap); 3557 } 3558 #endif /* VM_NRESERVLEVEL > 0 */ 3559 3560 /* 3561 * Insert the given physical page (p) at 3562 * the specified virtual address (v) in the 3563 * target physical map with the protection requested. 3564 * 3565 * If specified, the page will be wired down, meaning 3566 * that the related pte can not be reclaimed. 3567 * 3568 * NB: This is the only routine which MAY NOT lazy-evaluate 3569 * or lose information. That is, this routine must actually 3570 * insert this page into the given map NOW. 3571 */ 3572 static int 3573 __CONCAT(PMTYPE, enter)(pmap_t pmap, vm_offset_t va, vm_page_t m, 3574 vm_prot_t prot, u_int flags, int8_t psind) 3575 { 3576 pd_entry_t *pde; 3577 pt_entry_t *pte; 3578 pt_entry_t newpte, origpte; 3579 pv_entry_t pv; 3580 vm_paddr_t opa, pa; 3581 vm_page_t mpte, om; 3582 int rv; 3583 3584 va = trunc_page(va); 3585 KASSERT((pmap == kernel_pmap && va < VM_MAX_KERNEL_ADDRESS) || 3586 (pmap != kernel_pmap && va < VM_MAXUSER_ADDRESS), 3587 ("pmap_enter: toobig k%d %#x", pmap == kernel_pmap, va)); 3588 KASSERT(va < PMAP_TRM_MIN_ADDRESS, 3589 ("pmap_enter: invalid to pmap_enter into trampoline (va: 0x%x)", 3590 va)); 3591 KASSERT(pmap != kernel_pmap || (m->oflags & VPO_UNMANAGED) != 0 || 3592 va < kmi.clean_sva || va >= kmi.clean_eva, 3593 ("pmap_enter: managed mapping within the clean submap")); 3594 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m)) 3595 VM_OBJECT_ASSERT_LOCKED(m->object); 3596 KASSERT((flags & PMAP_ENTER_RESERVED) == 0, 3597 ("pmap_enter: flags %u has reserved bits set", flags)); 3598 pa = VM_PAGE_TO_PHYS(m); 3599 newpte = (pt_entry_t)(pa | PG_A | PG_V); 3600 if ((flags & VM_PROT_WRITE) != 0) 3601 newpte |= PG_M; 3602 if ((prot & VM_PROT_WRITE) != 0) 3603 newpte |= PG_RW; 3604 KASSERT((newpte & (PG_M | PG_RW)) != PG_M, 3605 ("pmap_enter: flags includes VM_PROT_WRITE but prot doesn't")); 3606 #ifdef PMAP_PAE_COMP 3607 if ((prot & VM_PROT_EXECUTE) == 0 && !i386_read_exec) 3608 newpte |= pg_nx; 3609 #endif 3610 if ((flags & PMAP_ENTER_WIRED) != 0) 3611 newpte |= PG_W; 3612 if (pmap != kernel_pmap) 3613 newpte |= PG_U; 3614 newpte |= pmap_cache_bits(pmap, m->md.pat_mode, psind > 0); 3615 if ((m->oflags & VPO_UNMANAGED) == 0) 3616 newpte |= PG_MANAGED; 3617 3618 rw_wlock(&pvh_global_lock); 3619 PMAP_LOCK(pmap); 3620 sched_pin(); 3621 if (psind == 1) { 3622 /* Assert the required virtual and physical alignment. */ 3623 KASSERT((va & PDRMASK) == 0, ("pmap_enter: va unaligned")); 3624 KASSERT(m->psind > 0, ("pmap_enter: m->psind < psind")); 3625 rv = pmap_enter_pde(pmap, va, newpte | PG_PS, flags, m); 3626 goto out; 3627 } 3628 3629 pde = pmap_pde(pmap, va); 3630 if (pmap != kernel_pmap) { 3631 /* 3632 * va is for UVA. 3633 * In the case that a page table page is not resident, 3634 * we are creating it here. pmap_allocpte() handles 3635 * demotion. 3636 */ 3637 mpte = pmap_allocpte(pmap, va, flags); 3638 if (mpte == NULL) { 3639 KASSERT((flags & PMAP_ENTER_NOSLEEP) != 0, 3640 ("pmap_allocpte failed with sleep allowed")); 3641 rv = KERN_RESOURCE_SHORTAGE; 3642 goto out; 3643 } 3644 } else { 3645 /* 3646 * va is for KVA, so pmap_demote_pde() will never fail 3647 * to install a page table page. PG_V is also 3648 * asserted by pmap_demote_pde(). 3649 */ 3650 mpte = NULL; 3651 KASSERT(pde != NULL && (*pde & PG_V) != 0, 3652 ("KVA %#x invalid pde pdir %#jx", va, 3653 (uintmax_t)pmap->pm_pdir[PTDPTDI])); 3654 if ((*pde & PG_PS) != 0) 3655 pmap_demote_pde(pmap, pde, va); 3656 } 3657 pte = pmap_pte_quick(pmap, va); 3658 3659 /* 3660 * Page Directory table entry is not valid, which should not 3661 * happen. We should have either allocated the page table 3662 * page or demoted the existing mapping above. 3663 */ 3664 if (pte == NULL) { 3665 panic("pmap_enter: invalid page directory pdir=%#jx, va=%#x", 3666 (uintmax_t)pmap->pm_pdir[PTDPTDI], va); 3667 } 3668 3669 origpte = *pte; 3670 pv = NULL; 3671 3672 /* 3673 * Is the specified virtual address already mapped? 3674 */ 3675 if ((origpte & PG_V) != 0) { 3676 /* 3677 * Wiring change, just update stats. We don't worry about 3678 * wiring PT pages as they remain resident as long as there 3679 * are valid mappings in them. Hence, if a user page is wired, 3680 * the PT page will be also. 3681 */ 3682 if ((newpte & PG_W) != 0 && (origpte & PG_W) == 0) 3683 pmap->pm_stats.wired_count++; 3684 else if ((newpte & PG_W) == 0 && (origpte & PG_W) != 0) 3685 pmap->pm_stats.wired_count--; 3686 3687 /* 3688 * Remove the extra PT page reference. 3689 */ 3690 if (mpte != NULL) { 3691 mpte->wire_count--; 3692 KASSERT(mpte->wire_count > 0, 3693 ("pmap_enter: missing reference to page table page," 3694 " va: 0x%x", va)); 3695 } 3696 3697 /* 3698 * Has the physical page changed? 3699 */ 3700 opa = origpte & PG_FRAME; 3701 if (opa == pa) { 3702 /* 3703 * No, might be a protection or wiring change. 3704 */ 3705 if ((origpte & PG_MANAGED) != 0 && 3706 (newpte & PG_RW) != 0) 3707 vm_page_aflag_set(m, PGA_WRITEABLE); 3708 if (((origpte ^ newpte) & ~(PG_M | PG_A)) == 0) 3709 goto unchanged; 3710 goto validate; 3711 } 3712 3713 /* 3714 * The physical page has changed. Temporarily invalidate 3715 * the mapping. This ensures that all threads sharing the 3716 * pmap keep a consistent view of the mapping, which is 3717 * necessary for the correct handling of COW faults. It 3718 * also permits reuse of the old mapping's PV entry, 3719 * avoiding an allocation. 3720 * 3721 * For consistency, handle unmanaged mappings the same way. 3722 */ 3723 origpte = pte_load_clear(pte); 3724 KASSERT((origpte & PG_FRAME) == opa, 3725 ("pmap_enter: unexpected pa update for %#x", va)); 3726 if ((origpte & PG_MANAGED) != 0) { 3727 om = PHYS_TO_VM_PAGE(opa); 3728 3729 /* 3730 * The pmap lock is sufficient to synchronize with 3731 * concurrent calls to pmap_page_test_mappings() and 3732 * pmap_ts_referenced(). 3733 */ 3734 if ((origpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 3735 vm_page_dirty(om); 3736 if ((origpte & PG_A) != 0) 3737 vm_page_aflag_set(om, PGA_REFERENCED); 3738 pv = pmap_pvh_remove(&om->md, pmap, va); 3739 KASSERT(pv != NULL, 3740 ("pmap_enter: no PV entry for %#x", va)); 3741 if ((newpte & PG_MANAGED) == 0) 3742 free_pv_entry(pmap, pv); 3743 if ((om->aflags & PGA_WRITEABLE) != 0 && 3744 TAILQ_EMPTY(&om->md.pv_list) && 3745 ((om->flags & PG_FICTITIOUS) != 0 || 3746 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list))) 3747 vm_page_aflag_clear(om, PGA_WRITEABLE); 3748 } 3749 if ((origpte & PG_A) != 0) 3750 pmap_invalidate_page_int(pmap, va); 3751 origpte = 0; 3752 } else { 3753 /* 3754 * Increment the counters. 3755 */ 3756 if ((newpte & PG_W) != 0) 3757 pmap->pm_stats.wired_count++; 3758 pmap->pm_stats.resident_count++; 3759 } 3760 3761 /* 3762 * Enter on the PV list if part of our managed memory. 3763 */ 3764 if ((newpte & PG_MANAGED) != 0) { 3765 if (pv == NULL) { 3766 pv = get_pv_entry(pmap, FALSE); 3767 pv->pv_va = va; 3768 } 3769 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next); 3770 if ((newpte & PG_RW) != 0) 3771 vm_page_aflag_set(m, PGA_WRITEABLE); 3772 } 3773 3774 /* 3775 * Update the PTE. 3776 */ 3777 if ((origpte & PG_V) != 0) { 3778 validate: 3779 origpte = pte_load_store(pte, newpte); 3780 KASSERT((origpte & PG_FRAME) == pa, 3781 ("pmap_enter: unexpected pa update for %#x", va)); 3782 if ((newpte & PG_M) == 0 && (origpte & (PG_M | PG_RW)) == 3783 (PG_M | PG_RW)) { 3784 if ((origpte & PG_MANAGED) != 0) 3785 vm_page_dirty(m); 3786 3787 /* 3788 * Although the PTE may still have PG_RW set, TLB 3789 * invalidation may nonetheless be required because 3790 * the PTE no longer has PG_M set. 3791 */ 3792 } 3793 #ifdef PMAP_PAE_COMP 3794 else if ((origpte & PG_NX) != 0 || (newpte & PG_NX) == 0) { 3795 /* 3796 * This PTE change does not require TLB invalidation. 3797 */ 3798 goto unchanged; 3799 } 3800 #endif 3801 if ((origpte & PG_A) != 0) 3802 pmap_invalidate_page_int(pmap, va); 3803 } else 3804 pte_store(pte, newpte); 3805 3806 unchanged: 3807 3808 #if VM_NRESERVLEVEL > 0 3809 /* 3810 * If both the page table page and the reservation are fully 3811 * populated, then attempt promotion. 3812 */ 3813 if ((mpte == NULL || mpte->wire_count == NPTEPG) && 3814 pg_ps_enabled && (m->flags & PG_FICTITIOUS) == 0 && 3815 vm_reserv_level_iffullpop(m) == 0) 3816 pmap_promote_pde(pmap, pde, va); 3817 #endif 3818 3819 rv = KERN_SUCCESS; 3820 out: 3821 sched_unpin(); 3822 rw_wunlock(&pvh_global_lock); 3823 PMAP_UNLOCK(pmap); 3824 return (rv); 3825 } 3826 3827 /* 3828 * Tries to create a read- and/or execute-only 2 or 4 MB page mapping. Returns 3829 * true if successful. Returns false if (1) a mapping already exists at the 3830 * specified virtual address or (2) a PV entry cannot be allocated without 3831 * reclaiming another PV entry. 3832 */ 3833 static bool 3834 pmap_enter_4mpage(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot) 3835 { 3836 pd_entry_t newpde; 3837 3838 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 3839 newpde = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(pmap, m->md.pat_mode, 1) | 3840 PG_PS | PG_V; 3841 if ((m->oflags & VPO_UNMANAGED) == 0) 3842 newpde |= PG_MANAGED; 3843 #ifdef PMAP_PAE_COMP 3844 if ((prot & VM_PROT_EXECUTE) == 0 && !i386_read_exec) 3845 newpde |= pg_nx; 3846 #endif 3847 if (pmap != kernel_pmap) 3848 newpde |= PG_U; 3849 return (pmap_enter_pde(pmap, va, newpde, PMAP_ENTER_NOSLEEP | 3850 PMAP_ENTER_NOREPLACE | PMAP_ENTER_NORECLAIM, NULL) == 3851 KERN_SUCCESS); 3852 } 3853 3854 /* 3855 * Tries to create the specified 2 or 4 MB page mapping. Returns KERN_SUCCESS 3856 * if the mapping was created, and either KERN_FAILURE or 3857 * KERN_RESOURCE_SHORTAGE otherwise. Returns KERN_FAILURE if 3858 * PMAP_ENTER_NOREPLACE was specified and a mapping already exists at the 3859 * specified virtual address. Returns KERN_RESOURCE_SHORTAGE if 3860 * PMAP_ENTER_NORECLAIM was specified and a PV entry allocation failed. 3861 * 3862 * The parameter "m" is only used when creating a managed, writeable mapping. 3863 */ 3864 static int 3865 pmap_enter_pde(pmap_t pmap, vm_offset_t va, pd_entry_t newpde, u_int flags, 3866 vm_page_t m) 3867 { 3868 struct spglist free; 3869 pd_entry_t oldpde, *pde; 3870 vm_page_t mt; 3871 3872 rw_assert(&pvh_global_lock, RA_WLOCKED); 3873 KASSERT((newpde & (PG_M | PG_RW)) != PG_RW, 3874 ("pmap_enter_pde: newpde is missing PG_M")); 3875 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 3876 pde = pmap_pde(pmap, va); 3877 oldpde = *pde; 3878 if ((oldpde & PG_V) != 0) { 3879 if ((flags & PMAP_ENTER_NOREPLACE) != 0) { 3880 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx" 3881 " in pmap %p", va, pmap); 3882 return (KERN_FAILURE); 3883 } 3884 /* Break the existing mapping(s). */ 3885 SLIST_INIT(&free); 3886 if ((oldpde & PG_PS) != 0) { 3887 /* 3888 * If the PDE resulted from a promotion, then a 3889 * reserved PT page could be freed. 3890 */ 3891 (void)pmap_remove_pde(pmap, pde, va, &free); 3892 if ((oldpde & PG_G) == 0) 3893 pmap_invalidate_pde_page(pmap, va, oldpde); 3894 } else { 3895 if (pmap_remove_ptes(pmap, va, va + NBPDR, &free)) 3896 pmap_invalidate_all_int(pmap); 3897 } 3898 vm_page_free_pages_toq(&free, true); 3899 if (pmap == kernel_pmap) { 3900 mt = PHYS_TO_VM_PAGE(*pde & PG_FRAME); 3901 if (pmap_insert_pt_page(pmap, mt)) { 3902 /* 3903 * XXX Currently, this can't happen because 3904 * we do not perform pmap_enter(psind == 1) 3905 * on the kernel pmap. 3906 */ 3907 panic("pmap_enter_pde: trie insert failed"); 3908 } 3909 } else 3910 KASSERT(*pde == 0, ("pmap_enter_pde: non-zero pde %p", 3911 pde)); 3912 } 3913 if ((newpde & PG_MANAGED) != 0) { 3914 /* 3915 * Abort this mapping if its PV entry could not be created. 3916 */ 3917 if (!pmap_pv_insert_pde(pmap, va, newpde, flags)) { 3918 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx" 3919 " in pmap %p", va, pmap); 3920 return (KERN_RESOURCE_SHORTAGE); 3921 } 3922 if ((newpde & PG_RW) != 0) { 3923 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++) 3924 vm_page_aflag_set(mt, PGA_WRITEABLE); 3925 } 3926 } 3927 3928 /* 3929 * Increment counters. 3930 */ 3931 if ((newpde & PG_W) != 0) 3932 pmap->pm_stats.wired_count += NBPDR / PAGE_SIZE; 3933 pmap->pm_stats.resident_count += NBPDR / PAGE_SIZE; 3934 3935 /* 3936 * Map the superpage. (This is not a promoted mapping; there will not 3937 * be any lingering 4KB page mappings in the TLB.) 3938 */ 3939 pde_store(pde, newpde); 3940 3941 pmap_pde_mappings++; 3942 CTR2(KTR_PMAP, "pmap_enter_pde: success for va %#lx" 3943 " in pmap %p", va, pmap); 3944 return (KERN_SUCCESS); 3945 } 3946 3947 /* 3948 * Maps a sequence of resident pages belonging to the same object. 3949 * The sequence begins with the given page m_start. This page is 3950 * mapped at the given virtual address start. Each subsequent page is 3951 * mapped at a virtual address that is offset from start by the same 3952 * amount as the page is offset from m_start within the object. The 3953 * last page in the sequence is the page with the largest offset from 3954 * m_start that can be mapped at a virtual address less than the given 3955 * virtual address end. Not every virtual page between start and end 3956 * is mapped; only those for which a resident page exists with the 3957 * corresponding offset from m_start are mapped. 3958 */ 3959 static void 3960 __CONCAT(PMTYPE, enter_object)(pmap_t pmap, vm_offset_t start, vm_offset_t end, 3961 vm_page_t m_start, vm_prot_t prot) 3962 { 3963 vm_offset_t va; 3964 vm_page_t m, mpte; 3965 vm_pindex_t diff, psize; 3966 3967 VM_OBJECT_ASSERT_LOCKED(m_start->object); 3968 3969 psize = atop(end - start); 3970 mpte = NULL; 3971 m = m_start; 3972 rw_wlock(&pvh_global_lock); 3973 PMAP_LOCK(pmap); 3974 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 3975 va = start + ptoa(diff); 3976 if ((va & PDRMASK) == 0 && va + NBPDR <= end && 3977 m->psind == 1 && pg_ps_enabled && 3978 pmap_enter_4mpage(pmap, va, m, prot)) 3979 m = &m[NBPDR / PAGE_SIZE - 1]; 3980 else 3981 mpte = pmap_enter_quick_locked(pmap, va, m, prot, 3982 mpte); 3983 m = TAILQ_NEXT(m, listq); 3984 } 3985 rw_wunlock(&pvh_global_lock); 3986 PMAP_UNLOCK(pmap); 3987 } 3988 3989 /* 3990 * this code makes some *MAJOR* assumptions: 3991 * 1. Current pmap & pmap exists. 3992 * 2. Not wired. 3993 * 3. Read access. 3994 * 4. No page table pages. 3995 * but is *MUCH* faster than pmap_enter... 3996 */ 3997 3998 static void 3999 __CONCAT(PMTYPE, enter_quick)(pmap_t pmap, vm_offset_t va, vm_page_t m, 4000 vm_prot_t prot) 4001 { 4002 4003 rw_wlock(&pvh_global_lock); 4004 PMAP_LOCK(pmap); 4005 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL); 4006 rw_wunlock(&pvh_global_lock); 4007 PMAP_UNLOCK(pmap); 4008 } 4009 4010 static vm_page_t 4011 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, 4012 vm_prot_t prot, vm_page_t mpte) 4013 { 4014 pt_entry_t newpte, *pte; 4015 struct spglist free; 4016 4017 KASSERT(pmap != kernel_pmap || va < kmi.clean_sva || 4018 va >= kmi.clean_eva || (m->oflags & VPO_UNMANAGED) != 0, 4019 ("pmap_enter_quick_locked: managed mapping within the clean submap")); 4020 rw_assert(&pvh_global_lock, RA_WLOCKED); 4021 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 4022 4023 /* 4024 * In the case that a page table page is not 4025 * resident, we are creating it here. 4026 */ 4027 if (pmap != kernel_pmap) { 4028 u_int ptepindex; 4029 pd_entry_t ptepa; 4030 4031 /* 4032 * Calculate pagetable page index 4033 */ 4034 ptepindex = va >> PDRSHIFT; 4035 if (mpte && (mpte->pindex == ptepindex)) { 4036 mpte->wire_count++; 4037 } else { 4038 /* 4039 * Get the page directory entry 4040 */ 4041 ptepa = pmap->pm_pdir[ptepindex]; 4042 4043 /* 4044 * If the page table page is mapped, we just increment 4045 * the hold count, and activate it. 4046 */ 4047 if (ptepa) { 4048 if (ptepa & PG_PS) 4049 return (NULL); 4050 mpte = PHYS_TO_VM_PAGE(ptepa & PG_FRAME); 4051 mpte->wire_count++; 4052 } else { 4053 mpte = _pmap_allocpte(pmap, ptepindex, 4054 PMAP_ENTER_NOSLEEP); 4055 if (mpte == NULL) 4056 return (mpte); 4057 } 4058 } 4059 } else { 4060 mpte = NULL; 4061 } 4062 4063 sched_pin(); 4064 pte = pmap_pte_quick(pmap, va); 4065 if (*pte) { 4066 if (mpte != NULL) { 4067 mpte->wire_count--; 4068 mpte = NULL; 4069 } 4070 sched_unpin(); 4071 return (mpte); 4072 } 4073 4074 /* 4075 * Enter on the PV list if part of our managed memory. 4076 */ 4077 if ((m->oflags & VPO_UNMANAGED) == 0 && 4078 !pmap_try_insert_pv_entry(pmap, va, m)) { 4079 if (mpte != NULL) { 4080 SLIST_INIT(&free); 4081 if (pmap_unwire_ptp(pmap, mpte, &free)) { 4082 pmap_invalidate_page_int(pmap, va); 4083 vm_page_free_pages_toq(&free, true); 4084 } 4085 4086 mpte = NULL; 4087 } 4088 sched_unpin(); 4089 return (mpte); 4090 } 4091 4092 /* 4093 * Increment counters 4094 */ 4095 pmap->pm_stats.resident_count++; 4096 4097 newpte = VM_PAGE_TO_PHYS(m) | PG_V | 4098 pmap_cache_bits(pmap, m->md.pat_mode, 0); 4099 if ((m->oflags & VPO_UNMANAGED) == 0) 4100 newpte |= PG_MANAGED; 4101 #ifdef PMAP_PAE_COMP 4102 if ((prot & VM_PROT_EXECUTE) == 0 && !i386_read_exec) 4103 newpte |= pg_nx; 4104 #endif 4105 if (pmap != kernel_pmap) 4106 newpte |= PG_U; 4107 pte_store(pte, newpte); 4108 sched_unpin(); 4109 return (mpte); 4110 } 4111 4112 /* 4113 * Make a temporary mapping for a physical address. This is only intended 4114 * to be used for panic dumps. 4115 */ 4116 static void * 4117 __CONCAT(PMTYPE, kenter_temporary)(vm_paddr_t pa, int i) 4118 { 4119 vm_offset_t va; 4120 4121 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE); 4122 pmap_kenter(va, pa); 4123 invlpg(va); 4124 return ((void *)crashdumpmap); 4125 } 4126 4127 /* 4128 * This code maps large physical mmap regions into the 4129 * processor address space. Note that some shortcuts 4130 * are taken, but the code works. 4131 */ 4132 static void 4133 __CONCAT(PMTYPE, object_init_pt)(pmap_t pmap, vm_offset_t addr, 4134 vm_object_t object, vm_pindex_t pindex, vm_size_t size) 4135 { 4136 pd_entry_t *pde; 4137 vm_paddr_t pa, ptepa; 4138 vm_page_t p; 4139 int pat_mode; 4140 4141 VM_OBJECT_ASSERT_WLOCKED(object); 4142 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG, 4143 ("pmap_object_init_pt: non-device object")); 4144 if (pg_ps_enabled && 4145 (addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) { 4146 if (!vm_object_populate(object, pindex, pindex + atop(size))) 4147 return; 4148 p = vm_page_lookup(object, pindex); 4149 KASSERT(p->valid == VM_PAGE_BITS_ALL, 4150 ("pmap_object_init_pt: invalid page %p", p)); 4151 pat_mode = p->md.pat_mode; 4152 4153 /* 4154 * Abort the mapping if the first page is not physically 4155 * aligned to a 2/4MB page boundary. 4156 */ 4157 ptepa = VM_PAGE_TO_PHYS(p); 4158 if (ptepa & (NBPDR - 1)) 4159 return; 4160 4161 /* 4162 * Skip the first page. Abort the mapping if the rest of 4163 * the pages are not physically contiguous or have differing 4164 * memory attributes. 4165 */ 4166 p = TAILQ_NEXT(p, listq); 4167 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size; 4168 pa += PAGE_SIZE) { 4169 KASSERT(p->valid == VM_PAGE_BITS_ALL, 4170 ("pmap_object_init_pt: invalid page %p", p)); 4171 if (pa != VM_PAGE_TO_PHYS(p) || 4172 pat_mode != p->md.pat_mode) 4173 return; 4174 p = TAILQ_NEXT(p, listq); 4175 } 4176 4177 /* 4178 * Map using 2/4MB pages. Since "ptepa" is 2/4M aligned and 4179 * "size" is a multiple of 2/4M, adding the PAT setting to 4180 * "pa" will not affect the termination of this loop. 4181 */ 4182 PMAP_LOCK(pmap); 4183 for (pa = ptepa | pmap_cache_bits(pmap, pat_mode, 1); 4184 pa < ptepa + size; pa += NBPDR) { 4185 pde = pmap_pde(pmap, addr); 4186 if (*pde == 0) { 4187 pde_store(pde, pa | PG_PS | PG_M | PG_A | 4188 PG_U | PG_RW | PG_V); 4189 pmap->pm_stats.resident_count += NBPDR / 4190 PAGE_SIZE; 4191 pmap_pde_mappings++; 4192 } 4193 /* Else continue on if the PDE is already valid. */ 4194 addr += NBPDR; 4195 } 4196 PMAP_UNLOCK(pmap); 4197 } 4198 } 4199 4200 /* 4201 * Clear the wired attribute from the mappings for the specified range of 4202 * addresses in the given pmap. Every valid mapping within that range 4203 * must have the wired attribute set. In contrast, invalid mappings 4204 * cannot have the wired attribute set, so they are ignored. 4205 * 4206 * The wired attribute of the page table entry is not a hardware feature, 4207 * so there is no need to invalidate any TLB entries. 4208 */ 4209 static void 4210 __CONCAT(PMTYPE, unwire)(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 4211 { 4212 vm_offset_t pdnxt; 4213 pd_entry_t *pde; 4214 pt_entry_t *pte; 4215 boolean_t pv_lists_locked; 4216 4217 if (pmap_is_current(pmap)) 4218 pv_lists_locked = FALSE; 4219 else { 4220 pv_lists_locked = TRUE; 4221 resume: 4222 rw_wlock(&pvh_global_lock); 4223 sched_pin(); 4224 } 4225 PMAP_LOCK(pmap); 4226 for (; sva < eva; sva = pdnxt) { 4227 pdnxt = (sva + NBPDR) & ~PDRMASK; 4228 if (pdnxt < sva) 4229 pdnxt = eva; 4230 pde = pmap_pde(pmap, sva); 4231 if ((*pde & PG_V) == 0) 4232 continue; 4233 if ((*pde & PG_PS) != 0) { 4234 if ((*pde & PG_W) == 0) 4235 panic("pmap_unwire: pde %#jx is missing PG_W", 4236 (uintmax_t)*pde); 4237 4238 /* 4239 * Are we unwiring the entire large page? If not, 4240 * demote the mapping and fall through. 4241 */ 4242 if (sva + NBPDR == pdnxt && eva >= pdnxt) { 4243 /* 4244 * Regardless of whether a pde (or pte) is 32 4245 * or 64 bits in size, PG_W is among the least 4246 * significant 32 bits. 4247 */ 4248 atomic_clear_int((u_int *)pde, PG_W); 4249 pmap->pm_stats.wired_count -= NBPDR / 4250 PAGE_SIZE; 4251 continue; 4252 } else { 4253 if (!pv_lists_locked) { 4254 pv_lists_locked = TRUE; 4255 if (!rw_try_wlock(&pvh_global_lock)) { 4256 PMAP_UNLOCK(pmap); 4257 /* Repeat sva. */ 4258 goto resume; 4259 } 4260 sched_pin(); 4261 } 4262 if (!pmap_demote_pde(pmap, pde, sva)) 4263 panic("pmap_unwire: demotion failed"); 4264 } 4265 } 4266 if (pdnxt > eva) 4267 pdnxt = eva; 4268 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++, 4269 sva += PAGE_SIZE) { 4270 if ((*pte & PG_V) == 0) 4271 continue; 4272 if ((*pte & PG_W) == 0) 4273 panic("pmap_unwire: pte %#jx is missing PG_W", 4274 (uintmax_t)*pte); 4275 4276 /* 4277 * PG_W must be cleared atomically. Although the pmap 4278 * lock synchronizes access to PG_W, another processor 4279 * could be setting PG_M and/or PG_A concurrently. 4280 * 4281 * PG_W is among the least significant 32 bits. 4282 */ 4283 atomic_clear_int((u_int *)pte, PG_W); 4284 pmap->pm_stats.wired_count--; 4285 } 4286 } 4287 if (pv_lists_locked) { 4288 sched_unpin(); 4289 rw_wunlock(&pvh_global_lock); 4290 } 4291 PMAP_UNLOCK(pmap); 4292 } 4293 4294 4295 /* 4296 * Copy the range specified by src_addr/len 4297 * from the source map to the range dst_addr/len 4298 * in the destination map. 4299 * 4300 * This routine is only advisory and need not do anything. Since 4301 * current pmap is always the kernel pmap when executing in 4302 * kernel, and we do not copy from the kernel pmap to a user 4303 * pmap, this optimization is not usable in 4/4G full split i386 4304 * world. 4305 */ 4306 4307 static void 4308 __CONCAT(PMTYPE, copy)(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, 4309 vm_size_t len, vm_offset_t src_addr) 4310 { 4311 struct spglist free; 4312 pt_entry_t *src_pte, *dst_pte, ptetemp; 4313 pd_entry_t srcptepaddr; 4314 vm_page_t dstmpte, srcmpte; 4315 vm_offset_t addr, end_addr, pdnxt; 4316 u_int ptepindex; 4317 4318 if (dst_addr != src_addr) 4319 return; 4320 4321 end_addr = src_addr + len; 4322 4323 rw_wlock(&pvh_global_lock); 4324 if (dst_pmap < src_pmap) { 4325 PMAP_LOCK(dst_pmap); 4326 PMAP_LOCK(src_pmap); 4327 } else { 4328 PMAP_LOCK(src_pmap); 4329 PMAP_LOCK(dst_pmap); 4330 } 4331 sched_pin(); 4332 for (addr = src_addr; addr < end_addr; addr = pdnxt) { 4333 KASSERT(addr < PMAP_TRM_MIN_ADDRESS, 4334 ("pmap_copy: invalid to pmap_copy the trampoline")); 4335 4336 pdnxt = (addr + NBPDR) & ~PDRMASK; 4337 if (pdnxt < addr) 4338 pdnxt = end_addr; 4339 ptepindex = addr >> PDRSHIFT; 4340 4341 srcptepaddr = src_pmap->pm_pdir[ptepindex]; 4342 if (srcptepaddr == 0) 4343 continue; 4344 4345 if (srcptepaddr & PG_PS) { 4346 if ((addr & PDRMASK) != 0 || addr + NBPDR > end_addr) 4347 continue; 4348 if (dst_pmap->pm_pdir[ptepindex] == 0 && 4349 ((srcptepaddr & PG_MANAGED) == 0 || 4350 pmap_pv_insert_pde(dst_pmap, addr, srcptepaddr, 4351 PMAP_ENTER_NORECLAIM))) { 4352 dst_pmap->pm_pdir[ptepindex] = srcptepaddr & 4353 ~PG_W; 4354 dst_pmap->pm_stats.resident_count += 4355 NBPDR / PAGE_SIZE; 4356 pmap_pde_mappings++; 4357 } 4358 continue; 4359 } 4360 4361 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr & PG_FRAME); 4362 KASSERT(srcmpte->wire_count > 0, 4363 ("pmap_copy: source page table page is unused")); 4364 4365 if (pdnxt > end_addr) 4366 pdnxt = end_addr; 4367 4368 src_pte = pmap_pte_quick3(src_pmap, addr); 4369 while (addr < pdnxt) { 4370 ptetemp = *src_pte; 4371 /* 4372 * we only virtual copy managed pages 4373 */ 4374 if ((ptetemp & PG_MANAGED) != 0) { 4375 dstmpte = pmap_allocpte(dst_pmap, addr, 4376 PMAP_ENTER_NOSLEEP); 4377 if (dstmpte == NULL) 4378 goto out; 4379 dst_pte = pmap_pte_quick(dst_pmap, addr); 4380 if (*dst_pte == 0 && 4381 pmap_try_insert_pv_entry(dst_pmap, addr, 4382 PHYS_TO_VM_PAGE(ptetemp & PG_FRAME))) { 4383 /* 4384 * Clear the wired, modified, and 4385 * accessed (referenced) bits 4386 * during the copy. 4387 */ 4388 *dst_pte = ptetemp & ~(PG_W | PG_M | 4389 PG_A); 4390 dst_pmap->pm_stats.resident_count++; 4391 } else { 4392 SLIST_INIT(&free); 4393 if (pmap_unwire_ptp(dst_pmap, dstmpte, 4394 &free)) { 4395 pmap_invalidate_page_int( 4396 dst_pmap, addr); 4397 vm_page_free_pages_toq(&free, 4398 true); 4399 } 4400 goto out; 4401 } 4402 if (dstmpte->wire_count >= srcmpte->wire_count) 4403 break; 4404 } 4405 addr += PAGE_SIZE; 4406 src_pte++; 4407 } 4408 } 4409 out: 4410 sched_unpin(); 4411 rw_wunlock(&pvh_global_lock); 4412 PMAP_UNLOCK(src_pmap); 4413 PMAP_UNLOCK(dst_pmap); 4414 } 4415 4416 /* 4417 * Zero 1 page of virtual memory mapped from a hardware page by the caller. 4418 */ 4419 static __inline void 4420 pagezero(void *page) 4421 { 4422 #if defined(I686_CPU) 4423 if (cpu_class == CPUCLASS_686) { 4424 if (cpu_feature & CPUID_SSE2) 4425 sse2_pagezero(page); 4426 else 4427 i686_pagezero(page); 4428 } else 4429 #endif 4430 bzero(page, PAGE_SIZE); 4431 } 4432 4433 /* 4434 * Zero the specified hardware page. 4435 */ 4436 static void 4437 __CONCAT(PMTYPE, zero_page)(vm_page_t m) 4438 { 4439 pt_entry_t *cmap_pte2; 4440 struct pcpu *pc; 4441 4442 sched_pin(); 4443 pc = get_pcpu(); 4444 cmap_pte2 = pc->pc_cmap_pte2; 4445 mtx_lock(&pc->pc_cmap_lock); 4446 if (*cmap_pte2) 4447 panic("pmap_zero_page: CMAP2 busy"); 4448 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M | 4449 pmap_cache_bits(kernel_pmap, m->md.pat_mode, 0); 4450 invlcaddr(pc->pc_cmap_addr2); 4451 pagezero(pc->pc_cmap_addr2); 4452 *cmap_pte2 = 0; 4453 4454 /* 4455 * Unpin the thread before releasing the lock. Otherwise the thread 4456 * could be rescheduled while still bound to the current CPU, only 4457 * to unpin itself immediately upon resuming execution. 4458 */ 4459 sched_unpin(); 4460 mtx_unlock(&pc->pc_cmap_lock); 4461 } 4462 4463 /* 4464 * Zero an an area within a single hardware page. off and size must not 4465 * cover an area beyond a single hardware page. 4466 */ 4467 static void 4468 __CONCAT(PMTYPE, zero_page_area)(vm_page_t m, int off, int size) 4469 { 4470 pt_entry_t *cmap_pte2; 4471 struct pcpu *pc; 4472 4473 sched_pin(); 4474 pc = get_pcpu(); 4475 cmap_pte2 = pc->pc_cmap_pte2; 4476 mtx_lock(&pc->pc_cmap_lock); 4477 if (*cmap_pte2) 4478 panic("pmap_zero_page_area: CMAP2 busy"); 4479 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M | 4480 pmap_cache_bits(kernel_pmap, m->md.pat_mode, 0); 4481 invlcaddr(pc->pc_cmap_addr2); 4482 if (off == 0 && size == PAGE_SIZE) 4483 pagezero(pc->pc_cmap_addr2); 4484 else 4485 bzero(pc->pc_cmap_addr2 + off, size); 4486 *cmap_pte2 = 0; 4487 sched_unpin(); 4488 mtx_unlock(&pc->pc_cmap_lock); 4489 } 4490 4491 /* 4492 * Copy 1 specified hardware page to another. 4493 */ 4494 static void 4495 __CONCAT(PMTYPE, copy_page)(vm_page_t src, vm_page_t dst) 4496 { 4497 pt_entry_t *cmap_pte1, *cmap_pte2; 4498 struct pcpu *pc; 4499 4500 sched_pin(); 4501 pc = get_pcpu(); 4502 cmap_pte1 = pc->pc_cmap_pte1; 4503 cmap_pte2 = pc->pc_cmap_pte2; 4504 mtx_lock(&pc->pc_cmap_lock); 4505 if (*cmap_pte1) 4506 panic("pmap_copy_page: CMAP1 busy"); 4507 if (*cmap_pte2) 4508 panic("pmap_copy_page: CMAP2 busy"); 4509 *cmap_pte1 = PG_V | VM_PAGE_TO_PHYS(src) | PG_A | 4510 pmap_cache_bits(kernel_pmap, src->md.pat_mode, 0); 4511 invlcaddr(pc->pc_cmap_addr1); 4512 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(dst) | PG_A | PG_M | 4513 pmap_cache_bits(kernel_pmap, dst->md.pat_mode, 0); 4514 invlcaddr(pc->pc_cmap_addr2); 4515 bcopy(pc->pc_cmap_addr1, pc->pc_cmap_addr2, PAGE_SIZE); 4516 *cmap_pte1 = 0; 4517 *cmap_pte2 = 0; 4518 sched_unpin(); 4519 mtx_unlock(&pc->pc_cmap_lock); 4520 } 4521 4522 static void 4523 __CONCAT(PMTYPE, copy_pages)(vm_page_t ma[], vm_offset_t a_offset, 4524 vm_page_t mb[], vm_offset_t b_offset, int xfersize) 4525 { 4526 vm_page_t a_pg, b_pg; 4527 char *a_cp, *b_cp; 4528 vm_offset_t a_pg_offset, b_pg_offset; 4529 pt_entry_t *cmap_pte1, *cmap_pte2; 4530 struct pcpu *pc; 4531 int cnt; 4532 4533 sched_pin(); 4534 pc = get_pcpu(); 4535 cmap_pte1 = pc->pc_cmap_pte1; 4536 cmap_pte2 = pc->pc_cmap_pte2; 4537 mtx_lock(&pc->pc_cmap_lock); 4538 if (*cmap_pte1 != 0) 4539 panic("pmap_copy_pages: CMAP1 busy"); 4540 if (*cmap_pte2 != 0) 4541 panic("pmap_copy_pages: CMAP2 busy"); 4542 while (xfersize > 0) { 4543 a_pg = ma[a_offset >> PAGE_SHIFT]; 4544 a_pg_offset = a_offset & PAGE_MASK; 4545 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 4546 b_pg = mb[b_offset >> PAGE_SHIFT]; 4547 b_pg_offset = b_offset & PAGE_MASK; 4548 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 4549 *cmap_pte1 = PG_V | VM_PAGE_TO_PHYS(a_pg) | PG_A | 4550 pmap_cache_bits(kernel_pmap, a_pg->md.pat_mode, 0); 4551 invlcaddr(pc->pc_cmap_addr1); 4552 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(b_pg) | PG_A | 4553 PG_M | pmap_cache_bits(kernel_pmap, b_pg->md.pat_mode, 0); 4554 invlcaddr(pc->pc_cmap_addr2); 4555 a_cp = pc->pc_cmap_addr1 + a_pg_offset; 4556 b_cp = pc->pc_cmap_addr2 + b_pg_offset; 4557 bcopy(a_cp, b_cp, cnt); 4558 a_offset += cnt; 4559 b_offset += cnt; 4560 xfersize -= cnt; 4561 } 4562 *cmap_pte1 = 0; 4563 *cmap_pte2 = 0; 4564 sched_unpin(); 4565 mtx_unlock(&pc->pc_cmap_lock); 4566 } 4567 4568 /* 4569 * Returns true if the pmap's pv is one of the first 4570 * 16 pvs linked to from this page. This count may 4571 * be changed upwards or downwards in the future; it 4572 * is only necessary that true be returned for a small 4573 * subset of pmaps for proper page aging. 4574 */ 4575 static boolean_t 4576 __CONCAT(PMTYPE, page_exists_quick)(pmap_t pmap, vm_page_t m) 4577 { 4578 struct md_page *pvh; 4579 pv_entry_t pv; 4580 int loops = 0; 4581 boolean_t rv; 4582 4583 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 4584 ("pmap_page_exists_quick: page %p is not managed", m)); 4585 rv = FALSE; 4586 rw_wlock(&pvh_global_lock); 4587 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) { 4588 if (PV_PMAP(pv) == pmap) { 4589 rv = TRUE; 4590 break; 4591 } 4592 loops++; 4593 if (loops >= 16) 4594 break; 4595 } 4596 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) { 4597 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 4598 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) { 4599 if (PV_PMAP(pv) == pmap) { 4600 rv = TRUE; 4601 break; 4602 } 4603 loops++; 4604 if (loops >= 16) 4605 break; 4606 } 4607 } 4608 rw_wunlock(&pvh_global_lock); 4609 return (rv); 4610 } 4611 4612 /* 4613 * pmap_page_wired_mappings: 4614 * 4615 * Return the number of managed mappings to the given physical page 4616 * that are wired. 4617 */ 4618 static int 4619 __CONCAT(PMTYPE, page_wired_mappings)(vm_page_t m) 4620 { 4621 int count; 4622 4623 count = 0; 4624 if ((m->oflags & VPO_UNMANAGED) != 0) 4625 return (count); 4626 rw_wlock(&pvh_global_lock); 4627 count = pmap_pvh_wired_mappings(&m->md, count); 4628 if ((m->flags & PG_FICTITIOUS) == 0) { 4629 count = pmap_pvh_wired_mappings(pa_to_pvh(VM_PAGE_TO_PHYS(m)), 4630 count); 4631 } 4632 rw_wunlock(&pvh_global_lock); 4633 return (count); 4634 } 4635 4636 /* 4637 * pmap_pvh_wired_mappings: 4638 * 4639 * Return the updated number "count" of managed mappings that are wired. 4640 */ 4641 static int 4642 pmap_pvh_wired_mappings(struct md_page *pvh, int count) 4643 { 4644 pmap_t pmap; 4645 pt_entry_t *pte; 4646 pv_entry_t pv; 4647 4648 rw_assert(&pvh_global_lock, RA_WLOCKED); 4649 sched_pin(); 4650 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) { 4651 pmap = PV_PMAP(pv); 4652 PMAP_LOCK(pmap); 4653 pte = pmap_pte_quick(pmap, pv->pv_va); 4654 if ((*pte & PG_W) != 0) 4655 count++; 4656 PMAP_UNLOCK(pmap); 4657 } 4658 sched_unpin(); 4659 return (count); 4660 } 4661 4662 /* 4663 * Returns TRUE if the given page is mapped individually or as part of 4664 * a 4mpage. Otherwise, returns FALSE. 4665 */ 4666 static boolean_t 4667 __CONCAT(PMTYPE, page_is_mapped)(vm_page_t m) 4668 { 4669 boolean_t rv; 4670 4671 if ((m->oflags & VPO_UNMANAGED) != 0) 4672 return (FALSE); 4673 rw_wlock(&pvh_global_lock); 4674 rv = !TAILQ_EMPTY(&m->md.pv_list) || 4675 ((m->flags & PG_FICTITIOUS) == 0 && 4676 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list)); 4677 rw_wunlock(&pvh_global_lock); 4678 return (rv); 4679 } 4680 4681 /* 4682 * Remove all pages from specified address space 4683 * this aids process exit speeds. Also, this code 4684 * is special cased for current process only, but 4685 * can have the more generic (and slightly slower) 4686 * mode enabled. This is much faster than pmap_remove 4687 * in the case of running down an entire address space. 4688 */ 4689 static void 4690 __CONCAT(PMTYPE, remove_pages)(pmap_t pmap) 4691 { 4692 pt_entry_t *pte, tpte; 4693 vm_page_t m, mpte, mt; 4694 pv_entry_t pv; 4695 struct md_page *pvh; 4696 struct pv_chunk *pc, *npc; 4697 struct spglist free; 4698 int field, idx; 4699 int32_t bit; 4700 uint32_t inuse, bitmask; 4701 int allfree; 4702 4703 if (pmap != PCPU_GET(curpmap)) { 4704 printf("warning: pmap_remove_pages called with non-current pmap\n"); 4705 return; 4706 } 4707 SLIST_INIT(&free); 4708 rw_wlock(&pvh_global_lock); 4709 PMAP_LOCK(pmap); 4710 sched_pin(); 4711 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) { 4712 KASSERT(pc->pc_pmap == pmap, ("Wrong pmap %p %p", pmap, 4713 pc->pc_pmap)); 4714 allfree = 1; 4715 for (field = 0; field < _NPCM; field++) { 4716 inuse = ~pc->pc_map[field] & pc_freemask[field]; 4717 while (inuse != 0) { 4718 bit = bsfl(inuse); 4719 bitmask = 1UL << bit; 4720 idx = field * 32 + bit; 4721 pv = &pc->pc_pventry[idx]; 4722 inuse &= ~bitmask; 4723 4724 pte = pmap_pde(pmap, pv->pv_va); 4725 tpte = *pte; 4726 if ((tpte & PG_PS) == 0) { 4727 pte = pmap_pte_quick(pmap, pv->pv_va); 4728 tpte = *pte & ~PG_PTE_PAT; 4729 } 4730 4731 if (tpte == 0) { 4732 printf( 4733 "TPTE at %p IS ZERO @ VA %08x\n", 4734 pte, pv->pv_va); 4735 panic("bad pte"); 4736 } 4737 4738 /* 4739 * We cannot remove wired pages from a process' mapping at this time 4740 */ 4741 if (tpte & PG_W) { 4742 allfree = 0; 4743 continue; 4744 } 4745 4746 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME); 4747 KASSERT(m->phys_addr == (tpte & PG_FRAME), 4748 ("vm_page_t %p phys_addr mismatch %016jx %016jx", 4749 m, (uintmax_t)m->phys_addr, 4750 (uintmax_t)tpte)); 4751 4752 KASSERT((m->flags & PG_FICTITIOUS) != 0 || 4753 m < &vm_page_array[vm_page_array_size], 4754 ("pmap_remove_pages: bad tpte %#jx", 4755 (uintmax_t)tpte)); 4756 4757 pte_clear(pte); 4758 4759 /* 4760 * Update the vm_page_t clean/reference bits. 4761 */ 4762 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) { 4763 if ((tpte & PG_PS) != 0) { 4764 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++) 4765 vm_page_dirty(mt); 4766 } else 4767 vm_page_dirty(m); 4768 } 4769 4770 /* Mark free */ 4771 PV_STAT(pv_entry_frees++); 4772 PV_STAT(pv_entry_spare++); 4773 pv_entry_count--; 4774 pc->pc_map[field] |= bitmask; 4775 if ((tpte & PG_PS) != 0) { 4776 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE; 4777 pvh = pa_to_pvh(tpte & PG_PS_FRAME); 4778 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next); 4779 if (TAILQ_EMPTY(&pvh->pv_list)) { 4780 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++) 4781 if (TAILQ_EMPTY(&mt->md.pv_list)) 4782 vm_page_aflag_clear(mt, PGA_WRITEABLE); 4783 } 4784 mpte = pmap_remove_pt_page(pmap, pv->pv_va); 4785 if (mpte != NULL) { 4786 pmap->pm_stats.resident_count--; 4787 KASSERT(mpte->wire_count == NPTEPG, 4788 ("pmap_remove_pages: pte page wire count error")); 4789 mpte->wire_count = 0; 4790 pmap_add_delayed_free_list(mpte, &free, FALSE); 4791 } 4792 } else { 4793 pmap->pm_stats.resident_count--; 4794 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next); 4795 if (TAILQ_EMPTY(&m->md.pv_list) && 4796 (m->flags & PG_FICTITIOUS) == 0) { 4797 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 4798 if (TAILQ_EMPTY(&pvh->pv_list)) 4799 vm_page_aflag_clear(m, PGA_WRITEABLE); 4800 } 4801 pmap_unuse_pt(pmap, pv->pv_va, &free); 4802 } 4803 } 4804 } 4805 if (allfree) { 4806 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 4807 free_pv_chunk(pc); 4808 } 4809 } 4810 sched_unpin(); 4811 pmap_invalidate_all_int(pmap); 4812 rw_wunlock(&pvh_global_lock); 4813 PMAP_UNLOCK(pmap); 4814 vm_page_free_pages_toq(&free, true); 4815 } 4816 4817 /* 4818 * pmap_is_modified: 4819 * 4820 * Return whether or not the specified physical page was modified 4821 * in any physical maps. 4822 */ 4823 static boolean_t 4824 __CONCAT(PMTYPE, is_modified)(vm_page_t m) 4825 { 4826 boolean_t rv; 4827 4828 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 4829 ("pmap_is_modified: page %p is not managed", m)); 4830 4831 /* 4832 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 4833 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE 4834 * is clear, no PTEs can have PG_M set. 4835 */ 4836 VM_OBJECT_ASSERT_WLOCKED(m->object); 4837 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 4838 return (FALSE); 4839 rw_wlock(&pvh_global_lock); 4840 rv = pmap_is_modified_pvh(&m->md) || 4841 ((m->flags & PG_FICTITIOUS) == 0 && 4842 pmap_is_modified_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m)))); 4843 rw_wunlock(&pvh_global_lock); 4844 return (rv); 4845 } 4846 4847 /* 4848 * Returns TRUE if any of the given mappings were used to modify 4849 * physical memory. Otherwise, returns FALSE. Both page and 2mpage 4850 * mappings are supported. 4851 */ 4852 static boolean_t 4853 pmap_is_modified_pvh(struct md_page *pvh) 4854 { 4855 pv_entry_t pv; 4856 pt_entry_t *pte; 4857 pmap_t pmap; 4858 boolean_t rv; 4859 4860 rw_assert(&pvh_global_lock, RA_WLOCKED); 4861 rv = FALSE; 4862 sched_pin(); 4863 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) { 4864 pmap = PV_PMAP(pv); 4865 PMAP_LOCK(pmap); 4866 pte = pmap_pte_quick(pmap, pv->pv_va); 4867 rv = (*pte & (PG_M | PG_RW)) == (PG_M | PG_RW); 4868 PMAP_UNLOCK(pmap); 4869 if (rv) 4870 break; 4871 } 4872 sched_unpin(); 4873 return (rv); 4874 } 4875 4876 /* 4877 * pmap_is_prefaultable: 4878 * 4879 * Return whether or not the specified virtual address is elgible 4880 * for prefault. 4881 */ 4882 static boolean_t 4883 __CONCAT(PMTYPE, is_prefaultable)(pmap_t pmap, vm_offset_t addr) 4884 { 4885 pd_entry_t pde; 4886 boolean_t rv; 4887 4888 rv = FALSE; 4889 PMAP_LOCK(pmap); 4890 pde = *pmap_pde(pmap, addr); 4891 if (pde != 0 && (pde & PG_PS) == 0) 4892 rv = pmap_pte_ufast(pmap, addr, pde) == 0; 4893 PMAP_UNLOCK(pmap); 4894 return (rv); 4895 } 4896 4897 /* 4898 * pmap_is_referenced: 4899 * 4900 * Return whether or not the specified physical page was referenced 4901 * in any physical maps. 4902 */ 4903 static boolean_t 4904 __CONCAT(PMTYPE, is_referenced)(vm_page_t m) 4905 { 4906 boolean_t rv; 4907 4908 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 4909 ("pmap_is_referenced: page %p is not managed", m)); 4910 rw_wlock(&pvh_global_lock); 4911 rv = pmap_is_referenced_pvh(&m->md) || 4912 ((m->flags & PG_FICTITIOUS) == 0 && 4913 pmap_is_referenced_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m)))); 4914 rw_wunlock(&pvh_global_lock); 4915 return (rv); 4916 } 4917 4918 /* 4919 * Returns TRUE if any of the given mappings were referenced and FALSE 4920 * otherwise. Both page and 4mpage mappings are supported. 4921 */ 4922 static boolean_t 4923 pmap_is_referenced_pvh(struct md_page *pvh) 4924 { 4925 pv_entry_t pv; 4926 pt_entry_t *pte; 4927 pmap_t pmap; 4928 boolean_t rv; 4929 4930 rw_assert(&pvh_global_lock, RA_WLOCKED); 4931 rv = FALSE; 4932 sched_pin(); 4933 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) { 4934 pmap = PV_PMAP(pv); 4935 PMAP_LOCK(pmap); 4936 pte = pmap_pte_quick(pmap, pv->pv_va); 4937 rv = (*pte & (PG_A | PG_V)) == (PG_A | PG_V); 4938 PMAP_UNLOCK(pmap); 4939 if (rv) 4940 break; 4941 } 4942 sched_unpin(); 4943 return (rv); 4944 } 4945 4946 /* 4947 * Clear the write and modified bits in each of the given page's mappings. 4948 */ 4949 static void 4950 __CONCAT(PMTYPE, remove_write)(vm_page_t m) 4951 { 4952 struct md_page *pvh; 4953 pv_entry_t next_pv, pv; 4954 pmap_t pmap; 4955 pd_entry_t *pde; 4956 pt_entry_t oldpte, *pte; 4957 vm_offset_t va; 4958 4959 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 4960 ("pmap_remove_write: page %p is not managed", m)); 4961 4962 /* 4963 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 4964 * set by another thread while the object is locked. Thus, 4965 * if PGA_WRITEABLE is clear, no page table entries need updating. 4966 */ 4967 VM_OBJECT_ASSERT_WLOCKED(m->object); 4968 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 4969 return; 4970 rw_wlock(&pvh_global_lock); 4971 sched_pin(); 4972 if ((m->flags & PG_FICTITIOUS) != 0) 4973 goto small_mappings; 4974 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 4975 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) { 4976 va = pv->pv_va; 4977 pmap = PV_PMAP(pv); 4978 PMAP_LOCK(pmap); 4979 pde = pmap_pde(pmap, va); 4980 if ((*pde & PG_RW) != 0) 4981 (void)pmap_demote_pde(pmap, pde, va); 4982 PMAP_UNLOCK(pmap); 4983 } 4984 small_mappings: 4985 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) { 4986 pmap = PV_PMAP(pv); 4987 PMAP_LOCK(pmap); 4988 pde = pmap_pde(pmap, pv->pv_va); 4989 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_write: found" 4990 " a 4mpage in page %p's pv list", m)); 4991 pte = pmap_pte_quick(pmap, pv->pv_va); 4992 retry: 4993 oldpte = *pte; 4994 if ((oldpte & PG_RW) != 0) { 4995 /* 4996 * Regardless of whether a pte is 32 or 64 bits 4997 * in size, PG_RW and PG_M are among the least 4998 * significant 32 bits. 4999 */ 5000 if (!atomic_cmpset_int((u_int *)pte, oldpte, 5001 oldpte & ~(PG_RW | PG_M))) 5002 goto retry; 5003 if ((oldpte & PG_M) != 0) 5004 vm_page_dirty(m); 5005 pmap_invalidate_page_int(pmap, pv->pv_va); 5006 } 5007 PMAP_UNLOCK(pmap); 5008 } 5009 vm_page_aflag_clear(m, PGA_WRITEABLE); 5010 sched_unpin(); 5011 rw_wunlock(&pvh_global_lock); 5012 } 5013 5014 /* 5015 * pmap_ts_referenced: 5016 * 5017 * Return a count of reference bits for a page, clearing those bits. 5018 * It is not necessary for every reference bit to be cleared, but it 5019 * is necessary that 0 only be returned when there are truly no 5020 * reference bits set. 5021 * 5022 * As an optimization, update the page's dirty field if a modified bit is 5023 * found while counting reference bits. This opportunistic update can be 5024 * performed at low cost and can eliminate the need for some future calls 5025 * to pmap_is_modified(). However, since this function stops after 5026 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some 5027 * dirty pages. Those dirty pages will only be detected by a future call 5028 * to pmap_is_modified(). 5029 */ 5030 static int 5031 __CONCAT(PMTYPE, ts_referenced)(vm_page_t m) 5032 { 5033 struct md_page *pvh; 5034 pv_entry_t pv, pvf; 5035 pmap_t pmap; 5036 pd_entry_t *pde; 5037 pt_entry_t *pte; 5038 vm_paddr_t pa; 5039 int rtval = 0; 5040 5041 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 5042 ("pmap_ts_referenced: page %p is not managed", m)); 5043 pa = VM_PAGE_TO_PHYS(m); 5044 pvh = pa_to_pvh(pa); 5045 rw_wlock(&pvh_global_lock); 5046 sched_pin(); 5047 if ((m->flags & PG_FICTITIOUS) != 0 || 5048 (pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL) 5049 goto small_mappings; 5050 pv = pvf; 5051 do { 5052 pmap = PV_PMAP(pv); 5053 PMAP_LOCK(pmap); 5054 pde = pmap_pde(pmap, pv->pv_va); 5055 if ((*pde & (PG_M | PG_RW)) == (PG_M | PG_RW)) { 5056 /* 5057 * Although "*pde" is mapping a 2/4MB page, because 5058 * this function is called at a 4KB page granularity, 5059 * we only update the 4KB page under test. 5060 */ 5061 vm_page_dirty(m); 5062 } 5063 if ((*pde & PG_A) != 0) { 5064 /* 5065 * Since this reference bit is shared by either 1024 5066 * or 512 4KB pages, it should not be cleared every 5067 * time it is tested. Apply a simple "hash" function 5068 * on the physical page number, the virtual superpage 5069 * number, and the pmap address to select one 4KB page 5070 * out of the 1024 or 512 on which testing the 5071 * reference bit will result in clearing that bit. 5072 * This function is designed to avoid the selection of 5073 * the same 4KB page for every 2- or 4MB page mapping. 5074 * 5075 * On demotion, a mapping that hasn't been referenced 5076 * is simply destroyed. To avoid the possibility of a 5077 * subsequent page fault on a demoted wired mapping, 5078 * always leave its reference bit set. Moreover, 5079 * since the superpage is wired, the current state of 5080 * its reference bit won't affect page replacement. 5081 */ 5082 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> PDRSHIFT) ^ 5083 (uintptr_t)pmap) & (NPTEPG - 1)) == 0 && 5084 (*pde & PG_W) == 0) { 5085 atomic_clear_int((u_int *)pde, PG_A); 5086 pmap_invalidate_page_int(pmap, pv->pv_va); 5087 } 5088 rtval++; 5089 } 5090 PMAP_UNLOCK(pmap); 5091 /* Rotate the PV list if it has more than one entry. */ 5092 if (TAILQ_NEXT(pv, pv_next) != NULL) { 5093 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next); 5094 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next); 5095 } 5096 if (rtval >= PMAP_TS_REFERENCED_MAX) 5097 goto out; 5098 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf); 5099 small_mappings: 5100 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL) 5101 goto out; 5102 pv = pvf; 5103 do { 5104 pmap = PV_PMAP(pv); 5105 PMAP_LOCK(pmap); 5106 pde = pmap_pde(pmap, pv->pv_va); 5107 KASSERT((*pde & PG_PS) == 0, 5108 ("pmap_ts_referenced: found a 4mpage in page %p's pv list", 5109 m)); 5110 pte = pmap_pte_quick(pmap, pv->pv_va); 5111 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 5112 vm_page_dirty(m); 5113 if ((*pte & PG_A) != 0) { 5114 atomic_clear_int((u_int *)pte, PG_A); 5115 pmap_invalidate_page_int(pmap, pv->pv_va); 5116 rtval++; 5117 } 5118 PMAP_UNLOCK(pmap); 5119 /* Rotate the PV list if it has more than one entry. */ 5120 if (TAILQ_NEXT(pv, pv_next) != NULL) { 5121 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next); 5122 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next); 5123 } 5124 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && rtval < 5125 PMAP_TS_REFERENCED_MAX); 5126 out: 5127 sched_unpin(); 5128 rw_wunlock(&pvh_global_lock); 5129 return (rtval); 5130 } 5131 5132 /* 5133 * Apply the given advice to the specified range of addresses within the 5134 * given pmap. Depending on the advice, clear the referenced and/or 5135 * modified flags in each mapping and set the mapped page's dirty field. 5136 */ 5137 static void 5138 __CONCAT(PMTYPE, advise)(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, 5139 int advice) 5140 { 5141 pd_entry_t oldpde, *pde; 5142 pt_entry_t *pte; 5143 vm_offset_t va, pdnxt; 5144 vm_page_t m; 5145 boolean_t anychanged, pv_lists_locked; 5146 5147 if (advice != MADV_DONTNEED && advice != MADV_FREE) 5148 return; 5149 if (pmap_is_current(pmap)) 5150 pv_lists_locked = FALSE; 5151 else { 5152 pv_lists_locked = TRUE; 5153 resume: 5154 rw_wlock(&pvh_global_lock); 5155 sched_pin(); 5156 } 5157 anychanged = FALSE; 5158 PMAP_LOCK(pmap); 5159 for (; sva < eva; sva = pdnxt) { 5160 pdnxt = (sva + NBPDR) & ~PDRMASK; 5161 if (pdnxt < sva) 5162 pdnxt = eva; 5163 pde = pmap_pde(pmap, sva); 5164 oldpde = *pde; 5165 if ((oldpde & PG_V) == 0) 5166 continue; 5167 else if ((oldpde & PG_PS) != 0) { 5168 if ((oldpde & PG_MANAGED) == 0) 5169 continue; 5170 if (!pv_lists_locked) { 5171 pv_lists_locked = TRUE; 5172 if (!rw_try_wlock(&pvh_global_lock)) { 5173 if (anychanged) 5174 pmap_invalidate_all_int(pmap); 5175 PMAP_UNLOCK(pmap); 5176 goto resume; 5177 } 5178 sched_pin(); 5179 } 5180 if (!pmap_demote_pde(pmap, pde, sva)) { 5181 /* 5182 * The large page mapping was destroyed. 5183 */ 5184 continue; 5185 } 5186 5187 /* 5188 * Unless the page mappings are wired, remove the 5189 * mapping to a single page so that a subsequent 5190 * access may repromote. Since the underlying page 5191 * table page is fully populated, this removal never 5192 * frees a page table page. 5193 */ 5194 if ((oldpde & PG_W) == 0) { 5195 pte = pmap_pte_quick(pmap, sva); 5196 KASSERT((*pte & PG_V) != 0, 5197 ("pmap_advise: invalid PTE")); 5198 pmap_remove_pte(pmap, pte, sva, NULL); 5199 anychanged = TRUE; 5200 } 5201 } 5202 if (pdnxt > eva) 5203 pdnxt = eva; 5204 va = pdnxt; 5205 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++, 5206 sva += PAGE_SIZE) { 5207 if ((*pte & (PG_MANAGED | PG_V)) != (PG_MANAGED | PG_V)) 5208 goto maybe_invlrng; 5209 else if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) { 5210 if (advice == MADV_DONTNEED) { 5211 /* 5212 * Future calls to pmap_is_modified() 5213 * can be avoided by making the page 5214 * dirty now. 5215 */ 5216 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME); 5217 vm_page_dirty(m); 5218 } 5219 atomic_clear_int((u_int *)pte, PG_M | PG_A); 5220 } else if ((*pte & PG_A) != 0) 5221 atomic_clear_int((u_int *)pte, PG_A); 5222 else 5223 goto maybe_invlrng; 5224 if ((*pte & PG_G) != 0) { 5225 if (va == pdnxt) 5226 va = sva; 5227 } else 5228 anychanged = TRUE; 5229 continue; 5230 maybe_invlrng: 5231 if (va != pdnxt) { 5232 pmap_invalidate_range_int(pmap, va, sva); 5233 va = pdnxt; 5234 } 5235 } 5236 if (va != pdnxt) 5237 pmap_invalidate_range_int(pmap, va, sva); 5238 } 5239 if (anychanged) 5240 pmap_invalidate_all_int(pmap); 5241 if (pv_lists_locked) { 5242 sched_unpin(); 5243 rw_wunlock(&pvh_global_lock); 5244 } 5245 PMAP_UNLOCK(pmap); 5246 } 5247 5248 /* 5249 * Clear the modify bits on the specified physical page. 5250 */ 5251 static void 5252 __CONCAT(PMTYPE, clear_modify)(vm_page_t m) 5253 { 5254 struct md_page *pvh; 5255 pv_entry_t next_pv, pv; 5256 pmap_t pmap; 5257 pd_entry_t oldpde, *pde; 5258 pt_entry_t oldpte, *pte; 5259 vm_offset_t va; 5260 5261 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 5262 ("pmap_clear_modify: page %p is not managed", m)); 5263 VM_OBJECT_ASSERT_WLOCKED(m->object); 5264 KASSERT(!vm_page_xbusied(m), 5265 ("pmap_clear_modify: page %p is exclusive busied", m)); 5266 5267 /* 5268 * If the page is not PGA_WRITEABLE, then no PTEs can have PG_M set. 5269 * If the object containing the page is locked and the page is not 5270 * exclusive busied, then PGA_WRITEABLE cannot be concurrently set. 5271 */ 5272 if ((m->aflags & PGA_WRITEABLE) == 0) 5273 return; 5274 rw_wlock(&pvh_global_lock); 5275 sched_pin(); 5276 if ((m->flags & PG_FICTITIOUS) != 0) 5277 goto small_mappings; 5278 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 5279 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) { 5280 va = pv->pv_va; 5281 pmap = PV_PMAP(pv); 5282 PMAP_LOCK(pmap); 5283 pde = pmap_pde(pmap, va); 5284 oldpde = *pde; 5285 if ((oldpde & PG_RW) != 0) { 5286 if (pmap_demote_pde(pmap, pde, va)) { 5287 if ((oldpde & PG_W) == 0) { 5288 /* 5289 * Write protect the mapping to a 5290 * single page so that a subsequent 5291 * write access may repromote. 5292 */ 5293 va += VM_PAGE_TO_PHYS(m) - (oldpde & 5294 PG_PS_FRAME); 5295 pte = pmap_pte_quick(pmap, va); 5296 oldpte = *pte; 5297 if ((oldpte & PG_V) != 0) { 5298 /* 5299 * Regardless of whether a pte is 32 or 64 bits 5300 * in size, PG_RW and PG_M are among the least 5301 * significant 32 bits. 5302 */ 5303 while (!atomic_cmpset_int((u_int *)pte, 5304 oldpte, 5305 oldpte & ~(PG_M | PG_RW))) 5306 oldpte = *pte; 5307 vm_page_dirty(m); 5308 pmap_invalidate_page_int(pmap, 5309 va); 5310 } 5311 } 5312 } 5313 } 5314 PMAP_UNLOCK(pmap); 5315 } 5316 small_mappings: 5317 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) { 5318 pmap = PV_PMAP(pv); 5319 PMAP_LOCK(pmap); 5320 pde = pmap_pde(pmap, pv->pv_va); 5321 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_modify: found" 5322 " a 4mpage in page %p's pv list", m)); 5323 pte = pmap_pte_quick(pmap, pv->pv_va); 5324 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) { 5325 /* 5326 * Regardless of whether a pte is 32 or 64 bits 5327 * in size, PG_M is among the least significant 5328 * 32 bits. 5329 */ 5330 atomic_clear_int((u_int *)pte, PG_M); 5331 pmap_invalidate_page_int(pmap, pv->pv_va); 5332 } 5333 PMAP_UNLOCK(pmap); 5334 } 5335 sched_unpin(); 5336 rw_wunlock(&pvh_global_lock); 5337 } 5338 5339 /* 5340 * Miscellaneous support routines follow 5341 */ 5342 5343 /* Adjust the cache mode for a 4KB page mapped via a PTE. */ 5344 static __inline void 5345 pmap_pte_attr(pt_entry_t *pte, int cache_bits) 5346 { 5347 u_int opte, npte; 5348 5349 /* 5350 * The cache mode bits are all in the low 32-bits of the 5351 * PTE, so we can just spin on updating the low 32-bits. 5352 */ 5353 do { 5354 opte = *(u_int *)pte; 5355 npte = opte & ~PG_PTE_CACHE; 5356 npte |= cache_bits; 5357 } while (npte != opte && !atomic_cmpset_int((u_int *)pte, opte, npte)); 5358 } 5359 5360 /* Adjust the cache mode for a 2/4MB page mapped via a PDE. */ 5361 static __inline void 5362 pmap_pde_attr(pd_entry_t *pde, int cache_bits) 5363 { 5364 u_int opde, npde; 5365 5366 /* 5367 * The cache mode bits are all in the low 32-bits of the 5368 * PDE, so we can just spin on updating the low 32-bits. 5369 */ 5370 do { 5371 opde = *(u_int *)pde; 5372 npde = opde & ~PG_PDE_CACHE; 5373 npde |= cache_bits; 5374 } while (npde != opde && !atomic_cmpset_int((u_int *)pde, opde, npde)); 5375 } 5376 5377 /* 5378 * Map a set of physical memory pages into the kernel virtual 5379 * address space. Return a pointer to where it is mapped. This 5380 * routine is intended to be used for mapping device memory, 5381 * NOT real memory. 5382 */ 5383 static void * 5384 __CONCAT(PMTYPE, mapdev_attr)(vm_paddr_t pa, vm_size_t size, int mode) 5385 { 5386 struct pmap_preinit_mapping *ppim; 5387 vm_offset_t va, offset; 5388 vm_size_t tmpsize; 5389 int i; 5390 5391 offset = pa & PAGE_MASK; 5392 size = round_page(offset + size); 5393 pa = pa & PG_FRAME; 5394 5395 if (pa < PMAP_MAP_LOW && pa + size <= PMAP_MAP_LOW) 5396 va = pa + PMAP_MAP_LOW; 5397 else if (!pmap_initialized) { 5398 va = 0; 5399 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) { 5400 ppim = pmap_preinit_mapping + i; 5401 if (ppim->va == 0) { 5402 ppim->pa = pa; 5403 ppim->sz = size; 5404 ppim->mode = mode; 5405 ppim->va = virtual_avail; 5406 virtual_avail += size; 5407 va = ppim->va; 5408 break; 5409 } 5410 } 5411 if (va == 0) 5412 panic("%s: too many preinit mappings", __func__); 5413 } else { 5414 /* 5415 * If we have a preinit mapping, re-use it. 5416 */ 5417 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) { 5418 ppim = pmap_preinit_mapping + i; 5419 if (ppim->pa == pa && ppim->sz == size && 5420 ppim->mode == mode) 5421 return ((void *)(ppim->va + offset)); 5422 } 5423 va = kva_alloc(size); 5424 if (va == 0) 5425 panic("%s: Couldn't allocate KVA", __func__); 5426 } 5427 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE) 5428 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode); 5429 pmap_invalidate_range_int(kernel_pmap, va, va + tmpsize); 5430 pmap_invalidate_cache_range(va, va + size); 5431 return ((void *)(va + offset)); 5432 } 5433 5434 static void 5435 __CONCAT(PMTYPE, unmapdev)(vm_offset_t va, vm_size_t size) 5436 { 5437 struct pmap_preinit_mapping *ppim; 5438 vm_offset_t offset; 5439 int i; 5440 5441 if (va >= PMAP_MAP_LOW && va <= KERNBASE && va + size <= KERNBASE) 5442 return; 5443 offset = va & PAGE_MASK; 5444 size = round_page(offset + size); 5445 va = trunc_page(va); 5446 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) { 5447 ppim = pmap_preinit_mapping + i; 5448 if (ppim->va == va && ppim->sz == size) { 5449 if (pmap_initialized) 5450 return; 5451 ppim->pa = 0; 5452 ppim->va = 0; 5453 ppim->sz = 0; 5454 ppim->mode = 0; 5455 if (va + size == virtual_avail) 5456 virtual_avail = va; 5457 return; 5458 } 5459 } 5460 if (pmap_initialized) 5461 kva_free(va, size); 5462 } 5463 5464 /* 5465 * Sets the memory attribute for the specified page. 5466 */ 5467 static void 5468 __CONCAT(PMTYPE, page_set_memattr)(vm_page_t m, vm_memattr_t ma) 5469 { 5470 5471 m->md.pat_mode = ma; 5472 if ((m->flags & PG_FICTITIOUS) != 0) 5473 return; 5474 5475 /* 5476 * If "m" is a normal page, flush it from the cache. 5477 * See pmap_invalidate_cache_range(). 5478 * 5479 * First, try to find an existing mapping of the page by sf 5480 * buffer. sf_buf_invalidate_cache() modifies mapping and 5481 * flushes the cache. 5482 */ 5483 if (sf_buf_invalidate_cache(m)) 5484 return; 5485 5486 /* 5487 * If page is not mapped by sf buffer, but CPU does not 5488 * support self snoop, map the page transient and do 5489 * invalidation. In the worst case, whole cache is flushed by 5490 * pmap_invalidate_cache_range(). 5491 */ 5492 if ((cpu_feature & CPUID_SS) == 0) 5493 pmap_flush_page(m); 5494 } 5495 5496 static void 5497 __CONCAT(PMTYPE, flush_page)(vm_page_t m) 5498 { 5499 pt_entry_t *cmap_pte2; 5500 struct pcpu *pc; 5501 vm_offset_t sva, eva; 5502 bool useclflushopt; 5503 5504 useclflushopt = (cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0; 5505 if (useclflushopt || (cpu_feature & CPUID_CLFSH) != 0) { 5506 sched_pin(); 5507 pc = get_pcpu(); 5508 cmap_pte2 = pc->pc_cmap_pte2; 5509 mtx_lock(&pc->pc_cmap_lock); 5510 if (*cmap_pte2) 5511 panic("pmap_flush_page: CMAP2 busy"); 5512 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | 5513 PG_A | PG_M | pmap_cache_bits(kernel_pmap, m->md.pat_mode, 5514 0); 5515 invlcaddr(pc->pc_cmap_addr2); 5516 sva = (vm_offset_t)pc->pc_cmap_addr2; 5517 eva = sva + PAGE_SIZE; 5518 5519 /* 5520 * Use mfence or sfence despite the ordering implied by 5521 * mtx_{un,}lock() because clflush on non-Intel CPUs 5522 * and clflushopt are not guaranteed to be ordered by 5523 * any other instruction. 5524 */ 5525 if (useclflushopt) 5526 sfence(); 5527 else if (cpu_vendor_id != CPU_VENDOR_INTEL) 5528 mfence(); 5529 for (; sva < eva; sva += cpu_clflush_line_size) { 5530 if (useclflushopt) 5531 clflushopt(sva); 5532 else 5533 clflush(sva); 5534 } 5535 if (useclflushopt) 5536 sfence(); 5537 else if (cpu_vendor_id != CPU_VENDOR_INTEL) 5538 mfence(); 5539 *cmap_pte2 = 0; 5540 sched_unpin(); 5541 mtx_unlock(&pc->pc_cmap_lock); 5542 } else 5543 pmap_invalidate_cache(); 5544 } 5545 5546 /* 5547 * Changes the specified virtual address range's memory type to that given by 5548 * the parameter "mode". The specified virtual address range must be 5549 * completely contained within either the kernel map. 5550 * 5551 * Returns zero if the change completed successfully, and either EINVAL or 5552 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part 5553 * of the virtual address range was not mapped, and ENOMEM is returned if 5554 * there was insufficient memory available to complete the change. 5555 */ 5556 static int 5557 __CONCAT(PMTYPE, change_attr)(vm_offset_t va, vm_size_t size, int mode) 5558 { 5559 vm_offset_t base, offset, tmpva; 5560 pd_entry_t *pde; 5561 pt_entry_t *pte; 5562 int cache_bits_pte, cache_bits_pde; 5563 boolean_t changed; 5564 5565 base = trunc_page(va); 5566 offset = va & PAGE_MASK; 5567 size = round_page(offset + size); 5568 5569 /* 5570 * Only supported on kernel virtual addresses above the recursive map. 5571 */ 5572 if (base < VM_MIN_KERNEL_ADDRESS) 5573 return (EINVAL); 5574 5575 cache_bits_pde = pmap_cache_bits(kernel_pmap, mode, 1); 5576 cache_bits_pte = pmap_cache_bits(kernel_pmap, mode, 0); 5577 changed = FALSE; 5578 5579 /* 5580 * Pages that aren't mapped aren't supported. Also break down 5581 * 2/4MB pages into 4KB pages if required. 5582 */ 5583 PMAP_LOCK(kernel_pmap); 5584 for (tmpva = base; tmpva < base + size; ) { 5585 pde = pmap_pde(kernel_pmap, tmpva); 5586 if (*pde == 0) { 5587 PMAP_UNLOCK(kernel_pmap); 5588 return (EINVAL); 5589 } 5590 if (*pde & PG_PS) { 5591 /* 5592 * If the current 2/4MB page already has 5593 * the required memory type, then we need not 5594 * demote this page. Just increment tmpva to 5595 * the next 2/4MB page frame. 5596 */ 5597 if ((*pde & PG_PDE_CACHE) == cache_bits_pde) { 5598 tmpva = trunc_4mpage(tmpva) + NBPDR; 5599 continue; 5600 } 5601 5602 /* 5603 * If the current offset aligns with a 2/4MB 5604 * page frame and there is at least 2/4MB left 5605 * within the range, then we need not break 5606 * down this page into 4KB pages. 5607 */ 5608 if ((tmpva & PDRMASK) == 0 && 5609 tmpva + PDRMASK < base + size) { 5610 tmpva += NBPDR; 5611 continue; 5612 } 5613 if (!pmap_demote_pde(kernel_pmap, pde, tmpva)) { 5614 PMAP_UNLOCK(kernel_pmap); 5615 return (ENOMEM); 5616 } 5617 } 5618 pte = vtopte(tmpva); 5619 if (*pte == 0) { 5620 PMAP_UNLOCK(kernel_pmap); 5621 return (EINVAL); 5622 } 5623 tmpva += PAGE_SIZE; 5624 } 5625 PMAP_UNLOCK(kernel_pmap); 5626 5627 /* 5628 * Ok, all the pages exist, so run through them updating their 5629 * cache mode if required. 5630 */ 5631 for (tmpva = base; tmpva < base + size; ) { 5632 pde = pmap_pde(kernel_pmap, tmpva); 5633 if (*pde & PG_PS) { 5634 if ((*pde & PG_PDE_CACHE) != cache_bits_pde) { 5635 pmap_pde_attr(pde, cache_bits_pde); 5636 changed = TRUE; 5637 } 5638 tmpva = trunc_4mpage(tmpva) + NBPDR; 5639 } else { 5640 pte = vtopte(tmpva); 5641 if ((*pte & PG_PTE_CACHE) != cache_bits_pte) { 5642 pmap_pte_attr(pte, cache_bits_pte); 5643 changed = TRUE; 5644 } 5645 tmpva += PAGE_SIZE; 5646 } 5647 } 5648 5649 /* 5650 * Flush CPU caches to make sure any data isn't cached that 5651 * shouldn't be, etc. 5652 */ 5653 if (changed) { 5654 pmap_invalidate_range_int(kernel_pmap, base, tmpva); 5655 pmap_invalidate_cache_range(base, tmpva); 5656 } 5657 return (0); 5658 } 5659 5660 /* 5661 * perform the pmap work for mincore 5662 */ 5663 static int 5664 __CONCAT(PMTYPE, mincore)(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa) 5665 { 5666 pd_entry_t pde; 5667 pt_entry_t pte; 5668 vm_paddr_t pa; 5669 int val; 5670 5671 PMAP_LOCK(pmap); 5672 retry: 5673 pde = *pmap_pde(pmap, addr); 5674 if (pde != 0) { 5675 if ((pde & PG_PS) != 0) { 5676 pte = pde; 5677 /* Compute the physical address of the 4KB page. */ 5678 pa = ((pde & PG_PS_FRAME) | (addr & PDRMASK)) & 5679 PG_FRAME; 5680 val = MINCORE_SUPER; 5681 } else { 5682 pte = pmap_pte_ufast(pmap, addr, pde); 5683 pa = pte & PG_FRAME; 5684 val = 0; 5685 } 5686 } else { 5687 pte = 0; 5688 pa = 0; 5689 val = 0; 5690 } 5691 if ((pte & PG_V) != 0) { 5692 val |= MINCORE_INCORE; 5693 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 5694 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER; 5695 if ((pte & PG_A) != 0) 5696 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER; 5697 } 5698 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) != 5699 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) && 5700 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) { 5701 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */ 5702 if (vm_page_pa_tryrelock(pmap, pa, locked_pa)) 5703 goto retry; 5704 } else 5705 PA_UNLOCK_COND(*locked_pa); 5706 PMAP_UNLOCK(pmap); 5707 return (val); 5708 } 5709 5710 static void 5711 __CONCAT(PMTYPE, activate)(struct thread *td) 5712 { 5713 pmap_t pmap, oldpmap; 5714 u_int cpuid; 5715 u_int32_t cr3; 5716 5717 critical_enter(); 5718 pmap = vmspace_pmap(td->td_proc->p_vmspace); 5719 oldpmap = PCPU_GET(curpmap); 5720 cpuid = PCPU_GET(cpuid); 5721 #if defined(SMP) 5722 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active); 5723 CPU_SET_ATOMIC(cpuid, &pmap->pm_active); 5724 #else 5725 CPU_CLR(cpuid, &oldpmap->pm_active); 5726 CPU_SET(cpuid, &pmap->pm_active); 5727 #endif 5728 #ifdef PMAP_PAE_COMP 5729 cr3 = vtophys(pmap->pm_pdpt); 5730 #else 5731 cr3 = vtophys(pmap->pm_pdir); 5732 #endif 5733 /* 5734 * pmap_activate is for the current thread on the current cpu 5735 */ 5736 td->td_pcb->pcb_cr3 = cr3; 5737 PCPU_SET(curpmap, pmap); 5738 critical_exit(); 5739 } 5740 5741 static void 5742 __CONCAT(PMTYPE, activate_boot)(pmap_t pmap) 5743 { 5744 u_int cpuid; 5745 5746 cpuid = PCPU_GET(cpuid); 5747 #if defined(SMP) 5748 CPU_SET_ATOMIC(cpuid, &pmap->pm_active); 5749 #else 5750 CPU_SET(cpuid, &pmap->pm_active); 5751 #endif 5752 PCPU_SET(curpmap, pmap); 5753 } 5754 5755 /* 5756 * Increase the starting virtual address of the given mapping if a 5757 * different alignment might result in more superpage mappings. 5758 */ 5759 static void 5760 __CONCAT(PMTYPE, align_superpage)(vm_object_t object, vm_ooffset_t offset, 5761 vm_offset_t *addr, vm_size_t size) 5762 { 5763 vm_offset_t superpage_offset; 5764 5765 if (size < NBPDR) 5766 return; 5767 if (object != NULL && (object->flags & OBJ_COLORED) != 0) 5768 offset += ptoa(object->pg_color); 5769 superpage_offset = offset & PDRMASK; 5770 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR || 5771 (*addr & PDRMASK) == superpage_offset) 5772 return; 5773 if ((*addr & PDRMASK) < superpage_offset) 5774 *addr = (*addr & ~PDRMASK) + superpage_offset; 5775 else 5776 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset; 5777 } 5778 5779 static vm_offset_t 5780 __CONCAT(PMTYPE, quick_enter_page)(vm_page_t m) 5781 { 5782 vm_offset_t qaddr; 5783 pt_entry_t *pte; 5784 5785 critical_enter(); 5786 qaddr = PCPU_GET(qmap_addr); 5787 pte = vtopte(qaddr); 5788 5789 KASSERT(*pte == 0, 5790 ("pmap_quick_enter_page: PTE busy %#jx", (uintmax_t)*pte)); 5791 *pte = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M | 5792 pmap_cache_bits(kernel_pmap, pmap_page_get_memattr(m), 0); 5793 invlpg(qaddr); 5794 5795 return (qaddr); 5796 } 5797 5798 static void 5799 __CONCAT(PMTYPE, quick_remove_page)(vm_offset_t addr) 5800 { 5801 vm_offset_t qaddr; 5802 pt_entry_t *pte; 5803 5804 qaddr = PCPU_GET(qmap_addr); 5805 pte = vtopte(qaddr); 5806 5807 KASSERT(*pte != 0, ("pmap_quick_remove_page: PTE not in use")); 5808 KASSERT(addr == qaddr, ("pmap_quick_remove_page: invalid address")); 5809 5810 *pte = 0; 5811 critical_exit(); 5812 } 5813 5814 static vmem_t *pmap_trm_arena; 5815 static vmem_addr_t pmap_trm_arena_last = PMAP_TRM_MIN_ADDRESS; 5816 static int trm_guard = PAGE_SIZE; 5817 5818 static int 5819 pmap_trm_import(void *unused __unused, vmem_size_t size, int flags, 5820 vmem_addr_t *addrp) 5821 { 5822 vm_page_t m; 5823 vmem_addr_t af, addr, prev_addr; 5824 pt_entry_t *trm_pte; 5825 5826 prev_addr = atomic_load_long(&pmap_trm_arena_last); 5827 size = round_page(size) + trm_guard; 5828 for (;;) { 5829 if (prev_addr + size < prev_addr || prev_addr + size < size || 5830 prev_addr + size > PMAP_TRM_MAX_ADDRESS) 5831 return (ENOMEM); 5832 addr = prev_addr + size; 5833 if (atomic_fcmpset_int(&pmap_trm_arena_last, &prev_addr, addr)) 5834 break; 5835 } 5836 prev_addr += trm_guard; 5837 trm_pte = PTmap + atop(prev_addr); 5838 for (af = prev_addr; af < addr; af += PAGE_SIZE) { 5839 m = vm_page_alloc(NULL, 0, VM_ALLOC_NOOBJ | VM_ALLOC_NOBUSY | 5840 VM_ALLOC_NORMAL | VM_ALLOC_WIRED | VM_ALLOC_WAITOK); 5841 pte_store(&trm_pte[atop(af - prev_addr)], VM_PAGE_TO_PHYS(m) | 5842 PG_M | PG_A | PG_RW | PG_V | pgeflag | 5843 pmap_cache_bits(kernel_pmap, VM_MEMATTR_DEFAULT, FALSE)); 5844 } 5845 *addrp = prev_addr; 5846 return (0); 5847 } 5848 5849 void 5850 pmap_init_trm(void) 5851 { 5852 vm_page_t pd_m; 5853 5854 TUNABLE_INT_FETCH("machdep.trm_guard", &trm_guard); 5855 if ((trm_guard & PAGE_MASK) != 0) 5856 trm_guard = 0; 5857 pmap_trm_arena = vmem_create("i386trampoline", 0, 0, 1, 0, M_WAITOK); 5858 vmem_set_import(pmap_trm_arena, pmap_trm_import, NULL, NULL, PAGE_SIZE); 5859 pd_m = vm_page_alloc(NULL, 0, VM_ALLOC_NOOBJ | VM_ALLOC_NOBUSY | 5860 VM_ALLOC_NORMAL | VM_ALLOC_WIRED | VM_ALLOC_WAITOK | VM_ALLOC_ZERO); 5861 if ((pd_m->flags & PG_ZERO) == 0) 5862 pmap_zero_page(pd_m); 5863 PTD[TRPTDI] = VM_PAGE_TO_PHYS(pd_m) | PG_M | PG_A | PG_RW | PG_V | 5864 pmap_cache_bits(kernel_pmap, VM_MEMATTR_DEFAULT, TRUE); 5865 } 5866 5867 static void * 5868 __CONCAT(PMTYPE, trm_alloc)(size_t size, int flags) 5869 { 5870 vmem_addr_t res; 5871 int error; 5872 5873 MPASS((flags & ~(M_WAITOK | M_NOWAIT | M_ZERO)) == 0); 5874 error = vmem_xalloc(pmap_trm_arena, roundup2(size, 4), sizeof(int), 5875 0, 0, VMEM_ADDR_MIN, VMEM_ADDR_MAX, flags | M_FIRSTFIT, &res); 5876 if (error != 0) 5877 return (NULL); 5878 if ((flags & M_ZERO) != 0) 5879 bzero((void *)res, size); 5880 return ((void *)res); 5881 } 5882 5883 static void 5884 __CONCAT(PMTYPE, trm_free)(void *addr, size_t size) 5885 { 5886 5887 vmem_free(pmap_trm_arena, (uintptr_t)addr, roundup2(size, 4)); 5888 } 5889 5890 #if defined(PMAP_DEBUG) 5891 pmap_pid_dump(int pid) 5892 { 5893 pmap_t pmap; 5894 struct proc *p; 5895 int npte = 0; 5896 int index; 5897 5898 sx_slock(&allproc_lock); 5899 FOREACH_PROC_IN_SYSTEM(p) { 5900 if (p->p_pid != pid) 5901 continue; 5902 5903 if (p->p_vmspace) { 5904 int i,j; 5905 index = 0; 5906 pmap = vmspace_pmap(p->p_vmspace); 5907 for (i = 0; i < NPDEPTD; i++) { 5908 pd_entry_t *pde; 5909 pt_entry_t *pte; 5910 vm_offset_t base = i << PDRSHIFT; 5911 5912 pde = &pmap->pm_pdir[i]; 5913 if (pde && pmap_pde_v(pde)) { 5914 for (j = 0; j < NPTEPG; j++) { 5915 vm_offset_t va = base + (j << PAGE_SHIFT); 5916 if (va >= (vm_offset_t) VM_MIN_KERNEL_ADDRESS) { 5917 if (index) { 5918 index = 0; 5919 printf("\n"); 5920 } 5921 sx_sunlock(&allproc_lock); 5922 return (npte); 5923 } 5924 pte = pmap_pte(pmap, va); 5925 if (pte && pmap_pte_v(pte)) { 5926 pt_entry_t pa; 5927 vm_page_t m; 5928 pa = *pte; 5929 m = PHYS_TO_VM_PAGE(pa & PG_FRAME); 5930 printf("va: 0x%x, pt: 0x%x, h: %d, w: %d, f: 0x%x", 5931 va, pa, m->hold_count, m->wire_count, m->flags); 5932 npte++; 5933 index++; 5934 if (index >= 2) { 5935 index = 0; 5936 printf("\n"); 5937 } else { 5938 printf(" "); 5939 } 5940 } 5941 } 5942 } 5943 } 5944 } 5945 } 5946 sx_sunlock(&allproc_lock); 5947 return (npte); 5948 } 5949 #endif 5950 5951 static void 5952 __CONCAT(PMTYPE, ksetrw)(vm_offset_t va) 5953 { 5954 5955 *vtopte(va) |= PG_RW; 5956 } 5957 5958 static void 5959 __CONCAT(PMTYPE, remap_lowptdi)(bool enable) 5960 { 5961 5962 PTD[KPTDI] = enable ? PTD[LOWPTDI] : 0; 5963 invltlb_glob(); 5964 } 5965 5966 static vm_offset_t 5967 __CONCAT(PMTYPE, get_map_low)(void) 5968 { 5969 5970 return (PMAP_MAP_LOW); 5971 } 5972 5973 static vm_offset_t 5974 __CONCAT(PMTYPE, get_vm_maxuser_address)(void) 5975 { 5976 5977 return (VM_MAXUSER_ADDRESS); 5978 } 5979 5980 static vm_paddr_t 5981 __CONCAT(PMTYPE, pg_frame)(vm_paddr_t pa) 5982 { 5983 5984 return (pa & PG_FRAME); 5985 } 5986 5987 static void 5988 __CONCAT(PMTYPE, sf_buf_map)(struct sf_buf *sf) 5989 { 5990 pt_entry_t opte, *ptep; 5991 5992 /* 5993 * Update the sf_buf's virtual-to-physical mapping, flushing the 5994 * virtual address from the TLB. Since the reference count for 5995 * the sf_buf's old mapping was zero, that mapping is not 5996 * currently in use. Consequently, there is no need to exchange 5997 * the old and new PTEs atomically, even under PAE. 5998 */ 5999 ptep = vtopte(sf->kva); 6000 opte = *ptep; 6001 *ptep = VM_PAGE_TO_PHYS(sf->m) | PG_RW | PG_V | 6002 pmap_cache_bits(kernel_pmap, sf->m->md.pat_mode, 0); 6003 6004 /* 6005 * Avoid unnecessary TLB invalidations: If the sf_buf's old 6006 * virtual-to-physical mapping was not used, then any processor 6007 * that has invalidated the sf_buf's virtual address from its TLB 6008 * since the last used mapping need not invalidate again. 6009 */ 6010 #ifdef SMP 6011 if ((opte & (PG_V | PG_A)) == (PG_V | PG_A)) 6012 CPU_ZERO(&sf->cpumask); 6013 #else 6014 if ((opte & (PG_V | PG_A)) == (PG_V | PG_A)) 6015 pmap_invalidate_page_int(kernel_pmap, sf->kva); 6016 #endif 6017 } 6018 6019 static void 6020 __CONCAT(PMTYPE, cp_slow0_map)(vm_offset_t kaddr, int plen, vm_page_t *ma) 6021 { 6022 pt_entry_t *pte; 6023 int i; 6024 6025 for (i = 0, pte = vtopte(kaddr); i < plen; i++, pte++) { 6026 *pte = PG_V | PG_RW | PG_A | PG_M | VM_PAGE_TO_PHYS(ma[i]) | 6027 pmap_cache_bits(kernel_pmap, pmap_page_get_memattr(ma[i]), 6028 FALSE); 6029 invlpg(kaddr + ptoa(i)); 6030 } 6031 } 6032 6033 static u_int 6034 __CONCAT(PMTYPE, get_kcr3)(void) 6035 { 6036 6037 #ifdef PMAP_PAE_COMP 6038 return ((u_int)IdlePDPT); 6039 #else 6040 return ((u_int)IdlePTD); 6041 #endif 6042 } 6043 6044 static u_int 6045 __CONCAT(PMTYPE, get_cr3)(pmap_t pmap) 6046 { 6047 6048 #ifdef PMAP_PAE_COMP 6049 return ((u_int)vtophys(pmap->pm_pdpt)); 6050 #else 6051 return ((u_int)vtophys(pmap->pm_pdir)); 6052 #endif 6053 } 6054 6055 static caddr_t 6056 __CONCAT(PMTYPE, cmap3)(vm_paddr_t pa, u_int pte_bits) 6057 { 6058 pt_entry_t *pte; 6059 6060 pte = CMAP3; 6061 *pte = pa | pte_bits; 6062 invltlb(); 6063 return (CADDR3); 6064 } 6065 6066 static void 6067 __CONCAT(PMTYPE, basemem_setup)(u_int basemem) 6068 { 6069 pt_entry_t *pte; 6070 int i; 6071 6072 /* 6073 * Map pages between basemem and ISA_HOLE_START, if any, r/w into 6074 * the vm86 page table so that vm86 can scribble on them using 6075 * the vm86 map too. XXX: why 2 ways for this and only 1 way for 6076 * page 0, at least as initialized here? 6077 */ 6078 pte = (pt_entry_t *)vm86paddr; 6079 for (i = basemem / 4; i < 160; i++) 6080 pte[i] = (i << PAGE_SHIFT) | PG_V | PG_RW | PG_U; 6081 } 6082 6083 struct bios16_pmap_handle { 6084 pt_entry_t *pte; 6085 pd_entry_t *ptd; 6086 pt_entry_t orig_ptd; 6087 }; 6088 6089 static void * 6090 __CONCAT(PMTYPE, bios16_enter)(void) 6091 { 6092 struct bios16_pmap_handle *h; 6093 6094 /* 6095 * no page table, so create one and install it. 6096 */ 6097 h = malloc(sizeof(struct bios16_pmap_handle), M_TEMP, M_WAITOK); 6098 h->pte = (pt_entry_t *)malloc(PAGE_SIZE, M_TEMP, M_WAITOK); 6099 h->ptd = IdlePTD; 6100 *h->pte = vm86phystk | PG_RW | PG_V; 6101 h->orig_ptd = *h->ptd; 6102 *h->ptd = vtophys(h->pte) | PG_RW | PG_V; 6103 pmap_invalidate_all_int(kernel_pmap); /* XXX insurance for now */ 6104 return (h); 6105 } 6106 6107 static void 6108 __CONCAT(PMTYPE, bios16_leave)(void *arg) 6109 { 6110 struct bios16_pmap_handle *h; 6111 6112 h = arg; 6113 *h->ptd = h->orig_ptd; /* remove page table */ 6114 /* 6115 * XXX only needs to be invlpg(0) but that doesn't work on the 386 6116 */ 6117 pmap_invalidate_all_int(kernel_pmap); 6118 free(h->pte, M_TEMP); /* ... and free it */ 6119 } 6120 6121 #define PMM(a) \ 6122 .pm_##a = __CONCAT(PMTYPE, a), 6123 6124 struct pmap_methods __CONCAT(PMTYPE, methods) = { 6125 PMM(ksetrw) 6126 PMM(remap_lower) 6127 PMM(remap_lowptdi) 6128 PMM(align_superpage) 6129 PMM(quick_enter_page) 6130 PMM(quick_remove_page) 6131 PMM(trm_alloc) 6132 PMM(trm_free) 6133 PMM(get_map_low) 6134 PMM(get_vm_maxuser_address) 6135 PMM(kextract) 6136 PMM(pg_frame) 6137 PMM(sf_buf_map) 6138 PMM(cp_slow0_map) 6139 PMM(get_kcr3) 6140 PMM(get_cr3) 6141 PMM(cmap3) 6142 PMM(basemem_setup) 6143 PMM(set_nx) 6144 PMM(bios16_enter) 6145 PMM(bios16_leave) 6146 PMM(bootstrap) 6147 PMM(is_valid_memattr) 6148 PMM(cache_bits) 6149 PMM(ps_enabled) 6150 PMM(pinit0) 6151 PMM(pinit) 6152 PMM(activate) 6153 PMM(activate_boot) 6154 PMM(advise) 6155 PMM(clear_modify) 6156 PMM(change_attr) 6157 PMM(mincore) 6158 PMM(copy) 6159 PMM(copy_page) 6160 PMM(copy_pages) 6161 PMM(zero_page) 6162 PMM(zero_page_area) 6163 PMM(enter) 6164 PMM(enter_object) 6165 PMM(enter_quick) 6166 PMM(kenter_temporary) 6167 PMM(object_init_pt) 6168 PMM(unwire) 6169 PMM(page_exists_quick) 6170 PMM(page_wired_mappings) 6171 PMM(page_is_mapped) 6172 PMM(remove_pages) 6173 PMM(is_modified) 6174 PMM(is_prefaultable) 6175 PMM(is_referenced) 6176 PMM(remove_write) 6177 PMM(ts_referenced) 6178 PMM(mapdev_attr) 6179 PMM(unmapdev) 6180 PMM(page_set_memattr) 6181 PMM(extract) 6182 PMM(extract_and_hold) 6183 PMM(map) 6184 PMM(qenter) 6185 PMM(qremove) 6186 PMM(release) 6187 PMM(remove) 6188 PMM(protect) 6189 PMM(remove_all) 6190 PMM(init) 6191 PMM(init_pat) 6192 PMM(growkernel) 6193 PMM(invalidate_page) 6194 PMM(invalidate_range) 6195 PMM(invalidate_all) 6196 PMM(invalidate_cache) 6197 PMM(flush_page) 6198 PMM(kenter) 6199 PMM(kremove) 6200 }; 6201